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[PATCH] W1: cleanups
[linux-2.6/verdex.git] / sound / sparc / dbri.c
blobe622d08215c97e65bda17aa3642bb306071c7b51
1 /*
2 * Driver for DBRI sound chip found on Sparcs.
3 * Copyright (C) 2004, 2005 Martin Habets (mhabets@users.sourceforge.net)
4 *
5 * Based entirely upon drivers/sbus/audio/dbri.c which is:
6 * Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de)
7 * Copyright (C) 1998, 1999 Brent Baccala (baccala@freesoft.org)
8 *
9 * This is the lowlevel driver for the DBRI & MMCODEC duo used for ISDN & AUDIO
10 * on Sun SPARCstation 10, 20, LX and Voyager models.
11 *
12 * - DBRI: AT&T T5900FX Dual Basic Rates ISDN Interface. It is a 32 channel
13 * data time multiplexer with ISDN support (aka T7259)
14 * Interfaces: SBus,ISDN NT & TE, CHI, 4 bits parallel.
15 * CHI: (spelled ki) Concentration Highway Interface (AT&T or Intel bus ?).
16 * Documentation:
17 * - "STP 4000SBus Dual Basic Rate ISDN (DBRI) Tranceiver" from
18 * Sparc Technology Business (courtesy of Sun Support)
19 * - Data sheet of the T7903, a newer but very similar ISA bus equivalent
20 * available from the Lucent (formarly AT&T microelectronics) home
21 * page.
22 * - http://www.freesoft.org/Linux/DBRI/
23 * - MMCODEC: Crystal Semiconductor CS4215 16 bit Multimedia Audio Codec
24 * Interfaces: CHI, Audio In & Out, 2 bits parallel
25 * Documentation: from the Crystal Semiconductor home page.
26 *
27 * The DBRI is a 32 pipe machine, each pipe can transfer some bits between
28 * memory and a serial device (long pipes, nr 0-15) or between two serial
29 * devices (short pipes, nr 16-31), or simply send a fixed data to a serial
30 * device (short pipes).
31 * A timeslot defines the bit-offset and nr of bits read from a serial device.
32 * The timeslots are linked to 6 circular lists, one for each direction for
33 * each serial device (NT,TE,CHI). A timeslot is associated to 1 or 2 pipes
34 * (the second one is a monitor/tee pipe, valid only for serial input).
35 *
36 * The mmcodec is connected via the CHI bus and needs the data & some
37 * parameters (volume, balance, output selection) timemultiplexed in 8 byte
38 * chunks. It also has a control mode, which serves for audio format setting.
39 *
40 * Looking at the CS4215 data sheet it is easy to set up 2 or 4 codecs on
41 * the same CHI bus, so I thought perhaps it is possible to use the onboard
42 * & the speakerbox codec simultanously, giving 2 (not very independent :-)
43 * audio devices. But the SUN HW group decided against it, at least on my
44 * LX the speakerbox connector has at least 1 pin missing and 1 wrongly
45 * connected.
46 *
47 * I've tried to stick to the following function naming conventions:
48 * snd_* ALSA stuff
49 * cs4215_* CS4215 codec specfic stuff
50 * dbri_* DBRI high-level stuff
51 * other DBRI low-level stuff
52 */
53
54 #include <sound/driver.h>
55 #include <linux/interrupt.h>
56 #include <linux/delay.h>
57
58 #include <sound/core.h>
59 #include <sound/pcm.h>
60 #include <sound/pcm_params.h>
61 #include <sound/info.h>
62 #include <sound/control.h>
63 #include <sound/initval.h>
64
65 #include <asm/irq.h>
66 #include <asm/io.h>
67 #include <asm/sbus.h>
68 #include <asm/atomic.h>
69
70 MODULE_AUTHOR("Rudolf Koenig, Brent Baccala and Martin Habets");
71 MODULE_DESCRIPTION("Sun DBRI");
72 MODULE_LICENSE("GPL");
73 MODULE_SUPPORTED_DEVICE("{{Sun,DBRI}}");
74
75 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
76 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
77 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP; /* Enable this card */
78
79 module_param_array(index, int, NULL, 0444);
80 MODULE_PARM_DESC(index, "Index value for Sun DBRI soundcard.");
81 module_param_array(id, charp, NULL, 0444);
82 MODULE_PARM_DESC(id, "ID string for Sun DBRI soundcard.");
83 module_param_array(enable, bool, NULL, 0444);
84 MODULE_PARM_DESC(enable, "Enable Sun DBRI soundcard.");
85
86 #define DBRI_DEBUG
87
88 #define D_INT (1<<0)
89 #define D_GEN (1<<1)
90 #define D_CMD (1<<2)
91 #define D_MM (1<<3)
92 #define D_USR (1<<4)
93 #define D_DESC (1<<5)
94
95 static int dbri_debug = 0;
96 module_param(dbri_debug, int, 0644);
97 MODULE_PARM_DESC(dbri_debug, "Debug value for Sun DBRI soundcard.");
98
99 #ifdef DBRI_DEBUG
100 static char *cmds[] = {
101 "WAIT", "PAUSE", "JUMP", "IIQ", "REX", "SDP", "CDP", "DTS",
102 "SSP", "CHI", "NT", "TE", "CDEC", "TEST", "CDM", "RESRV"
103 };
104
105 #define dprintk(a, x...) if(dbri_debug & a) printk(KERN_DEBUG x)
106
107 #define DBRI_CMD(cmd, intr, value) ((cmd << 28) | \
108 (1 << 27) | \
109 value)
110 #else
111 #define dprintk(a, x...)
112
113 #define DBRI_CMD(cmd, intr, value) ((cmd << 28) | \
114 (intr << 27) | \
115 value)
116 #endif /* DBRI_DEBUG */
117
118 /***************************************************************************
119 CS4215 specific definitions and structures
120 ****************************************************************************/
121
122 struct cs4215 {
123 __u8 data[4]; /* Data mode: Time slots 5-8 */
124 __u8 ctrl[4]; /* Ctrl mode: Time slots 1-4 */
125 __u8 onboard;
126 __u8 offset; /* Bit offset from frame sync to time slot 1 */
127 volatile __u32 status;
128 volatile __u32 version;
129 __u8 precision; /* In bits, either 8 or 16 */
130 __u8 channels; /* 1 or 2 */
131 };
132
133 /*
134 * Control mode first
135 */
136
137 /* Time Slot 1, Status register */
138 #define CS4215_CLB (1<<2) /* Control Latch Bit */
139 #define CS4215_OLB (1<<3) /* 1: line: 2.0V, speaker 4V */
140 /* 0: line: 2.8V, speaker 8V */
141 #define CS4215_MLB (1<<4) /* 1: Microphone: 20dB gain disabled */
142 #define CS4215_RSRVD_1 (1<<5)
143
144 /* Time Slot 2, Data Format Register */
145 #define CS4215_DFR_LINEAR16 0
146 #define CS4215_DFR_ULAW 1
147 #define CS4215_DFR_ALAW 2
148 #define CS4215_DFR_LINEAR8 3
149 #define CS4215_DFR_STEREO (1<<2)
150 static struct {
151 unsigned short freq;
152 unsigned char xtal;
153 unsigned char csval;
154 } CS4215_FREQ[] = {
155 { 8000, (1 << 4), (0 << 3) },
156 { 16000, (1 << 4), (1 << 3) },
157 { 27429, (1 << 4), (2 << 3) }, /* Actually 24428.57 */
158 { 32000, (1 << 4), (3 << 3) },
159 /* { NA, (1 << 4), (4 << 3) }, */
160 /* { NA, (1 << 4), (5 << 3) }, */
161 { 48000, (1 << 4), (6 << 3) },
162 { 9600, (1 << 4), (7 << 3) },
163 { 5513, (2 << 4), (0 << 3) }, /* Actually 5512.5 */
164 { 11025, (2 << 4), (1 << 3) },
165 { 18900, (2 << 4), (2 << 3) },
166 { 22050, (2 << 4), (3 << 3) },
167 { 37800, (2 << 4), (4 << 3) },
168 { 44100, (2 << 4), (5 << 3) },
169 { 33075, (2 << 4), (6 << 3) },
170 { 6615, (2 << 4), (7 << 3) },
171 { 0, 0, 0}
172 };
173
174 #define CS4215_HPF (1<<7) /* High Pass Filter, 1: Enabled */
175
176 #define CS4215_12_MASK 0xfcbf /* Mask off reserved bits in slot 1 & 2 */
177
178 /* Time Slot 3, Serial Port Control register */
179 #define CS4215_XEN (1<<0) /* 0: Enable serial output */
180 #define CS4215_XCLK (1<<1) /* 1: Master mode: Generate SCLK */
181 #define CS4215_BSEL_64 (0<<2) /* Bitrate: 64 bits per frame */
182 #define CS4215_BSEL_128 (1<<2)
183 #define CS4215_BSEL_256 (2<<2)
184 #define CS4215_MCK_MAST (0<<4) /* Master clock */
185 #define CS4215_MCK_XTL1 (1<<4) /* 24.576 MHz clock source */
186 #define CS4215_MCK_XTL2 (2<<4) /* 16.9344 MHz clock source */
187 #define CS4215_MCK_CLK1 (3<<4) /* Clockin, 256 x Fs */
188 #define CS4215_MCK_CLK2 (4<<4) /* Clockin, see DFR */
189
190 /* Time Slot 4, Test Register */
191 #define CS4215_DAD (1<<0) /* 0:Digital-Dig loop, 1:Dig-Analog-Dig loop */
192 #define CS4215_ENL (1<<1) /* Enable Loopback Testing */
193
194 /* Time Slot 5, Parallel Port Register */
195 /* Read only here and the same as the in data mode */
196
197 /* Time Slot 6, Reserved */
198
199 /* Time Slot 7, Version Register */
200 #define CS4215_VERSION_MASK 0xf /* Known versions 0/C, 1/D, 2/E */
201
202 /* Time Slot 8, Reserved */
203
204 /*
205 * Data mode
206 */
207 /* Time Slot 1-2: Left Channel Data, 2-3: Right Channel Data */
208
209 /* Time Slot 5, Output Setting */
210 #define CS4215_LO(v) v /* Left Output Attenuation 0x3f: -94.5 dB */
211 #define CS4215_LE (1<<6) /* Line Out Enable */
212 #define CS4215_HE (1<<7) /* Headphone Enable */
213
214 /* Time Slot 6, Output Setting */
215 #define CS4215_RO(v) v /* Right Output Attenuation 0x3f: -94.5 dB */
216 #define CS4215_SE (1<<6) /* Speaker Enable */
217 #define CS4215_ADI (1<<7) /* A/D Data Invalid: Busy in calibration */
218
219 /* Time Slot 7, Input Setting */
220 #define CS4215_LG(v) v /* Left Gain Setting 0xf: 22.5 dB */
221 #define CS4215_IS (1<<4) /* Input Select: 1=Microphone, 0=Line */
222 #define CS4215_OVR (1<<5) /* 1: Overrange condition occurred */
223 #define CS4215_PIO0 (1<<6) /* Parallel I/O 0 */
224 #define CS4215_PIO1 (1<<7)
225
226 /* Time Slot 8, Input Setting */
227 #define CS4215_RG(v) v /* Right Gain Setting 0xf: 22.5 dB */
228 #define CS4215_MA(v) (v<<4) /* Monitor Path Attenuation 0xf: mute */
229
230 /***************************************************************************
231 DBRI specific definitions and structures
232 ****************************************************************************/
233
234 /* DBRI main registers */
235 #define REG0 0x00UL /* Status and Control */
236 #define REG1 0x04UL /* Mode and Interrupt */
237 #define REG2 0x08UL /* Parallel IO */
238 #define REG3 0x0cUL /* Test */
239 #define REG8 0x20UL /* Command Queue Pointer */
240 #define REG9 0x24UL /* Interrupt Queue Pointer */
241
242 #define DBRI_NO_CMDS 64
243 #define DBRI_NO_INTS 1 /* Note: the value of this define was
244 * originally 2. The ringbuffer to store
245 * interrupts in dma is currently broken.
246 * This is a temporary fix until the ringbuffer
247 * is fixed.
248 */
249 #define DBRI_INT_BLK 64
250 #define DBRI_NO_DESCS 64
251 #define DBRI_NO_PIPES 32
252
253 #define DBRI_MM_ONB 1
254 #define DBRI_MM_SB 2
255
256 #define DBRI_REC 0
257 #define DBRI_PLAY 1
258 #define DBRI_NO_STREAMS 2
259
260 /* One transmit/receive descriptor */
261 struct dbri_mem {
262 volatile __u32 word1;
263 volatile __u32 ba; /* Transmit/Receive Buffer Address */
264 volatile __u32 nda; /* Next Descriptor Address */
265 volatile __u32 word4;
266 };
267
268 /* This structure is in a DMA region where it can accessed by both
269 * the CPU and the DBRI
270 */
271 struct dbri_dma {
272 volatile s32 cmd[DBRI_NO_CMDS]; /* Place for commands */
273 volatile s32 intr[DBRI_NO_INTS * DBRI_INT_BLK]; /* Interrupt field */
274 struct dbri_mem desc[DBRI_NO_DESCS]; /* Xmit/receive descriptors */
275 };
276
277 #define dbri_dma_off(member, elem) \
278 ((u32)(unsigned long) \
279 (&(((struct dbri_dma *)0)->member[elem])))
280
281 enum in_or_out { PIPEinput, PIPEoutput };
282
283 struct dbri_pipe {
284 u32 sdp; /* SDP command word */
285 enum in_or_out direction;
286 int nextpipe; /* Next pipe in linked list */
287 int prevpipe;
288 int cycle; /* Offset of timeslot (bits) */
289 int length; /* Length of timeslot (bits) */
290 int first_desc; /* Index of first descriptor */
291 int desc; /* Index of active descriptor */
292 volatile __u32 *recv_fixed_ptr; /* Ptr to receive fixed data */
293 };
294
295 struct dbri_desc {
296 int inuse; /* Boolean flag */
297 int next; /* Index of next desc, or -1 */
298 unsigned int len;
299 };
300
301 /* Per stream (playback or record) information */
302 struct dbri_streaminfo {
303 struct snd_pcm_substream *substream;
304 u32 dvma_buffer; /* Device view of Alsa DMA buffer */
305 int left; /* # of bytes left in DMA buffer */
306 int size; /* Size of DMA buffer */
307 size_t offset; /* offset in user buffer */
308 int pipe; /* Data pipe used */
309 int left_gain; /* mixer elements */
310 int right_gain;
311 int balance;
312 };
313
314 /* This structure holds the information for both chips (DBRI & CS4215) */
315 struct snd_dbri {
316 struct snd_card *card; /* ALSA card */
317 struct snd_pcm *pcm;
318
319 int regs_size, irq; /* Needed for unload */
320 struct sbus_dev *sdev; /* SBUS device info */
321 spinlock_t lock;
322
323 volatile struct dbri_dma *dma; /* Pointer to our DMA block */
324 u32 dma_dvma; /* DBRI visible DMA address */
325
326 void __iomem *regs; /* dbri HW regs */
327 int dbri_version; /* 'e' and up is OK */
328 int dbri_irqp; /* intr queue pointer */
329 int wait_send; /* sequence of command buffers send */
330 int wait_ackd; /* sequence of command buffers acknowledged */
331
332 struct dbri_pipe pipes[DBRI_NO_PIPES]; /* DBRI's 32 data pipes */
333 struct dbri_desc descs[DBRI_NO_DESCS];
334
335 int chi_in_pipe;
336 int chi_out_pipe;
337 int chi_bpf;
338
339 struct cs4215 mm; /* mmcodec special info */
340 /* per stream (playback/record) info */
341 struct dbri_streaminfo stream_info[DBRI_NO_STREAMS];
342
343 struct snd_dbri *next;
344 };
345
346 #define DBRI_MAX_VOLUME 63 /* Output volume */
347 #define DBRI_MAX_GAIN 15 /* Input gain */
348 #define DBRI_RIGHT_BALANCE 255
349 #define DBRI_MID_BALANCE (DBRI_RIGHT_BALANCE >> 1)
350
351 /* DBRI Reg0 - Status Control Register - defines. (Page 17) */
352 #define D_P (1<<15) /* Program command & queue pointer valid */
353 #define D_G (1<<14) /* Allow 4-Word SBus Burst */
354 #define D_S (1<<13) /* Allow 16-Word SBus Burst */
355 #define D_E (1<<12) /* Allow 8-Word SBus Burst */
356 #define D_X (1<<7) /* Sanity Timer Disable */
357 #define D_T (1<<6) /* Permit activation of the TE interface */
358 #define D_N (1<<5) /* Permit activation of the NT interface */
359 #define D_C (1<<4) /* Permit activation of the CHI interface */
360 #define D_F (1<<3) /* Force Sanity Timer Time-Out */
361 #define D_D (1<<2) /* Disable Master Mode */
362 #define D_H (1<<1) /* Halt for Analysis */
363 #define D_R (1<<0) /* Soft Reset */
364
365 /* DBRI Reg1 - Mode and Interrupt Register - defines. (Page 18) */
366 #define D_LITTLE_END (1<<8) /* Byte Order */
367 #define D_BIG_END (0<<8) /* Byte Order */
368 #define D_MRR (1<<4) /* Multiple Error Ack on SBus (readonly) */
369 #define D_MLE (1<<3) /* Multiple Late Error on SBus (readonly) */
370 #define D_LBG (1<<2) /* Lost Bus Grant on SBus (readonly) */
371 #define D_MBE (1<<1) /* Burst Error on SBus (readonly) */
372 #define D_IR (1<<0) /* Interrupt Indicator (readonly) */
373
374 /* DBRI Reg2 - Parallel IO Register - defines. (Page 18) */
375 #define D_ENPIO3 (1<<7) /* Enable Pin 3 */
376 #define D_ENPIO2 (1<<6) /* Enable Pin 2 */
377 #define D_ENPIO1 (1<<5) /* Enable Pin 1 */
378 #define D_ENPIO0 (1<<4) /* Enable Pin 0 */
379 #define D_ENPIO (0xf0) /* Enable all the pins */
380 #define D_PIO3 (1<<3) /* Pin 3: 1: Data mode, 0: Ctrl mode */
381 #define D_PIO2 (1<<2) /* Pin 2: 1: Onboard PDN */
382 #define D_PIO1 (1<<1) /* Pin 1: 0: Reset */
383 #define D_PIO0 (1<<0) /* Pin 0: 1: Speakerbox PDN */
384
385 /* DBRI Commands (Page 20) */
386 #define D_WAIT 0x0 /* Stop execution */
387 #define D_PAUSE 0x1 /* Flush long pipes */
388 #define D_JUMP 0x2 /* New command queue */
389 #define D_IIQ 0x3 /* Initialize Interrupt Queue */
390 #define D_REX 0x4 /* Report command execution via interrupt */
391 #define D_SDP 0x5 /* Setup Data Pipe */
392 #define D_CDP 0x6 /* Continue Data Pipe (reread NULL Pointer) */
393 #define D_DTS 0x7 /* Define Time Slot */
394 #define D_SSP 0x8 /* Set short Data Pipe */
395 #define D_CHI 0x9 /* Set CHI Global Mode */
396 #define D_NT 0xa /* NT Command */
397 #define D_TE 0xb /* TE Command */
398 #define D_CDEC 0xc /* Codec setup */
399 #define D_TEST 0xd /* No comment */
400 #define D_CDM 0xe /* CHI Data mode command */
401
402 /* Special bits for some commands */
403 #define D_PIPE(v) ((v)<<0) /* Pipe Nr: 0-15 long, 16-21 short */
404
405 /* Setup Data Pipe */
406 /* IRM */
407 #define D_SDP_2SAME (1<<18) /* Report 2nd time in a row value rcvd */
408 #define D_SDP_CHANGE (2<<18) /* Report any changes */
409 #define D_SDP_EVERY (3<<18) /* Report any changes */
410 #define D_SDP_EOL (1<<17) /* EOL interrupt enable */
411 #define D_SDP_IDLE (1<<16) /* HDLC idle interrupt enable */
412
413 /* Pipe data MODE */
414 #define D_SDP_MEM (0<<13) /* To/from memory */
415 #define D_SDP_HDLC (2<<13)
416 #define D_SDP_HDLC_D (3<<13) /* D Channel (prio control) */
417 #define D_SDP_SER (4<<13) /* Serial to serial */
418 #define D_SDP_FIXED (6<<13) /* Short only */
419 #define D_SDP_MODE(v) ((v)&(7<<13))
420
421 #define D_SDP_TO_SER (1<<12) /* Direction */
422 #define D_SDP_FROM_SER (0<<12) /* Direction */
423 #define D_SDP_MSB (1<<11) /* Bit order within Byte */
424 #define D_SDP_LSB (0<<11) /* Bit order within Byte */
425 #define D_SDP_P (1<<10) /* Pointer Valid */
426 #define D_SDP_A (1<<8) /* Abort */
427 #define D_SDP_C (1<<7) /* Clear */
428
429 /* Define Time Slot */
430 #define D_DTS_VI (1<<17) /* Valid Input Time-Slot Descriptor */
431 #define D_DTS_VO (1<<16) /* Valid Output Time-Slot Descriptor */
432 #define D_DTS_INS (1<<15) /* Insert Time Slot */
433 #define D_DTS_DEL (0<<15) /* Delete Time Slot */
434 #define D_DTS_PRVIN(v) ((v)<<10) /* Previous In Pipe */
435 #define D_DTS_PRVOUT(v) ((v)<<5) /* Previous Out Pipe */
436
437 /* Time Slot defines */
438 #define D_TS_LEN(v) ((v)<<24) /* Number of bits in this time slot */
439 #define D_TS_CYCLE(v) ((v)<<14) /* Bit Count at start of TS */
440 #define D_TS_DI (1<<13) /* Data Invert */
441 #define D_TS_1CHANNEL (0<<10) /* Single Channel / Normal mode */
442 #define D_TS_MONITOR (2<<10) /* Monitor pipe */
443 #define D_TS_NONCONTIG (3<<10) /* Non contiguous mode */
444 #define D_TS_ANCHOR (7<<10) /* Starting short pipes */
445 #define D_TS_MON(v) ((v)<<5) /* Monitor Pipe */
446 #define D_TS_NEXT(v) ((v)<<0) /* Pipe Nr: 0-15 long, 16-21 short */
447
448 /* Concentration Highway Interface Modes */
449 #define D_CHI_CHICM(v) ((v)<<16) /* Clock mode */
450 #define D_CHI_IR (1<<15) /* Immediate Interrupt Report */
451 #define D_CHI_EN (1<<14) /* CHIL Interrupt enabled */
452 #define D_CHI_OD (1<<13) /* Open Drain Enable */
453 #define D_CHI_FE (1<<12) /* Sample CHIFS on Rising Frame Edge */
454 #define D_CHI_FD (1<<11) /* Frame Drive */
455 #define D_CHI_BPF(v) ((v)<<0) /* Bits per Frame */
456
457 /* NT: These are here for completeness */
458 #define D_NT_FBIT (1<<17) /* Frame Bit */
459 #define D_NT_NBF (1<<16) /* Number of bad frames to loose framing */
460 #define D_NT_IRM_IMM (1<<15) /* Interrupt Report & Mask: Immediate */
461 #define D_NT_IRM_EN (1<<14) /* Interrupt Report & Mask: Enable */
462 #define D_NT_ISNT (1<<13) /* Configfure interface as NT */
463 #define D_NT_FT (1<<12) /* Fixed Timing */
464 #define D_NT_EZ (1<<11) /* Echo Channel is Zeros */
465 #define D_NT_IFA (1<<10) /* Inhibit Final Activation */
466 #define D_NT_ACT (1<<9) /* Activate Interface */
467 #define D_NT_MFE (1<<8) /* Multiframe Enable */
468 #define D_NT_RLB(v) ((v)<<5) /* Remote Loopback */
469 #define D_NT_LLB(v) ((v)<<2) /* Local Loopback */
470 #define D_NT_FACT (1<<1) /* Force Activation */
471 #define D_NT_ABV (1<<0) /* Activate Bipolar Violation */
472
473 /* Codec Setup */
474 #define D_CDEC_CK(v) ((v)<<24) /* Clock Select */
475 #define D_CDEC_FED(v) ((v)<<12) /* FSCOD Falling Edge Delay */
476 #define D_CDEC_RED(v) ((v)<<0) /* FSCOD Rising Edge Delay */
477
478 /* Test */
479 #define D_TEST_RAM(v) ((v)<<16) /* RAM Pointer */
480 #define D_TEST_SIZE(v) ((v)<<11) /* */
481 #define D_TEST_ROMONOFF 0x5 /* Toggle ROM opcode monitor on/off */
482 #define D_TEST_PROC 0x6 /* MicroProcessor test */
483 #define D_TEST_SER 0x7 /* Serial-Controller test */
484 #define D_TEST_RAMREAD 0x8 /* Copy from Ram to system memory */
485 #define D_TEST_RAMWRITE 0x9 /* Copy into Ram from system memory */
486 #define D_TEST_RAMBIST 0xa /* RAM Built-In Self Test */
487 #define D_TEST_MCBIST 0xb /* Microcontroller Built-In Self Test */
488 #define D_TEST_DUMP 0xe /* ROM Dump */
489
490 /* CHI Data Mode */
491 #define D_CDM_THI (1<<8) /* Transmit Data on CHIDR Pin */
492 #define D_CDM_RHI (1<<7) /* Receive Data on CHIDX Pin */
493 #define D_CDM_RCE (1<<6) /* Receive on Rising Edge of CHICK */
494 #define D_CDM_XCE (1<<2) /* Transmit Data on Rising Edge of CHICK */
495 #define D_CDM_XEN (1<<1) /* Transmit Highway Enable */
496 #define D_CDM_REN (1<<0) /* Receive Highway Enable */
497
498 /* The Interrupts */
499 #define D_INTR_BRDY 1 /* Buffer Ready for processing */
500 #define D_INTR_MINT 2 /* Marked Interrupt in RD/TD */
501 #define D_INTR_IBEG 3 /* Flag to idle transition detected (HDLC) */
502 #define D_INTR_IEND 4 /* Idle to flag transition detected (HDLC) */
503 #define D_INTR_EOL 5 /* End of List */
504 #define D_INTR_CMDI 6 /* Command has bean read */
505 #define D_INTR_XCMP 8 /* Transmission of frame complete */
506 #define D_INTR_SBRI 9 /* BRI status change info */
507 #define D_INTR_FXDT 10 /* Fixed data change */
508 #define D_INTR_CHIL 11 /* CHI lost frame sync (channel 36 only) */
509 #define D_INTR_COLL 11 /* Unrecoverable D-Channel collision */
510 #define D_INTR_DBYT 12 /* Dropped by frame slip */
511 #define D_INTR_RBYT 13 /* Repeated by frame slip */
512 #define D_INTR_LINT 14 /* Lost Interrupt */
513 #define D_INTR_UNDR 15 /* DMA underrun */
514
515 #define D_INTR_TE 32
516 #define D_INTR_NT 34
517 #define D_INTR_CHI 36
518 #define D_INTR_CMD 38
519
520 #define D_INTR_GETCHAN(v) (((v)>>24) & 0x3f)
521 #define D_INTR_GETCODE(v) (((v)>>20) & 0xf)
522 #define D_INTR_GETCMD(v) (((v)>>16) & 0xf)
523 #define D_INTR_GETVAL(v) ((v) & 0xffff)
524 #define D_INTR_GETRVAL(v) ((v) & 0xfffff)
525
526 #define D_P_0 0 /* TE receive anchor */
527 #define D_P_1 1 /* TE transmit anchor */
528 #define D_P_2 2 /* NT transmit anchor */
529 #define D_P_3 3 /* NT receive anchor */
530 #define D_P_4 4 /* CHI send data */
531 #define D_P_5 5 /* CHI receive data */
532 #define D_P_6 6 /* */
533 #define D_P_7 7 /* */
534 #define D_P_8 8 /* */
535 #define D_P_9 9 /* */
536 #define D_P_10 10 /* */
537 #define D_P_11 11 /* */
538 #define D_P_12 12 /* */
539 #define D_P_13 13 /* */
540 #define D_P_14 14 /* */
541 #define D_P_15 15 /* */
542 #define D_P_16 16 /* CHI anchor pipe */
543 #define D_P_17 17 /* CHI send */
544 #define D_P_18 18 /* CHI receive */
545 #define D_P_19 19 /* CHI receive */
546 #define D_P_20 20 /* CHI receive */
547 #define D_P_21 21 /* */
548 #define D_P_22 22 /* */
549 #define D_P_23 23 /* */
550 #define D_P_24 24 /* */
551 #define D_P_25 25 /* */
552 #define D_P_26 26 /* */
553 #define D_P_27 27 /* */
554 #define D_P_28 28 /* */
555 #define D_P_29 29 /* */
556 #define D_P_30 30 /* */
557 #define D_P_31 31 /* */
558
559 /* Transmit descriptor defines */
560 #define DBRI_TD_F (1<<31) /* End of Frame */
561 #define DBRI_TD_D (1<<30) /* Do not append CRC */
562 #define DBRI_TD_CNT(v) ((v)<<16) /* Number of valid bytes in the buffer */
563 #define DBRI_TD_B (1<<15) /* Final interrupt */
564 #define DBRI_TD_M (1<<14) /* Marker interrupt */
565 #define DBRI_TD_I (1<<13) /* Transmit Idle Characters */
566 #define DBRI_TD_FCNT(v) (v) /* Flag Count */
567 #define DBRI_TD_UNR (1<<3) /* Underrun: transmitter is out of data */
568 #define DBRI_TD_ABT (1<<2) /* Abort: frame aborted */
569 #define DBRI_TD_TBC (1<<0) /* Transmit buffer Complete */
570 #define DBRI_TD_STATUS(v) ((v)&0xff) /* Transmit status */
571 /* Maximum buffer size per TD: almost 8Kb */
572 #define DBRI_TD_MAXCNT ((1 << 13) - 1)
573
574 /* Receive descriptor defines */
575 #define DBRI_RD_F (1<<31) /* End of Frame */
576 #define DBRI_RD_C (1<<30) /* Completed buffer */
577 #define DBRI_RD_B (1<<15) /* Final interrupt */
578 #define DBRI_RD_M (1<<14) /* Marker interrupt */
579 #define DBRI_RD_BCNT(v) (v) /* Buffer size */
580 #define DBRI_RD_CRC (1<<7) /* 0: CRC is correct */
581 #define DBRI_RD_BBC (1<<6) /* 1: Bad Byte received */
582 #define DBRI_RD_ABT (1<<5) /* Abort: frame aborted */
583 #define DBRI_RD_OVRN (1<<3) /* Overrun: data lost */
584 #define DBRI_RD_STATUS(v) ((v)&0xff) /* Receive status */
585 #define DBRI_RD_CNT(v) (((v)>>16)&0x1fff) /* Valid bytes in the buffer */
586
587 /* stream_info[] access */
588 /* Translate the ALSA direction into the array index */
589 #define DBRI_STREAMNO(substream) \
590 (substream->stream == \
591 SNDRV_PCM_STREAM_PLAYBACK? DBRI_PLAY: DBRI_REC)
592
593 /* Return a pointer to dbri_streaminfo */
594 #define DBRI_STREAM(dbri, substream) &dbri->stream_info[DBRI_STREAMNO(substream)]
595
596 static struct snd_dbri *dbri_list = NULL; /* All DBRI devices */
597
598 /*
599 * Short data pipes transmit LSB first. The CS4215 receives MSB first. Grrr.
600 * So we have to reverse the bits. Note: not all bit lengths are supported
601 */
602 static __u32 reverse_bytes(__u32 b, int len)
603 {
604 switch (len) {
605 case 32:
606 b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16);
607 case 16:
608 b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8);
609 case 8:
610 b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4);
611 case 4:
612 b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2);
613 case 2:
614 b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1);
615 case 1:
616 case 0:
617 break;
618 default:
619 printk(KERN_ERR "DBRI reverse_bytes: unsupported length\n");
620 };
621
622 return b;
623 }
624
625 /*
626 ****************************************************************************
627 ************** DBRI initialization and command synchronization *************
628 ****************************************************************************
629
630 Commands are sent to the DBRI by building a list of them in memory,
631 then writing the address of the first list item to DBRI register 8.
632 The list is terminated with a WAIT command, which generates a
633 CPU interrupt to signal completion.
634
635 Since the DBRI can run in parallel with the CPU, several means of
636 synchronization present themselves. The method implemented here is close
637 to the original scheme (Rudolf's), and uses 2 counters (wait_send and
638 wait_ackd) to synchronize the command buffer between the CPU and the DBRI.
639
640 A more sophisticated scheme might involve a circular command buffer
641 or an array of command buffers. A routine could fill one with
642 commands and link it onto a list. When a interrupt signaled
643 completion of the current command buffer, look on the list for
644 the next one.
645
646 Every time a routine wants to write commands to the DBRI, it must
647 first call dbri_cmdlock() and get an initial pointer into dbri->dma->cmd
648 in return. dbri_cmdlock() will block if the previous commands have not
649 been completed yet. After this the commands can be written to the buffer,
650 and dbri_cmdsend() is called with the final pointer value to send them
651 to the DBRI.
652
653 */
654
655 static void dbri_process_interrupt_buffer(struct snd_dbri * dbri);
656
657 enum dbri_lock { NoGetLock, GetLock };
658 #define MAXLOOPS 10
659
660 static volatile s32 *dbri_cmdlock(struct snd_dbri * dbri, enum dbri_lock get)
661 {
662 int maxloops = MAXLOOPS;
663
664 #ifndef SMP
665 if ((get == GetLock) && spin_is_locked(&dbri->lock)) {
666 printk(KERN_ERR "DBRI: cmdlock called while in spinlock.");
667 }
668 #endif
669
670 /* Delay if previous commands are still being processed */
671 while ((--maxloops) > 0 && (dbri->wait_send != dbri->wait_ackd)) {
672 msleep_interruptible(1);
673 /* If dbri_cmdlock() got called from inside the
674 * interrupt handler, this will do the processing.
675 */
676 dbri_process_interrupt_buffer(dbri);
677 }
678 if (maxloops == 0) {
679 printk(KERN_ERR "DBRI: Chip never completed command buffer %d\n",
680 dbri->wait_send);
681 } else {
682 dprintk(D_CMD, "Chip completed command buffer (%d)\n",
683 MAXLOOPS - maxloops - 1);
684 }
685
686 /*if (get == GetLock) spin_lock(&dbri->lock); */
687 return &dbri->dma->cmd[0];
688 }
689
690 static void dbri_cmdsend(struct snd_dbri * dbri, volatile s32 * cmd)
691 {
692 volatile s32 *ptr;
693 u32 reg;
694
695 for (ptr = &dbri->dma->cmd[0]; ptr < cmd; ptr++) {
696 dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr);
697 }
698
699 if ((cmd - &dbri->dma->cmd[0]) >= DBRI_NO_CMDS - 1) {
700 printk(KERN_ERR "DBRI: Command buffer overflow! (bug in driver)\n");
701 /* Ignore the last part. */
702 cmd = &dbri->dma->cmd[DBRI_NO_CMDS - 3];
703 }
704
705 dbri->wait_send++;
706 dbri->wait_send &= 0xffff; /* restrict it to a 16 bit counter. */
707 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
708 *(cmd++) = DBRI_CMD(D_WAIT, 1, dbri->wait_send);
709
710 /* Set command pointer and signal it is valid. */
711 sbus_writel(dbri->dma_dvma, dbri->regs + REG8);
712 reg = sbus_readl(dbri->regs + REG0);
713 reg |= D_P;
714 sbus_writel(reg, dbri->regs + REG0);
715
716 /*spin_unlock(&dbri->lock); */
717 }
718
719 /* Lock must be held when calling this */
720 static void dbri_reset(struct snd_dbri * dbri)
721 {
722 int i;
723
724 dprintk(D_GEN, "reset 0:%x 2:%x 8:%x 9:%x\n",
725 sbus_readl(dbri->regs + REG0),
726 sbus_readl(dbri->regs + REG2),
727 sbus_readl(dbri->regs + REG8), sbus_readl(dbri->regs + REG9));
728
729 sbus_writel(D_R, dbri->regs + REG0); /* Soft Reset */
730 for (i = 0; (sbus_readl(dbri->regs + REG0) & D_R) && i < 64; i++)
731 udelay(10);
732 }
733
734 /* Lock must not be held before calling this */
735 static void dbri_initialize(struct snd_dbri * dbri)
736 {
737 volatile s32 *cmd;
738 u32 dma_addr, tmp;
739 unsigned long flags;
740 int n;
741
742 spin_lock_irqsave(&dbri->lock, flags);
743
744 dbri_reset(dbri);
745
746 cmd = dbri_cmdlock(dbri, NoGetLock);
747 dprintk(D_GEN, "init: cmd: %p, int: %p\n",
748 &dbri->dma->cmd[0], &dbri->dma->intr[0]);
749
750 /*
751 * Initialize the interrupt ringbuffer.
752 */
753 for (n = 0; n < DBRI_NO_INTS - 1; n++) {
754 dma_addr = dbri->dma_dvma;
755 dma_addr += dbri_dma_off(intr, ((n + 1) & DBRI_INT_BLK));
756 dbri->dma->intr[n * DBRI_INT_BLK] = dma_addr;
757 }
758 dma_addr = dbri->dma_dvma + dbri_dma_off(intr, 0);
759 dbri->dma->intr[n * DBRI_INT_BLK] = dma_addr;
760 dbri->dbri_irqp = 1;
761
762 /* Initialize pipes */
763 for (n = 0; n < DBRI_NO_PIPES; n++)
764 dbri->pipes[n].desc = dbri->pipes[n].first_desc = -1;
765
766 /* A brute approach - DBRI falls back to working burst size by itself
767 * On SS20 D_S does not work, so do not try so high. */
768 tmp = sbus_readl(dbri->regs + REG0);
769 tmp |= D_G | D_E;
770 tmp &= ~D_S;
771 sbus_writel(tmp, dbri->regs + REG0);
772
773 /*
774 * Set up the interrupt queue
775 */
776 dma_addr = dbri->dma_dvma + dbri_dma_off(intr, 0);
777 *(cmd++) = DBRI_CMD(D_IIQ, 0, 0);
778 *(cmd++) = dma_addr;
779
780 dbri_cmdsend(dbri, cmd);
781 spin_unlock_irqrestore(&dbri->lock, flags);
782 }
783
784 /*
785 ****************************************************************************
786 ************************** DBRI data pipe management ***********************
787 ****************************************************************************
788
789 While DBRI control functions use the command and interrupt buffers, the
790 main data path takes the form of data pipes, which can be short (command
791 and interrupt driven), or long (attached to DMA buffers). These functions
792 provide a rudimentary means of setting up and managing the DBRI's pipes,
793 but the calling functions have to make sure they respect the pipes' linked
794 list ordering, among other things. The transmit and receive functions
795 here interface closely with the transmit and receive interrupt code.
796
797 */
798 static int pipe_active(struct snd_dbri * dbri, int pipe)
799 {
800 return ((pipe >= 0) && (dbri->pipes[pipe].desc != -1));
801 }
802
803 /* reset_pipe(dbri, pipe)
804 *
805 * Called on an in-use pipe to clear anything being transmitted or received
806 * Lock must be held before calling this.
807 */
808 static void reset_pipe(struct snd_dbri * dbri, int pipe)
809 {
810 int sdp;
811 int desc;
812 volatile int *cmd;
813
814 if (pipe < 0 || pipe > 31) {
815 printk(KERN_ERR "DBRI: reset_pipe called with illegal pipe number\n");
816 return;
817 }
818
819 sdp = dbri->pipes[pipe].sdp;
820 if (sdp == 0) {
821 printk(KERN_ERR "DBRI: reset_pipe called on uninitialized pipe\n");
822 return;
823 }
824
825 cmd = dbri_cmdlock(dbri, NoGetLock);
826 *(cmd++) = DBRI_CMD(D_SDP, 0, sdp | D_SDP_C | D_SDP_P);
827 *(cmd++) = 0;
828 dbri_cmdsend(dbri, cmd);
829
830 desc = dbri->pipes[pipe].first_desc;
831 while (desc != -1) {
832 dbri->descs[desc].inuse = 0;
833 desc = dbri->descs[desc].next;
834 }
835
836 dbri->pipes[pipe].desc = -1;
837 dbri->pipes[pipe].first_desc = -1;
838 }
839
840 /* FIXME: direction as an argument? */
841 static void setup_pipe(struct snd_dbri * dbri, int pipe, int sdp)
842 {
843 if (pipe < 0 || pipe > 31) {
844 printk(KERN_ERR "DBRI: setup_pipe called with illegal pipe number\n");
845 return;
846 }
847
848 if ((sdp & 0xf800) != sdp) {
849 printk(KERN_ERR "DBRI: setup_pipe called with strange SDP value\n");
850 /* sdp &= 0xf800; */
851 }
852
853 /* If this is a fixed receive pipe, arrange for an interrupt
854 * every time its data changes
855 */
856 if (D_SDP_MODE(sdp) == D_SDP_FIXED && !(sdp & D_SDP_TO_SER))
857 sdp |= D_SDP_CHANGE;
858
859 sdp |= D_PIPE(pipe);
860 dbri->pipes[pipe].sdp = sdp;
861 dbri->pipes[pipe].desc = -1;
862 dbri->pipes[pipe].first_desc = -1;
863 if (sdp & D_SDP_TO_SER)
864 dbri->pipes[pipe].direction = PIPEoutput;
865 else
866 dbri->pipes[pipe].direction = PIPEinput;
867
868 reset_pipe(dbri, pipe);
869 }
870
871 /* FIXME: direction not needed */
872 static void link_time_slot(struct snd_dbri * dbri, int pipe,
873 enum in_or_out direction, int basepipe,
874 int length, int cycle)
875 {
876 volatile s32 *cmd;
877 int val;
878 int prevpipe;
879 int nextpipe;
880
881 if (pipe < 0 || pipe > 31 || basepipe < 0 || basepipe > 31) {
882 printk(KERN_ERR
883 "DBRI: link_time_slot called with illegal pipe number\n");
884 return;
885 }
886
887 if (dbri->pipes[pipe].sdp == 0 || dbri->pipes[basepipe].sdp == 0) {
888 printk(KERN_ERR "DBRI: link_time_slot called on uninitialized pipe\n");
889 return;
890 }
891
892 /* Deal with CHI special case:
893 * "If transmission on edges 0 or 1 is desired, then cycle n
894 * (where n = # of bit times per frame...) must be used."
895 * - DBRI data sheet, page 11
896 */
897 if (basepipe == 16 && direction == PIPEoutput && cycle == 0)
898 cycle = dbri->chi_bpf;
899
900 if (basepipe == pipe) {
901 prevpipe = pipe;
902 nextpipe = pipe;
903 } else {
904 /* We're not initializing a new linked list (basepipe != pipe),
905 * so run through the linked list and find where this pipe
906 * should be sloted in, based on its cycle. CHI confuses
907 * things a bit, since it has a single anchor for both its
908 * transmit and receive lists.
909 */
910 if (basepipe == 16) {
911 if (direction == PIPEinput) {
912 prevpipe = dbri->chi_in_pipe;
913 } else {
914 prevpipe = dbri->chi_out_pipe;
915 }
916 } else {
917 prevpipe = basepipe;
918 }
919
920 nextpipe = dbri->pipes[prevpipe].nextpipe;
921
922 while (dbri->pipes[nextpipe].cycle < cycle
923 && dbri->pipes[nextpipe].nextpipe != basepipe) {
924 prevpipe = nextpipe;
925 nextpipe = dbri->pipes[nextpipe].nextpipe;
926 }
927 }
928
929 if (prevpipe == 16) {
930 if (direction == PIPEinput) {
931 dbri->chi_in_pipe = pipe;
932 } else {
933 dbri->chi_out_pipe = pipe;
934 }
935 } else {
936 dbri->pipes[prevpipe].nextpipe = pipe;
937 }
938
939 dbri->pipes[pipe].nextpipe = nextpipe;
940 dbri->pipes[pipe].cycle = cycle;
941 dbri->pipes[pipe].length = length;
942
943 cmd = dbri_cmdlock(dbri, NoGetLock);
944
945 if (direction == PIPEinput) {
946 val = D_DTS_VI | D_DTS_INS | D_DTS_PRVIN(prevpipe) | pipe;
947 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
948 *(cmd++) =
949 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
950 *(cmd++) = 0;
951 } else {
952 val = D_DTS_VO | D_DTS_INS | D_DTS_PRVOUT(prevpipe) | pipe;
953 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
954 *(cmd++) = 0;
955 *(cmd++) =
956 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
957 }
958
959 dbri_cmdsend(dbri, cmd);
960 }
961
962 static void unlink_time_slot(struct snd_dbri * dbri, int pipe,
963 enum in_or_out direction, int prevpipe,
964 int nextpipe)
965 {
966 volatile s32 *cmd;
967 int val;
968
969 if (pipe < 0 || pipe > 31 || prevpipe < 0 || prevpipe > 31) {
970 printk(KERN_ERR
971 "DBRI: unlink_time_slot called with illegal pipe number\n");
972 return;
973 }
974
975 cmd = dbri_cmdlock(dbri, NoGetLock);
976
977 if (direction == PIPEinput) {
978 val = D_DTS_VI | D_DTS_DEL | D_DTS_PRVIN(prevpipe) | pipe;
979 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
980 *(cmd++) = D_TS_NEXT(nextpipe);
981 *(cmd++) = 0;
982 } else {
983 val = D_DTS_VO | D_DTS_DEL | D_DTS_PRVOUT(prevpipe) | pipe;
984 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
985 *(cmd++) = 0;
986 *(cmd++) = D_TS_NEXT(nextpipe);
987 }
988
989 dbri_cmdsend(dbri, cmd);
990 }
991
992 /* xmit_fixed() / recv_fixed()
993 *
994 * Transmit/receive data on a "fixed" pipe - i.e, one whose contents are not
995 * expected to change much, and which we don't need to buffer.
996 * The DBRI only interrupts us when the data changes (receive pipes),
997 * or only changes the data when this function is called (transmit pipes).
998 * Only short pipes (numbers 16-31) can be used in fixed data mode.
999 *
1000 * These function operate on a 32-bit field, no matter how large
1001 * the actual time slot is. The interrupt handler takes care of bit
1002 * ordering and alignment. An 8-bit time slot will always end up
1003 * in the low-order 8 bits, filled either MSB-first or LSB-first,
1004 * depending on the settings passed to setup_pipe()
1005 */
1006 static void xmit_fixed(struct snd_dbri * dbri, int pipe, unsigned int data)
1007 {
1008 volatile s32 *cmd;
1009
1010 if (pipe < 16 || pipe > 31) {
1011 printk(KERN_ERR "DBRI: xmit_fixed: Illegal pipe number\n");
1012 return;
1013 }
1014
1015 if (D_SDP_MODE(dbri->pipes[pipe].sdp) == 0) {
1016 printk(KERN_ERR "DBRI: xmit_fixed: Uninitialized pipe %d\n", pipe);
1017 return;
1018 }
1019
1020 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
1021 printk(KERN_ERR "DBRI: xmit_fixed: Non-fixed pipe %d\n", pipe);
1022 return;
1023 }
1024
1025 if (!(dbri->pipes[pipe].sdp & D_SDP_TO_SER)) {
1026 printk(KERN_ERR "DBRI: xmit_fixed: Called on receive pipe %d\n", pipe);
1027 return;
1028 }
1029
1030 /* DBRI short pipes always transmit LSB first */
1031
1032 if (dbri->pipes[pipe].sdp & D_SDP_MSB)
1033 data = reverse_bytes(data, dbri->pipes[pipe].length);
1034
1035 cmd = dbri_cmdlock(dbri, GetLock);
1036
1037 *(cmd++) = DBRI_CMD(D_SSP, 0, pipe);
1038 *(cmd++) = data;
1039
1040 dbri_cmdsend(dbri, cmd);
1041 }
1042
1043 static void recv_fixed(struct snd_dbri * dbri, int pipe, volatile __u32 * ptr)
1044 {
1045 if (pipe < 16 || pipe > 31) {
1046 printk(KERN_ERR "DBRI: recv_fixed called with illegal pipe number\n");
1047 return;
1048 }
1049
1050 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
1051 printk(KERN_ERR "DBRI: recv_fixed called on non-fixed pipe %d\n", pipe);
1052 return;
1053 }
1054
1055 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
1056 printk(KERN_ERR "DBRI: recv_fixed called on transmit pipe %d\n", pipe);
1057 return;
1058 }
1059
1060 dbri->pipes[pipe].recv_fixed_ptr = ptr;
1061 }
1062
1063 /* setup_descs()
1064 *
1065 * Setup transmit/receive data on a "long" pipe - i.e, one associated
1066 * with a DMA buffer.
1067 *
1068 * Only pipe numbers 0-15 can be used in this mode.
1069 *
1070 * This function takes a stream number pointing to a data buffer,
1071 * and work by building chains of descriptors which identify the
1072 * data buffers. Buffers too large for a single descriptor will
1073 * be spread across multiple descriptors.
1074 */
1075 static int setup_descs(struct snd_dbri * dbri, int streamno, unsigned int period)
1076 {
1077 struct dbri_streaminfo *info = &dbri->stream_info[streamno];
1078 __u32 dvma_buffer;
1079 int desc = 0;
1080 int len;
1081 int first_desc = -1;
1082 int last_desc = -1;
1083
1084 if (info->pipe < 0 || info->pipe > 15) {
1085 printk(KERN_ERR "DBRI: setup_descs: Illegal pipe number\n");
1086 return -2;
1087 }
1088
1089 if (dbri->pipes[info->pipe].sdp == 0) {
1090 printk(KERN_ERR "DBRI: setup_descs: Uninitialized pipe %d\n",
1091 info->pipe);
1092 return -2;
1093 }
1094
1095 dvma_buffer = info->dvma_buffer;
1096 len = info->size;
1097
1098 if (streamno == DBRI_PLAY) {
1099 if (!(dbri->pipes[info->pipe].sdp & D_SDP_TO_SER)) {
1100 printk(KERN_ERR "DBRI: setup_descs: Called on receive pipe %d\n",
1101 info->pipe);
1102 return -2;
1103 }
1104 } else {
1105 if (dbri->pipes[info->pipe].sdp & D_SDP_TO_SER) {
1106 printk(KERN_ERR
1107 "DBRI: setup_descs: Called on transmit pipe %d\n",
1108 info->pipe);
1109 return -2;
1110 }
1111 /* Should be able to queue multiple buffers to receive on a pipe */
1112 if (pipe_active(dbri, info->pipe)) {
1113 printk(KERN_ERR "DBRI: recv_on_pipe: Called on active pipe %d\n",
1114 info->pipe);
1115 return -2;
1116 }
1117
1118 /* Make sure buffer size is multiple of four */
1119 len &= ~3;
1120 }
1121
1122 while (len > 0) {
1123 int mylen;
1124
1125 for (; desc < DBRI_NO_DESCS; desc++) {
1126 if (!dbri->descs[desc].inuse)
1127 break;
1128 }
1129 if (desc == DBRI_NO_DESCS) {
1130 printk(KERN_ERR "DBRI: setup_descs: No descriptors\n");
1131 return -1;
1132 }
1133
1134 if (len > DBRI_TD_MAXCNT) {
1135 mylen = DBRI_TD_MAXCNT; /* 8KB - 1 */
1136 } else {
1137 mylen = len;
1138 }
1139 if (mylen > period) {
1140 mylen = period;
1141 }
1142
1143 dbri->descs[desc].inuse = 1;
1144 dbri->descs[desc].next = -1;
1145 dbri->dma->desc[desc].ba = dvma_buffer;
1146 dbri->dma->desc[desc].nda = 0;
1147
1148 if (streamno == DBRI_PLAY) {
1149 dbri->descs[desc].len = mylen;
1150 dbri->dma->desc[desc].word1 = DBRI_TD_CNT(mylen);
1151 dbri->dma->desc[desc].word4 = 0;
1152 if (first_desc != -1)
1153 dbri->dma->desc[desc].word1 |= DBRI_TD_M;
1154 } else {
1155 dbri->descs[desc].len = 0;
1156 dbri->dma->desc[desc].word1 = 0;
1157 dbri->dma->desc[desc].word4 =
1158 DBRI_RD_B | DBRI_RD_BCNT(mylen);
1159 }
1160
1161 if (first_desc == -1) {
1162 first_desc = desc;
1163 } else {
1164 dbri->descs[last_desc].next = desc;
1165 dbri->dma->desc[last_desc].nda =
1166 dbri->dma_dvma + dbri_dma_off(desc, desc);
1167 }
1168
1169 last_desc = desc;
1170 dvma_buffer += mylen;
1171 len -= mylen;
1172 }
1173
1174 if (first_desc == -1 || last_desc == -1) {
1175 printk(KERN_ERR "DBRI: setup_descs: Not enough descriptors available\n");
1176 return -1;
1177 }
1178
1179 dbri->dma->desc[last_desc].word1 &= ~DBRI_TD_M;
1180 if (streamno == DBRI_PLAY) {
1181 dbri->dma->desc[last_desc].word1 |=
1182 DBRI_TD_I | DBRI_TD_F | DBRI_TD_B;
1183 }
1184 dbri->pipes[info->pipe].first_desc = first_desc;
1185 dbri->pipes[info->pipe].desc = first_desc;
1186
1187 for (desc = first_desc; desc != -1; desc = dbri->descs[desc].next) {
1188 dprintk(D_DESC, "DESC %d: %08x %08x %08x %08x\n",
1189 desc,
1190 dbri->dma->desc[desc].word1,
1191 dbri->dma->desc[desc].ba,
1192 dbri->dma->desc[desc].nda, dbri->dma->desc[desc].word4);
1193 }
1194 return 0;
1195 }
1196
1197 /*
1198 ****************************************************************************
1199 ************************** DBRI - CHI interface ****************************
1200 ****************************************************************************
1201
1202 The CHI is a four-wire (clock, frame sync, data in, data out) time-division
1203 multiplexed serial interface which the DBRI can operate in either master
1204 (give clock/frame sync) or slave (take clock/frame sync) mode.
1205
1206 */
1207
1208 enum master_or_slave { CHImaster, CHIslave };
1209
1210 static void reset_chi(struct snd_dbri * dbri, enum master_or_slave master_or_slave,
1211 int bits_per_frame)
1212 {
1213 volatile s32 *cmd;
1214 int val;
1215 static int chi_initialized = 0; /* FIXME: mutex? */
1216
1217 if (!chi_initialized) {
1218
1219 cmd = dbri_cmdlock(dbri, GetLock);
1220
1221 /* Set CHI Anchor: Pipe 16 */
1222
1223 val = D_DTS_VI | D_DTS_INS | D_DTS_PRVIN(16) | D_PIPE(16);
1224 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
1225 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
1226 *(cmd++) = 0;
1227
1228 val = D_DTS_VO | D_DTS_INS | D_DTS_PRVOUT(16) | D_PIPE(16);
1229 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
1230 *(cmd++) = 0;
1231 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
1232
1233 dbri->pipes[16].sdp = 1;
1234 dbri->pipes[16].nextpipe = 16;
1235 dbri->chi_in_pipe = 16;
1236 dbri->chi_out_pipe = 16;
1237
1238 #if 0
1239 chi_initialized++;
1240 #endif
1241 } else {
1242 int pipe;
1243
1244 for (pipe = dbri->chi_in_pipe;
1245 pipe != 16; pipe = dbri->pipes[pipe].nextpipe) {
1246 unlink_time_slot(dbri, pipe, PIPEinput,
1247 16, dbri->pipes[pipe].nextpipe);
1248 }
1249 for (pipe = dbri->chi_out_pipe;
1250 pipe != 16; pipe = dbri->pipes[pipe].nextpipe) {
1251 unlink_time_slot(dbri, pipe, PIPEoutput,
1252 16, dbri->pipes[pipe].nextpipe);
1253 }
1254
1255 dbri->chi_in_pipe = 16;
1256 dbri->chi_out_pipe = 16;
1257
1258 cmd = dbri_cmdlock(dbri, GetLock);
1259 }
1260
1261 if (master_or_slave == CHIslave) {
1262 /* Setup DBRI for CHI Slave - receive clock, frame sync (FS)
1263 *
1264 * CHICM = 0 (slave mode, 8 kHz frame rate)
1265 * IR = give immediate CHI status interrupt
1266 * EN = give CHI status interrupt upon change
1267 */
1268 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(0));
1269 } else {
1270 /* Setup DBRI for CHI Master - generate clock, FS
1271 *
1272 * BPF = bits per 8 kHz frame
1273 * 12.288 MHz / CHICM_divisor = clock rate
1274 * FD = 1 - drive CHIFS on rising edge of CHICK
1275 */
1276 int clockrate = bits_per_frame * 8;
1277 int divisor = 12288 / clockrate;
1278
1279 if (divisor > 255 || divisor * clockrate != 12288)
1280 printk(KERN_ERR "DBRI: illegal bits_per_frame in setup_chi\n");
1281
1282 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(divisor) | D_CHI_FD
1283 | D_CHI_BPF(bits_per_frame));
1284 }
1285
1286 dbri->chi_bpf = bits_per_frame;
1287
1288 /* CHI Data Mode
1289 *
1290 * RCE = 0 - receive on falling edge of CHICK
1291 * XCE = 1 - transmit on rising edge of CHICK
1292 * XEN = 1 - enable transmitter
1293 * REN = 1 - enable receiver
1294 */
1295
1296 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1297 *(cmd++) = DBRI_CMD(D_CDM, 0, D_CDM_XCE | D_CDM_XEN | D_CDM_REN);
1298
1299 dbri_cmdsend(dbri, cmd);
1300 }
1301
1302 /*
1303 ****************************************************************************
1304 *********************** CS4215 audio codec management **********************
1305 ****************************************************************************
1306
1307 In the standard SPARC audio configuration, the CS4215 codec is attached
1308 to the DBRI via the CHI interface and few of the DBRI's PIO pins.
1309
1310 */
1311 static void cs4215_setup_pipes(struct snd_dbri * dbri)
1312 {
1313 /*
1314 * Data mode:
1315 * Pipe 4: Send timeslots 1-4 (audio data)
1316 * Pipe 20: Send timeslots 5-8 (part of ctrl data)
1317 * Pipe 6: Receive timeslots 1-4 (audio data)
1318 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
1319 * interrupt, and the rest of the data (slot 5 and 8) is
1320 * not relevant for us (only for doublechecking).
1321 *
1322 * Control mode:
1323 * Pipe 17: Send timeslots 1-4 (slots 5-8 are readonly)
1324 * Pipe 18: Receive timeslot 1 (clb).
1325 * Pipe 19: Receive timeslot 7 (version).
1326 */
1327
1328 setup_pipe(dbri, 4, D_SDP_MEM | D_SDP_TO_SER | D_SDP_MSB);
1329 setup_pipe(dbri, 20, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1330 setup_pipe(dbri, 6, D_SDP_MEM | D_SDP_FROM_SER | D_SDP_MSB);
1331 setup_pipe(dbri, 21, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1332
1333 setup_pipe(dbri, 17, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1334 setup_pipe(dbri, 18, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1335 setup_pipe(dbri, 19, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1336 }
1337
1338 static int cs4215_init_data(struct cs4215 *mm)
1339 {
1340 /*
1341 * No action, memory resetting only.
1342 *
1343 * Data Time Slot 5-8
1344 * Speaker,Line and Headphone enable. Gain set to the half.
1345 * Input is mike.
1346 */
1347 mm->data[0] = CS4215_LO(0x20) | CS4215_HE | CS4215_LE;
1348 mm->data[1] = CS4215_RO(0x20) | CS4215_SE;
1349 mm->data[2] = CS4215_LG(0x8) | CS4215_IS | CS4215_PIO0 | CS4215_PIO1;
1350 mm->data[3] = CS4215_RG(0x8) | CS4215_MA(0xf);
1351
1352 /*
1353 * Control Time Slot 1-4
1354 * 0: Default I/O voltage scale
1355 * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled
1356 * 2: Serial enable, CHI master, 128 bits per frame, clock 1
1357 * 3: Tests disabled
1358 */
1359 mm->ctrl[0] = CS4215_RSRVD_1 | CS4215_MLB;
1360 mm->ctrl[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval;
1361 mm->ctrl[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal;
1362 mm->ctrl[3] = 0;
1363
1364 mm->status = 0;
1365 mm->version = 0xff;
1366 mm->precision = 8; /* For ULAW */
1367 mm->channels = 2;
1368
1369 return 0;
1370 }
1371
1372 static void cs4215_setdata(struct snd_dbri * dbri, int muted)
1373 {
1374 if (muted) {
1375 dbri->mm.data[0] |= 63;
1376 dbri->mm.data[1] |= 63;
1377 dbri->mm.data[2] &= ~15;
1378 dbri->mm.data[3] &= ~15;
1379 } else {
1380 /* Start by setting the playback attenuation. */
1381 struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY];
1382 int left_gain = info->left_gain % 64;
1383 int right_gain = info->right_gain % 64;
1384
1385 if (info->balance < DBRI_MID_BALANCE) {
1386 right_gain *= info->balance;
1387 right_gain /= DBRI_MID_BALANCE;
1388 } else {
1389 left_gain *= DBRI_RIGHT_BALANCE - info->balance;
1390 left_gain /= DBRI_MID_BALANCE;
1391 }
1392
1393 dbri->mm.data[0] &= ~0x3f; /* Reset the volume bits */
1394 dbri->mm.data[1] &= ~0x3f;
1395 dbri->mm.data[0] |= (DBRI_MAX_VOLUME - left_gain);
1396 dbri->mm.data[1] |= (DBRI_MAX_VOLUME - right_gain);
1397
1398 /* Now set the recording gain. */
1399 info = &dbri->stream_info[DBRI_REC];
1400 left_gain = info->left_gain % 16;
1401 right_gain = info->right_gain % 16;
1402 dbri->mm.data[2] |= CS4215_LG(left_gain);
1403 dbri->mm.data[3] |= CS4215_RG(right_gain);
1404 }
1405
1406 xmit_fixed(dbri, 20, *(int *)dbri->mm.data);
1407 }
1408
1409 /*
1410 * Set the CS4215 to data mode.
1411 */
1412 static void cs4215_open(struct snd_dbri * dbri)
1413 {
1414 int data_width;
1415 u32 tmp;
1416
1417 dprintk(D_MM, "cs4215_open: %d channels, %d bits\n",
1418 dbri->mm.channels, dbri->mm.precision);
1419
1420 /* Temporarily mute outputs, and wait 1/8000 sec (125 us)
1421 * to make sure this takes. This avoids clicking noises.
1422 */
1423
1424 cs4215_setdata(dbri, 1);
1425 udelay(125);
1426
1427 /*
1428 * Data mode:
1429 * Pipe 4: Send timeslots 1-4 (audio data)
1430 * Pipe 20: Send timeslots 5-8 (part of ctrl data)
1431 * Pipe 6: Receive timeslots 1-4 (audio data)
1432 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
1433 * interrupt, and the rest of the data (slot 5 and 8) is
1434 * not relevant for us (only for doublechecking).
1435 *
1436 * Just like in control mode, the time slots are all offset by eight
1437 * bits. The CS4215, it seems, observes TSIN (the delayed signal)
1438 * even if it's the CHI master. Don't ask me...
1439 */
1440 tmp = sbus_readl(dbri->regs + REG0);
1441 tmp &= ~(D_C); /* Disable CHI */
1442 sbus_writel(tmp, dbri->regs + REG0);
1443
1444 /* Switch CS4215 to data mode - set PIO3 to 1 */
1445 sbus_writel(D_ENPIO | D_PIO1 | D_PIO3 |
1446 (dbri->mm.onboard ? D_PIO0 : D_PIO2), dbri->regs + REG2);
1447
1448 reset_chi(dbri, CHIslave, 128);
1449
1450 /* Note: this next doesn't work for 8-bit stereo, because the two
1451 * channels would be on timeslots 1 and 3, with 2 and 4 idle.
1452 * (See CS4215 datasheet Fig 15)
1453 *
1454 * DBRI non-contiguous mode would be required to make this work.
1455 */
1456 data_width = dbri->mm.channels * dbri->mm.precision;
1457
1458 link_time_slot(dbri, 20, PIPEoutput, 16, 32, dbri->mm.offset + 32);
1459 link_time_slot(dbri, 4, PIPEoutput, 16, data_width, dbri->mm.offset);
1460 link_time_slot(dbri, 6, PIPEinput, 16, data_width, dbri->mm.offset);
1461 link_time_slot(dbri, 21, PIPEinput, 16, 16, dbri->mm.offset + 40);
1462
1463 /* FIXME: enable CHI after _setdata? */
1464 tmp = sbus_readl(dbri->regs + REG0);
1465 tmp |= D_C; /* Enable CHI */
1466 sbus_writel(tmp, dbri->regs + REG0);
1467
1468 cs4215_setdata(dbri, 0);
1469 }
1470
1471 /*
1472 * Send the control information (i.e. audio format)
1473 */
1474 static int cs4215_setctrl(struct snd_dbri * dbri)
1475 {
1476 int i, val;
1477 u32 tmp;
1478
1479 /* FIXME - let the CPU do something useful during these delays */
1480
1481 /* Temporarily mute outputs, and wait 1/8000 sec (125 us)
1482 * to make sure this takes. This avoids clicking noises.
1483 */
1484 cs4215_setdata(dbri, 1);
1485 udelay(125);
1486
1487 /*
1488 * Enable Control mode: Set DBRI's PIO3 (4215's D/~C) to 0, then wait
1489 * 12 cycles <= 12/(5512.5*64) sec = 34.01 usec
1490 */
1491 val = D_ENPIO | D_PIO1 | (dbri->mm.onboard ? D_PIO0 : D_PIO2);
1492 sbus_writel(val, dbri->regs + REG2);
1493 dprintk(D_MM, "cs4215_setctrl: reg2=0x%x\n", val);
1494 udelay(34);
1495
1496 /* In Control mode, the CS4215 is a slave device, so the DBRI must
1497 * operate as CHI master, supplying clocking and frame synchronization.
1498 *
1499 * In Data mode, however, the CS4215 must be CHI master to insure
1500 * that its data stream is synchronous with its codec.
1501 *
1502 * The upshot of all this? We start by putting the DBRI into master
1503 * mode, program the CS4215 in Control mode, then switch the CS4215
1504 * into Data mode and put the DBRI into slave mode. Various timing
1505 * requirements must be observed along the way.
1506 *
1507 * Oh, and one more thing, on a SPARCStation 20 (and maybe
1508 * others?), the addressing of the CS4215's time slots is
1509 * offset by eight bits, so we add eight to all the "cycle"
1510 * values in the Define Time Slot (DTS) commands. This is
1511 * done in hardware by a TI 248 that delays the DBRI->4215
1512 * frame sync signal by eight clock cycles. Anybody know why?
1513 */
1514 tmp = sbus_readl(dbri->regs + REG0);
1515 tmp &= ~D_C; /* Disable CHI */
1516 sbus_writel(tmp, dbri->regs + REG0);
1517
1518 reset_chi(dbri, CHImaster, 128);
1519
1520 /*
1521 * Control mode:
1522 * Pipe 17: Send timeslots 1-4 (slots 5-8 are readonly)
1523 * Pipe 18: Receive timeslot 1 (clb).
1524 * Pipe 19: Receive timeslot 7 (version).
1525 */
1526
1527 link_time_slot(dbri, 17, PIPEoutput, 16, 32, dbri->mm.offset);
1528 link_time_slot(dbri, 18, PIPEinput, 16, 8, dbri->mm.offset);
1529 link_time_slot(dbri, 19, PIPEinput, 16, 8, dbri->mm.offset + 48);
1530
1531 /* Wait for the chip to echo back CLB (Control Latch Bit) as zero */
1532 dbri->mm.ctrl[0] &= ~CS4215_CLB;
1533 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1534
1535 tmp = sbus_readl(dbri->regs + REG0);
1536 tmp |= D_C; /* Enable CHI */
1537 sbus_writel(tmp, dbri->regs + REG0);
1538
1539 for (i = 10; ((dbri->mm.status & 0xe4) != 0x20); --i) {
1540 msleep_interruptible(1);
1541 }
1542 if (i == 0) {
1543 dprintk(D_MM, "CS4215 didn't respond to CLB (0x%02x)\n",
1544 dbri->mm.status);
1545 return -1;
1546 }
1547
1548 /* Disable changes to our copy of the version number, as we are about
1549 * to leave control mode.
1550 */
1551 recv_fixed(dbri, 19, NULL);
1552
1553 /* Terminate CS4215 control mode - data sheet says
1554 * "Set CLB=1 and send two more frames of valid control info"
1555 */
1556 dbri->mm.ctrl[0] |= CS4215_CLB;
1557 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1558
1559 /* Two frames of control info @ 8kHz frame rate = 250 us delay */
1560 udelay(250);
1561
1562 cs4215_setdata(dbri, 0);
1563
1564 return 0;
1565 }
1566
1567 /*
1568 * Setup the codec with the sampling rate, audio format and number of
1569 * channels.
1570 * As part of the process we resend the settings for the data
1571 * timeslots as well.
1572 */
1573 static int cs4215_prepare(struct snd_dbri * dbri, unsigned int rate,
1574 snd_pcm_format_t format, unsigned int channels)
1575 {
1576 int freq_idx;
1577 int ret = 0;
1578
1579 /* Lookup index for this rate */
1580 for (freq_idx = 0; CS4215_FREQ[freq_idx].freq != 0; freq_idx++) {
1581 if (CS4215_FREQ[freq_idx].freq == rate)
1582 break;
1583 }
1584 if (CS4215_FREQ[freq_idx].freq != rate) {
1585 printk(KERN_WARNING "DBRI: Unsupported rate %d Hz\n", rate);
1586 return -1;
1587 }
1588
1589 switch (format) {
1590 case SNDRV_PCM_FORMAT_MU_LAW:
1591 dbri->mm.ctrl[1] = CS4215_DFR_ULAW;
1592 dbri->mm.precision = 8;
1593 break;
1594 case SNDRV_PCM_FORMAT_A_LAW:
1595 dbri->mm.ctrl[1] = CS4215_DFR_ALAW;
1596 dbri->mm.precision = 8;
1597 break;
1598 case SNDRV_PCM_FORMAT_U8:
1599 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR8;
1600 dbri->mm.precision = 8;
1601 break;
1602 case SNDRV_PCM_FORMAT_S16_BE:
1603 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR16;
1604 dbri->mm.precision = 16;
1605 break;
1606 default:
1607 printk(KERN_WARNING "DBRI: Unsupported format %d\n", format);
1608 return -1;
1609 }
1610
1611 /* Add rate parameters */
1612 dbri->mm.ctrl[1] |= CS4215_FREQ[freq_idx].csval;
1613 dbri->mm.ctrl[2] = CS4215_XCLK |
1614 CS4215_BSEL_128 | CS4215_FREQ[freq_idx].xtal;
1615
1616 dbri->mm.channels = channels;
1617 /* Stereo bit: 8 bit stereo not working yet. */
1618 if ((channels > 1) && (dbri->mm.precision == 16))
1619 dbri->mm.ctrl[1] |= CS4215_DFR_STEREO;
1620
1621 ret = cs4215_setctrl(dbri);
1622 if (ret == 0)
1623 cs4215_open(dbri); /* set codec to data mode */
1624
1625 return ret;
1626 }
1627
1628 /*
1629 *
1630 */
1631 static int cs4215_init(struct snd_dbri * dbri)
1632 {
1633 u32 reg2 = sbus_readl(dbri->regs + REG2);
1634 dprintk(D_MM, "cs4215_init: reg2=0x%x\n", reg2);
1635
1636 /* Look for the cs4215 chips */
1637 if (reg2 & D_PIO2) {
1638 dprintk(D_MM, "Onboard CS4215 detected\n");
1639 dbri->mm.onboard = 1;
1640 }
1641 if (reg2 & D_PIO0) {
1642 dprintk(D_MM, "Speakerbox detected\n");
1643 dbri->mm.onboard = 0;
1644
1645 if (reg2 & D_PIO2) {
1646 printk(KERN_INFO "DBRI: Using speakerbox / "
1647 "ignoring onboard mmcodec.\n");
1648 sbus_writel(D_ENPIO2, dbri->regs + REG2);
1649 }
1650 }
1651
1652 if (!(reg2 & (D_PIO0 | D_PIO2))) {
1653 printk(KERN_ERR "DBRI: no mmcodec found.\n");
1654 return -EIO;
1655 }
1656
1657 cs4215_setup_pipes(dbri);
1658
1659 cs4215_init_data(&dbri->mm);
1660
1661 /* Enable capture of the status & version timeslots. */
1662 recv_fixed(dbri, 18, &dbri->mm.status);
1663 recv_fixed(dbri, 19, &dbri->mm.version);
1664
1665 dbri->mm.offset = dbri->mm.onboard ? 0 : 8;
1666 if (cs4215_setctrl(dbri) == -1 || dbri->mm.version == 0xff) {
1667 dprintk(D_MM, "CS4215 failed probe at offset %d\n",
1668 dbri->mm.offset);
1669 return -EIO;
1670 }
1671 dprintk(D_MM, "Found CS4215 at offset %d\n", dbri->mm.offset);
1672
1673 return 0;
1674 }
1675
1676 /*
1677 ****************************************************************************
1678 *************************** DBRI interrupt handler *************************
1679 ****************************************************************************
1680
1681 The DBRI communicates with the CPU mainly via a circular interrupt
1682 buffer. When an interrupt is signaled, the CPU walks through the
1683 buffer and calls dbri_process_one_interrupt() for each interrupt word.
1684 Complicated interrupts are handled by dedicated functions (which
1685 appear first in this file). Any pending interrupts can be serviced by
1686 calling dbri_process_interrupt_buffer(), which works even if the CPU's
1687 interrupts are disabled. This function is used by dbri_cmdlock()
1688 to make sure we're synced up with the chip before each command sequence,
1689 even if we're running cli'ed.
1690
1691 */
1692
1693 /* xmit_descs()
1694 *
1695 * Transmit the current TD's for recording/playing, if needed.
1696 * For playback, ALSA has filled the DMA memory with new data (we hope).
1697 */
1698 static void xmit_descs(unsigned long data)
1699 {
1700 struct snd_dbri *dbri = (struct snd_dbri *) data;
1701 struct dbri_streaminfo *info;
1702 volatile s32 *cmd;
1703 unsigned long flags;
1704 int first_td;
1705
1706 if (dbri == NULL)
1707 return; /* Disabled */
1708
1709 /* First check the recording stream for buffer overflow */
1710 info = &dbri->stream_info[DBRI_REC];
1711 spin_lock_irqsave(&dbri->lock, flags);
1712
1713 if ((info->left >= info->size) && (info->pipe >= 0)) {
1714 first_td = dbri->pipes[info->pipe].first_desc;
1715
1716 dprintk(D_DESC, "xmit_descs rec @ TD %d\n", first_td);
1717
1718 /* Stream could be closed by the time we run. */
1719 if (first_td < 0) {
1720 goto play;
1721 }
1722
1723 cmd = dbri_cmdlock(dbri, NoGetLock);
1724 *(cmd++) = DBRI_CMD(D_SDP, 0,
1725 dbri->pipes[info->pipe].sdp
1726 | D_SDP_P | D_SDP_EVERY | D_SDP_C);
1727 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, first_td);
1728 dbri_cmdsend(dbri, cmd);
1729
1730 /* Reset our admin of the pipe & bytes read. */
1731 dbri->pipes[info->pipe].desc = first_td;
1732 info->left = 0;
1733 }
1734
1735 play:
1736 spin_unlock_irqrestore(&dbri->lock, flags);
1737
1738 /* Now check the playback stream for buffer underflow */
1739 info = &dbri->stream_info[DBRI_PLAY];
1740 spin_lock_irqsave(&dbri->lock, flags);
1741
1742 if ((info->left <= 0) && (info->pipe >= 0)) {
1743 first_td = dbri->pipes[info->pipe].first_desc;
1744
1745 dprintk(D_DESC, "xmit_descs play @ TD %d\n", first_td);
1746
1747 /* Stream could be closed by the time we run. */
1748 if (first_td < 0) {
1749 spin_unlock_irqrestore(&dbri->lock, flags);
1750 return;
1751 }
1752
1753 cmd = dbri_cmdlock(dbri, NoGetLock);
1754 *(cmd++) = DBRI_CMD(D_SDP, 0,
1755 dbri->pipes[info->pipe].sdp
1756 | D_SDP_P | D_SDP_EVERY | D_SDP_C);
1757 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, first_td);
1758 dbri_cmdsend(dbri, cmd);
1759
1760 /* Reset our admin of the pipe & bytes written. */
1761 dbri->pipes[info->pipe].desc = first_td;
1762 info->left = info->size;
1763 }
1764 spin_unlock_irqrestore(&dbri->lock, flags);
1765 }
1766
1767 static DECLARE_TASKLET(xmit_descs_task, xmit_descs, 0);
1768
1769 /* transmission_complete_intr()
1770 *
1771 * Called by main interrupt handler when DBRI signals transmission complete
1772 * on a pipe (interrupt triggered by the B bit in a transmit descriptor).
1773 *
1774 * Walks through the pipe's list of transmit buffer descriptors and marks
1775 * them as available. Stops when the first descriptor is found without
1776 * TBC (Transmit Buffer Complete) set, or we've run through them all.
1777 *
1778 * The DMA buffers are not released, but re-used. Since the transmit buffer
1779 * descriptors are not clobbered, they can be re-submitted as is. This is
1780 * done by the xmit_descs() tasklet above since that could take longer.
1781 */
1782
1783 static void transmission_complete_intr(struct snd_dbri * dbri, int pipe)
1784 {
1785 struct dbri_streaminfo *info;
1786 int td;
1787 int status;
1788
1789 info = &dbri->stream_info[DBRI_PLAY];
1790
1791 td = dbri->pipes[pipe].desc;
1792 while (td >= 0) {
1793 if (td >= DBRI_NO_DESCS) {
1794 printk(KERN_ERR "DBRI: invalid td on pipe %d\n", pipe);
1795 return;
1796 }
1797
1798 status = DBRI_TD_STATUS(dbri->dma->desc[td].word4);
1799 if (!(status & DBRI_TD_TBC)) {
1800 break;
1801 }
1802
1803 dprintk(D_INT, "TD %d, status 0x%02x\n", td, status);
1804
1805 dbri->dma->desc[td].word4 = 0; /* Reset it for next time. */
1806 info->offset += dbri->descs[td].len;
1807 info->left -= dbri->descs[td].len;
1808
1809 /* On the last TD, transmit them all again. */
1810 if (dbri->descs[td].next == -1) {
1811 if (info->left > 0) {
1812 printk(KERN_WARNING
1813 "%d bytes left after last transfer.\n",
1814 info->left);
1815 info->left = 0;
1816 }
1817 tasklet_schedule(&xmit_descs_task);
1818 }
1819
1820 td = dbri->descs[td].next;
1821 dbri->pipes[pipe].desc = td;
1822 }
1823
1824 /* Notify ALSA */
1825 if (spin_is_locked(&dbri->lock)) {
1826 spin_unlock(&dbri->lock);
1827 snd_pcm_period_elapsed(info->substream);
1828 spin_lock(&dbri->lock);
1829 } else
1830 snd_pcm_period_elapsed(info->substream);
1831 }
1832
1833 static void reception_complete_intr(struct snd_dbri * dbri, int pipe)
1834 {
1835 struct dbri_streaminfo *info;
1836 int rd = dbri->pipes[pipe].desc;
1837 s32 status;
1838
1839 if (rd < 0 || rd >= DBRI_NO_DESCS) {
1840 printk(KERN_ERR "DBRI: invalid rd on pipe %d\n", pipe);
1841 return;
1842 }
1843
1844 dbri->descs[rd].inuse = 0;
1845 dbri->pipes[pipe].desc = dbri->descs[rd].next;
1846 status = dbri->dma->desc[rd].word1;
1847 dbri->dma->desc[rd].word1 = 0; /* Reset it for next time. */
1848
1849 info = &dbri->stream_info[DBRI_REC];
1850 info->offset += DBRI_RD_CNT(status);
1851 info->left += DBRI_RD_CNT(status);
1852
1853 /* FIXME: Check status */
1854
1855 dprintk(D_INT, "Recv RD %d, status 0x%02x, len %d\n",
1856 rd, DBRI_RD_STATUS(status), DBRI_RD_CNT(status));
1857
1858 /* On the last TD, transmit them all again. */
1859 if (dbri->descs[rd].next == -1) {
1860 if (info->left > info->size) {
1861 printk(KERN_WARNING
1862 "%d bytes recorded in %d size buffer.\n",
1863 info->left, info->size);
1864 }
1865 tasklet_schedule(&xmit_descs_task);
1866 }
1867
1868 /* Notify ALSA */
1869 if (spin_is_locked(&dbri->lock)) {
1870 spin_unlock(&dbri->lock);
1871 snd_pcm_period_elapsed(info->substream);
1872 spin_lock(&dbri->lock);
1873 } else
1874 snd_pcm_period_elapsed(info->substream);
1875 }
1876
1877 static void dbri_process_one_interrupt(struct snd_dbri * dbri, int x)
1878 {
1879 int val = D_INTR_GETVAL(x);
1880 int channel = D_INTR_GETCHAN(x);
1881 int command = D_INTR_GETCMD(x);
1882 int code = D_INTR_GETCODE(x);
1883 #ifdef DBRI_DEBUG
1884 int rval = D_INTR_GETRVAL(x);
1885 #endif
1886
1887 if (channel == D_INTR_CMD) {
1888 dprintk(D_CMD, "INTR: Command: %-5s Value:%d\n",
1889 cmds[command], val);
1890 } else {
1891 dprintk(D_INT, "INTR: Chan:%d Code:%d Val:%#x\n",
1892 channel, code, rval);
1893 }
1894
1895 if (channel == D_INTR_CMD && command == D_WAIT) {
1896 dbri->wait_ackd = val;
1897 if (dbri->wait_send != val) {
1898 printk(KERN_ERR "Processing wait command %d when %d was send.\n",
1899 val, dbri->wait_send);
1900 }
1901 return;
1902 }
1903
1904 switch (code) {
1905 case D_INTR_BRDY:
1906 reception_complete_intr(dbri, channel);
1907 break;
1908 case D_INTR_XCMP:
1909 case D_INTR_MINT:
1910 transmission_complete_intr(dbri, channel);
1911 break;
1912 case D_INTR_UNDR:
1913 /* UNDR - Transmission underrun
1914 * resend SDP command with clear pipe bit (C) set
1915 */
1916 {
1917 volatile s32 *cmd;
1918
1919 int pipe = channel;
1920 int td = dbri->pipes[pipe].desc;
1921
1922 dbri->dma->desc[td].word4 = 0;
1923 cmd = dbri_cmdlock(dbri, NoGetLock);
1924 *(cmd++) = DBRI_CMD(D_SDP, 0,
1925 dbri->pipes[pipe].sdp
1926 | D_SDP_P | D_SDP_C | D_SDP_2SAME);
1927 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, td);
1928 dbri_cmdsend(dbri, cmd);
1929 }
1930 break;
1931 case D_INTR_FXDT:
1932 /* FXDT - Fixed data change */
1933 if (dbri->pipes[channel].sdp & D_SDP_MSB)
1934 val = reverse_bytes(val, dbri->pipes[channel].length);
1935
1936 if (dbri->pipes[channel].recv_fixed_ptr)
1937 *(dbri->pipes[channel].recv_fixed_ptr) = val;
1938 break;
1939 default:
1940 if (channel != D_INTR_CMD)
1941 printk(KERN_WARNING
1942 "DBRI: Ignored Interrupt: %d (0x%x)\n", code, x);
1943 }
1944 }
1945
1946 /* dbri_process_interrupt_buffer advances through the DBRI's interrupt
1947 * buffer until it finds a zero word (indicating nothing more to do
1948 * right now). Non-zero words require processing and are handed off
1949 * to dbri_process_one_interrupt AFTER advancing the pointer. This
1950 * order is important since we might recurse back into this function
1951 * and need to make sure the pointer has been advanced first.
1952 */
1953 static void dbri_process_interrupt_buffer(struct snd_dbri * dbri)
1954 {
1955 s32 x;
1956
1957 while ((x = dbri->dma->intr[dbri->dbri_irqp]) != 0) {
1958 dbri->dma->intr[dbri->dbri_irqp] = 0;
1959 dbri->dbri_irqp++;
1960 if (dbri->dbri_irqp == (DBRI_NO_INTS * DBRI_INT_BLK))
1961 dbri->dbri_irqp = 1;
1962 else if ((dbri->dbri_irqp & (DBRI_INT_BLK - 1)) == 0)
1963 dbri->dbri_irqp++;
1964
1965 dbri_process_one_interrupt(dbri, x);
1966 }
1967 }
1968
1969 static irqreturn_t snd_dbri_interrupt(int irq, void *dev_id,
1970 struct pt_regs *regs)
1971 {
1972 struct snd_dbri *dbri = dev_id;
1973 static int errcnt = 0;
1974 int x;
1975
1976 if (dbri == NULL)
1977 return IRQ_NONE;
1978 spin_lock(&dbri->lock);
1979
1980 /*
1981 * Read it, so the interrupt goes away.
1982 */
1983 x = sbus_readl(dbri->regs + REG1);
1984
1985 if (x & (D_MRR | D_MLE | D_LBG | D_MBE)) {
1986 u32 tmp;
1987
1988 if (x & D_MRR)
1989 printk(KERN_ERR
1990 "DBRI: Multiple Error Ack on SBus reg1=0x%x\n",
1991 x);
1992 if (x & D_MLE)
1993 printk(KERN_ERR
1994 "DBRI: Multiple Late Error on SBus reg1=0x%x\n",
1995 x);
1996 if (x & D_LBG)
1997 printk(KERN_ERR
1998 "DBRI: Lost Bus Grant on SBus reg1=0x%x\n", x);
1999 if (x & D_MBE)
2000 printk(KERN_ERR
2001 "DBRI: Burst Error on SBus reg1=0x%x\n", x);
2002
2003 /* Some of these SBus errors cause the chip's SBus circuitry
2004 * to be disabled, so just re-enable and try to keep going.
2005 *
2006 * The only one I've seen is MRR, which will be triggered
2007 * if you let a transmit pipe underrun, then try to CDP it.
2008 *
2009 * If these things persist, we reset the chip.
2010 */
2011 if ((++errcnt) % 10 == 0) {
2012 dprintk(D_INT, "Interrupt errors exceeded.\n");
2013 dbri_reset(dbri);
2014 } else {
2015 tmp = sbus_readl(dbri->regs + REG0);
2016 tmp &= ~(D_D);
2017 sbus_writel(tmp, dbri->regs + REG0);
2018 }
2019 }
2020
2021 dbri_process_interrupt_buffer(dbri);
2022
2023 /* FIXME: Write 0 into regs to ACK interrupt */
2024
2025 spin_unlock(&dbri->lock);
2026
2027 return IRQ_HANDLED;
2028 }
2029
2030 /****************************************************************************
2031 PCM Interface
2032 ****************************************************************************/
2033 static struct snd_pcm_hardware snd_dbri_pcm_hw = {
2034 .info = (SNDRV_PCM_INFO_MMAP |
2035 SNDRV_PCM_INFO_INTERLEAVED |
2036 SNDRV_PCM_INFO_BLOCK_TRANSFER |
2037 SNDRV_PCM_INFO_MMAP_VALID),
2038 .formats = SNDRV_PCM_FMTBIT_MU_LAW |
2039 SNDRV_PCM_FMTBIT_A_LAW |
2040 SNDRV_PCM_FMTBIT_U8 |
2041 SNDRV_PCM_FMTBIT_S16_BE,
2042 .rates = SNDRV_PCM_RATE_8000_48000,
2043 .rate_min = 8000,
2044 .rate_max = 48000,
2045 .channels_min = 1,
2046 .channels_max = 2,
2047 .buffer_bytes_max = (64 * 1024),
2048 .period_bytes_min = 1,
2049 .period_bytes_max = DBRI_TD_MAXCNT,
2050 .periods_min = 1,
2051 .periods_max = 1024,
2052 };
2053
2054 static int snd_dbri_open(struct snd_pcm_substream *substream)
2055 {
2056 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2057 struct snd_pcm_runtime *runtime = substream->runtime;
2058 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2059 unsigned long flags;
2060
2061 dprintk(D_USR, "open audio output.\n");
2062 runtime->hw = snd_dbri_pcm_hw;
2063
2064 spin_lock_irqsave(&dbri->lock, flags);
2065 info->substream = substream;
2066 info->left = 0;
2067 info->offset = 0;
2068 info->dvma_buffer = 0;
2069 info->pipe = -1;
2070 spin_unlock_irqrestore(&dbri->lock, flags);
2071
2072 cs4215_open(dbri);
2073
2074 return 0;
2075 }
2076
2077 static int snd_dbri_close(struct snd_pcm_substream *substream)
2078 {
2079 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2080 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2081
2082 dprintk(D_USR, "close audio output.\n");
2083 info->substream = NULL;
2084 info->left = 0;
2085 info->offset = 0;
2086
2087 return 0;
2088 }
2089
2090 static int snd_dbri_hw_params(struct snd_pcm_substream *substream,
2091 struct snd_pcm_hw_params *hw_params)
2092 {
2093 struct snd_pcm_runtime *runtime = substream->runtime;
2094 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2095 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2096 int direction;
2097 int ret;
2098
2099 /* set sampling rate, audio format and number of channels */
2100 ret = cs4215_prepare(dbri, params_rate(hw_params),
2101 params_format(hw_params),
2102 params_channels(hw_params));
2103 if (ret != 0)
2104 return ret;
2105
2106 if ((ret = snd_pcm_lib_malloc_pages(substream,
2107 params_buffer_bytes(hw_params))) < 0) {
2108 printk(KERN_ERR "malloc_pages failed with %d\n", ret);
2109 return ret;
2110 }
2111
2112 /* hw_params can get called multiple times. Only map the DMA once.
2113 */
2114 if (info->dvma_buffer == 0) {
2115 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2116 direction = SBUS_DMA_TODEVICE;
2117 else
2118 direction = SBUS_DMA_FROMDEVICE;
2119
2120 info->dvma_buffer = sbus_map_single(dbri->sdev,
2121 runtime->dma_area,
2122 params_buffer_bytes(hw_params),
2123 direction);
2124 }
2125
2126 direction = params_buffer_bytes(hw_params);
2127 dprintk(D_USR, "hw_params: %d bytes, dvma=%x\n",
2128 direction, info->dvma_buffer);
2129 return 0;
2130 }
2131
2132 static int snd_dbri_hw_free(struct snd_pcm_substream *substream)
2133 {
2134 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2135 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2136 int direction;
2137 dprintk(D_USR, "hw_free.\n");
2138
2139 /* hw_free can get called multiple times. Only unmap the DMA once.
2140 */
2141 if (info->dvma_buffer) {
2142 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2143 direction = SBUS_DMA_TODEVICE;
2144 else
2145 direction = SBUS_DMA_FROMDEVICE;
2146
2147 sbus_unmap_single(dbri->sdev, info->dvma_buffer,
2148 substream->runtime->buffer_size, direction);
2149 info->dvma_buffer = 0;
2150 }
2151 info->pipe = -1;
2152
2153 return snd_pcm_lib_free_pages(substream);
2154 }
2155
2156 static int snd_dbri_prepare(struct snd_pcm_substream *substream)
2157 {
2158 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2159 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2160 struct snd_pcm_runtime *runtime = substream->runtime;
2161 int ret;
2162
2163 info->size = snd_pcm_lib_buffer_bytes(substream);
2164 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2165 info->pipe = 4; /* Send pipe */
2166 else {
2167 info->pipe = 6; /* Receive pipe */
2168 info->left = info->size; /* To trigger submittal */
2169 }
2170
2171 spin_lock_irq(&dbri->lock);
2172
2173 /* Setup the all the transmit/receive desciptors to cover the
2174 * whole DMA buffer.
2175 */
2176 ret = setup_descs(dbri, DBRI_STREAMNO(substream),
2177 snd_pcm_lib_period_bytes(substream));
2178
2179 runtime->stop_threshold = DBRI_TD_MAXCNT / runtime->channels;
2180
2181 spin_unlock_irq(&dbri->lock);
2182
2183 dprintk(D_USR, "prepare audio output. %d bytes\n", info->size);
2184 return ret;
2185 }
2186
2187 static int snd_dbri_trigger(struct snd_pcm_substream *substream, int cmd)
2188 {
2189 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2190 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2191 int ret = 0;
2192
2193 switch (cmd) {
2194 case SNDRV_PCM_TRIGGER_START:
2195 dprintk(D_USR, "start audio, period is %d bytes\n",
2196 (int)snd_pcm_lib_period_bytes(substream));
2197 /* Enable & schedule the tasklet that re-submits the TDs. */
2198 xmit_descs_task.data = (unsigned long)dbri;
2199 tasklet_schedule(&xmit_descs_task);
2200 break;
2201 case SNDRV_PCM_TRIGGER_STOP:
2202 dprintk(D_USR, "stop audio.\n");
2203 /* Make the tasklet bail out immediately. */
2204 xmit_descs_task.data = 0;
2205 reset_pipe(dbri, info->pipe);
2206 break;
2207 default:
2208 ret = -EINVAL;
2209 }
2210
2211 return ret;
2212 }
2213
2214 static snd_pcm_uframes_t snd_dbri_pointer(struct snd_pcm_substream *substream)
2215 {
2216 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2217 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
2218 snd_pcm_uframes_t ret;
2219
2220 ret = bytes_to_frames(substream->runtime, info->offset)
2221 % substream->runtime->buffer_size;
2222 dprintk(D_USR, "I/O pointer: %ld frames, %d bytes left.\n",
2223 ret, info->left);
2224 return ret;
2225 }
2226
2227 static struct snd_pcm_ops snd_dbri_ops = {
2228 .open = snd_dbri_open,
2229 .close = snd_dbri_close,
2230 .ioctl = snd_pcm_lib_ioctl,
2231 .hw_params = snd_dbri_hw_params,
2232 .hw_free = snd_dbri_hw_free,
2233 .prepare = snd_dbri_prepare,
2234 .trigger = snd_dbri_trigger,
2235 .pointer = snd_dbri_pointer,
2236 };
2237
2238 static int __devinit snd_dbri_pcm(struct snd_dbri * dbri)
2239 {
2240 struct snd_pcm *pcm;
2241 int err;
2242
2243 if ((err = snd_pcm_new(dbri->card,
2244 /* ID */ "sun_dbri",
2245 /* device */ 0,
2246 /* playback count */ 1,
2247 /* capture count */ 1, &pcm)) < 0)
2248 return err;
2249 snd_assert(pcm != NULL, return -EINVAL);
2250
2251 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_dbri_ops);
2252 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_dbri_ops);
2253
2254 pcm->private_data = dbri;
2255 pcm->info_flags = 0;
2256 strcpy(pcm->name, dbri->card->shortname);
2257 dbri->pcm = pcm;
2258
2259 if ((err = snd_pcm_lib_preallocate_pages_for_all(pcm,
2260 SNDRV_DMA_TYPE_CONTINUOUS,
2261 snd_dma_continuous_data(GFP_KERNEL),
2262 64 * 1024, 64 * 1024)) < 0) {
2263 return err;
2264 }
2265
2266 return 0;
2267 }
2268
2269 /*****************************************************************************
2270 Mixer interface
2271 *****************************************************************************/
2272
2273 static int snd_cs4215_info_volume(struct snd_kcontrol *kcontrol,
2274 struct snd_ctl_elem_info *uinfo)
2275 {
2276 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2277 uinfo->count = 2;
2278 uinfo->value.integer.min = 0;
2279 if (kcontrol->private_value == DBRI_PLAY) {
2280 uinfo->value.integer.max = DBRI_MAX_VOLUME;
2281 } else {
2282 uinfo->value.integer.max = DBRI_MAX_GAIN;
2283 }
2284 return 0;
2285 }
2286
2287 static int snd_cs4215_get_volume(struct snd_kcontrol *kcontrol,
2288 struct snd_ctl_elem_value *ucontrol)
2289 {
2290 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2291 struct dbri_streaminfo *info;
2292 snd_assert(dbri != NULL, return -EINVAL);
2293 info = &dbri->stream_info[kcontrol->private_value];
2294 snd_assert(info != NULL, return -EINVAL);
2295
2296 ucontrol->value.integer.value[0] = info->left_gain;
2297 ucontrol->value.integer.value[1] = info->right_gain;
2298 return 0;
2299 }
2300
2301 static int snd_cs4215_put_volume(struct snd_kcontrol *kcontrol,
2302 struct snd_ctl_elem_value *ucontrol)
2303 {
2304 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2305 struct dbri_streaminfo *info = &dbri->stream_info[kcontrol->private_value];
2306 unsigned long flags;
2307 int changed = 0;
2308
2309 if (info->left_gain != ucontrol->value.integer.value[0]) {
2310 info->left_gain = ucontrol->value.integer.value[0];
2311 changed = 1;
2312 }
2313 if (info->right_gain != ucontrol->value.integer.value[1]) {
2314 info->right_gain = ucontrol->value.integer.value[1];
2315 changed = 1;
2316 }
2317 if (changed == 1) {
2318 /* First mute outputs, and wait 1/8000 sec (125 us)
2319 * to make sure this takes. This avoids clicking noises.
2320 */
2321 spin_lock_irqsave(&dbri->lock, flags);
2322
2323 cs4215_setdata(dbri, 1);
2324 udelay(125);
2325 cs4215_setdata(dbri, 0);
2326
2327 spin_unlock_irqrestore(&dbri->lock, flags);
2328 }
2329 return changed;
2330 }
2331
2332 static int snd_cs4215_info_single(struct snd_kcontrol *kcontrol,
2333 struct snd_ctl_elem_info *uinfo)
2334 {
2335 int mask = (kcontrol->private_value >> 16) & 0xff;
2336
2337 uinfo->type = (mask == 1) ?
2338 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2339 uinfo->count = 1;
2340 uinfo->value.integer.min = 0;
2341 uinfo->value.integer.max = mask;
2342 return 0;
2343 }
2344
2345 static int snd_cs4215_get_single(struct snd_kcontrol *kcontrol,
2346 struct snd_ctl_elem_value *ucontrol)
2347 {
2348 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2349 int elem = kcontrol->private_value & 0xff;
2350 int shift = (kcontrol->private_value >> 8) & 0xff;
2351 int mask = (kcontrol->private_value >> 16) & 0xff;
2352 int invert = (kcontrol->private_value >> 24) & 1;
2353 snd_assert(dbri != NULL, return -EINVAL);
2354
2355 if (elem < 4) {
2356 ucontrol->value.integer.value[0] =
2357 (dbri->mm.data[elem] >> shift) & mask;
2358 } else {
2359 ucontrol->value.integer.value[0] =
2360 (dbri->mm.ctrl[elem - 4] >> shift) & mask;
2361 }
2362
2363 if (invert == 1) {
2364 ucontrol->value.integer.value[0] =
2365 mask - ucontrol->value.integer.value[0];
2366 }
2367 return 0;
2368 }
2369
2370 static int snd_cs4215_put_single(struct snd_kcontrol *kcontrol,
2371 struct snd_ctl_elem_value *ucontrol)
2372 {
2373 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2374 unsigned long flags;
2375 int elem = kcontrol->private_value & 0xff;
2376 int shift = (kcontrol->private_value >> 8) & 0xff;
2377 int mask = (kcontrol->private_value >> 16) & 0xff;
2378 int invert = (kcontrol->private_value >> 24) & 1;
2379 int changed = 0;
2380 unsigned short val;
2381 snd_assert(dbri != NULL, return -EINVAL);
2382
2383 val = (ucontrol->value.integer.value[0] & mask);
2384 if (invert == 1)
2385 val = mask - val;
2386 val <<= shift;
2387
2388 if (elem < 4) {
2389 dbri->mm.data[elem] = (dbri->mm.data[elem] &
2390 ~(mask << shift)) | val;
2391 changed = (val != dbri->mm.data[elem]);
2392 } else {
2393 dbri->mm.ctrl[elem - 4] = (dbri->mm.ctrl[elem - 4] &
2394 ~(mask << shift)) | val;
2395 changed = (val != dbri->mm.ctrl[elem - 4]);
2396 }
2397
2398 dprintk(D_GEN, "put_single: mask=0x%x, changed=%d, "
2399 "mixer-value=%ld, mm-value=0x%x\n",
2400 mask, changed, ucontrol->value.integer.value[0],
2401 dbri->mm.data[elem & 3]);
2402
2403 if (changed) {
2404 /* First mute outputs, and wait 1/8000 sec (125 us)
2405 * to make sure this takes. This avoids clicking noises.
2406 */
2407 spin_lock_irqsave(&dbri->lock, flags);
2408
2409 cs4215_setdata(dbri, 1);
2410 udelay(125);
2411 cs4215_setdata(dbri, 0);
2412
2413 spin_unlock_irqrestore(&dbri->lock, flags);
2414 }
2415 return changed;
2416 }
2417
2418 /* Entries 0-3 map to the 4 data timeslots, entries 4-7 map to the 4 control
2419 timeslots. Shift is the bit offset in the timeslot, mask defines the
2420 number of bits. invert is a boolean for use with attenuation.
2421 */
2422 #define CS4215_SINGLE(xname, entry, shift, mask, invert) \
2423 { .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
2424 .info = snd_cs4215_info_single, \
2425 .get = snd_cs4215_get_single, .put = snd_cs4215_put_single, \
2426 .private_value = entry | (shift << 8) | (mask << 16) | (invert << 24) },
2427
2428 static struct snd_kcontrol_new dbri_controls[] __devinitdata = {
2429 {
2430 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2431 .name = "Playback Volume",
2432 .info = snd_cs4215_info_volume,
2433 .get = snd_cs4215_get_volume,
2434 .put = snd_cs4215_put_volume,
2435 .private_value = DBRI_PLAY,
2436 },
2437 CS4215_SINGLE("Headphone switch", 0, 7, 1, 0)
2438 CS4215_SINGLE("Line out switch", 0, 6, 1, 0)
2439 CS4215_SINGLE("Speaker switch", 1, 6, 1, 0)
2440 {
2441 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2442 .name = "Capture Volume",
2443 .info = snd_cs4215_info_volume,
2444 .get = snd_cs4215_get_volume,
2445 .put = snd_cs4215_put_volume,
2446 .private_value = DBRI_REC,
2447 },
2448 /* FIXME: mic/line switch */
2449 CS4215_SINGLE("Line in switch", 2, 4, 1, 0)
2450 CS4215_SINGLE("High Pass Filter switch", 5, 7, 1, 0)
2451 CS4215_SINGLE("Monitor Volume", 3, 4, 0xf, 1)
2452 CS4215_SINGLE("Mic boost", 4, 4, 1, 1)
2453 };
2454
2455 #define NUM_CS4215_CONTROLS (sizeof(dbri_controls)/sizeof(struct snd_kcontrol_new))
2456
2457 static int __init snd_dbri_mixer(struct snd_dbri * dbri)
2458 {
2459 struct snd_card *card;
2460 int idx, err;
2461
2462 snd_assert(dbri != NULL && dbri->card != NULL, return -EINVAL);
2463
2464 card = dbri->card;
2465 strcpy(card->mixername, card->shortname);
2466
2467 for (idx = 0; idx < NUM_CS4215_CONTROLS; idx++) {
2468 if ((err = snd_ctl_add(card,
2469 snd_ctl_new1(&dbri_controls[idx], dbri))) < 0)
2470 return err;
2471 }
2472
2473 for (idx = DBRI_REC; idx < DBRI_NO_STREAMS; idx++) {
2474 dbri->stream_info[idx].left_gain = 0;
2475 dbri->stream_info[idx].right_gain = 0;
2476 dbri->stream_info[idx].balance = DBRI_MID_BALANCE;
2477 }
2478
2479 return 0;
2480 }
2481
2482 /****************************************************************************
2483 /proc interface
2484 ****************************************************************************/
2485 static void dbri_regs_read(struct snd_info_entry * entry, struct snd_info_buffer *buffer)
2486 {
2487 struct snd_dbri *dbri = entry->private_data;
2488
2489 snd_iprintf(buffer, "REG0: 0x%x\n", sbus_readl(dbri->regs + REG0));
2490 snd_iprintf(buffer, "REG2: 0x%x\n", sbus_readl(dbri->regs + REG2));
2491 snd_iprintf(buffer, "REG8: 0x%x\n", sbus_readl(dbri->regs + REG8));
2492 snd_iprintf(buffer, "REG9: 0x%x\n", sbus_readl(dbri->regs + REG9));
2493 }
2494
2495 #ifdef DBRI_DEBUG
2496 static void dbri_debug_read(struct snd_info_entry * entry,
2497 struct snd_info_buffer *buffer)
2498 {
2499 struct snd_dbri *dbri = entry->private_data;
2500 int pipe;
2501 snd_iprintf(buffer, "debug=%d\n", dbri_debug);
2502
2503 for (pipe = 0; pipe < 32; pipe++) {
2504 if (pipe_active(dbri, pipe)) {
2505 struct dbri_pipe *pptr = &dbri->pipes[pipe];
2506 snd_iprintf(buffer,
2507 "Pipe %d: %s SDP=0x%x desc=%d, "
2508 "len=%d @ %d prev: %d next %d\n",
2509 pipe,
2510 (pptr->direction ==
2511 PIPEinput ? "input" : "output"), pptr->sdp,
2512 pptr->desc, pptr->length, pptr->cycle,
2513 pptr->prevpipe, pptr->nextpipe);
2514 }
2515 }
2516 }
2517 #endif
2518
2519 void snd_dbri_proc(struct snd_dbri * dbri)
2520 {
2521 struct snd_info_entry *entry;
2522
2523 if (! snd_card_proc_new(dbri->card, "regs", &entry))
2524 snd_info_set_text_ops(entry, dbri, 1024, dbri_regs_read);
2525
2526 #ifdef DBRI_DEBUG
2527 if (! snd_card_proc_new(dbri->card, "debug", &entry)) {
2528 snd_info_set_text_ops(entry, dbri, 4096, dbri_debug_read);
2529 entry->mode = S_IFREG | S_IRUGO; /* Readable only. */
2530 }
2531 #endif
2532 }
2533
2534 /*
2535 ****************************************************************************
2536 **************************** Initialization ********************************
2537 ****************************************************************************
2538 */
2539 static void snd_dbri_free(struct snd_dbri * dbri);
2540
2541 static int __init snd_dbri_create(struct snd_card *card,
2542 struct sbus_dev *sdev,
2543 struct linux_prom_irqs *irq, int dev)
2544 {
2545 struct snd_dbri *dbri = card->private_data;
2546 int err;
2547
2548 spin_lock_init(&dbri->lock);
2549 dbri->card = card;
2550 dbri->sdev = sdev;
2551 dbri->irq = irq->pri;
2552 dbri->dbri_version = sdev->prom_name[9];
2553
2554 dbri->dma = sbus_alloc_consistent(sdev, sizeof(struct dbri_dma),
2555 &dbri->dma_dvma);
2556 memset((void *)dbri->dma, 0, sizeof(struct dbri_dma));
2557
2558 dprintk(D_GEN, "DMA Cmd Block 0x%p (0x%08x)\n",
2559 dbri->dma, dbri->dma_dvma);
2560
2561 /* Map the registers into memory. */
2562 dbri->regs_size = sdev->reg_addrs[0].reg_size;
2563 dbri->regs = sbus_ioremap(&sdev->resource[0], 0,
2564 dbri->regs_size, "DBRI Registers");
2565 if (!dbri->regs) {
2566 printk(KERN_ERR "DBRI: could not allocate registers\n");
2567 sbus_free_consistent(sdev, sizeof(struct dbri_dma),
2568 (void *)dbri->dma, dbri->dma_dvma);
2569 return -EIO;
2570 }
2571
2572 err = request_irq(dbri->irq, snd_dbri_interrupt, SA_SHIRQ,
2573 "DBRI audio", dbri);
2574 if (err) {
2575 printk(KERN_ERR "DBRI: Can't get irq %d\n", dbri->irq);
2576 sbus_iounmap(dbri->regs, dbri->regs_size);
2577 sbus_free_consistent(sdev, sizeof(struct dbri_dma),
2578 (void *)dbri->dma, dbri->dma_dvma);
2579 return err;
2580 }
2581
2582 /* Do low level initialization of the DBRI and CS4215 chips */
2583 dbri_initialize(dbri);
2584 err = cs4215_init(dbri);
2585 if (err) {
2586 snd_dbri_free(dbri);
2587 return err;
2588 }
2589
2590 dbri->next = dbri_list;
2591 dbri_list = dbri;
2592
2593 return 0;
2594 }
2595
2596 static void snd_dbri_free(struct snd_dbri * dbri)
2597 {
2598 dprintk(D_GEN, "snd_dbri_free\n");
2599 dbri_reset(dbri);
2600
2601 if (dbri->irq)
2602 free_irq(dbri->irq, dbri);
2603
2604 if (dbri->regs)
2605 sbus_iounmap(dbri->regs, dbri->regs_size);
2606
2607 if (dbri->dma)
2608 sbus_free_consistent(dbri->sdev, sizeof(struct dbri_dma),
2609 (void *)dbri->dma, dbri->dma_dvma);
2610 }
2611
2612 static int __init dbri_attach(int prom_node, struct sbus_dev *sdev)
2613 {
2614 struct snd_dbri *dbri;
2615 struct linux_prom_irqs irq;
2616 struct resource *rp;
2617 struct snd_card *card;
2618 static int dev = 0;
2619 int err;
2620
2621 if (sdev->prom_name[9] < 'e') {
2622 printk(KERN_ERR "DBRI: unsupported chip version %c found.\n",
2623 sdev->prom_name[9]);
2624 return -EIO;
2625 }
2626
2627 if (dev >= SNDRV_CARDS)
2628 return -ENODEV;
2629 if (!enable[dev]) {
2630 dev++;
2631 return -ENOENT;
2632 }
2633
2634 err = prom_getproperty(prom_node, "intr", (char *)&irq, sizeof(irq));
2635 if (err < 0) {
2636 printk(KERN_ERR "DBRI-%d: Firmware node lacks IRQ property.\n", dev);
2637 return -ENODEV;
2638 }
2639
2640 card = snd_card_new(index[dev], id[dev], THIS_MODULE,
2641 sizeof(struct snd_dbri));
2642 if (card == NULL)
2643 return -ENOMEM;
2644
2645 strcpy(card->driver, "DBRI");
2646 strcpy(card->shortname, "Sun DBRI");
2647 rp = &sdev->resource[0];
2648 sprintf(card->longname, "%s at 0x%02lx:0x%08lx, irq %d",
2649 card->shortname,
2650 rp->flags & 0xffL, rp->start, irq.pri);
2651
2652 if ((err = snd_dbri_create(card, sdev, &irq, dev)) < 0) {
2653 snd_card_free(card);
2654 return err;
2655 }
2656
2657 dbri = card->private_data;
2658 if ((err = snd_dbri_pcm(dbri)) < 0)
2659 goto _err;
2660
2661 if ((err = snd_dbri_mixer(dbri)) < 0)
2662 goto _err;
2663
2664 /* /proc file handling */
2665 snd_dbri_proc(dbri);
2666
2667 if ((err = snd_card_register(card)) < 0)
2668 goto _err;
2669
2670 printk(KERN_INFO "audio%d at %p (irq %d) is DBRI(%c)+CS4215(%d)\n",
2671 dev, dbri->regs,
2672 dbri->irq, dbri->dbri_version, dbri->mm.version);
2673 dev++;
2674
2675 return 0;
2676
2677 _err:
2678 snd_dbri_free(dbri);
2679 snd_card_free(card);
2680 return err;
2681 }
2682
2683 /* Probe for the dbri chip and then attach the driver. */
2684 static int __init dbri_init(void)
2685 {
2686 struct sbus_bus *sbus;
2687 struct sbus_dev *sdev;
2688 int found = 0;
2689
2690 /* Probe each SBUS for the DBRI chip(s). */
2691 for_all_sbusdev(sdev, sbus) {
2692 /*
2693 * The version is coded in the last character
2694 */
2695 if (!strncmp(sdev->prom_name, "SUNW,DBRI", 9)) {
2696 dprintk(D_GEN, "DBRI: Found %s in SBUS slot %d\n",
2697 sdev->prom_name, sdev->slot);
2698
2699 if (dbri_attach(sdev->prom_node, sdev) == 0)
2700 found++;
2701 }
2702 }
2703
2704 return (found > 0) ? 0 : -EIO;
2705 }
2706
2707 static void __exit dbri_exit(void)
2708 {
2709 struct snd_dbri *this = dbri_list;
2710
2711 while (this != NULL) {
2712 struct snd_dbri *next = this->next;
2713 struct snd_card *card = this->card;
2714
2715 snd_dbri_free(this);
2716 snd_card_free(card);
2717 this = next;
2718 }
2719 dbri_list = NULL;
2720 }
2721
2722 module_init(dbri_init);
2723 module_exit(dbri_exit);
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