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[linux-2.6/verdex.git] / drivers / message / fusion / lsi / mpi_cnfg.h
blobd8339896f7343c60732c3f0f5f6c92bf8391373f
1 /*
2 * Copyright (c) 2000-2005 LSI Logic Corporation.
3 *
4 *
5 * Name: mpi_cnfg.h
6 * Title: MPI Config message, structures, and Pages
7 * Creation Date: July 27, 2000
8 *
9 * mpi_cnfg.h Version: 01.05.09
10 *
11 * Version History
12 * ---------------
13 *
14 * Date Version Description
15 * -------- -------- ------------------------------------------------------
16 * 05-08-00 00.10.01 Original release for 0.10 spec dated 4/26/2000.
17 * 06-06-00 01.00.01 Update version number for 1.0 release.
18 * 06-08-00 01.00.02 Added _PAGEVERSION definitions for all pages.
19 * Added FcPhLowestVersion, FcPhHighestVersion, Reserved2
20 * fields to FC_DEVICE_0 page, updated the page version.
21 * Changed _FREE_RUNNING_CLOCK to _PACING_TRANSFERS in
22 * SCSI_PORT_0, SCSI_DEVICE_0 and SCSI_DEVICE_1 pages
23 * and updated the page versions.
24 * Added _RESPONSE_ID_MASK definition to SCSI_PORT_1
25 * page and updated the page version.
26 * Added Information field and _INFO_PARAMS_NEGOTIATED
27 * definitionto SCSI_DEVICE_0 page.
28 * 06-22-00 01.00.03 Removed batch controls from LAN_0 page and updated the
29 * page version.
30 * Added BucketsRemaining to LAN_1 page, redefined the
31 * state values, and updated the page version.
32 * Revised bus width definitions in SCSI_PORT_0,
33 * SCSI_DEVICE_0 and SCSI_DEVICE_1 pages.
34 * 06-30-00 01.00.04 Added MaxReplySize to LAN_1 page and updated the page
35 * version.
36 * Moved FC_DEVICE_0 PageAddress description to spec.
37 * 07-27-00 01.00.05 Corrected the SubsystemVendorID and SubsystemID field
38 * widths in IOC_0 page and updated the page version.
39 * 11-02-00 01.01.01 Original release for post 1.0 work
40 * Added Manufacturing pages, IO Unit Page 2, SCSI SPI
41 * Port Page 2, FC Port Page 4, FC Port Page 5
42 * 11-15-00 01.01.02 Interim changes to match proposals
43 * 12-04-00 01.01.03 Config page changes to match MPI rev 1.00.01.
44 * 12-05-00 01.01.04 Modified config page actions.
45 * 01-09-01 01.01.05 Added defines for page address formats.
46 * Data size for Manufacturing pages 2 and 3 no longer
47 * defined here.
48 * Io Unit Page 2 size is fixed at 4 adapters and some
49 * flags were changed.
50 * SCSI Port Page 2 Device Settings modified.
51 * New fields added to FC Port Page 0 and some flags
52 * cleaned up.
53 * Removed impedance flash from FC Port Page 1.
54 * Added FC Port pages 6 and 7.
55 * 01-25-01 01.01.06 Added MaxInitiators field to FcPortPage0.
56 * 01-29-01 01.01.07 Changed some defines to make them 32 character unique.
57 * Added some LinkType defines for FcPortPage0.
58 * 02-20-01 01.01.08 Started using MPI_POINTER.
59 * 02-27-01 01.01.09 Replaced MPI_CONFIG_PAGETYPE_SCSI_LUN with
60 * MPI_CONFIG_PAGETYPE_RAID_VOLUME.
61 * Added definitions and structures for IOC Page 2 and
62 * RAID Volume Page 2.
63 * 03-27-01 01.01.10 Added CONFIG_PAGE_FC_PORT_8 and CONFIG_PAGE_FC_PORT_9.
64 * CONFIG_PAGE_FC_PORT_3 now supports persistent by DID.
65 * Added VendorId and ProductRevLevel fields to
66 * RAIDVOL2_IM_PHYS_ID struct.
67 * Modified values for MPI_FCPORTPAGE0_FLAGS_ATTACH_
68 * defines to make them compatible to MPI version 1.0.
69 * Added structure offset comments.
70 * 04-09-01 01.01.11 Added some new defines for the PageAddress field and
71 * removed some obsolete ones.
72 * Added IO Unit Page 3.
73 * Modified defines for Scsi Port Page 2.
74 * Modified RAID Volume Pages.
75 * 08-08-01 01.02.01 Original release for v1.2 work.
76 * Added SepID and SepBus to RVP2 IMPhysicalDisk struct.
77 * Added defines for the SEP bits in RVP2 VolumeSettings.
78 * Modified the DeviceSettings field in RVP2 to use the
79 * proper structure.
80 * Added defines for SES, SAF-TE, and cross channel for
81 * IOCPage2 CapabilitiesFlags.
82 * Removed define for MPI_IOUNITPAGE2_FLAGS_RAID_DISABLE.
83 * Removed define for
84 * MPI_SCSIPORTPAGE2_PORT_FLAGS_PARITY_ENABLE.
85 * Added define for MPI_CONFIG_PAGEATTR_RO_PERSISTENT.
86 * 08-29-01 01.02.02 Fixed value for MPI_MANUFACTPAGE_DEVID_53C1035.
87 * Added defines for MPI_FCPORTPAGE1_FLAGS_HARD_ALPA_ONLY
88 * and MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY.
89 * Removed MPI_SCSIPORTPAGE0_CAP_PACING_TRANSFERS,
90 * MPI_SCSIDEVPAGE0_NP_PACING_TRANSFERS, and
91 * MPI_SCSIDEVPAGE1_RP_PACING_TRANSFERS, and
92 * MPI_SCSIDEVPAGE1_CONF_PPR_ALLOWED.
93 * Added defines for MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED
94 * and MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED.
95 * Added OnBusTimerValue to CONFIG_PAGE_SCSI_PORT_1.
96 * Added rejected bits to SCSI Device Page 0 Information.
97 * Increased size of ALPA array in FC Port Page 2 by one
98 * and removed a one byte reserved field.
99 * 09-28-01 01.02.03 Swapped NegWireSpeedLow and NegWireSpeedLow in
100 * CONFIG_PAGE_LAN_1 to match preferred 64-bit ordering.
101 * Added structures for Manufacturing Page 4, IO Unit
102 * Page 3, IOC Page 3, IOC Page 4, RAID Volume Page 0, and
103 * RAID PhysDisk Page 0.
104 * 10-04-01 01.02.04 Added define for MPI_CONFIG_PAGETYPE_RAID_PHYSDISK.
105 * Modified some of the new defines to make them 32
106 * character unique.
107 * Modified how variable length pages (arrays) are defined.
108 * Added generic defines for hot spare pools and RAID
109 * volume types.
110 * 11-01-01 01.02.05 Added define for MPI_IOUNITPAGE1_DISABLE_IR.
111 * 03-14-02 01.02.06 Added PCISlotNum field to CONFIG_PAGE_IOC_1 along with
112 * related define, and bumped the page version define.
113 * 05-31-02 01.02.07 Added a Flags field to CONFIG_PAGE_IOC_2_RAID_VOL in a
114 * reserved byte and added a define.
115 * Added define for
116 * MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE.
117 * Added new config page: CONFIG_PAGE_IOC_5.
118 * Added MaxAliases, MaxHardAliases, and NumCurrentAliases
119 * fields to CONFIG_PAGE_FC_PORT_0.
120 * Added AltConnector and NumRequestedAliases fields to
121 * CONFIG_PAGE_FC_PORT_1.
122 * Added new config page: CONFIG_PAGE_FC_PORT_10.
123 * 07-12-02 01.02.08 Added more MPI_MANUFACTPAGE_DEVID_ defines.
124 * Added additional MPI_SCSIDEVPAGE0_NP_ defines.
125 * Added more MPI_SCSIDEVPAGE1_RP_ defines.
126 * Added define for
127 * MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE.
128 * Added new config page: CONFIG_PAGE_SCSI_DEVICE_3.
129 * Modified MPI_FCPORTPAGE5_FLAGS_ defines.
130 * 09-16-02 01.02.09 Added MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG define.
131 * 11-15-02 01.02.10 Added ConnectedID defines for CONFIG_PAGE_SCSI_PORT_0.
132 * Added more Flags defines for CONFIG_PAGE_FC_PORT_1.
133 * Added more Flags defines for CONFIG_PAGE_FC_DEVICE_0.
134 * 04-01-03 01.02.11 Added RR_TOV field and additional Flags defines for
135 * CONFIG_PAGE_FC_PORT_1.
136 * Added define MPI_FCPORTPAGE5_FLAGS_DISABLE to disable
137 * an alias.
138 * Added more device id defines.
139 * 06-26-03 01.02.12 Added MPI_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID define.
140 * Added TargetConfig and IDConfig fields to
141 * CONFIG_PAGE_SCSI_PORT_1.
142 * Added more PortFlags defines for CONFIG_PAGE_SCSI_PORT_2
143 * to control DV.
144 * Added more Flags defines for CONFIG_PAGE_FC_PORT_1.
145 * In CONFIG_PAGE_FC_DEVICE_0, replaced Reserved1 field
146 * with ADISCHardALPA.
147 * Added MPI_FC_DEVICE_PAGE0_PROT_FCP_RETRY define.
148 * 01-16-04 01.02.13 Added InitiatorDeviceTimeout and InitiatorIoPendTimeout
149 * fields and related defines to CONFIG_PAGE_FC_PORT_1.
150 * Added define for
151 * MPI_FCPORTPAGE1_FLAGS_SOFT_ALPA_FALLBACK.
152 * Added new fields to the substructures of
153 * CONFIG_PAGE_FC_PORT_10.
154 * 04-29-04 01.02.14 Added define for IDP bit for CONFIG_PAGE_SCSI_PORT_0,
155 * CONFIG_PAGE_SCSI_DEVICE_0, and
156 * CONFIG_PAGE_SCSI_DEVICE_1. Also bumped Page Version for
157 * these pages.
158 * 05-11-04 01.03.01 Added structure for CONFIG_PAGE_INBAND_0.
159 * 08-19-04 01.05.01 Modified MSG_CONFIG request to support extended config
160 * pages.
161 * Added a new structure for extended config page header.
162 * Added new extended config pages types and structures for
163 * SAS IO Unit, SAS Expander, SAS Device, and SAS PHY.
164 * Replaced a reserved byte in CONFIG_PAGE_MANUFACTURING_4
165 * to add a Flags field.
166 * Two new Manufacturing config pages (5 and 6).
167 * Two new bits defined for IO Unit Page 1 Flags field.
168 * Modified CONFIG_PAGE_IO_UNIT_2 to add three new fields
169 * to specify the BIOS boot device.
170 * Four new Flags bits defined for IO Unit Page 2.
171 * Added IO Unit Page 4.
172 * Added EEDP Flags settings to IOC Page 1.
173 * Added new BIOS Page 1 config page.
174 * 10-05-04 01.05.02 Added define for
175 * MPI_IOCPAGE1_INITIATOR_CONTEXT_REPLY_DISABLE.
176 * Added new Flags field to CONFIG_PAGE_MANUFACTURING_5 and
177 * associated defines.
178 * Added more defines for SAS IO Unit Page 0
179 * DiscoveryStatus field.
180 * Added define for MPI_SAS_IOUNIT0_DS_SUBTRACTIVE_LINK
181 * and MPI_SAS_IOUNIT0_DS_TABLE_LINK.
182 * Added defines for Physical Mapping Modes to SAS IO Unit
183 * Page 2.
184 * Added define for
185 * MPI_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH.
186 * 10-27-04 01.05.03 Added defines for new SAS PHY page addressing mode.
187 * Added defines for MaxTargetSpinUp to BIOS Page 1.
188 * Added 5 new ControlFlags defines for SAS IO Unit
189 * Page 1.
190 * Added MaxNumPhysicalMappedIDs field to SAS IO Unit
191 * Page 2.
192 * Added AccessStatus field to SAS Device Page 0 and added
193 * new Flags bits for supported SATA features.
194 * 12-07-04 01.05.04 Added config page structures for BIOS Page 2, RAID
195 * Volume Page 1, and RAID Physical Disk Page 1.
196 * Replaced IO Unit Page 1 BootTargetID,BootBus, and
197 * BootAdapterNum with reserved field.
198 * Added DataScrubRate and ResyncRate to RAID Volume
199 * Page 0.
200 * Added MPI_SAS_IOUNIT2_FLAGS_RESERVE_ID_0_FOR_BOOT
201 * define.
202 * 12-09-04 01.05.05 Added Target Mode Large CDB Enable to FC Port Page 1
203 * Flags field.
204 * Added Auto Port Config flag define for SAS IOUNIT
205 * Page 1 ControlFlags.
206 * Added Disabled bad Phy define to Expander Page 1
207 * Discovery Info field.
208 * Added SAS/SATA device support to SAS IOUnit Page 1
209 * ControlFlags.
210 * Added Unsupported device to SAS Dev Page 0 Flags field
211 * Added disable use SATA Hash Address for SAS IOUNIT
212 * page 1 in ControlFields.
213 * 01-15-05 01.05.06 Added defaults for data scrub rate and resync rate to
214 * Manufacturing Page 4.
215 * Added new defines for BIOS Page 1 IOCSettings field.
216 * Added ExtDiskIdentifier field to RAID Physical Disk
217 * Page 0.
218 * Added new defines for SAS IO Unit Page 1 ControlFlags
219 * and to SAS Device Page 0 Flags to control SATA devices.
220 * Added defines and structures for the new Log Page 0, a
221 * new type of configuration page.
222 * 02-09-05 01.05.07 Added InactiveStatus field to RAID Volume Page 0.
223 * Added WWID field to RAID Volume Page 1.
224 * Added PhysicalPort field to SAS Expander pages 0 and 1.
225 * 03-11-05 01.05.08 Removed the EEDP flags from IOC Page 1.
226 * Added Enclosure/Slot boot device format to BIOS Page 2.
227 * New status value for RAID Volume Page 0 VolumeStatus
228 * (VolumeState subfield).
229 * New value for RAID Physical Page 0 InactiveStatus.
230 * Added Inactive Volume Member flag RAID Physical Disk
231 * Page 0 PhysDiskStatus field.
232 * New physical mapping mode in SAS IO Unit Page 2.
233 * Added CONFIG_PAGE_SAS_ENCLOSURE_0.
234 * Added Slot and Enclosure fields to SAS Device Page 0.
235 * 06-24-05 01.05.09 Added EEDP defines to IOC Page 1.
236 * Added more RAID type defines to IOC Page 2.
237 * Added Port Enable Delay settings to BIOS Page 1.
238 * Added Bad Block Table Full define to RAID Volume Page 0.
239 * Added Previous State defines to RAID Physical Disk
240 * Page 0.
241 * Added Max Sata Targets define for DiscoveryStatus field
242 * of SAS IO Unit Page 0.
243 * Added Device Self Test to Control Flags of SAS IO Unit
244 * Page 1.
245 * Added Direct Attach Starting Slot Number define for SAS
246 * IO Unit Page 2.
247 * Added new fields in SAS Device Page 2 for enclosure
248 * mapping.
249 * Added OwnerDevHandle and Flags field to SAS PHY Page 0.
250 * Added IOC GPIO Flags define to SAS Enclosure Page 0.
251 * Fixed the value for MPI_SAS_IOUNIT1_CONTROL_DEV_SATA_SUPPORT.
252 * --------------------------------------------------------------------------
253 */
254
255 #ifndef MPI_CNFG_H
256 #define MPI_CNFG_H
257
258
259 /*****************************************************************************
260 *
261 * C o n f i g M e s s a g e a n d S t r u c t u r e s
262 *
263 *****************************************************************************/
264
265 typedef struct _CONFIG_PAGE_HEADER
266 {
267 U8 PageVersion; /* 00h */
268 U8 PageLength; /* 01h */
269 U8 PageNumber; /* 02h */
270 U8 PageType; /* 03h */
271 } CONFIG_PAGE_HEADER, MPI_POINTER PTR_CONFIG_PAGE_HEADER,
272 ConfigPageHeader_t, MPI_POINTER pConfigPageHeader_t;
273
274 typedef union _CONFIG_PAGE_HEADER_UNION
275 {
276 ConfigPageHeader_t Struct;
277 U8 Bytes[4];
278 U16 Word16[2];
279 U32 Word32;
280 } ConfigPageHeaderUnion, MPI_POINTER pConfigPageHeaderUnion,
281 CONFIG_PAGE_HEADER_UNION, MPI_POINTER PTR_CONFIG_PAGE_HEADER_UNION;
282
283 typedef struct _CONFIG_EXTENDED_PAGE_HEADER
284 {
285 U8 PageVersion; /* 00h */
286 U8 Reserved1; /* 01h */
287 U8 PageNumber; /* 02h */
288 U8 PageType; /* 03h */
289 U16 ExtPageLength; /* 04h */
290 U8 ExtPageType; /* 06h */
291 U8 Reserved2; /* 07h */
292 } CONFIG_EXTENDED_PAGE_HEADER, MPI_POINTER PTR_CONFIG_EXTENDED_PAGE_HEADER,
293 ConfigExtendedPageHeader_t, MPI_POINTER pConfigExtendedPageHeader_t;
294
295
296
297 /****************************************************************************
298 * PageType field values
299 ****************************************************************************/
300 #define MPI_CONFIG_PAGEATTR_READ_ONLY (0x00)
301 #define MPI_CONFIG_PAGEATTR_CHANGEABLE (0x10)
302 #define MPI_CONFIG_PAGEATTR_PERSISTENT (0x20)
303 #define MPI_CONFIG_PAGEATTR_RO_PERSISTENT (0x30)
304 #define MPI_CONFIG_PAGEATTR_MASK (0xF0)
305
306 #define MPI_CONFIG_PAGETYPE_IO_UNIT (0x00)
307 #define MPI_CONFIG_PAGETYPE_IOC (0x01)
308 #define MPI_CONFIG_PAGETYPE_BIOS (0x02)
309 #define MPI_CONFIG_PAGETYPE_SCSI_PORT (0x03)
310 #define MPI_CONFIG_PAGETYPE_SCSI_DEVICE (0x04)
311 #define MPI_CONFIG_PAGETYPE_FC_PORT (0x05)
312 #define MPI_CONFIG_PAGETYPE_FC_DEVICE (0x06)
313 #define MPI_CONFIG_PAGETYPE_LAN (0x07)
314 #define MPI_CONFIG_PAGETYPE_RAID_VOLUME (0x08)
315 #define MPI_CONFIG_PAGETYPE_MANUFACTURING (0x09)
316 #define MPI_CONFIG_PAGETYPE_RAID_PHYSDISK (0x0A)
317 #define MPI_CONFIG_PAGETYPE_INBAND (0x0B)
318 #define MPI_CONFIG_PAGETYPE_EXTENDED (0x0F)
319 #define MPI_CONFIG_PAGETYPE_MASK (0x0F)
320
321 #define MPI_CONFIG_TYPENUM_MASK (0x0FFF)
322
323
324 /****************************************************************************
325 * ExtPageType field values
326 ****************************************************************************/
327 #define MPI_CONFIG_EXTPAGETYPE_SAS_IO_UNIT (0x10)
328 #define MPI_CONFIG_EXTPAGETYPE_SAS_EXPANDER (0x11)
329 #define MPI_CONFIG_EXTPAGETYPE_SAS_DEVICE (0x12)
330 #define MPI_CONFIG_EXTPAGETYPE_SAS_PHY (0x13)
331 #define MPI_CONFIG_EXTPAGETYPE_LOG (0x14)
332 #define MPI_CONFIG_EXTPAGETYPE_ENCLOSURE (0x15)
333
334
335 /****************************************************************************
336 * PageAddress field values
337 ****************************************************************************/
338 #define MPI_SCSI_PORT_PGAD_PORT_MASK (0x000000FF)
339
340 #define MPI_SCSI_DEVICE_FORM_MASK (0xF0000000)
341 #define MPI_SCSI_DEVICE_FORM_BUS_TID (0x00000000)
342 #define MPI_SCSI_DEVICE_TARGET_ID_MASK (0x000000FF)
343 #define MPI_SCSI_DEVICE_TARGET_ID_SHIFT (0)
344 #define MPI_SCSI_DEVICE_BUS_MASK (0x0000FF00)
345 #define MPI_SCSI_DEVICE_BUS_SHIFT (8)
346 #define MPI_SCSI_DEVICE_FORM_TARGET_MODE (0x10000000)
347 #define MPI_SCSI_DEVICE_TM_RESPOND_ID_MASK (0x000000FF)
348 #define MPI_SCSI_DEVICE_TM_RESPOND_ID_SHIFT (0)
349 #define MPI_SCSI_DEVICE_TM_BUS_MASK (0x0000FF00)
350 #define MPI_SCSI_DEVICE_TM_BUS_SHIFT (8)
351 #define MPI_SCSI_DEVICE_TM_INIT_ID_MASK (0x00FF0000)
352 #define MPI_SCSI_DEVICE_TM_INIT_ID_SHIFT (16)
353
354 #define MPI_FC_PORT_PGAD_PORT_MASK (0xF0000000)
355 #define MPI_FC_PORT_PGAD_PORT_SHIFT (28)
356 #define MPI_FC_PORT_PGAD_FORM_MASK (0x0F000000)
357 #define MPI_FC_PORT_PGAD_FORM_INDEX (0x01000000)
358 #define MPI_FC_PORT_PGAD_INDEX_MASK (0x0000FFFF)
359 #define MPI_FC_PORT_PGAD_INDEX_SHIFT (0)
360
361 #define MPI_FC_DEVICE_PGAD_PORT_MASK (0xF0000000)
362 #define MPI_FC_DEVICE_PGAD_PORT_SHIFT (28)
363 #define MPI_FC_DEVICE_PGAD_FORM_MASK (0x0F000000)
364 #define MPI_FC_DEVICE_PGAD_FORM_NEXT_DID (0x00000000)
365 #define MPI_FC_DEVICE_PGAD_ND_PORT_MASK (0xF0000000)
366 #define MPI_FC_DEVICE_PGAD_ND_PORT_SHIFT (28)
367 #define MPI_FC_DEVICE_PGAD_ND_DID_MASK (0x00FFFFFF)
368 #define MPI_FC_DEVICE_PGAD_ND_DID_SHIFT (0)
369 #define MPI_FC_DEVICE_PGAD_FORM_BUS_TID (0x01000000)
370 #define MPI_FC_DEVICE_PGAD_BT_BUS_MASK (0x0000FF00)
371 #define MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT (8)
372 #define MPI_FC_DEVICE_PGAD_BT_TID_MASK (0x000000FF)
373 #define MPI_FC_DEVICE_PGAD_BT_TID_SHIFT (0)
374
375 #define MPI_PHYSDISK_PGAD_PHYSDISKNUM_MASK (0x000000FF)
376 #define MPI_PHYSDISK_PGAD_PHYSDISKNUM_SHIFT (0)
377
378 #define MPI_SAS_EXPAND_PGAD_FORM_MASK (0xF0000000)
379 #define MPI_SAS_EXPAND_PGAD_FORM_SHIFT (28)
380 #define MPI_SAS_EXPAND_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
381 #define MPI_SAS_EXPAND_PGAD_FORM_HANDLE_PHY_NUM (0x00000001)
382 #define MPI_SAS_EXPAND_PGAD_FORM_HANDLE (0x00000002)
383 #define MPI_SAS_EXPAND_PGAD_GNH_MASK_HANDLE (0x0000FFFF)
384 #define MPI_SAS_EXPAND_PGAD_GNH_SHIFT_HANDLE (0)
385 #define MPI_SAS_EXPAND_PGAD_HPN_MASK_PHY (0x00FF0000)
386 #define MPI_SAS_EXPAND_PGAD_HPN_SHIFT_PHY (16)
387 #define MPI_SAS_EXPAND_PGAD_HPN_MASK_HANDLE (0x0000FFFF)
388 #define MPI_SAS_EXPAND_PGAD_HPN_SHIFT_HANDLE (0)
389 #define MPI_SAS_EXPAND_PGAD_H_MASK_HANDLE (0x0000FFFF)
390 #define MPI_SAS_EXPAND_PGAD_H_SHIFT_HANDLE (0)
391
392 #define MPI_SAS_DEVICE_PGAD_FORM_MASK (0xF0000000)
393 #define MPI_SAS_DEVICE_PGAD_FORM_SHIFT (28)
394 #define MPI_SAS_DEVICE_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
395 #define MPI_SAS_DEVICE_PGAD_FORM_BUS_TARGET_ID (0x00000001)
396 #define MPI_SAS_DEVICE_PGAD_FORM_HANDLE (0x00000002)
397 #define MPI_SAS_DEVICE_PGAD_GNH_HANDLE_MASK (0x0000FFFF)
398 #define MPI_SAS_DEVICE_PGAD_GNH_HANDLE_SHIFT (0)
399 #define MPI_SAS_DEVICE_PGAD_BT_BUS_MASK (0x0000FF00)
400 #define MPI_SAS_DEVICE_PGAD_BT_BUS_SHIFT (8)
401 #define MPI_SAS_DEVICE_PGAD_BT_TID_MASK (0x000000FF)
402 #define MPI_SAS_DEVICE_PGAD_BT_TID_SHIFT (0)
403 #define MPI_SAS_DEVICE_PGAD_H_HANDLE_MASK (0x0000FFFF)
404 #define MPI_SAS_DEVICE_PGAD_H_HANDLE_SHIFT (0)
405
406 #define MPI_SAS_PHY_PGAD_FORM_MASK (0xF0000000)
407 #define MPI_SAS_PHY_PGAD_FORM_SHIFT (28)
408 #define MPI_SAS_PHY_PGAD_FORM_PHY_NUMBER (0x0)
409 #define MPI_SAS_PHY_PGAD_FORM_PHY_TBL_INDEX (0x1)
410 #define MPI_SAS_PHY_PGAD_PHY_NUMBER_MASK (0x000000FF)
411 #define MPI_SAS_PHY_PGAD_PHY_NUMBER_SHIFT (0)
412 #define MPI_SAS_PHY_PGAD_PHY_TBL_INDEX_MASK (0x0000FFFF)
413 #define MPI_SAS_PHY_PGAD_PHY_TBL_INDEX_SHIFT (0)
414
415 #define MPI_SAS_ENCLOS_PGAD_FORM_MASK (0xF0000000)
416 #define MPI_SAS_ENCLOS_PGAD_FORM_SHIFT (28)
417 #define MPI_SAS_ENCLOS_PGAD_FORM_GET_NEXT_HANDLE (0x00000000)
418 #define MPI_SAS_ENCLOS_PGAD_FORM_HANDLE (0x00000001)
419 #define MPI_SAS_ENCLOS_PGAD_GNH_HANDLE_MASK (0x0000FFFF)
420 #define MPI_SAS_ENCLOS_PGAD_GNH_HANDLE_SHIFT (0)
421 #define MPI_SAS_ENCLOS_PGAD_H_HANDLE_MASK (0x0000FFFF)
422 #define MPI_SAS_ENCLOS_PGAD_H_HANDLE_SHIFT (0)
423
424
425
426 /****************************************************************************
427 * Config Request Message
428 ****************************************************************************/
429 typedef struct _MSG_CONFIG
430 {
431 U8 Action; /* 00h */
432 U8 Reserved; /* 01h */
433 U8 ChainOffset; /* 02h */
434 U8 Function; /* 03h */
435 U16 ExtPageLength; /* 04h */
436 U8 ExtPageType; /* 06h */
437 U8 MsgFlags; /* 07h */
438 U32 MsgContext; /* 08h */
439 U8 Reserved2[8]; /* 0Ch */
440 CONFIG_PAGE_HEADER Header; /* 14h */
441 U32 PageAddress; /* 18h */
442 SGE_IO_UNION PageBufferSGE; /* 1Ch */
443 } MSG_CONFIG, MPI_POINTER PTR_MSG_CONFIG,
444 Config_t, MPI_POINTER pConfig_t;
445
446
447 /****************************************************************************
448 * Action field values
449 ****************************************************************************/
450 #define MPI_CONFIG_ACTION_PAGE_HEADER (0x00)
451 #define MPI_CONFIG_ACTION_PAGE_READ_CURRENT (0x01)
452 #define MPI_CONFIG_ACTION_PAGE_WRITE_CURRENT (0x02)
453 #define MPI_CONFIG_ACTION_PAGE_DEFAULT (0x03)
454 #define MPI_CONFIG_ACTION_PAGE_WRITE_NVRAM (0x04)
455 #define MPI_CONFIG_ACTION_PAGE_READ_DEFAULT (0x05)
456 #define MPI_CONFIG_ACTION_PAGE_READ_NVRAM (0x06)
457
458
459 /* Config Reply Message */
460 typedef struct _MSG_CONFIG_REPLY
461 {
462 U8 Action; /* 00h */
463 U8 Reserved; /* 01h */
464 U8 MsgLength; /* 02h */
465 U8 Function; /* 03h */
466 U16 ExtPageLength; /* 04h */
467 U8 ExtPageType; /* 06h */
468 U8 MsgFlags; /* 07h */
469 U32 MsgContext; /* 08h */
470 U8 Reserved2[2]; /* 0Ch */
471 U16 IOCStatus; /* 0Eh */
472 U32 IOCLogInfo; /* 10h */
473 CONFIG_PAGE_HEADER Header; /* 14h */
474 } MSG_CONFIG_REPLY, MPI_POINTER PTR_MSG_CONFIG_REPLY,
475 ConfigReply_t, MPI_POINTER pConfigReply_t;
476
477
478
479 /*****************************************************************************
480 *
481 * C o n f i g u r a t i o n P a g e s
482 *
483 *****************************************************************************/
484
485 /****************************************************************************
486 * Manufacturing Config pages
487 ****************************************************************************/
488 #define MPI_MANUFACTPAGE_VENDORID_LSILOGIC (0x1000)
489 /* Fibre Channel */
490 #define MPI_MANUFACTPAGE_DEVICEID_FC909 (0x0621)
491 #define MPI_MANUFACTPAGE_DEVICEID_FC919 (0x0624)
492 #define MPI_MANUFACTPAGE_DEVICEID_FC929 (0x0622)
493 #define MPI_MANUFACTPAGE_DEVICEID_FC919X (0x0628)
494 #define MPI_MANUFACTPAGE_DEVICEID_FC929X (0x0626)
495 #define MPI_MANUFACTPAGE_DEVICEID_FC939X (0x0642)
496 #define MPI_MANUFACTPAGE_DEVICEID_FC949X (0x0640)
497 #define MPI_MANUFACTPAGE_DEVICEID_FC949ES (0x0646)
498 /* SCSI */
499 #define MPI_MANUFACTPAGE_DEVID_53C1030 (0x0030)
500 #define MPI_MANUFACTPAGE_DEVID_53C1030ZC (0x0031)
501 #define MPI_MANUFACTPAGE_DEVID_1030_53C1035 (0x0032)
502 #define MPI_MANUFACTPAGE_DEVID_1030ZC_53C1035 (0x0033)
503 #define MPI_MANUFACTPAGE_DEVID_53C1035 (0x0040)
504 #define MPI_MANUFACTPAGE_DEVID_53C1035ZC (0x0041)
505 /* SAS */
506 #define MPI_MANUFACTPAGE_DEVID_SAS1064 (0x0050)
507 #define MPI_MANUFACTPAGE_DEVID_SAS1064A (0x005C)
508 #define MPI_MANUFACTPAGE_DEVID_SAS1064E (0x0056)
509 #define MPI_MANUFACTPAGE_DEVID_SAS1066 (0x005E)
510 #define MPI_MANUFACTPAGE_DEVID_SAS1066E (0x005A)
511 #define MPI_MANUFACTPAGE_DEVID_SAS1068 (0x0054)
512 #define MPI_MANUFACTPAGE_DEVID_SAS1068E (0x0058)
513 #define MPI_MANUFACTPAGE_DEVID_SAS1078 (0x0060)
514
515
516 typedef struct _CONFIG_PAGE_MANUFACTURING_0
517 {
518 CONFIG_PAGE_HEADER Header; /* 00h */
519 U8 ChipName[16]; /* 04h */
520 U8 ChipRevision[8]; /* 14h */
521 U8 BoardName[16]; /* 1Ch */
522 U8 BoardAssembly[16]; /* 2Ch */
523 U8 BoardTracerNumber[16]; /* 3Ch */
524
525 } CONFIG_PAGE_MANUFACTURING_0, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_0,
526 ManufacturingPage0_t, MPI_POINTER pManufacturingPage0_t;
527
528 #define MPI_MANUFACTURING0_PAGEVERSION (0x00)
529
530
531 typedef struct _CONFIG_PAGE_MANUFACTURING_1
532 {
533 CONFIG_PAGE_HEADER Header; /* 00h */
534 U8 VPD[256]; /* 04h */
535 } CONFIG_PAGE_MANUFACTURING_1, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_1,
536 ManufacturingPage1_t, MPI_POINTER pManufacturingPage1_t;
537
538 #define MPI_MANUFACTURING1_PAGEVERSION (0x00)
539
540
541 typedef struct _MPI_CHIP_REVISION_ID
542 {
543 U16 DeviceID; /* 00h */
544 U8 PCIRevisionID; /* 02h */
545 U8 Reserved; /* 03h */
546 } MPI_CHIP_REVISION_ID, MPI_POINTER PTR_MPI_CHIP_REVISION_ID,
547 MpiChipRevisionId_t, MPI_POINTER pMpiChipRevisionId_t;
548
549
550 /*
551 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
552 * one and check Header.PageLength at runtime.
553 */
554 #ifndef MPI_MAN_PAGE_2_HW_SETTINGS_WORDS
555 #define MPI_MAN_PAGE_2_HW_SETTINGS_WORDS (1)
556 #endif
557
558 typedef struct _CONFIG_PAGE_MANUFACTURING_2
559 {
560 CONFIG_PAGE_HEADER Header; /* 00h */
561 MPI_CHIP_REVISION_ID ChipId; /* 04h */
562 U32 HwSettings[MPI_MAN_PAGE_2_HW_SETTINGS_WORDS];/* 08h */
563 } CONFIG_PAGE_MANUFACTURING_2, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_2,
564 ManufacturingPage2_t, MPI_POINTER pManufacturingPage2_t;
565
566 #define MPI_MANUFACTURING2_PAGEVERSION (0x00)
567
568
569 /*
570 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
571 * one and check Header.PageLength at runtime.
572 */
573 #ifndef MPI_MAN_PAGE_3_INFO_WORDS
574 #define MPI_MAN_PAGE_3_INFO_WORDS (1)
575 #endif
576
577 typedef struct _CONFIG_PAGE_MANUFACTURING_3
578 {
579 CONFIG_PAGE_HEADER Header; /* 00h */
580 MPI_CHIP_REVISION_ID ChipId; /* 04h */
581 U32 Info[MPI_MAN_PAGE_3_INFO_WORDS];/* 08h */
582 } CONFIG_PAGE_MANUFACTURING_3, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_3,
583 ManufacturingPage3_t, MPI_POINTER pManufacturingPage3_t;
584
585 #define MPI_MANUFACTURING3_PAGEVERSION (0x00)
586
587
588 typedef struct _CONFIG_PAGE_MANUFACTURING_4
589 {
590 CONFIG_PAGE_HEADER Header; /* 00h */
591 U32 Reserved1; /* 04h */
592 U8 InfoOffset0; /* 08h */
593 U8 InfoSize0; /* 09h */
594 U8 InfoOffset1; /* 0Ah */
595 U8 InfoSize1; /* 0Bh */
596 U8 InquirySize; /* 0Ch */
597 U8 Flags; /* 0Dh */
598 U16 Reserved2; /* 0Eh */
599 U8 InquiryData[56]; /* 10h */
600 U32 ISVolumeSettings; /* 48h */
601 U32 IMEVolumeSettings; /* 4Ch */
602 U32 IMVolumeSettings; /* 50h */
603 U32 Reserved3; /* 54h */
604 U32 Reserved4; /* 58h */
605 U8 ISDataScrubRate; /* 5Ch */
606 U8 ISResyncRate; /* 5Dh */
607 U16 Reserved5; /* 5Eh */
608 U8 IMEDataScrubRate; /* 60h */
609 U8 IMEResyncRate; /* 61h */
610 U16 Reserved6; /* 62h */
611 U8 IMDataScrubRate; /* 64h */
612 U8 IMResyncRate; /* 65h */
613 U16 Reserved7; /* 66h */
614 U32 Reserved8; /* 68h */
615 U32 Reserved9; /* 6Ch */
616 } CONFIG_PAGE_MANUFACTURING_4, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_4,
617 ManufacturingPage4_t, MPI_POINTER pManufacturingPage4_t;
618
619 #define MPI_MANUFACTURING4_PAGEVERSION (0x02)
620
621 /* defines for the Flags field */
622 #define MPI_MANPAGE4_IR_NO_MIX_SAS_SATA (0x01)
623
624
625 typedef struct _CONFIG_PAGE_MANUFACTURING_5
626 {
627 CONFIG_PAGE_HEADER Header; /* 00h */
628 U64 BaseWWID; /* 04h */
629 U8 Flags; /* 0Ch */
630 U8 Reserved1; /* 0Dh */
631 U16 Reserved2; /* 0Eh */
632 } CONFIG_PAGE_MANUFACTURING_5, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_5,
633 ManufacturingPage5_t, MPI_POINTER pManufacturingPage5_t;
634
635 #define MPI_MANUFACTURING5_PAGEVERSION (0x01)
636
637 /* defines for the Flags field */
638 #define MPI_MANPAGE5_TWO_WWID_PER_PHY (0x01)
639
640
641 typedef struct _CONFIG_PAGE_MANUFACTURING_6
642 {
643 CONFIG_PAGE_HEADER Header; /* 00h */
644 U32 ProductSpecificInfo;/* 04h */
645 } CONFIG_PAGE_MANUFACTURING_6, MPI_POINTER PTR_CONFIG_PAGE_MANUFACTURING_6,
646 ManufacturingPage6_t, MPI_POINTER pManufacturingPage6_t;
647
648 #define MPI_MANUFACTURING6_PAGEVERSION (0x00)
649
650
651 /****************************************************************************
652 * IO Unit Config Pages
653 ****************************************************************************/
654
655 typedef struct _CONFIG_PAGE_IO_UNIT_0
656 {
657 CONFIG_PAGE_HEADER Header; /* 00h */
658 U64 UniqueValue; /* 04h */
659 } CONFIG_PAGE_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_0,
660 IOUnitPage0_t, MPI_POINTER pIOUnitPage0_t;
661
662 #define MPI_IOUNITPAGE0_PAGEVERSION (0x00)
663
664
665 typedef struct _CONFIG_PAGE_IO_UNIT_1
666 {
667 CONFIG_PAGE_HEADER Header; /* 00h */
668 U32 Flags; /* 04h */
669 } CONFIG_PAGE_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_1,
670 IOUnitPage1_t, MPI_POINTER pIOUnitPage1_t;
671
672 #define MPI_IOUNITPAGE1_PAGEVERSION (0x01)
673
674 /* IO Unit Page 1 Flags defines */
675 #define MPI_IOUNITPAGE1_MULTI_FUNCTION (0x00000000)
676 #define MPI_IOUNITPAGE1_SINGLE_FUNCTION (0x00000001)
677 #define MPI_IOUNITPAGE1_MULTI_PATHING (0x00000002)
678 #define MPI_IOUNITPAGE1_SINGLE_PATHING (0x00000000)
679 #define MPI_IOUNITPAGE1_IR_USE_STATIC_VOLUME_ID (0x00000004)
680 #define MPI_IOUNITPAGE1_DISABLE_QUEUE_FULL_HANDLING (0x00000020)
681 #define MPI_IOUNITPAGE1_DISABLE_IR (0x00000040)
682 #define MPI_IOUNITPAGE1_FORCE_32 (0x00000080)
683 #define MPI_IOUNITPAGE1_NATIVE_COMMAND_Q_DISABLE (0x00000100)
684
685
686 typedef struct _MPI_ADAPTER_INFO
687 {
688 U8 PciBusNumber; /* 00h */
689 U8 PciDeviceAndFunctionNumber; /* 01h */
690 U16 AdapterFlags; /* 02h */
691 } MPI_ADAPTER_INFO, MPI_POINTER PTR_MPI_ADAPTER_INFO,
692 MpiAdapterInfo_t, MPI_POINTER pMpiAdapterInfo_t;
693
694 #define MPI_ADAPTER_INFO_FLAGS_EMBEDDED (0x0001)
695 #define MPI_ADAPTER_INFO_FLAGS_INIT_STATUS (0x0002)
696
697 typedef struct _CONFIG_PAGE_IO_UNIT_2
698 {
699 CONFIG_PAGE_HEADER Header; /* 00h */
700 U32 Flags; /* 04h */
701 U32 BiosVersion; /* 08h */
702 MPI_ADAPTER_INFO AdapterOrder[4]; /* 0Ch */
703 U32 Reserved1; /* 1Ch */
704 } CONFIG_PAGE_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_2,
705 IOUnitPage2_t, MPI_POINTER pIOUnitPage2_t;
706
707 #define MPI_IOUNITPAGE2_PAGEVERSION (0x02)
708
709 #define MPI_IOUNITPAGE2_FLAGS_PAUSE_ON_ERROR (0x00000002)
710 #define MPI_IOUNITPAGE2_FLAGS_VERBOSE_ENABLE (0x00000004)
711 #define MPI_IOUNITPAGE2_FLAGS_COLOR_VIDEO_DISABLE (0x00000008)
712 #define MPI_IOUNITPAGE2_FLAGS_DONT_HOOK_INT_40 (0x00000010)
713
714 #define MPI_IOUNITPAGE2_FLAGS_DEV_LIST_DISPLAY_MASK (0x000000E0)
715 #define MPI_IOUNITPAGE2_FLAGS_INSTALLED_DEV_DISPLAY (0x00000000)
716 #define MPI_IOUNITPAGE2_FLAGS_ADAPTER_DISPLAY (0x00000020)
717 #define MPI_IOUNITPAGE2_FLAGS_ADAPTER_DEV_DISPLAY (0x00000040)
718
719
720 /*
721 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
722 * one and check Header.PageLength at runtime.
723 */
724 #ifndef MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX
725 #define MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX (1)
726 #endif
727
728 typedef struct _CONFIG_PAGE_IO_UNIT_3
729 {
730 CONFIG_PAGE_HEADER Header; /* 00h */
731 U8 GPIOCount; /* 04h */
732 U8 Reserved1; /* 05h */
733 U16 Reserved2; /* 06h */
734 U16 GPIOVal[MPI_IO_UNIT_PAGE_3_GPIO_VAL_MAX]; /* 08h */
735 } CONFIG_PAGE_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_3,
736 IOUnitPage3_t, MPI_POINTER pIOUnitPage3_t;
737
738 #define MPI_IOUNITPAGE3_PAGEVERSION (0x01)
739
740 #define MPI_IOUNITPAGE3_GPIO_FUNCTION_MASK (0xFC)
741 #define MPI_IOUNITPAGE3_GPIO_FUNCTION_SHIFT (2)
742 #define MPI_IOUNITPAGE3_GPIO_SETTING_OFF (0x00)
743 #define MPI_IOUNITPAGE3_GPIO_SETTING_ON (0x01)
744
745
746 typedef struct _CONFIG_PAGE_IO_UNIT_4
747 {
748 CONFIG_PAGE_HEADER Header; /* 00h */
749 U32 Reserved1; /* 04h */
750 SGE_SIMPLE_UNION FWImageSGE; /* 08h */
751 } CONFIG_PAGE_IO_UNIT_4, MPI_POINTER PTR_CONFIG_PAGE_IO_UNIT_4,
752 IOUnitPage4_t, MPI_POINTER pIOUnitPage4_t;
753
754 #define MPI_IOUNITPAGE4_PAGEVERSION (0x00)
755
756
757 /****************************************************************************
758 * IOC Config Pages
759 ****************************************************************************/
760
761 typedef struct _CONFIG_PAGE_IOC_0
762 {
763 CONFIG_PAGE_HEADER Header; /* 00h */
764 U32 TotalNVStore; /* 04h */
765 U32 FreeNVStore; /* 08h */
766 U16 VendorID; /* 0Ch */
767 U16 DeviceID; /* 0Eh */
768 U8 RevisionID; /* 10h */
769 U8 Reserved[3]; /* 11h */
770 U32 ClassCode; /* 14h */
771 U16 SubsystemVendorID; /* 18h */
772 U16 SubsystemID; /* 1Ah */
773 } CONFIG_PAGE_IOC_0, MPI_POINTER PTR_CONFIG_PAGE_IOC_0,
774 IOCPage0_t, MPI_POINTER pIOCPage0_t;
775
776 #define MPI_IOCPAGE0_PAGEVERSION (0x01)
777
778
779 typedef struct _CONFIG_PAGE_IOC_1
780 {
781 CONFIG_PAGE_HEADER Header; /* 00h */
782 U32 Flags; /* 04h */
783 U32 CoalescingTimeout; /* 08h */
784 U8 CoalescingDepth; /* 0Ch */
785 U8 PCISlotNum; /* 0Dh */
786 U8 Reserved[2]; /* 0Eh */
787 } CONFIG_PAGE_IOC_1, MPI_POINTER PTR_CONFIG_PAGE_IOC_1,
788 IOCPage1_t, MPI_POINTER pIOCPage1_t;
789
790 #define MPI_IOCPAGE1_PAGEVERSION (0x03)
791
792 /* defines for the Flags field */
793 #define MPI_IOCPAGE1_EEDP_MODE_MASK (0x07000000)
794 #define MPI_IOCPAGE1_EEDP_MODE_OFF (0x00000000)
795 #define MPI_IOCPAGE1_EEDP_MODE_T10 (0x01000000)
796 #define MPI_IOCPAGE1_EEDP_MODE_LSI_1 (0x02000000)
797 #define MPI_IOCPAGE1_INITIATOR_CONTEXT_REPLY_DISABLE (0x00000010)
798 #define MPI_IOCPAGE1_REPLY_COALESCING (0x00000001)
799
800 #define MPI_IOCPAGE1_PCISLOTNUM_UNKNOWN (0xFF)
801
802
803 typedef struct _CONFIG_PAGE_IOC_2_RAID_VOL
804 {
805 U8 VolumeID; /* 00h */
806 U8 VolumeBus; /* 01h */
807 U8 VolumeIOC; /* 02h */
808 U8 VolumePageNumber; /* 03h */
809 U8 VolumeType; /* 04h */
810 U8 Flags; /* 05h */
811 U16 Reserved3; /* 06h */
812 } CONFIG_PAGE_IOC_2_RAID_VOL, MPI_POINTER PTR_CONFIG_PAGE_IOC_2_RAID_VOL,
813 ConfigPageIoc2RaidVol_t, MPI_POINTER pConfigPageIoc2RaidVol_t;
814
815 /* IOC Page 2 Volume RAID Type values, also used in RAID Volume pages */
816
817 #define MPI_RAID_VOL_TYPE_IS (0x00)
818 #define MPI_RAID_VOL_TYPE_IME (0x01)
819 #define MPI_RAID_VOL_TYPE_IM (0x02)
820 #define MPI_RAID_VOL_TYPE_RAID_5 (0x03)
821 #define MPI_RAID_VOL_TYPE_RAID_6 (0x04)
822 #define MPI_RAID_VOL_TYPE_RAID_10 (0x05)
823 #define MPI_RAID_VOL_TYPE_RAID_50 (0x06)
824 #define MPI_RAID_VOL_TYPE_UNKNOWN (0xFF)
825
826 /* IOC Page 2 Volume Flags values */
827
828 #define MPI_IOCPAGE2_FLAG_VOLUME_INACTIVE (0x08)
829
830 /*
831 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
832 * one and check Header.PageLength at runtime.
833 */
834 #ifndef MPI_IOC_PAGE_2_RAID_VOLUME_MAX
835 #define MPI_IOC_PAGE_2_RAID_VOLUME_MAX (1)
836 #endif
837
838 typedef struct _CONFIG_PAGE_IOC_2
839 {
840 CONFIG_PAGE_HEADER Header; /* 00h */
841 U32 CapabilitiesFlags; /* 04h */
842 U8 NumActiveVolumes; /* 08h */
843 U8 MaxVolumes; /* 09h */
844 U8 NumActivePhysDisks; /* 0Ah */
845 U8 MaxPhysDisks; /* 0Bh */
846 CONFIG_PAGE_IOC_2_RAID_VOL RaidVolume[MPI_IOC_PAGE_2_RAID_VOLUME_MAX];/* 0Ch */
847 } CONFIG_PAGE_IOC_2, MPI_POINTER PTR_CONFIG_PAGE_IOC_2,
848 IOCPage2_t, MPI_POINTER pIOCPage2_t;
849
850 #define MPI_IOCPAGE2_PAGEVERSION (0x03)
851
852 /* IOC Page 2 Capabilities flags */
853
854 #define MPI_IOCPAGE2_CAP_FLAGS_IS_SUPPORT (0x00000001)
855 #define MPI_IOCPAGE2_CAP_FLAGS_IME_SUPPORT (0x00000002)
856 #define MPI_IOCPAGE2_CAP_FLAGS_IM_SUPPORT (0x00000004)
857 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_5_SUPPORT (0x00000008)
858 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_6_SUPPORT (0x00000010)
859 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_10_SUPPORT (0x00000020)
860 #define MPI_IOCPAGE2_CAP_FLAGS_RAID_50_SUPPORT (0x00000040)
861 #define MPI_IOCPAGE2_CAP_FLAGS_SES_SUPPORT (0x20000000)
862 #define MPI_IOCPAGE2_CAP_FLAGS_SAFTE_SUPPORT (0x40000000)
863 #define MPI_IOCPAGE2_CAP_FLAGS_CROSS_CHANNEL_SUPPORT (0x80000000)
864
865
866 typedef struct _IOC_3_PHYS_DISK
867 {
868 U8 PhysDiskID; /* 00h */
869 U8 PhysDiskBus; /* 01h */
870 U8 PhysDiskIOC; /* 02h */
871 U8 PhysDiskNum; /* 03h */
872 } IOC_3_PHYS_DISK, MPI_POINTER PTR_IOC_3_PHYS_DISK,
873 Ioc3PhysDisk_t, MPI_POINTER pIoc3PhysDisk_t;
874
875 /*
876 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
877 * one and check Header.PageLength at runtime.
878 */
879 #ifndef MPI_IOC_PAGE_3_PHYSDISK_MAX
880 #define MPI_IOC_PAGE_3_PHYSDISK_MAX (1)
881 #endif
882
883 typedef struct _CONFIG_PAGE_IOC_3
884 {
885 CONFIG_PAGE_HEADER Header; /* 00h */
886 U8 NumPhysDisks; /* 04h */
887 U8 Reserved1; /* 05h */
888 U16 Reserved2; /* 06h */
889 IOC_3_PHYS_DISK PhysDisk[MPI_IOC_PAGE_3_PHYSDISK_MAX]; /* 08h */
890 } CONFIG_PAGE_IOC_3, MPI_POINTER PTR_CONFIG_PAGE_IOC_3,
891 IOCPage3_t, MPI_POINTER pIOCPage3_t;
892
893 #define MPI_IOCPAGE3_PAGEVERSION (0x00)
894
895
896 typedef struct _IOC_4_SEP
897 {
898 U8 SEPTargetID; /* 00h */
899 U8 SEPBus; /* 01h */
900 U16 Reserved; /* 02h */
901 } IOC_4_SEP, MPI_POINTER PTR_IOC_4_SEP,
902 Ioc4Sep_t, MPI_POINTER pIoc4Sep_t;
903
904 /*
905 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
906 * one and check Header.PageLength at runtime.
907 */
908 #ifndef MPI_IOC_PAGE_4_SEP_MAX
909 #define MPI_IOC_PAGE_4_SEP_MAX (1)
910 #endif
911
912 typedef struct _CONFIG_PAGE_IOC_4
913 {
914 CONFIG_PAGE_HEADER Header; /* 00h */
915 U8 ActiveSEP; /* 04h */
916 U8 MaxSEP; /* 05h */
917 U16 Reserved1; /* 06h */
918 IOC_4_SEP SEP[MPI_IOC_PAGE_4_SEP_MAX]; /* 08h */
919 } CONFIG_PAGE_IOC_4, MPI_POINTER PTR_CONFIG_PAGE_IOC_4,
920 IOCPage4_t, MPI_POINTER pIOCPage4_t;
921
922 #define MPI_IOCPAGE4_PAGEVERSION (0x00)
923
924
925 typedef struct _IOC_5_HOT_SPARE
926 {
927 U8 PhysDiskNum; /* 00h */
928 U8 Reserved; /* 01h */
929 U8 HotSparePool; /* 02h */
930 U8 Flags; /* 03h */
931 } IOC_5_HOT_SPARE, MPI_POINTER PTR_IOC_5_HOT_SPARE,
932 Ioc5HotSpare_t, MPI_POINTER pIoc5HotSpare_t;
933
934 /* IOC Page 5 HotSpare Flags */
935 #define MPI_IOC_PAGE_5_HOT_SPARE_ACTIVE (0x01)
936
937 /*
938 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
939 * one and check Header.PageLength at runtime.
940 */
941 #ifndef MPI_IOC_PAGE_5_HOT_SPARE_MAX
942 #define MPI_IOC_PAGE_5_HOT_SPARE_MAX (1)
943 #endif
944
945 typedef struct _CONFIG_PAGE_IOC_5
946 {
947 CONFIG_PAGE_HEADER Header; /* 00h */
948 U32 Reserved1; /* 04h */
949 U8 NumHotSpares; /* 08h */
950 U8 Reserved2; /* 09h */
951 U16 Reserved3; /* 0Ah */
952 IOC_5_HOT_SPARE HotSpare[MPI_IOC_PAGE_5_HOT_SPARE_MAX]; /* 0Ch */
953 } CONFIG_PAGE_IOC_5, MPI_POINTER PTR_CONFIG_PAGE_IOC_5,
954 IOCPage5_t, MPI_POINTER pIOCPage5_t;
955
956 #define MPI_IOCPAGE5_PAGEVERSION (0x00)
957
958
959 /****************************************************************************
960 * BIOS Config Pages
961 ****************************************************************************/
962
963 typedef struct _CONFIG_PAGE_BIOS_1
964 {
965 CONFIG_PAGE_HEADER Header; /* 00h */
966 U32 BiosOptions; /* 04h */
967 U32 IOCSettings; /* 08h */
968 U32 Reserved1; /* 0Ch */
969 U32 DeviceSettings; /* 10h */
970 U16 NumberOfDevices; /* 14h */
971 U16 Reserved2; /* 16h */
972 U16 IOTimeoutBlockDevicesNonRM; /* 18h */
973 U16 IOTimeoutSequential; /* 1Ah */
974 U16 IOTimeoutOther; /* 1Ch */
975 U16 IOTimeoutBlockDevicesRM; /* 1Eh */
976 } CONFIG_PAGE_BIOS_1, MPI_POINTER PTR_CONFIG_PAGE_BIOS_1,
977 BIOSPage1_t, MPI_POINTER pBIOSPage1_t;
978
979 #define MPI_BIOSPAGE1_PAGEVERSION (0x02)
980
981 /* values for the BiosOptions field */
982 #define MPI_BIOSPAGE1_OPTIONS_SPI_ENABLE (0x00000400)
983 #define MPI_BIOSPAGE1_OPTIONS_FC_ENABLE (0x00000200)
984 #define MPI_BIOSPAGE1_OPTIONS_SAS_ENABLE (0x00000100)
985 #define MPI_BIOSPAGE1_OPTIONS_DISABLE_BIOS (0x00000001)
986
987 /* values for the IOCSettings field */
988 #define MPI_BIOSPAGE1_IOCSET_MASK_PORT_ENABLE_DELAY (0x00F00000)
989 #define MPI_BIOSPAGE1_IOCSET_SHIFT_PORT_ENABLE_DELAY (20)
990 #define MPI_BIOSPAGE1_IOCSET_MASK_BOOT_PREFERENCE (0x00030000)
991 #define MPI_BIOSPAGE1_IOCSET_ENCLOSURE_SLOT_BOOT (0x00000000)
992 #define MPI_BIOSPAGE1_IOCSET_SAS_ADDRESS_BOOT (0x00010000)
993
994 #define MPI_BIOSPAGE1_IOCSET_MASK_MAX_TARGET_SPIN_UP (0x0000F000)
995 #define MPI_BIOSPAGE1_IOCSET_SHIFT_MAX_TARGET_SPIN_UP (12)
996
997 #define MPI_BIOSPAGE1_IOCSET_MASK_SPINUP_DELAY (0x00000F00)
998 #define MPI_BIOSPAGE1_IOCSET_SHIFT_SPINUP_DELAY (8)
999
1000 #define MPI_BIOSPAGE1_IOCSET_MASK_RM_SETTING (0x000000C0)
1001 #define MPI_BIOSPAGE1_IOCSET_NONE_RM_SETTING (0x00000000)
1002 #define MPI_BIOSPAGE1_IOCSET_BOOT_RM_SETTING (0x00000040)
1003 #define MPI_BIOSPAGE1_IOCSET_MEDIA_RM_SETTING (0x00000080)
1004
1005 #define MPI_BIOSPAGE1_IOCSET_MASK_ADAPTER_SUPPORT (0x00000030)
1006 #define MPI_BIOSPAGE1_IOCSET_NO_SUPPORT (0x00000000)
1007 #define MPI_BIOSPAGE1_IOCSET_BIOS_SUPPORT (0x00000010)
1008 #define MPI_BIOSPAGE1_IOCSET_OS_SUPPORT (0x00000020)
1009 #define MPI_BIOSPAGE1_IOCSET_ALL_SUPPORT (0x00000030)
1010
1011 #define MPI_BIOSPAGE1_IOCSET_ALTERNATE_CHS (0x00000008)
1012
1013 /* values for the DeviceSettings field */
1014 #define MPI_BIOSPAGE1_DEVSET_DISABLE_SEQ_LUN (0x00000008)
1015 #define MPI_BIOSPAGE1_DEVSET_DISABLE_RM_LUN (0x00000004)
1016 #define MPI_BIOSPAGE1_DEVSET_DISABLE_NON_RM_LUN (0x00000002)
1017 #define MPI_BIOSPAGE1_DEVSET_DISABLE_OTHER_LUN (0x00000001)
1018
1019 typedef struct _MPI_BOOT_DEVICE_ADAPTER_ORDER
1020 {
1021 U32 Reserved1; /* 00h */
1022 U32 Reserved2; /* 04h */
1023 U32 Reserved3; /* 08h */
1024 U32 Reserved4; /* 0Ch */
1025 U32 Reserved5; /* 10h */
1026 U32 Reserved6; /* 14h */
1027 U32 Reserved7; /* 18h */
1028 U32 Reserved8; /* 1Ch */
1029 U32 Reserved9; /* 20h */
1030 U32 Reserved10; /* 24h */
1031 U32 Reserved11; /* 28h */
1032 U32 Reserved12; /* 2Ch */
1033 U32 Reserved13; /* 30h */
1034 U32 Reserved14; /* 34h */
1035 U32 Reserved15; /* 38h */
1036 U32 Reserved16; /* 3Ch */
1037 U32 Reserved17; /* 40h */
1038 } MPI_BOOT_DEVICE_ADAPTER_ORDER, MPI_POINTER PTR_MPI_BOOT_DEVICE_ADAPTER_ORDER;
1039
1040 typedef struct _MPI_BOOT_DEVICE_ADAPTER_NUMBER
1041 {
1042 U8 TargetID; /* 00h */
1043 U8 Bus; /* 01h */
1044 U8 AdapterNumber; /* 02h */
1045 U8 Reserved1; /* 03h */
1046 U32 Reserved2; /* 04h */
1047 U32 Reserved3; /* 08h */
1048 U32 Reserved4; /* 0Ch */
1049 U8 LUN[8]; /* 10h */
1050 U32 Reserved5; /* 18h */
1051 U32 Reserved6; /* 1Ch */
1052 U32 Reserved7; /* 20h */
1053 U32 Reserved8; /* 24h */
1054 U32 Reserved9; /* 28h */
1055 U32 Reserved10; /* 2Ch */
1056 U32 Reserved11; /* 30h */
1057 U32 Reserved12; /* 34h */
1058 U32 Reserved13; /* 38h */
1059 U32 Reserved14; /* 3Ch */
1060 U32 Reserved15; /* 40h */
1061 } MPI_BOOT_DEVICE_ADAPTER_NUMBER, MPI_POINTER PTR_MPI_BOOT_DEVICE_ADAPTER_NUMBER;
1062
1063 typedef struct _MPI_BOOT_DEVICE_PCI_ADDRESS
1064 {
1065 U8 TargetID; /* 00h */
1066 U8 Bus; /* 01h */
1067 U16 PCIAddress; /* 02h */
1068 U32 Reserved1; /* 04h */
1069 U32 Reserved2; /* 08h */
1070 U32 Reserved3; /* 0Ch */
1071 U8 LUN[8]; /* 10h */
1072 U32 Reserved4; /* 18h */
1073 U32 Reserved5; /* 1Ch */
1074 U32 Reserved6; /* 20h */
1075 U32 Reserved7; /* 24h */
1076 U32 Reserved8; /* 28h */
1077 U32 Reserved9; /* 2Ch */
1078 U32 Reserved10; /* 30h */
1079 U32 Reserved11; /* 34h */
1080 U32 Reserved12; /* 38h */
1081 U32 Reserved13; /* 3Ch */
1082 U32 Reserved14; /* 40h */
1083 } MPI_BOOT_DEVICE_PCI_ADDRESS, MPI_POINTER PTR_MPI_BOOT_DEVICE_PCI_ADDRESS;
1084
1085 typedef struct _MPI_BOOT_DEVICE_SLOT_NUMBER
1086 {
1087 U8 TargetID; /* 00h */
1088 U8 Bus; /* 01h */
1089 U8 PCISlotNumber; /* 02h */
1090 U8 Reserved1; /* 03h */
1091 U32 Reserved2; /* 04h */
1092 U32 Reserved3; /* 08h */
1093 U32 Reserved4; /* 0Ch */
1094 U8 LUN[8]; /* 10h */
1095 U32 Reserved5; /* 18h */
1096 U32 Reserved6; /* 1Ch */
1097 U32 Reserved7; /* 20h */
1098 U32 Reserved8; /* 24h */
1099 U32 Reserved9; /* 28h */
1100 U32 Reserved10; /* 2Ch */
1101 U32 Reserved11; /* 30h */
1102 U32 Reserved12; /* 34h */
1103 U32 Reserved13; /* 38h */
1104 U32 Reserved14; /* 3Ch */
1105 U32 Reserved15; /* 40h */
1106 } MPI_BOOT_DEVICE_PCI_SLOT_NUMBER, MPI_POINTER PTR_MPI_BOOT_DEVICE_PCI_SLOT_NUMBER;
1107
1108 typedef struct _MPI_BOOT_DEVICE_FC_WWN
1109 {
1110 U64 WWPN; /* 00h */
1111 U32 Reserved1; /* 08h */
1112 U32 Reserved2; /* 0Ch */
1113 U8 LUN[8]; /* 10h */
1114 U32 Reserved3; /* 18h */
1115 U32 Reserved4; /* 1Ch */
1116 U32 Reserved5; /* 20h */
1117 U32 Reserved6; /* 24h */
1118 U32 Reserved7; /* 28h */
1119 U32 Reserved8; /* 2Ch */
1120 U32 Reserved9; /* 30h */
1121 U32 Reserved10; /* 34h */
1122 U32 Reserved11; /* 38h */
1123 U32 Reserved12; /* 3Ch */
1124 U32 Reserved13; /* 40h */
1125 } MPI_BOOT_DEVICE_FC_WWN, MPI_POINTER PTR_MPI_BOOT_DEVICE_FC_WWN;
1126
1127 typedef struct _MPI_BOOT_DEVICE_SAS_WWN
1128 {
1129 U64 SASAddress; /* 00h */
1130 U32 Reserved1; /* 08h */
1131 U32 Reserved2; /* 0Ch */
1132 U8 LUN[8]; /* 10h */
1133 U32 Reserved3; /* 18h */
1134 U32 Reserved4; /* 1Ch */
1135 U32 Reserved5; /* 20h */
1136 U32 Reserved6; /* 24h */
1137 U32 Reserved7; /* 28h */
1138 U32 Reserved8; /* 2Ch */
1139 U32 Reserved9; /* 30h */
1140 U32 Reserved10; /* 34h */
1141 U32 Reserved11; /* 38h */
1142 U32 Reserved12; /* 3Ch */
1143 U32 Reserved13; /* 40h */
1144 } MPI_BOOT_DEVICE_SAS_WWN, MPI_POINTER PTR_MPI_BOOT_DEVICE_SAS_WWN;
1145
1146 typedef struct _MPI_BOOT_DEVICE_ENCLOSURE_SLOT
1147 {
1148 U64 EnclosureLogicalID; /* 00h */
1149 U32 Reserved1; /* 08h */
1150 U32 Reserved2; /* 0Ch */
1151 U8 LUN[8]; /* 10h */
1152 U16 SlotNumber; /* 18h */
1153 U16 Reserved3; /* 1Ah */
1154 U32 Reserved4; /* 1Ch */
1155 U32 Reserved5; /* 20h */
1156 U32 Reserved6; /* 24h */
1157 U32 Reserved7; /* 28h */
1158 U32 Reserved8; /* 2Ch */
1159 U32 Reserved9; /* 30h */
1160 U32 Reserved10; /* 34h */
1161 U32 Reserved11; /* 38h */
1162 U32 Reserved12; /* 3Ch */
1163 U32 Reserved13; /* 40h */
1164 } MPI_BOOT_DEVICE_ENCLOSURE_SLOT,
1165 MPI_POINTER PTR_MPI_BOOT_DEVICE_ENCLOSURE_SLOT;
1166
1167 typedef union _MPI_BIOSPAGE2_BOOT_DEVICE
1168 {
1169 MPI_BOOT_DEVICE_ADAPTER_ORDER AdapterOrder;
1170 MPI_BOOT_DEVICE_ADAPTER_NUMBER AdapterNumber;
1171 MPI_BOOT_DEVICE_PCI_ADDRESS PCIAddress;
1172 MPI_BOOT_DEVICE_PCI_SLOT_NUMBER PCISlotNumber;
1173 MPI_BOOT_DEVICE_FC_WWN FcWwn;
1174 MPI_BOOT_DEVICE_SAS_WWN SasWwn;
1175 MPI_BOOT_DEVICE_ENCLOSURE_SLOT EnclosureSlot;
1176 } MPI_BIOSPAGE2_BOOT_DEVICE, MPI_POINTER PTR_MPI_BIOSPAGE2_BOOT_DEVICE;
1177
1178 typedef struct _CONFIG_PAGE_BIOS_2
1179 {
1180 CONFIG_PAGE_HEADER Header; /* 00h */
1181 U32 Reserved1; /* 04h */
1182 U32 Reserved2; /* 08h */
1183 U32 Reserved3; /* 0Ch */
1184 U32 Reserved4; /* 10h */
1185 U32 Reserved5; /* 14h */
1186 U32 Reserved6; /* 18h */
1187 U8 BootDeviceForm; /* 1Ch */
1188 U8 Reserved7; /* 1Dh */
1189 U16 Reserved8; /* 1Eh */
1190 MPI_BIOSPAGE2_BOOT_DEVICE BootDevice; /* 20h */
1191 } CONFIG_PAGE_BIOS_2, MPI_POINTER PTR_CONFIG_PAGE_BIOS_2,
1192 BIOSPage2_t, MPI_POINTER pBIOSPage2_t;
1193
1194 #define MPI_BIOSPAGE2_PAGEVERSION (0x01)
1195
1196 #define MPI_BIOSPAGE2_FORM_MASK (0x0F)
1197 #define MPI_BIOSPAGE2_FORM_ADAPTER_ORDER (0x00)
1198 #define MPI_BIOSPAGE2_FORM_ADAPTER_NUMBER (0x01)
1199 #define MPI_BIOSPAGE2_FORM_PCI_ADDRESS (0x02)
1200 #define MPI_BIOSPAGE2_FORM_PCI_SLOT_NUMBER (0x03)
1201 #define MPI_BIOSPAGE2_FORM_FC_WWN (0x04)
1202 #define MPI_BIOSPAGE2_FORM_SAS_WWN (0x05)
1203 #define MPI_BIOSPAGE2_FORM_ENCLOSURE_SLOT (0x06)
1204
1205
1206 /****************************************************************************
1207 * SCSI Port Config Pages
1208 ****************************************************************************/
1209
1210 typedef struct _CONFIG_PAGE_SCSI_PORT_0
1211 {
1212 CONFIG_PAGE_HEADER Header; /* 00h */
1213 U32 Capabilities; /* 04h */
1214 U32 PhysicalInterface; /* 08h */
1215 } CONFIG_PAGE_SCSI_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_0,
1216 SCSIPortPage0_t, MPI_POINTER pSCSIPortPage0_t;
1217
1218 #define MPI_SCSIPORTPAGE0_PAGEVERSION (0x02)
1219
1220 #define MPI_SCSIPORTPAGE0_CAP_IU (0x00000001)
1221 #define MPI_SCSIPORTPAGE0_CAP_DT (0x00000002)
1222 #define MPI_SCSIPORTPAGE0_CAP_QAS (0x00000004)
1223 #define MPI_SCSIPORTPAGE0_CAP_MIN_SYNC_PERIOD_MASK (0x0000FF00)
1224 #define MPI_SCSIPORTPAGE0_SYNC_ASYNC (0x00)
1225 #define MPI_SCSIPORTPAGE0_SYNC_5 (0x32)
1226 #define MPI_SCSIPORTPAGE0_SYNC_10 (0x19)
1227 #define MPI_SCSIPORTPAGE0_SYNC_20 (0x0C)
1228 #define MPI_SCSIPORTPAGE0_SYNC_33_33 (0x0B)
1229 #define MPI_SCSIPORTPAGE0_SYNC_40 (0x0A)
1230 #define MPI_SCSIPORTPAGE0_SYNC_80 (0x09)
1231 #define MPI_SCSIPORTPAGE0_SYNC_160 (0x08)
1232 #define MPI_SCSIPORTPAGE0_SYNC_UNKNOWN (0xFF)
1233
1234 #define MPI_SCSIPORTPAGE0_CAP_SHIFT_MIN_SYNC_PERIOD (8)
1235 #define MPI_SCSIPORTPAGE0_CAP_GET_MIN_SYNC_PERIOD(Cap) \
1236 ( ((Cap) & MPI_SCSIPORTPAGE0_CAP_MASK_MIN_SYNC_PERIOD) \
1237 >> MPI_SCSIPORTPAGE0_CAP_SHIFT_MIN_SYNC_PERIOD \
1238 )
1239 #define MPI_SCSIPORTPAGE0_CAP_MAX_SYNC_OFFSET_MASK (0x00FF0000)
1240 #define MPI_SCSIPORTPAGE0_CAP_SHIFT_MAX_SYNC_OFFSET (16)
1241 #define MPI_SCSIPORTPAGE0_CAP_GET_MAX_SYNC_OFFSET(Cap) \
1242 ( ((Cap) & MPI_SCSIPORTPAGE0_CAP_MASK_MAX_SYNC_OFFSET) \
1243 >> MPI_SCSIPORTPAGE0_CAP_SHIFT_MAX_SYNC_OFFSET \
1244 )
1245 #define MPI_SCSIPORTPAGE0_CAP_IDP (0x08000000)
1246 #define MPI_SCSIPORTPAGE0_CAP_WIDE (0x20000000)
1247 #define MPI_SCSIPORTPAGE0_CAP_AIP (0x80000000)
1248
1249 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_TYPE_MASK (0x00000003)
1250 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_HVD (0x01)
1251 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_SE (0x02)
1252 #define MPI_SCSIPORTPAGE0_PHY_SIGNAL_LVD (0x03)
1253 #define MPI_SCSIPORTPAGE0_PHY_MASK_CONNECTED_ID (0xFF000000)
1254 #define MPI_SCSIPORTPAGE0_PHY_SHIFT_CONNECTED_ID (24)
1255 #define MPI_SCSIPORTPAGE0_PHY_BUS_FREE_CONNECTED_ID (0xFE)
1256 #define MPI_SCSIPORTPAGE0_PHY_UNKNOWN_CONNECTED_ID (0xFF)
1257
1258
1259 typedef struct _CONFIG_PAGE_SCSI_PORT_1
1260 {
1261 CONFIG_PAGE_HEADER Header; /* 00h */
1262 U32 Configuration; /* 04h */
1263 U32 OnBusTimerValue; /* 08h */
1264 U8 TargetConfig; /* 0Ch */
1265 U8 Reserved1; /* 0Dh */
1266 U16 IDConfig; /* 0Eh */
1267 } CONFIG_PAGE_SCSI_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_1,
1268 SCSIPortPage1_t, MPI_POINTER pSCSIPortPage1_t;
1269
1270 #define MPI_SCSIPORTPAGE1_PAGEVERSION (0x03)
1271
1272 /* Configuration values */
1273 #define MPI_SCSIPORTPAGE1_CFG_PORT_SCSI_ID_MASK (0x000000FF)
1274 #define MPI_SCSIPORTPAGE1_CFG_PORT_RESPONSE_ID_MASK (0xFFFF0000)
1275 #define MPI_SCSIPORTPAGE1_CFG_SHIFT_PORT_RESPONSE_ID (16)
1276
1277 /* TargetConfig values */
1278 #define MPI_SCSIPORTPAGE1_TARGCONFIG_TARG_ONLY (0x01)
1279 #define MPI_SCSIPORTPAGE1_TARGCONFIG_INIT_TARG (0x02)
1280
1281
1282 typedef struct _MPI_DEVICE_INFO
1283 {
1284 U8 Timeout; /* 00h */
1285 U8 SyncFactor; /* 01h */
1286 U16 DeviceFlags; /* 02h */
1287 } MPI_DEVICE_INFO, MPI_POINTER PTR_MPI_DEVICE_INFO,
1288 MpiDeviceInfo_t, MPI_POINTER pMpiDeviceInfo_t;
1289
1290 typedef struct _CONFIG_PAGE_SCSI_PORT_2
1291 {
1292 CONFIG_PAGE_HEADER Header; /* 00h */
1293 U32 PortFlags; /* 04h */
1294 U32 PortSettings; /* 08h */
1295 MPI_DEVICE_INFO DeviceSettings[16]; /* 0Ch */
1296 } CONFIG_PAGE_SCSI_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_PORT_2,
1297 SCSIPortPage2_t, MPI_POINTER pSCSIPortPage2_t;
1298
1299 #define MPI_SCSIPORTPAGE2_PAGEVERSION (0x02)
1300
1301 /* PortFlags values */
1302 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_SCAN_HIGH_TO_LOW (0x00000001)
1303 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_AVOID_SCSI_RESET (0x00000004)
1304 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_ALTERNATE_CHS (0x00000008)
1305 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_TERMINATION_DISABLE (0x00000010)
1306
1307 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_DV_MASK (0x00000060)
1308 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_FULL_DV (0x00000000)
1309 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_BASIC_DV_ONLY (0x00000020)
1310 #define MPI_SCSIPORTPAGE2_PORT_FLAGS_OFF_DV (0x00000060)
1311
1312
1313 /* PortSettings values */
1314 #define MPI_SCSIPORTPAGE2_PORT_HOST_ID_MASK (0x0000000F)
1315 #define MPI_SCSIPORTPAGE2_PORT_MASK_INIT_HBA (0x00000030)
1316 #define MPI_SCSIPORTPAGE2_PORT_DISABLE_INIT_HBA (0x00000000)
1317 #define MPI_SCSIPORTPAGE2_PORT_BIOS_INIT_HBA (0x00000010)
1318 #define MPI_SCSIPORTPAGE2_PORT_OS_INIT_HBA (0x00000020)
1319 #define MPI_SCSIPORTPAGE2_PORT_BIOS_OS_INIT_HBA (0x00000030)
1320 #define MPI_SCSIPORTPAGE2_PORT_REMOVABLE_MEDIA (0x000000C0)
1321 #define MPI_SCSIPORTPAGE2_PORT_RM_NONE (0x00000000)
1322 #define MPI_SCSIPORTPAGE2_PORT_RM_BOOT_ONLY (0x00000040)
1323 #define MPI_SCSIPORTPAGE2_PORT_RM_WITH_MEDIA (0x00000080)
1324 #define MPI_SCSIPORTPAGE2_PORT_SPINUP_DELAY_MASK (0x00000F00)
1325 #define MPI_SCSIPORTPAGE2_PORT_SHIFT_SPINUP_DELAY (8)
1326 #define MPI_SCSIPORTPAGE2_PORT_MASK_NEGO_MASTER_SETTINGS (0x00003000)
1327 #define MPI_SCSIPORTPAGE2_PORT_NEGO_MASTER_SETTINGS (0x00000000)
1328 #define MPI_SCSIPORTPAGE2_PORT_NONE_MASTER_SETTINGS (0x00001000)
1329 #define MPI_SCSIPORTPAGE2_PORT_ALL_MASTER_SETTINGS (0x00003000)
1330
1331 #define MPI_SCSIPORTPAGE2_DEVICE_DISCONNECT_ENABLE (0x0001)
1332 #define MPI_SCSIPORTPAGE2_DEVICE_ID_SCAN_ENABLE (0x0002)
1333 #define MPI_SCSIPORTPAGE2_DEVICE_LUN_SCAN_ENABLE (0x0004)
1334 #define MPI_SCSIPORTPAGE2_DEVICE_TAG_QUEUE_ENABLE (0x0008)
1335 #define MPI_SCSIPORTPAGE2_DEVICE_WIDE_DISABLE (0x0010)
1336 #define MPI_SCSIPORTPAGE2_DEVICE_BOOT_CHOICE (0x0020)
1337
1338
1339 /****************************************************************************
1340 * SCSI Target Device Config Pages
1341 ****************************************************************************/
1342
1343 typedef struct _CONFIG_PAGE_SCSI_DEVICE_0
1344 {
1345 CONFIG_PAGE_HEADER Header; /* 00h */
1346 U32 NegotiatedParameters; /* 04h */
1347 U32 Information; /* 08h */
1348 } CONFIG_PAGE_SCSI_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_0,
1349 SCSIDevicePage0_t, MPI_POINTER pSCSIDevicePage0_t;
1350
1351 #define MPI_SCSIDEVPAGE0_PAGEVERSION (0x04)
1352
1353 #define MPI_SCSIDEVPAGE0_NP_IU (0x00000001)
1354 #define MPI_SCSIDEVPAGE0_NP_DT (0x00000002)
1355 #define MPI_SCSIDEVPAGE0_NP_QAS (0x00000004)
1356 #define MPI_SCSIDEVPAGE0_NP_HOLD_MCS (0x00000008)
1357 #define MPI_SCSIDEVPAGE0_NP_WR_FLOW (0x00000010)
1358 #define MPI_SCSIDEVPAGE0_NP_RD_STRM (0x00000020)
1359 #define MPI_SCSIDEVPAGE0_NP_RTI (0x00000040)
1360 #define MPI_SCSIDEVPAGE0_NP_PCOMP_EN (0x00000080)
1361 #define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_PERIOD_MASK (0x0000FF00)
1362 #define MPI_SCSIDEVPAGE0_NP_SHIFT_SYNC_PERIOD (8)
1363 #define MPI_SCSIDEVPAGE0_NP_NEG_SYNC_OFFSET_MASK (0x00FF0000)
1364 #define MPI_SCSIDEVPAGE0_NP_SHIFT_SYNC_OFFSET (16)
1365 #define MPI_SCSIDEVPAGE0_NP_IDP (0x08000000)
1366 #define MPI_SCSIDEVPAGE0_NP_WIDE (0x20000000)
1367 #define MPI_SCSIDEVPAGE0_NP_AIP (0x80000000)
1368
1369 #define MPI_SCSIDEVPAGE0_INFO_PARAMS_NEGOTIATED (0x00000001)
1370 #define MPI_SCSIDEVPAGE0_INFO_SDTR_REJECTED (0x00000002)
1371 #define MPI_SCSIDEVPAGE0_INFO_WDTR_REJECTED (0x00000004)
1372 #define MPI_SCSIDEVPAGE0_INFO_PPR_REJECTED (0x00000008)
1373
1374
1375 typedef struct _CONFIG_PAGE_SCSI_DEVICE_1
1376 {
1377 CONFIG_PAGE_HEADER Header; /* 00h */
1378 U32 RequestedParameters; /* 04h */
1379 U32 Reserved; /* 08h */
1380 U32 Configuration; /* 0Ch */
1381 } CONFIG_PAGE_SCSI_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_1,
1382 SCSIDevicePage1_t, MPI_POINTER pSCSIDevicePage1_t;
1383
1384 #define MPI_SCSIDEVPAGE1_PAGEVERSION (0x05)
1385
1386 #define MPI_SCSIDEVPAGE1_RP_IU (0x00000001)
1387 #define MPI_SCSIDEVPAGE1_RP_DT (0x00000002)
1388 #define MPI_SCSIDEVPAGE1_RP_QAS (0x00000004)
1389 #define MPI_SCSIDEVPAGE1_RP_HOLD_MCS (0x00000008)
1390 #define MPI_SCSIDEVPAGE1_RP_WR_FLOW (0x00000010)
1391 #define MPI_SCSIDEVPAGE1_RP_RD_STRM (0x00000020)
1392 #define MPI_SCSIDEVPAGE1_RP_RTI (0x00000040)
1393 #define MPI_SCSIDEVPAGE1_RP_PCOMP_EN (0x00000080)
1394 #define MPI_SCSIDEVPAGE1_RP_MIN_SYNC_PERIOD_MASK (0x0000FF00)
1395 #define MPI_SCSIDEVPAGE1_RP_SHIFT_MIN_SYNC_PERIOD (8)
1396 #define MPI_SCSIDEVPAGE1_RP_MAX_SYNC_OFFSET_MASK (0x00FF0000)
1397 #define MPI_SCSIDEVPAGE1_RP_SHIFT_MAX_SYNC_OFFSET (16)
1398 #define MPI_SCSIDEVPAGE1_RP_IDP (0x08000000)
1399 #define MPI_SCSIDEVPAGE1_RP_WIDE (0x20000000)
1400 #define MPI_SCSIDEVPAGE1_RP_AIP (0x80000000)
1401
1402 #define MPI_SCSIDEVPAGE1_CONF_WDTR_DISALLOWED (0x00000002)
1403 #define MPI_SCSIDEVPAGE1_CONF_SDTR_DISALLOWED (0x00000004)
1404 #define MPI_SCSIDEVPAGE1_CONF_EXTENDED_PARAMS_ENABLE (0x00000008)
1405 #define MPI_SCSIDEVPAGE1_CONF_FORCE_PPR_MSG (0x00000010)
1406
1407
1408 typedef struct _CONFIG_PAGE_SCSI_DEVICE_2
1409 {
1410 CONFIG_PAGE_HEADER Header; /* 00h */
1411 U32 DomainValidation; /* 04h */
1412 U32 ParityPipeSelect; /* 08h */
1413 U32 DataPipeSelect; /* 0Ch */
1414 } CONFIG_PAGE_SCSI_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_2,
1415 SCSIDevicePage2_t, MPI_POINTER pSCSIDevicePage2_t;
1416
1417 #define MPI_SCSIDEVPAGE2_PAGEVERSION (0x01)
1418
1419 #define MPI_SCSIDEVPAGE2_DV_ISI_ENABLE (0x00000010)
1420 #define MPI_SCSIDEVPAGE2_DV_SECONDARY_DRIVER_ENABLE (0x00000020)
1421 #define MPI_SCSIDEVPAGE2_DV_SLEW_RATE_CTRL (0x00000380)
1422 #define MPI_SCSIDEVPAGE2_DV_PRIM_DRIVE_STR_CTRL (0x00001C00)
1423 #define MPI_SCSIDEVPAGE2_DV_SECOND_DRIVE_STR_CTRL (0x0000E000)
1424 #define MPI_SCSIDEVPAGE2_DV_XCLKH_ST (0x10000000)
1425 #define MPI_SCSIDEVPAGE2_DV_XCLKS_ST (0x20000000)
1426 #define MPI_SCSIDEVPAGE2_DV_XCLKH_DT (0x40000000)
1427 #define MPI_SCSIDEVPAGE2_DV_XCLKS_DT (0x80000000)
1428
1429 #define MPI_SCSIDEVPAGE2_PPS_PPS_MASK (0x00000003)
1430
1431 #define MPI_SCSIDEVPAGE2_DPS_BIT_0_PL_SELECT_MASK (0x00000003)
1432 #define MPI_SCSIDEVPAGE2_DPS_BIT_1_PL_SELECT_MASK (0x0000000C)
1433 #define MPI_SCSIDEVPAGE2_DPS_BIT_2_PL_SELECT_MASK (0x00000030)
1434 #define MPI_SCSIDEVPAGE2_DPS_BIT_3_PL_SELECT_MASK (0x000000C0)
1435 #define MPI_SCSIDEVPAGE2_DPS_BIT_4_PL_SELECT_MASK (0x00000300)
1436 #define MPI_SCSIDEVPAGE2_DPS_BIT_5_PL_SELECT_MASK (0x00000C00)
1437 #define MPI_SCSIDEVPAGE2_DPS_BIT_6_PL_SELECT_MASK (0x00003000)
1438 #define MPI_SCSIDEVPAGE2_DPS_BIT_7_PL_SELECT_MASK (0x0000C000)
1439 #define MPI_SCSIDEVPAGE2_DPS_BIT_8_PL_SELECT_MASK (0x00030000)
1440 #define MPI_SCSIDEVPAGE2_DPS_BIT_9_PL_SELECT_MASK (0x000C0000)
1441 #define MPI_SCSIDEVPAGE2_DPS_BIT_10_PL_SELECT_MASK (0x00300000)
1442 #define MPI_SCSIDEVPAGE2_DPS_BIT_11_PL_SELECT_MASK (0x00C00000)
1443 #define MPI_SCSIDEVPAGE2_DPS_BIT_12_PL_SELECT_MASK (0x03000000)
1444 #define MPI_SCSIDEVPAGE2_DPS_BIT_13_PL_SELECT_MASK (0x0C000000)
1445 #define MPI_SCSIDEVPAGE2_DPS_BIT_14_PL_SELECT_MASK (0x30000000)
1446 #define MPI_SCSIDEVPAGE2_DPS_BIT_15_PL_SELECT_MASK (0xC0000000)
1447
1448
1449 typedef struct _CONFIG_PAGE_SCSI_DEVICE_3
1450 {
1451 CONFIG_PAGE_HEADER Header; /* 00h */
1452 U16 MsgRejectCount; /* 04h */
1453 U16 PhaseErrorCount; /* 06h */
1454 U16 ParityErrorCount; /* 08h */
1455 U16 Reserved; /* 0Ah */
1456 } CONFIG_PAGE_SCSI_DEVICE_3, MPI_POINTER PTR_CONFIG_PAGE_SCSI_DEVICE_3,
1457 SCSIDevicePage3_t, MPI_POINTER pSCSIDevicePage3_t;
1458
1459 #define MPI_SCSIDEVPAGE3_PAGEVERSION (0x00)
1460
1461 #define MPI_SCSIDEVPAGE3_MAX_COUNTER (0xFFFE)
1462 #define MPI_SCSIDEVPAGE3_UNSUPPORTED_COUNTER (0xFFFF)
1463
1464
1465 /****************************************************************************
1466 * FC Port Config Pages
1467 ****************************************************************************/
1468
1469 typedef struct _CONFIG_PAGE_FC_PORT_0
1470 {
1471 CONFIG_PAGE_HEADER Header; /* 00h */
1472 U32 Flags; /* 04h */
1473 U8 MPIPortNumber; /* 08h */
1474 U8 LinkType; /* 09h */
1475 U8 PortState; /* 0Ah */
1476 U8 Reserved; /* 0Bh */
1477 U32 PortIdentifier; /* 0Ch */
1478 U64 WWNN; /* 10h */
1479 U64 WWPN; /* 18h */
1480 U32 SupportedServiceClass; /* 20h */
1481 U32 SupportedSpeeds; /* 24h */
1482 U32 CurrentSpeed; /* 28h */
1483 U32 MaxFrameSize; /* 2Ch */
1484 U64 FabricWWNN; /* 30h */
1485 U64 FabricWWPN; /* 38h */
1486 U32 DiscoveredPortsCount; /* 40h */
1487 U32 MaxInitiators; /* 44h */
1488 U8 MaxAliasesSupported; /* 48h */
1489 U8 MaxHardAliasesSupported; /* 49h */
1490 U8 NumCurrentAliases; /* 4Ah */
1491 U8 Reserved1; /* 4Bh */
1492 } CONFIG_PAGE_FC_PORT_0, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_0,
1493 FCPortPage0_t, MPI_POINTER pFCPortPage0_t;
1494
1495 #define MPI_FCPORTPAGE0_PAGEVERSION (0x02)
1496
1497 #define MPI_FCPORTPAGE0_FLAGS_PROT_MASK (0x0000000F)
1498 #define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_INIT (MPI_PORTFACTS_PROTOCOL_INITIATOR)
1499 #define MPI_FCPORTPAGE0_FLAGS_PROT_FCP_TARG (MPI_PORTFACTS_PROTOCOL_TARGET)
1500 #define MPI_FCPORTPAGE0_FLAGS_PROT_LAN (MPI_PORTFACTS_PROTOCOL_LAN)
1501 #define MPI_FCPORTPAGE0_FLAGS_PROT_LOGBUSADDR (MPI_PORTFACTS_PROTOCOL_LOGBUSADDR)
1502
1503 #define MPI_FCPORTPAGE0_FLAGS_ALIAS_ALPA_SUPPORTED (0x00000010)
1504 #define MPI_FCPORTPAGE0_FLAGS_ALIAS_WWN_SUPPORTED (0x00000020)
1505 #define MPI_FCPORTPAGE0_FLAGS_FABRIC_WWN_VALID (0x00000040)
1506
1507 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_TYPE_MASK (0x00000F00)
1508 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_NO_INIT (0x00000000)
1509 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_POINT_TO_POINT (0x00000100)
1510 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_PRIVATE_LOOP (0x00000200)
1511 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_FABRIC_DIRECT (0x00000400)
1512 #define MPI_FCPORTPAGE0_FLAGS_ATTACH_PUBLIC_LOOP (0x00000800)
1513
1514 #define MPI_FCPORTPAGE0_LTYPE_RESERVED (0x00)
1515 #define MPI_FCPORTPAGE0_LTYPE_OTHER (0x01)
1516 #define MPI_FCPORTPAGE0_LTYPE_UNKNOWN (0x02)
1517 #define MPI_FCPORTPAGE0_LTYPE_COPPER (0x03)
1518 #define MPI_FCPORTPAGE0_LTYPE_SINGLE_1300 (0x04)
1519 #define MPI_FCPORTPAGE0_LTYPE_SINGLE_1500 (0x05)
1520 #define MPI_FCPORTPAGE0_LTYPE_50_LASER_MULTI (0x06)
1521 #define MPI_FCPORTPAGE0_LTYPE_50_LED_MULTI (0x07)
1522 #define MPI_FCPORTPAGE0_LTYPE_62_LASER_MULTI (0x08)
1523 #define MPI_FCPORTPAGE0_LTYPE_62_LED_MULTI (0x09)
1524 #define MPI_FCPORTPAGE0_LTYPE_MULTI_LONG_WAVE (0x0A)
1525 #define MPI_FCPORTPAGE0_LTYPE_MULTI_SHORT_WAVE (0x0B)
1526 #define MPI_FCPORTPAGE0_LTYPE_LASER_SHORT_WAVE (0x0C)
1527 #define MPI_FCPORTPAGE0_LTYPE_LED_SHORT_WAVE (0x0D)
1528 #define MPI_FCPORTPAGE0_LTYPE_1300_LONG_WAVE (0x0E)
1529 #define MPI_FCPORTPAGE0_LTYPE_1500_LONG_WAVE (0x0F)
1530
1531 #define MPI_FCPORTPAGE0_PORTSTATE_UNKNOWN (0x01) /*(SNIA)HBA_PORTSTATE_UNKNOWN 1 Unknown */
1532 #define MPI_FCPORTPAGE0_PORTSTATE_ONLINE (0x02) /*(SNIA)HBA_PORTSTATE_ONLINE 2 Operational */
1533 #define MPI_FCPORTPAGE0_PORTSTATE_OFFLINE (0x03) /*(SNIA)HBA_PORTSTATE_OFFLINE 3 User Offline */
1534 #define MPI_FCPORTPAGE0_PORTSTATE_BYPASSED (0x04) /*(SNIA)HBA_PORTSTATE_BYPASSED 4 Bypassed */
1535 #define MPI_FCPORTPAGE0_PORTSTATE_DIAGNOST (0x05) /*(SNIA)HBA_PORTSTATE_DIAGNOSTICS 5 In diagnostics mode */
1536 #define MPI_FCPORTPAGE0_PORTSTATE_LINKDOWN (0x06) /*(SNIA)HBA_PORTSTATE_LINKDOWN 6 Link Down */
1537 #define MPI_FCPORTPAGE0_PORTSTATE_ERROR (0x07) /*(SNIA)HBA_PORTSTATE_ERROR 7 Port Error */
1538 #define MPI_FCPORTPAGE0_PORTSTATE_LOOPBACK (0x08) /*(SNIA)HBA_PORTSTATE_LOOPBACK 8 Loopback */
1539
1540 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_1 (0x00000001)
1541 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_2 (0x00000002)
1542 #define MPI_FCPORTPAGE0_SUPPORT_CLASS_3 (0x00000004)
1543
1544 #define MPI_FCPORTPAGE0_SUPPORT_SPEED_UKNOWN (0x00000000) /* (SNIA)HBA_PORTSPEED_UNKNOWN 0 Unknown - transceiver incapable of reporting */
1545 #define MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED (0x00000001) /* (SNIA)HBA_PORTSPEED_1GBIT 1 1 GBit/sec */
1546 #define MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED (0x00000002) /* (SNIA)HBA_PORTSPEED_2GBIT 2 2 GBit/sec */
1547 #define MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED (0x00000004) /* (SNIA)HBA_PORTSPEED_10GBIT 4 10 GBit/sec */
1548 #define MPI_FCPORTPAGE0_SUPPORT_4GBIT_SPEED (0x00000008) /* (SNIA)HBA_PORTSPEED_4GBIT 8 4 GBit/sec */
1549
1550 #define MPI_FCPORTPAGE0_CURRENT_SPEED_UKNOWN MPI_FCPORTPAGE0_SUPPORT_SPEED_UKNOWN
1551 #define MPI_FCPORTPAGE0_CURRENT_SPEED_1GBIT MPI_FCPORTPAGE0_SUPPORT_1GBIT_SPEED
1552 #define MPI_FCPORTPAGE0_CURRENT_SPEED_2GBIT MPI_FCPORTPAGE0_SUPPORT_2GBIT_SPEED
1553 #define MPI_FCPORTPAGE0_CURRENT_SPEED_10GBIT MPI_FCPORTPAGE0_SUPPORT_10GBIT_SPEED
1554 #define MPI_FCPORTPAGE0_CURRENT_SPEED_4GBIT MPI_FCPORTPAGE0_SUPPORT_4GBIT_SPEED
1555 #define MPI_FCPORTPAGE0_CURRENT_SPEED_NOT_NEGOTIATED (0x00008000) /* (SNIA)HBA_PORTSPEED_NOT_NEGOTIATED (1<<15) Speed not established */
1556
1557
1558 typedef struct _CONFIG_PAGE_FC_PORT_1
1559 {
1560 CONFIG_PAGE_HEADER Header; /* 00h */
1561 U32 Flags; /* 04h */
1562 U64 NoSEEPROMWWNN; /* 08h */
1563 U64 NoSEEPROMWWPN; /* 10h */
1564 U8 HardALPA; /* 18h */
1565 U8 LinkConfig; /* 19h */
1566 U8 TopologyConfig; /* 1Ah */
1567 U8 AltConnector; /* 1Bh */
1568 U8 NumRequestedAliases; /* 1Ch */
1569 U8 RR_TOV; /* 1Dh */
1570 U8 InitiatorDeviceTimeout; /* 1Eh */
1571 U8 InitiatorIoPendTimeout; /* 1Fh */
1572 } CONFIG_PAGE_FC_PORT_1, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_1,
1573 FCPortPage1_t, MPI_POINTER pFCPortPage1_t;
1574
1575 #define MPI_FCPORTPAGE1_PAGEVERSION (0x06)
1576
1577 #define MPI_FCPORTPAGE1_FLAGS_EXT_FCP_STATUS_EN (0x08000000)
1578 #define MPI_FCPORTPAGE1_FLAGS_IMMEDIATE_ERROR_REPLY (0x04000000)
1579 #define MPI_FCPORTPAGE1_FLAGS_FORCE_USE_NOSEEPROM_WWNS (0x02000000)
1580 #define MPI_FCPORTPAGE1_FLAGS_VERBOSE_RESCAN_EVENTS (0x01000000)
1581 #define MPI_FCPORTPAGE1_FLAGS_TARGET_MODE_OXID (0x00800000)
1582 #define MPI_FCPORTPAGE1_FLAGS_PORT_OFFLINE (0x00400000)
1583 #define MPI_FCPORTPAGE1_FLAGS_SOFT_ALPA_FALLBACK (0x00200000)
1584 #define MPI_FCPORTPAGE1_FLAGS_TARGET_LARGE_CDB_ENABLE (0x00000080)
1585 #define MPI_FCPORTPAGE1_FLAGS_MASK_RR_TOV_UNITS (0x00000070)
1586 #define MPI_FCPORTPAGE1_FLAGS_SUPPRESS_PROT_REG (0x00000008)
1587 #define MPI_FCPORTPAGE1_FLAGS_PLOGI_ON_LOGO (0x00000004)
1588 #define MPI_FCPORTPAGE1_FLAGS_MAINTAIN_LOGINS (0x00000002)
1589 #define MPI_FCPORTPAGE1_FLAGS_SORT_BY_DID (0x00000001)
1590 #define MPI_FCPORTPAGE1_FLAGS_SORT_BY_WWN (0x00000000)
1591
1592 #define MPI_FCPORTPAGE1_FLAGS_PROT_MASK (0xF0000000)
1593 #define MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT (28)
1594 #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_INIT ((U32)MPI_PORTFACTS_PROTOCOL_INITIATOR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1595 #define MPI_FCPORTPAGE1_FLAGS_PROT_FCP_TARG ((U32)MPI_PORTFACTS_PROTOCOL_TARGET << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1596 #define MPI_FCPORTPAGE1_FLAGS_PROT_LAN ((U32)MPI_PORTFACTS_PROTOCOL_LAN << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1597 #define MPI_FCPORTPAGE1_FLAGS_PROT_LOGBUSADDR ((U32)MPI_PORTFACTS_PROTOCOL_LOGBUSADDR << MPI_FCPORTPAGE1_FLAGS_PROT_SHIFT)
1598
1599 #define MPI_FCPORTPAGE1_FLAGS_NONE_RR_TOV_UNITS (0x00000000)
1600 #define MPI_FCPORTPAGE1_FLAGS_THOUSANDTH_RR_TOV_UNITS (0x00000010)
1601 #define MPI_FCPORTPAGE1_FLAGS_TENTH_RR_TOV_UNITS (0x00000030)
1602 #define MPI_FCPORTPAGE1_FLAGS_TEN_RR_TOV_UNITS (0x00000050)
1603
1604 #define MPI_FCPORTPAGE1_HARD_ALPA_NOT_USED (0xFF)
1605
1606 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_MASK (0x0F)
1607 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_1GIG (0x00)
1608 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_2GIG (0x01)
1609 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_4GIG (0x02)
1610 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_10GIG (0x03)
1611 #define MPI_FCPORTPAGE1_LCONFIG_SPEED_AUTO (0x0F)
1612
1613 #define MPI_FCPORTPAGE1_TOPOLOGY_MASK (0x0F)
1614 #define MPI_FCPORTPAGE1_TOPOLOGY_NLPORT (0x01)
1615 #define MPI_FCPORTPAGE1_TOPOLOGY_NPORT (0x02)
1616 #define MPI_FCPORTPAGE1_TOPOLOGY_AUTO (0x0F)
1617
1618 #define MPI_FCPORTPAGE1_ALT_CONN_UNKNOWN (0x00)
1619
1620 #define MPI_FCPORTPAGE1_INITIATOR_DEV_TIMEOUT_MASK (0x7F)
1621 #define MPI_FCPORTPAGE1_INITIATOR_DEV_UNIT_16 (0x80)
1622
1623
1624 typedef struct _CONFIG_PAGE_FC_PORT_2
1625 {
1626 CONFIG_PAGE_HEADER Header; /* 00h */
1627 U8 NumberActive; /* 04h */
1628 U8 ALPA[127]; /* 05h */
1629 } CONFIG_PAGE_FC_PORT_2, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_2,
1630 FCPortPage2_t, MPI_POINTER pFCPortPage2_t;
1631
1632 #define MPI_FCPORTPAGE2_PAGEVERSION (0x01)
1633
1634
1635 typedef struct _WWN_FORMAT
1636 {
1637 U64 WWNN; /* 00h */
1638 U64 WWPN; /* 08h */
1639 } WWN_FORMAT, MPI_POINTER PTR_WWN_FORMAT,
1640 WWNFormat, MPI_POINTER pWWNFormat;
1641
1642 typedef union _FC_PORT_PERSISTENT_PHYSICAL_ID
1643 {
1644 WWN_FORMAT WWN;
1645 U32 Did;
1646 } FC_PORT_PERSISTENT_PHYSICAL_ID, MPI_POINTER PTR_FC_PORT_PERSISTENT_PHYSICAL_ID,
1647 PersistentPhysicalId_t, MPI_POINTER pPersistentPhysicalId_t;
1648
1649 typedef struct _FC_PORT_PERSISTENT
1650 {
1651 FC_PORT_PERSISTENT_PHYSICAL_ID PhysicalIdentifier; /* 00h */
1652 U8 TargetID; /* 10h */
1653 U8 Bus; /* 11h */
1654 U16 Flags; /* 12h */
1655 } FC_PORT_PERSISTENT, MPI_POINTER PTR_FC_PORT_PERSISTENT,
1656 PersistentData_t, MPI_POINTER pPersistentData_t;
1657
1658 #define MPI_PERSISTENT_FLAGS_SHIFT (16)
1659 #define MPI_PERSISTENT_FLAGS_ENTRY_VALID (0x0001)
1660 #define MPI_PERSISTENT_FLAGS_SCAN_ID (0x0002)
1661 #define MPI_PERSISTENT_FLAGS_SCAN_LUNS (0x0004)
1662 #define MPI_PERSISTENT_FLAGS_BOOT_DEVICE (0x0008)
1663 #define MPI_PERSISTENT_FLAGS_BY_DID (0x0080)
1664
1665 /*
1666 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
1667 * one and check Header.PageLength at runtime.
1668 */
1669 #ifndef MPI_FC_PORT_PAGE_3_ENTRY_MAX
1670 #define MPI_FC_PORT_PAGE_3_ENTRY_MAX (1)
1671 #endif
1672
1673 typedef struct _CONFIG_PAGE_FC_PORT_3
1674 {
1675 CONFIG_PAGE_HEADER Header; /* 00h */
1676 FC_PORT_PERSISTENT Entry[MPI_FC_PORT_PAGE_3_ENTRY_MAX]; /* 04h */
1677 } CONFIG_PAGE_FC_PORT_3, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_3,
1678 FCPortPage3_t, MPI_POINTER pFCPortPage3_t;
1679
1680 #define MPI_FCPORTPAGE3_PAGEVERSION (0x01)
1681
1682
1683 typedef struct _CONFIG_PAGE_FC_PORT_4
1684 {
1685 CONFIG_PAGE_HEADER Header; /* 00h */
1686 U32 PortFlags; /* 04h */
1687 U32 PortSettings; /* 08h */
1688 } CONFIG_PAGE_FC_PORT_4, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_4,
1689 FCPortPage4_t, MPI_POINTER pFCPortPage4_t;
1690
1691 #define MPI_FCPORTPAGE4_PAGEVERSION (0x00)
1692
1693 #define MPI_FCPORTPAGE4_PORT_FLAGS_ALTERNATE_CHS (0x00000008)
1694
1695 #define MPI_FCPORTPAGE4_PORT_MASK_INIT_HBA (0x00000030)
1696 #define MPI_FCPORTPAGE4_PORT_DISABLE_INIT_HBA (0x00000000)
1697 #define MPI_FCPORTPAGE4_PORT_BIOS_INIT_HBA (0x00000010)
1698 #define MPI_FCPORTPAGE4_PORT_OS_INIT_HBA (0x00000020)
1699 #define MPI_FCPORTPAGE4_PORT_BIOS_OS_INIT_HBA (0x00000030)
1700 #define MPI_FCPORTPAGE4_PORT_REMOVABLE_MEDIA (0x000000C0)
1701 #define MPI_FCPORTPAGE4_PORT_SPINUP_DELAY_MASK (0x00000F00)
1702
1703
1704 typedef struct _CONFIG_PAGE_FC_PORT_5_ALIAS_INFO
1705 {
1706 U8 Flags; /* 00h */
1707 U8 AliasAlpa; /* 01h */
1708 U16 Reserved; /* 02h */
1709 U64 AliasWWNN; /* 04h */
1710 U64 AliasWWPN; /* 0Ch */
1711 } CONFIG_PAGE_FC_PORT_5_ALIAS_INFO,
1712 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5_ALIAS_INFO,
1713 FcPortPage5AliasInfo_t, MPI_POINTER pFcPortPage5AliasInfo_t;
1714
1715 typedef struct _CONFIG_PAGE_FC_PORT_5
1716 {
1717 CONFIG_PAGE_HEADER Header; /* 00h */
1718 CONFIG_PAGE_FC_PORT_5_ALIAS_INFO AliasInfo; /* 04h */
1719 } CONFIG_PAGE_FC_PORT_5, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_5,
1720 FCPortPage5_t, MPI_POINTER pFCPortPage5_t;
1721
1722 #define MPI_FCPORTPAGE5_PAGEVERSION (0x02)
1723
1724 #define MPI_FCPORTPAGE5_FLAGS_ALPA_ACQUIRED (0x01)
1725 #define MPI_FCPORTPAGE5_FLAGS_HARD_ALPA (0x02)
1726 #define MPI_FCPORTPAGE5_FLAGS_HARD_WWNN (0x04)
1727 #define MPI_FCPORTPAGE5_FLAGS_HARD_WWPN (0x08)
1728 #define MPI_FCPORTPAGE5_FLAGS_DISABLE (0x10)
1729
1730 typedef struct _CONFIG_PAGE_FC_PORT_6
1731 {
1732 CONFIG_PAGE_HEADER Header; /* 00h */
1733 U32 Reserved; /* 04h */
1734 U64 TimeSinceReset; /* 08h */
1735 U64 TxFrames; /* 10h */
1736 U64 RxFrames; /* 18h */
1737 U64 TxWords; /* 20h */
1738 U64 RxWords; /* 28h */
1739 U64 LipCount; /* 30h */
1740 U64 NosCount; /* 38h */
1741 U64 ErrorFrames; /* 40h */
1742 U64 DumpedFrames; /* 48h */
1743 U64 LinkFailureCount; /* 50h */
1744 U64 LossOfSyncCount; /* 58h */
1745 U64 LossOfSignalCount; /* 60h */
1746 U64 PrimativeSeqErrCount; /* 68h */
1747 U64 InvalidTxWordCount; /* 70h */
1748 U64 InvalidCrcCount; /* 78h */
1749 U64 FcpInitiatorIoCount; /* 80h */
1750 } CONFIG_PAGE_FC_PORT_6, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_6,
1751 FCPortPage6_t, MPI_POINTER pFCPortPage6_t;
1752
1753 #define MPI_FCPORTPAGE6_PAGEVERSION (0x00)
1754
1755
1756 typedef struct _CONFIG_PAGE_FC_PORT_7
1757 {
1758 CONFIG_PAGE_HEADER Header; /* 00h */
1759 U32 Reserved; /* 04h */
1760 U8 PortSymbolicName[256]; /* 08h */
1761 } CONFIG_PAGE_FC_PORT_7, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_7,
1762 FCPortPage7_t, MPI_POINTER pFCPortPage7_t;
1763
1764 #define MPI_FCPORTPAGE7_PAGEVERSION (0x00)
1765
1766
1767 typedef struct _CONFIG_PAGE_FC_PORT_8
1768 {
1769 CONFIG_PAGE_HEADER Header; /* 00h */
1770 U32 BitVector[8]; /* 04h */
1771 } CONFIG_PAGE_FC_PORT_8, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_8,
1772 FCPortPage8_t, MPI_POINTER pFCPortPage8_t;
1773
1774 #define MPI_FCPORTPAGE8_PAGEVERSION (0x00)
1775
1776
1777 typedef struct _CONFIG_PAGE_FC_PORT_9
1778 {
1779 CONFIG_PAGE_HEADER Header; /* 00h */
1780 U32 Reserved; /* 04h */
1781 U64 GlobalWWPN; /* 08h */
1782 U64 GlobalWWNN; /* 10h */
1783 U32 UnitType; /* 18h */
1784 U32 PhysicalPortNumber; /* 1Ch */
1785 U32 NumAttachedNodes; /* 20h */
1786 U16 IPVersion; /* 24h */
1787 U16 UDPPortNumber; /* 26h */
1788 U8 IPAddress[16]; /* 28h */
1789 U16 Reserved1; /* 38h */
1790 U16 TopologyDiscoveryFlags; /* 3Ah */
1791 } CONFIG_PAGE_FC_PORT_9, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_9,
1792 FCPortPage9_t, MPI_POINTER pFCPortPage9_t;
1793
1794 #define MPI_FCPORTPAGE9_PAGEVERSION (0x00)
1795
1796
1797 typedef struct _CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA
1798 {
1799 U8 Id; /* 10h */
1800 U8 ExtId; /* 11h */
1801 U8 Connector; /* 12h */
1802 U8 Transceiver[8]; /* 13h */
1803 U8 Encoding; /* 1Bh */
1804 U8 BitRate_100mbs; /* 1Ch */
1805 U8 Reserved1; /* 1Dh */
1806 U8 Length9u_km; /* 1Eh */
1807 U8 Length9u_100m; /* 1Fh */
1808 U8 Length50u_10m; /* 20h */
1809 U8 Length62p5u_10m; /* 21h */
1810 U8 LengthCopper_m; /* 22h */
1811 U8 Reseverved2; /* 22h */
1812 U8 VendorName[16]; /* 24h */
1813 U8 Reserved3; /* 34h */
1814 U8 VendorOUI[3]; /* 35h */
1815 U8 VendorPN[16]; /* 38h */
1816 U8 VendorRev[4]; /* 48h */
1817 U16 Wavelength; /* 4Ch */
1818 U8 Reserved4; /* 4Eh */
1819 U8 CC_BASE; /* 4Fh */
1820 } CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA,
1821 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA,
1822 FCPortPage10BaseSfpData_t, MPI_POINTER pFCPortPage10BaseSfpData_t;
1823
1824 #define MPI_FCPORT10_BASE_ID_UNKNOWN (0x00)
1825 #define MPI_FCPORT10_BASE_ID_GBIC (0x01)
1826 #define MPI_FCPORT10_BASE_ID_FIXED (0x02)
1827 #define MPI_FCPORT10_BASE_ID_SFP (0x03)
1828 #define MPI_FCPORT10_BASE_ID_SFP_MIN (0x04)
1829 #define MPI_FCPORT10_BASE_ID_SFP_MAX (0x7F)
1830 #define MPI_FCPORT10_BASE_ID_VEND_SPEC_MASK (0x80)
1831
1832 #define MPI_FCPORT10_BASE_EXTID_UNKNOWN (0x00)
1833 #define MPI_FCPORT10_BASE_EXTID_MODDEF1 (0x01)
1834 #define MPI_FCPORT10_BASE_EXTID_MODDEF2 (0x02)
1835 #define MPI_FCPORT10_BASE_EXTID_MODDEF3 (0x03)
1836 #define MPI_FCPORT10_BASE_EXTID_SEEPROM (0x04)
1837 #define MPI_FCPORT10_BASE_EXTID_MODDEF5 (0x05)
1838 #define MPI_FCPORT10_BASE_EXTID_MODDEF6 (0x06)
1839 #define MPI_FCPORT10_BASE_EXTID_MODDEF7 (0x07)
1840 #define MPI_FCPORT10_BASE_EXTID_VNDSPC_MASK (0x80)
1841
1842 #define MPI_FCPORT10_BASE_CONN_UNKNOWN (0x00)
1843 #define MPI_FCPORT10_BASE_CONN_SC (0x01)
1844 #define MPI_FCPORT10_BASE_CONN_COPPER1 (0x02)
1845 #define MPI_FCPORT10_BASE_CONN_COPPER2 (0x03)
1846 #define MPI_FCPORT10_BASE_CONN_BNC_TNC (0x04)
1847 #define MPI_FCPORT10_BASE_CONN_COAXIAL (0x05)
1848 #define MPI_FCPORT10_BASE_CONN_FIBERJACK (0x06)
1849 #define MPI_FCPORT10_BASE_CONN_LC (0x07)
1850 #define MPI_FCPORT10_BASE_CONN_MT_RJ (0x08)
1851 #define MPI_FCPORT10_BASE_CONN_MU (0x09)
1852 #define MPI_FCPORT10_BASE_CONN_SG (0x0A)
1853 #define MPI_FCPORT10_BASE_CONN_OPT_PIGT (0x0B)
1854 #define MPI_FCPORT10_BASE_CONN_RSV1_MIN (0x0C)
1855 #define MPI_FCPORT10_BASE_CONN_RSV1_MAX (0x1F)
1856 #define MPI_FCPORT10_BASE_CONN_HSSDC_II (0x20)
1857 #define MPI_FCPORT10_BASE_CONN_CPR_PIGT (0x21)
1858 #define MPI_FCPORT10_BASE_CONN_RSV2_MIN (0x22)
1859 #define MPI_FCPORT10_BASE_CONN_RSV2_MAX (0x7F)
1860 #define MPI_FCPORT10_BASE_CONN_VNDSPC_MASK (0x80)
1861
1862 #define MPI_FCPORT10_BASE_ENCODE_UNSPEC (0x00)
1863 #define MPI_FCPORT10_BASE_ENCODE_8B10B (0x01)
1864 #define MPI_FCPORT10_BASE_ENCODE_4B5B (0x02)
1865 #define MPI_FCPORT10_BASE_ENCODE_NRZ (0x03)
1866 #define MPI_FCPORT10_BASE_ENCODE_MANCHESTER (0x04)
1867
1868
1869 typedef struct _CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA
1870 {
1871 U8 Options[2]; /* 50h */
1872 U8 BitRateMax; /* 52h */
1873 U8 BitRateMin; /* 53h */
1874 U8 VendorSN[16]; /* 54h */
1875 U8 DateCode[8]; /* 64h */
1876 U8 DiagMonitoringType; /* 6Ch */
1877 U8 EnhancedOptions; /* 6Dh */
1878 U8 SFF8472Compliance; /* 6Eh */
1879 U8 CC_EXT; /* 6Fh */
1880 } CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA,
1881 MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA,
1882 FCPortPage10ExtendedSfpData_t, MPI_POINTER pFCPortPage10ExtendedSfpData_t;
1883
1884 #define MPI_FCPORT10_EXT_OPTION1_RATESEL (0x20)
1885 #define MPI_FCPORT10_EXT_OPTION1_TX_DISABLE (0x10)
1886 #define MPI_FCPORT10_EXT_OPTION1_TX_FAULT (0x08)
1887 #define MPI_FCPORT10_EXT_OPTION1_LOS_INVERT (0x04)
1888 #define MPI_FCPORT10_EXT_OPTION1_LOS (0x02)
1889
1890
1891 typedef struct _CONFIG_PAGE_FC_PORT_10
1892 {
1893 CONFIG_PAGE_HEADER Header; /* 00h */
1894 U8 Flags; /* 04h */
1895 U8 Reserved1; /* 05h */
1896 U16 Reserved2; /* 06h */
1897 U32 HwConfig1; /* 08h */
1898 U32 HwConfig2; /* 0Ch */
1899 CONFIG_PAGE_FC_PORT_10_BASE_SFP_DATA Base; /* 10h */
1900 CONFIG_PAGE_FC_PORT_10_EXTENDED_SFP_DATA Extended; /* 50h */
1901 U8 VendorSpecific[32]; /* 70h */
1902 } CONFIG_PAGE_FC_PORT_10, MPI_POINTER PTR_CONFIG_PAGE_FC_PORT_10,
1903 FCPortPage10_t, MPI_POINTER pFCPortPage10_t;
1904
1905 #define MPI_FCPORTPAGE10_PAGEVERSION (0x01)
1906
1907 /* standard MODDEF pin definitions (from GBIC spec.) */
1908 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_MASK (0x00000007)
1909 #define MPI_FCPORTPAGE10_FLAGS_MODDEF2 (0x00000001)
1910 #define MPI_FCPORTPAGE10_FLAGS_MODDEF1 (0x00000002)
1911 #define MPI_FCPORTPAGE10_FLAGS_MODDEF0 (0x00000004)
1912 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_NOGBIC (0x00000007)
1913 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_CPR_IEEE_CX (0x00000006)
1914 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_COPPER (0x00000005)
1915 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_OPTICAL_LW (0x00000004)
1916 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SEEPROM (0x00000003)
1917 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SW_OPTICAL (0x00000002)
1918 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_LX_IEEE_OPT_LW (0x00000001)
1919 #define MPI_FCPORTPAGE10_FLAGS_MODDEF_SX_IEEE_OPT_SW (0x00000000)
1920
1921 #define MPI_FCPORTPAGE10_FLAGS_CC_BASE_OK (0x00000010)
1922 #define MPI_FCPORTPAGE10_FLAGS_CC_EXT_OK (0x00000020)
1923
1924
1925 /****************************************************************************
1926 * FC Device Config Pages
1927 ****************************************************************************/
1928
1929 typedef struct _CONFIG_PAGE_FC_DEVICE_0
1930 {
1931 CONFIG_PAGE_HEADER Header; /* 00h */
1932 U64 WWNN; /* 04h */
1933 U64 WWPN; /* 0Ch */
1934 U32 PortIdentifier; /* 14h */
1935 U8 Protocol; /* 18h */
1936 U8 Flags; /* 19h */
1937 U16 BBCredit; /* 1Ah */
1938 U16 MaxRxFrameSize; /* 1Ch */
1939 U8 ADISCHardALPA; /* 1Eh */
1940 U8 PortNumber; /* 1Fh */
1941 U8 FcPhLowestVersion; /* 20h */
1942 U8 FcPhHighestVersion; /* 21h */
1943 U8 CurrentTargetID; /* 22h */
1944 U8 CurrentBus; /* 23h */
1945 } CONFIG_PAGE_FC_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_FC_DEVICE_0,
1946 FCDevicePage0_t, MPI_POINTER pFCDevicePage0_t;
1947
1948 #define MPI_FC_DEVICE_PAGE0_PAGEVERSION (0x03)
1949
1950 #define MPI_FC_DEVICE_PAGE0_FLAGS_TARGETID_BUS_VALID (0x01)
1951 #define MPI_FC_DEVICE_PAGE0_FLAGS_PLOGI_INVALID (0x02)
1952 #define MPI_FC_DEVICE_PAGE0_FLAGS_PRLI_INVALID (0x04)
1953
1954 #define MPI_FC_DEVICE_PAGE0_PROT_IP (0x01)
1955 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_TARGET (0x02)
1956 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_INITIATOR (0x04)
1957 #define MPI_FC_DEVICE_PAGE0_PROT_FCP_RETRY (0x08)
1958
1959 #define MPI_FC_DEVICE_PAGE0_PGAD_PORT_MASK (MPI_FC_DEVICE_PGAD_PORT_MASK)
1960 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_MASK (MPI_FC_DEVICE_PGAD_FORM_MASK)
1961 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_NEXT_DID (MPI_FC_DEVICE_PGAD_FORM_NEXT_DID)
1962 #define MPI_FC_DEVICE_PAGE0_PGAD_FORM_BUS_TID (MPI_FC_DEVICE_PGAD_FORM_BUS_TID)
1963 #define MPI_FC_DEVICE_PAGE0_PGAD_DID_MASK (MPI_FC_DEVICE_PGAD_ND_DID_MASK)
1964 #define MPI_FC_DEVICE_PAGE0_PGAD_BUS_MASK (MPI_FC_DEVICE_PGAD_BT_BUS_MASK)
1965 #define MPI_FC_DEVICE_PAGE0_PGAD_BUS_SHIFT (MPI_FC_DEVICE_PGAD_BT_BUS_SHIFT)
1966 #define MPI_FC_DEVICE_PAGE0_PGAD_TID_MASK (MPI_FC_DEVICE_PGAD_BT_TID_MASK)
1967
1968 #define MPI_FC_DEVICE_PAGE0_HARD_ALPA_UNKNOWN (0xFF)
1969
1970 /****************************************************************************
1971 * RAID Volume Config Pages
1972 ****************************************************************************/
1973
1974 typedef struct _RAID_VOL0_PHYS_DISK
1975 {
1976 U16 Reserved; /* 00h */
1977 U8 PhysDiskMap; /* 02h */
1978 U8 PhysDiskNum; /* 03h */
1979 } RAID_VOL0_PHYS_DISK, MPI_POINTER PTR_RAID_VOL0_PHYS_DISK,
1980 RaidVol0PhysDisk_t, MPI_POINTER pRaidVol0PhysDisk_t;
1981
1982 #define MPI_RAIDVOL0_PHYSDISK_PRIMARY (0x01)
1983 #define MPI_RAIDVOL0_PHYSDISK_SECONDARY (0x02)
1984
1985 typedef struct _RAID_VOL0_STATUS
1986 {
1987 U8 Flags; /* 00h */
1988 U8 State; /* 01h */
1989 U16 Reserved; /* 02h */
1990 } RAID_VOL0_STATUS, MPI_POINTER PTR_RAID_VOL0_STATUS,
1991 RaidVol0Status_t, MPI_POINTER pRaidVol0Status_t;
1992
1993 /* RAID Volume Page 0 VolumeStatus defines */
1994 #define MPI_RAIDVOL0_STATUS_FLAG_ENABLED (0x01)
1995 #define MPI_RAIDVOL0_STATUS_FLAG_QUIESCED (0x02)
1996 #define MPI_RAIDVOL0_STATUS_FLAG_RESYNC_IN_PROGRESS (0x04)
1997 #define MPI_RAIDVOL0_STATUS_FLAG_VOLUME_INACTIVE (0x08)
1998 #define MPI_RAIDVOL0_STATUS_FLAG_BAD_BLOCK_TABLE_FULL (0x10)
1999
2000 #define MPI_RAIDVOL0_STATUS_STATE_OPTIMAL (0x00)
2001 #define MPI_RAIDVOL0_STATUS_STATE_DEGRADED (0x01)
2002 #define MPI_RAIDVOL0_STATUS_STATE_FAILED (0x02)
2003 #define MPI_RAIDVOL0_STATUS_STATE_MISSING (0x03)
2004
2005 typedef struct _RAID_VOL0_SETTINGS
2006 {
2007 U16 Settings; /* 00h */
2008 U8 HotSparePool; /* 01h */ /* MPI_RAID_HOT_SPARE_POOL_ */
2009 U8 Reserved; /* 02h */
2010 } RAID_VOL0_SETTINGS, MPI_POINTER PTR_RAID_VOL0_SETTINGS,
2011 RaidVol0Settings, MPI_POINTER pRaidVol0Settings;
2012
2013 /* RAID Volume Page 0 VolumeSettings defines */
2014 #define MPI_RAIDVOL0_SETTING_WRITE_CACHING_ENABLE (0x0001)
2015 #define MPI_RAIDVOL0_SETTING_OFFLINE_ON_SMART (0x0002)
2016 #define MPI_RAIDVOL0_SETTING_AUTO_CONFIGURE (0x0004)
2017 #define MPI_RAIDVOL0_SETTING_PRIORITY_RESYNC (0x0008)
2018 #define MPI_RAIDVOL0_SETTING_FAST_DATA_SCRUBBING_0102 (0x0020) /* obsolete */
2019 #define MPI_RAIDVOL0_SETTING_USE_PRODUCT_ID_SUFFIX (0x0010)
2020 #define MPI_RAIDVOL0_SETTING_USE_DEFAULTS (0x8000)
2021
2022 /* RAID Volume Page 0 HotSparePool defines, also used in RAID Physical Disk */
2023 #define MPI_RAID_HOT_SPARE_POOL_0 (0x01)
2024 #define MPI_RAID_HOT_SPARE_POOL_1 (0x02)
2025 #define MPI_RAID_HOT_SPARE_POOL_2 (0x04)
2026 #define MPI_RAID_HOT_SPARE_POOL_3 (0x08)
2027 #define MPI_RAID_HOT_SPARE_POOL_4 (0x10)
2028 #define MPI_RAID_HOT_SPARE_POOL_5 (0x20)
2029 #define MPI_RAID_HOT_SPARE_POOL_6 (0x40)
2030 #define MPI_RAID_HOT_SPARE_POOL_7 (0x80)
2031
2032 /*
2033 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2034 * one and check Header.PageLength at runtime.
2035 */
2036 #ifndef MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX
2037 #define MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX (1)
2038 #endif
2039
2040 typedef struct _CONFIG_PAGE_RAID_VOL_0
2041 {
2042 CONFIG_PAGE_HEADER Header; /* 00h */
2043 U8 VolumeID; /* 04h */
2044 U8 VolumeBus; /* 05h */
2045 U8 VolumeIOC; /* 06h */
2046 U8 VolumeType; /* 07h */ /* MPI_RAID_VOL_TYPE_ */
2047 RAID_VOL0_STATUS VolumeStatus; /* 08h */
2048 RAID_VOL0_SETTINGS VolumeSettings; /* 0Ch */
2049 U32 MaxLBA; /* 10h */
2050 U32 Reserved1; /* 14h */
2051 U32 StripeSize; /* 18h */
2052 U32 Reserved2; /* 1Ch */
2053 U32 Reserved3; /* 20h */
2054 U8 NumPhysDisks; /* 24h */
2055 U8 DataScrubRate; /* 25h */
2056 U8 ResyncRate; /* 26h */
2057 U8 InactiveStatus; /* 27h */
2058 RAID_VOL0_PHYS_DISK PhysDisk[MPI_RAID_VOL_PAGE_0_PHYSDISK_MAX];/* 28h */
2059 } CONFIG_PAGE_RAID_VOL_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_0,
2060 RaidVolumePage0_t, MPI_POINTER pRaidVolumePage0_t;
2061
2062 #define MPI_RAIDVOLPAGE0_PAGEVERSION (0x05)
2063
2064 /* values for RAID Volume Page 0 InactiveStatus field */
2065 #define MPI_RAIDVOLPAGE0_UNKNOWN_INACTIVE (0x00)
2066 #define MPI_RAIDVOLPAGE0_STALE_METADATA_INACTIVE (0x01)
2067 #define MPI_RAIDVOLPAGE0_FOREIGN_VOLUME_INACTIVE (0x02)
2068 #define MPI_RAIDVOLPAGE0_INSUFFICIENT_RESOURCE_INACTIVE (0x03)
2069 #define MPI_RAIDVOLPAGE0_CLONE_VOLUME_INACTIVE (0x04)
2070 #define MPI_RAIDVOLPAGE0_INSUFFICIENT_METADATA_INACTIVE (0x05)
2071 #define MPI_RAIDVOLPAGE0_PREVIOUSLY_DELETED (0x06)
2072
2073
2074 typedef struct _CONFIG_PAGE_RAID_VOL_1
2075 {
2076 CONFIG_PAGE_HEADER Header; /* 00h */
2077 U8 VolumeID; /* 01h */
2078 U8 VolumeBus; /* 02h */
2079 U8 VolumeIOC; /* 03h */
2080 U8 Reserved0; /* 04h */
2081 U8 GUID[24]; /* 05h */
2082 U8 Name[32]; /* 20h */
2083 U64 WWID; /* 40h */
2084 U32 Reserved1; /* 48h */
2085 U32 Reserved2; /* 4Ch */
2086 } CONFIG_PAGE_RAID_VOL_1, MPI_POINTER PTR_CONFIG_PAGE_RAID_VOL_1,
2087 RaidVolumePage1_t, MPI_POINTER pRaidVolumePage1_t;
2088
2089 #define MPI_RAIDVOLPAGE1_PAGEVERSION (0x01)
2090
2091
2092 /****************************************************************************
2093 * RAID Physical Disk Config Pages
2094 ****************************************************************************/
2095
2096 typedef struct _RAID_PHYS_DISK0_ERROR_DATA
2097 {
2098 U8 ErrorCdbByte; /* 00h */
2099 U8 ErrorSenseKey; /* 01h */
2100 U16 Reserved; /* 02h */
2101 U16 ErrorCount; /* 04h */
2102 U8 ErrorASC; /* 06h */
2103 U8 ErrorASCQ; /* 07h */
2104 U16 SmartCount; /* 08h */
2105 U8 SmartASC; /* 0Ah */
2106 U8 SmartASCQ; /* 0Bh */
2107 } RAID_PHYS_DISK0_ERROR_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_ERROR_DATA,
2108 RaidPhysDisk0ErrorData_t, MPI_POINTER pRaidPhysDisk0ErrorData_t;
2109
2110 typedef struct _RAID_PHYS_DISK_INQUIRY_DATA
2111 {
2112 U8 VendorID[8]; /* 00h */
2113 U8 ProductID[16]; /* 08h */
2114 U8 ProductRevLevel[4]; /* 18h */
2115 U8 Info[32]; /* 1Ch */
2116 } RAID_PHYS_DISK0_INQUIRY_DATA, MPI_POINTER PTR_RAID_PHYS_DISK0_INQUIRY_DATA,
2117 RaidPhysDisk0InquiryData, MPI_POINTER pRaidPhysDisk0InquiryData;
2118
2119 typedef struct _RAID_PHYS_DISK0_SETTINGS
2120 {
2121 U8 SepID; /* 00h */
2122 U8 SepBus; /* 01h */
2123 U8 HotSparePool; /* 02h */ /* MPI_RAID_HOT_SPARE_POOL_ */
2124 U8 PhysDiskSettings; /* 03h */
2125 } RAID_PHYS_DISK0_SETTINGS, MPI_POINTER PTR_RAID_PHYS_DISK0_SETTINGS,
2126 RaidPhysDiskSettings_t, MPI_POINTER pRaidPhysDiskSettings_t;
2127
2128 typedef struct _RAID_PHYS_DISK0_STATUS
2129 {
2130 U8 Flags; /* 00h */
2131 U8 State; /* 01h */
2132 U16 Reserved; /* 02h */
2133 } RAID_PHYS_DISK0_STATUS, MPI_POINTER PTR_RAID_PHYS_DISK0_STATUS,
2134 RaidPhysDiskStatus_t, MPI_POINTER pRaidPhysDiskStatus_t;
2135
2136 /* RAID Volume 2 IM Physical Disk DiskStatus flags */
2137
2138 #define MPI_PHYSDISK0_STATUS_FLAG_OUT_OF_SYNC (0x01)
2139 #define MPI_PHYSDISK0_STATUS_FLAG_QUIESCED (0x02)
2140 #define MPI_PHYSDISK0_STATUS_FLAG_INACTIVE_VOLUME (0x04)
2141 #define MPI_PHYSDISK0_STATUS_FLAG_OPTIMAL_PREVIOUS (0x00)
2142 #define MPI_PHYSDISK0_STATUS_FLAG_NOT_OPTIMAL_PREVIOUS (0x08)
2143
2144 #define MPI_PHYSDISK0_STATUS_ONLINE (0x00)
2145 #define MPI_PHYSDISK0_STATUS_MISSING (0x01)
2146 #define MPI_PHYSDISK0_STATUS_NOT_COMPATIBLE (0x02)
2147 #define MPI_PHYSDISK0_STATUS_FAILED (0x03)
2148 #define MPI_PHYSDISK0_STATUS_INITIALIZING (0x04)
2149 #define MPI_PHYSDISK0_STATUS_OFFLINE_REQUESTED (0x05)
2150 #define MPI_PHYSDISK0_STATUS_FAILED_REQUESTED (0x06)
2151 #define MPI_PHYSDISK0_STATUS_OTHER_OFFLINE (0xFF)
2152
2153 typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_0
2154 {
2155 CONFIG_PAGE_HEADER Header; /* 00h */
2156 U8 PhysDiskID; /* 04h */
2157 U8 PhysDiskBus; /* 05h */
2158 U8 PhysDiskIOC; /* 06h */
2159 U8 PhysDiskNum; /* 07h */
2160 RAID_PHYS_DISK0_SETTINGS PhysDiskSettings; /* 08h */
2161 U32 Reserved1; /* 0Ch */
2162 U8 ExtDiskIdentifier[8]; /* 10h */
2163 U8 DiskIdentifier[16]; /* 18h */
2164 RAID_PHYS_DISK0_INQUIRY_DATA InquiryData; /* 28h */
2165 RAID_PHYS_DISK0_STATUS PhysDiskStatus; /* 64h */
2166 U32 MaxLBA; /* 68h */
2167 RAID_PHYS_DISK0_ERROR_DATA ErrorData; /* 6Ch */
2168 } CONFIG_PAGE_RAID_PHYS_DISK_0, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_0,
2169 RaidPhysDiskPage0_t, MPI_POINTER pRaidPhysDiskPage0_t;
2170
2171 #define MPI_RAIDPHYSDISKPAGE0_PAGEVERSION (0x02)
2172
2173
2174 typedef struct _RAID_PHYS_DISK1_PATH
2175 {
2176 U8 PhysDiskID; /* 00h */
2177 U8 PhysDiskBus; /* 01h */
2178 U16 Reserved1; /* 02h */
2179 U64 WWID; /* 04h */
2180 U64 OwnerWWID; /* 0Ch */
2181 U8 OwnerIdentifier; /* 14h */
2182 U8 Reserved2; /* 15h */
2183 U16 Flags; /* 16h */
2184 } RAID_PHYS_DISK1_PATH, MPI_POINTER PTR_RAID_PHYS_DISK1_PATH,
2185 RaidPhysDisk1Path_t, MPI_POINTER pRaidPhysDisk1Path_t;
2186
2187 /* RAID Physical Disk Page 1 Flags field defines */
2188 #define MPI_RAID_PHYSDISK1_FLAG_BROKEN (0x0002)
2189 #define MPI_RAID_PHYSDISK1_FLAG_INVALID (0x0001)
2190
2191 typedef struct _CONFIG_PAGE_RAID_PHYS_DISK_1
2192 {
2193 CONFIG_PAGE_HEADER Header; /* 00h */
2194 U8 NumPhysDiskPaths; /* 04h */
2195 U8 PhysDiskNum; /* 05h */
2196 U16 Reserved2; /* 06h */
2197 U32 Reserved1; /* 08h */
2198 RAID_PHYS_DISK1_PATH Path[1]; /* 0Ch */
2199 } CONFIG_PAGE_RAID_PHYS_DISK_1, MPI_POINTER PTR_CONFIG_PAGE_RAID_PHYS_DISK_1,
2200 RaidPhysDiskPage1_t, MPI_POINTER pRaidPhysDiskPage1_t;
2201
2202 #define MPI_RAIDPHYSDISKPAGE1_PAGEVERSION (0x00)
2203
2204
2205 /****************************************************************************
2206 * LAN Config Pages
2207 ****************************************************************************/
2208
2209 typedef struct _CONFIG_PAGE_LAN_0
2210 {
2211 ConfigPageHeader_t Header; /* 00h */
2212 U16 TxRxModes; /* 04h */
2213 U16 Reserved; /* 06h */
2214 U32 PacketPrePad; /* 08h */
2215 } CONFIG_PAGE_LAN_0, MPI_POINTER PTR_CONFIG_PAGE_LAN_0,
2216 LANPage0_t, MPI_POINTER pLANPage0_t;
2217
2218 #define MPI_LAN_PAGE0_PAGEVERSION (0x01)
2219
2220 #define MPI_LAN_PAGE0_RETURN_LOOPBACK (0x0000)
2221 #define MPI_LAN_PAGE0_SUPPRESS_LOOPBACK (0x0001)
2222 #define MPI_LAN_PAGE0_LOOPBACK_MASK (0x0001)
2223
2224 typedef struct _CONFIG_PAGE_LAN_1
2225 {
2226 ConfigPageHeader_t Header; /* 00h */
2227 U16 Reserved; /* 04h */
2228 U8 CurrentDeviceState; /* 06h */
2229 U8 Reserved1; /* 07h */
2230 U32 MinPacketSize; /* 08h */
2231 U32 MaxPacketSize; /* 0Ch */
2232 U32 HardwareAddressLow; /* 10h */
2233 U32 HardwareAddressHigh; /* 14h */
2234 U32 MaxWireSpeedLow; /* 18h */
2235 U32 MaxWireSpeedHigh; /* 1Ch */
2236 U32 BucketsRemaining; /* 20h */
2237 U32 MaxReplySize; /* 24h */
2238 U32 NegWireSpeedLow; /* 28h */
2239 U32 NegWireSpeedHigh; /* 2Ch */
2240 } CONFIG_PAGE_LAN_1, MPI_POINTER PTR_CONFIG_PAGE_LAN_1,
2241 LANPage1_t, MPI_POINTER pLANPage1_t;
2242
2243 #define MPI_LAN_PAGE1_PAGEVERSION (0x03)
2244
2245 #define MPI_LAN_PAGE1_DEV_STATE_RESET (0x00)
2246 #define MPI_LAN_PAGE1_DEV_STATE_OPERATIONAL (0x01)
2247
2248
2249 /****************************************************************************
2250 * Inband Config Pages
2251 ****************************************************************************/
2252
2253 typedef struct _CONFIG_PAGE_INBAND_0
2254 {
2255 CONFIG_PAGE_HEADER Header; /* 00h */
2256 MPI_VERSION_FORMAT InbandVersion; /* 04h */
2257 U16 MaximumBuffers; /* 08h */
2258 U16 Reserved1; /* 0Ah */
2259 } CONFIG_PAGE_INBAND_0, MPI_POINTER PTR_CONFIG_PAGE_INBAND_0,
2260 InbandPage0_t, MPI_POINTER pInbandPage0_t;
2261
2262 #define MPI_INBAND_PAGEVERSION (0x00)
2263
2264
2265
2266 /****************************************************************************
2267 * SAS IO Unit Config Pages
2268 ****************************************************************************/
2269
2270 typedef struct _MPI_SAS_IO_UNIT0_PHY_DATA
2271 {
2272 U8 Port; /* 00h */
2273 U8 PortFlags; /* 01h */
2274 U8 PhyFlags; /* 02h */
2275 U8 NegotiatedLinkRate; /* 03h */
2276 U32 ControllerPhyDeviceInfo;/* 04h */
2277 U16 AttachedDeviceHandle; /* 08h */
2278 U16 ControllerDevHandle; /* 0Ah */
2279 U32 DiscoveryStatus; /* 0Ch */
2280 } MPI_SAS_IO_UNIT0_PHY_DATA, MPI_POINTER PTR_MPI_SAS_IO_UNIT0_PHY_DATA,
2281 SasIOUnit0PhyData, MPI_POINTER pSasIOUnit0PhyData;
2282
2283 /*
2284 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2285 * one and check Header.PageLength at runtime.
2286 */
2287 #ifndef MPI_SAS_IOUNIT0_PHY_MAX
2288 #define MPI_SAS_IOUNIT0_PHY_MAX (1)
2289 #endif
2290
2291 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_0
2292 {
2293 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2294 U32 Reserved1; /* 08h */
2295 U8 NumPhys; /* 0Ch */
2296 U8 Reserved2; /* 0Dh */
2297 U16 Reserved3; /* 0Eh */
2298 MPI_SAS_IO_UNIT0_PHY_DATA PhyData[MPI_SAS_IOUNIT0_PHY_MAX]; /* 10h */
2299 } CONFIG_PAGE_SAS_IO_UNIT_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_0,
2300 SasIOUnitPage0_t, MPI_POINTER pSasIOUnitPage0_t;
2301
2302 #define MPI_SASIOUNITPAGE0_PAGEVERSION (0x03)
2303
2304 /* values for SAS IO Unit Page 0 PortFlags */
2305 #define MPI_SAS_IOUNIT0_PORT_FLAGS_DISCOVERY_IN_PROGRESS (0x08)
2306 #define MPI_SAS_IOUNIT0_PORT_FLAGS_0_TARGET_IOC_NUM (0x00)
2307 #define MPI_SAS_IOUNIT0_PORT_FLAGS_1_TARGET_IOC_NUM (0x04)
2308 #define MPI_SAS_IOUNIT0_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
2309
2310 /* values for SAS IO Unit Page 0 PhyFlags */
2311 #define MPI_SAS_IOUNIT0_PHY_FLAGS_PHY_DISABLED (0x04)
2312 #define MPI_SAS_IOUNIT0_PHY_FLAGS_TX_INVERT (0x02)
2313 #define MPI_SAS_IOUNIT0_PHY_FLAGS_RX_INVERT (0x01)
2314
2315 /* values for SAS IO Unit Page 0 NegotiatedLinkRate */
2316 #define MPI_SAS_IOUNIT0_RATE_UNKNOWN (0x00)
2317 #define MPI_SAS_IOUNIT0_RATE_PHY_DISABLED (0x01)
2318 #define MPI_SAS_IOUNIT0_RATE_FAILED_SPEED_NEGOTIATION (0x02)
2319 #define MPI_SAS_IOUNIT0_RATE_SATA_OOB_COMPLETE (0x03)
2320 #define MPI_SAS_IOUNIT0_RATE_1_5 (0x08)
2321 #define MPI_SAS_IOUNIT0_RATE_3_0 (0x09)
2322
2323 /* see mpi_sas.h for values for SAS IO Unit Page 0 ControllerPhyDeviceInfo values */
2324
2325 /* values for SAS IO Unit Page 0 DiscoveryStatus */
2326 #define MPI_SAS_IOUNIT0_DS_LOOP_DETECTED (0x00000001)
2327 #define MPI_SAS_IOUNIT0_DS_UNADDRESSABLE_DEVICE (0x00000002)
2328 #define MPI_SAS_IOUNIT0_DS_MULTIPLE_PORTS (0x00000004)
2329 #define MPI_SAS_IOUNIT0_DS_EXPANDER_ERR (0x00000008)
2330 #define MPI_SAS_IOUNIT0_DS_SMP_TIMEOUT (0x00000010)
2331 #define MPI_SAS_IOUNIT0_DS_OUT_ROUTE_ENTRIES (0x00000020)
2332 #define MPI_SAS_IOUNIT0_DS_INDEX_NOT_EXIST (0x00000040)
2333 #define MPI_SAS_IOUNIT0_DS_SMP_FUNCTION_FAILED (0x00000080)
2334 #define MPI_SAS_IOUNIT0_DS_SMP_CRC_ERROR (0x00000100)
2335 #define MPI_SAS_IOUNIT0_DS_SUBTRACTIVE_LINK (0x00000200)
2336 #define MPI_SAS_IOUNIT0_DS_TABLE_LINK (0x00000400)
2337 #define MPI_SAS_IOUNIT0_DS_UNSUPPORTED_DEVICE (0x00000800)
2338 #define MPI_SAS_IOUNIT0_DS_MAX_SATA_TARGETS (0x00001000)
2339
2340
2341 typedef struct _MPI_SAS_IO_UNIT1_PHY_DATA
2342 {
2343 U8 Port; /* 00h */
2344 U8 PortFlags; /* 01h */
2345 U8 PhyFlags; /* 02h */
2346 U8 MaxMinLinkRate; /* 03h */
2347 U32 ControllerPhyDeviceInfo;/* 04h */
2348 U32 Reserved1; /* 08h */
2349 } MPI_SAS_IO_UNIT1_PHY_DATA, MPI_POINTER PTR_MPI_SAS_IO_UNIT1_PHY_DATA,
2350 SasIOUnit1PhyData, MPI_POINTER pSasIOUnit1PhyData;
2351
2352 /*
2353 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2354 * one and check Header.PageLength at runtime.
2355 */
2356 #ifndef MPI_SAS_IOUNIT1_PHY_MAX
2357 #define MPI_SAS_IOUNIT1_PHY_MAX (1)
2358 #endif
2359
2360 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_1
2361 {
2362 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2363 U16 ControlFlags; /* 08h */
2364 U16 MaxNumSATATargets; /* 0Ah */
2365 U32 Reserved1; /* 0Ch */
2366 U8 NumPhys; /* 10h */
2367 U8 SATAMaxQDepth; /* 11h */
2368 U16 Reserved2; /* 12h */
2369 MPI_SAS_IO_UNIT1_PHY_DATA PhyData[MPI_SAS_IOUNIT1_PHY_MAX]; /* 14h */
2370 } CONFIG_PAGE_SAS_IO_UNIT_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_1,
2371 SasIOUnitPage1_t, MPI_POINTER pSasIOUnitPage1_t;
2372
2373 #define MPI_SASIOUNITPAGE1_PAGEVERSION (0x04)
2374
2375 /* values for SAS IO Unit Page 1 ControlFlags */
2376 #define MPI_SAS_IOUNIT1_CONTROL_DEVICE_SELF_TEST (0x8000)
2377 #define MPI_SAS_IOUNIT1_CONTROL_SATA_3_0_MAX (0x4000)
2378 #define MPI_SAS_IOUNIT1_CONTROL_SATA_1_5_MAX (0x2000)
2379 #define MPI_SAS_IOUNIT1_CONTROL_SATA_SW_PRESERVE (0x1000)
2380 #define MPI_SAS_IOUNIT1_CONTROL_DISABLE_SAS_HASH (0x0800)
2381
2382 #define MPI_SAS_IOUNIT1_CONTROL_MASK_DEV_SUPPORT (0x0600)
2383 #define MPI_SAS_IOUNIT1_CONTROL_SHIFT_DEV_SUPPORT (9)
2384 #define MPI_SAS_IOUNIT1_CONTROL_DEV_SUPPORT_BOTH (0x00)
2385 #define MPI_SAS_IOUNIT1_CONTROL_DEV_SAS_SUPPORT (0x01)
2386 #define MPI_SAS_IOUNIT1_CONTROL_DEV_SATA_SUPPORT (0x02)
2387
2388 #define MPI_SAS_IOUNIT1_CONTROL_SATA_48BIT_LBA_REQUIRED (0x0080)
2389 #define MPI_SAS_IOUNIT1_CONTROL_SATA_SMART_REQUIRED (0x0040)
2390 #define MPI_SAS_IOUNIT1_CONTROL_SATA_NCQ_REQUIRED (0x0020)
2391 #define MPI_SAS_IOUNIT1_CONTROL_SATA_FUA_REQUIRED (0x0010)
2392 #define MPI_SAS_IOUNIT1_CONTROL_PHY_ENABLE_ORDER_HIGH (0x0008)
2393 #define MPI_SAS_IOUNIT1_CONTROL_SUBTRACTIVE_ILLEGAL (0x0004)
2394 #define MPI_SAS_IOUNIT1_CONTROL_FIRST_LVL_DISC_ONLY (0x0002)
2395 #define MPI_SAS_IOUNIT1_CONTROL_CLEAR_AFFILIATION (0x0001)
2396
2397 /* values for SAS IO Unit Page 1 PortFlags */
2398 #define MPI_SAS_IOUNIT1_PORT_FLAGS_0_TARGET_IOC_NUM (0x00)
2399 #define MPI_SAS_IOUNIT1_PORT_FLAGS_1_TARGET_IOC_NUM (0x04)
2400 #define MPI_SAS_IOUNIT1_PORT_FLAGS_AUTO_PORT_CONFIG (0x01)
2401
2402 /* values for SAS IO Unit Page 0 PhyFlags */
2403 #define MPI_SAS_IOUNIT1_PHY_FLAGS_PHY_DISABLE (0x04)
2404 #define MPI_SAS_IOUNIT1_PHY_FLAGS_TX_INVERT (0x02)
2405 #define MPI_SAS_IOUNIT1_PHY_FLAGS_RX_INVERT (0x01)
2406
2407 /* values for SAS IO Unit Page 0 MaxMinLinkRate */
2408 #define MPI_SAS_IOUNIT1_MAX_RATE_MASK (0xF0)
2409 #define MPI_SAS_IOUNIT1_MAX_RATE_1_5 (0x80)
2410 #define MPI_SAS_IOUNIT1_MAX_RATE_3_0 (0x90)
2411 #define MPI_SAS_IOUNIT1_MIN_RATE_MASK (0x0F)
2412 #define MPI_SAS_IOUNIT1_MIN_RATE_1_5 (0x08)
2413 #define MPI_SAS_IOUNIT1_MIN_RATE_3_0 (0x09)
2414
2415 /* see mpi_sas.h for values for SAS IO Unit Page 1 ControllerPhyDeviceInfo values */
2416
2417
2418 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_2
2419 {
2420 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2421 U32 Reserved1; /* 08h */
2422 U16 MaxPersistentIDs; /* 0Ch */
2423 U16 NumPersistentIDsUsed; /* 0Eh */
2424 U8 Status; /* 10h */
2425 U8 Flags; /* 11h */
2426 U16 MaxNumPhysicalMappedIDs;/* 12h */ /* 12h */
2427 } CONFIG_PAGE_SAS_IO_UNIT_2, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_2,
2428 SasIOUnitPage2_t, MPI_POINTER pSasIOUnitPage2_t;
2429
2430 #define MPI_SASIOUNITPAGE2_PAGEVERSION (0x04)
2431
2432 /* values for SAS IO Unit Page 2 Status field */
2433 #define MPI_SAS_IOUNIT2_STATUS_DISABLED_PERSISTENT_MAPPINGS (0x02)
2434 #define MPI_SAS_IOUNIT2_STATUS_FULL_PERSISTENT_MAPPINGS (0x01)
2435
2436 /* values for SAS IO Unit Page 2 Flags field */
2437 #define MPI_SAS_IOUNIT2_FLAGS_DISABLE_PERSISTENT_MAPPINGS (0x01)
2438 /* Physical Mapping Modes */
2439 #define MPI_SAS_IOUNIT2_FLAGS_MASK_PHYS_MAP_MODE (0x0E)
2440 #define MPI_SAS_IOUNIT2_FLAGS_SHIFT_PHYS_MAP_MODE (1)
2441 #define MPI_SAS_IOUNIT2_FLAGS_NO_PHYS_MAP (0x00)
2442 #define MPI_SAS_IOUNIT2_FLAGS_DIRECT_ATTACH_PHYS_MAP (0x01)
2443 #define MPI_SAS_IOUNIT2_FLAGS_ENCLOSURE_SLOT_PHYS_MAP (0x02)
2444
2445 #define MPI_SAS_IOUNIT2_FLAGS_RESERVE_ID_0_FOR_BOOT (0x10)
2446 #define MPI_SAS_IOUNIT2_FLAGS_DA_STARTING_SLOT (0x20)
2447
2448
2449 typedef struct _CONFIG_PAGE_SAS_IO_UNIT_3
2450 {
2451 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2452 U32 Reserved1; /* 08h */
2453 U32 MaxInvalidDwordCount; /* 0Ch */
2454 U32 InvalidDwordCountTime; /* 10h */
2455 U32 MaxRunningDisparityErrorCount; /* 14h */
2456 U32 RunningDisparityErrorTime; /* 18h */
2457 U32 MaxLossDwordSynchCount; /* 1Ch */
2458 U32 LossDwordSynchCountTime; /* 20h */
2459 U32 MaxPhyResetProblemCount; /* 24h */
2460 U32 PhyResetProblemTime; /* 28h */
2461 } CONFIG_PAGE_SAS_IO_UNIT_3, MPI_POINTER PTR_CONFIG_PAGE_SAS_IO_UNIT_3,
2462 SasIOUnitPage3_t, MPI_POINTER pSasIOUnitPage3_t;
2463
2464 #define MPI_SASIOUNITPAGE3_PAGEVERSION (0x00)
2465
2466
2467 /****************************************************************************
2468 * SAS Expander Config Pages
2469 ****************************************************************************/
2470
2471 typedef struct _CONFIG_PAGE_SAS_EXPANDER_0
2472 {
2473 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2474 U8 PhysicalPort; /* 08h */
2475 U8 Reserved1; /* 09h */
2476 U16 Reserved2; /* 0Ah */
2477 U64 SASAddress; /* 0Ch */
2478 U32 DiscoveryStatus; /* 14h */
2479 U16 DevHandle; /* 18h */
2480 U16 ParentDevHandle; /* 1Ah */
2481 U16 ExpanderChangeCount; /* 1Ch */
2482 U16 ExpanderRouteIndexes; /* 1Eh */
2483 U8 NumPhys; /* 20h */
2484 U8 SASLevel; /* 21h */
2485 U8 Flags; /* 22h */
2486 U8 Reserved3; /* 23h */
2487 } CONFIG_PAGE_SAS_EXPANDER_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_EXPANDER_0,
2488 SasExpanderPage0_t, MPI_POINTER pSasExpanderPage0_t;
2489
2490 #define MPI_SASEXPANDER0_PAGEVERSION (0x02)
2491
2492 /* values for SAS Expander Page 0 DiscoveryStatus field */
2493 #define MPI_SAS_EXPANDER0_DS_LOOP_DETECTED (0x00000001)
2494 #define MPI_SAS_EXPANDER0_DS_UNADDRESSABLE_DEVICE (0x00000002)
2495 #define MPI_SAS_EXPANDER0_DS_MULTIPLE_PORTS (0x00000004)
2496 #define MPI_SAS_EXPANDER0_DS_EXPANDER_ERR (0x00000008)
2497 #define MPI_SAS_EXPANDER0_DS_SMP_TIMEOUT (0x00000010)
2498 #define MPI_SAS_EXPANDER0_DS_OUT_ROUTE_ENTRIES (0x00000020)
2499 #define MPI_SAS_EXPANDER0_DS_INDEX_NOT_EXIST (0x00000040)
2500 #define MPI_SAS_EXPANDER0_DS_SMP_FUNCTION_FAILED (0x00000080)
2501 #define MPI_SAS_EXPANDER0_DS_SMP_CRC_ERROR (0x00000100)
2502 #define MPI_SAS_EXPANDER0_DS_SUBTRACTIVE_LINK (0x00000200)
2503 #define MPI_SAS_EXPANDER0_DS_TABLE_LINK (0x00000400)
2504 #define MPI_SAS_EXPANDER0_DS_UNSUPPORTED_DEVICE (0x00000800)
2505
2506 /* values for SAS Expander Page 0 Flags field */
2507 #define MPI_SAS_EXPANDER0_FLAGS_ROUTE_TABLE_CONFIG (0x02)
2508 #define MPI_SAS_EXPANDER0_FLAGS_CONFIG_IN_PROGRESS (0x01)
2509
2510
2511 typedef struct _CONFIG_PAGE_SAS_EXPANDER_1
2512 {
2513 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2514 U8 PhysicalPort; /* 08h */
2515 U8 Reserved1; /* 09h */
2516 U16 Reserved2; /* 0Ah */
2517 U8 NumPhys; /* 0Ch */
2518 U8 Phy; /* 0Dh */
2519 U16 NumTableEntriesProgrammed; /* 0Eh */
2520 U8 ProgrammedLinkRate; /* 10h */
2521 U8 HwLinkRate; /* 11h */
2522 U16 AttachedDevHandle; /* 12h */
2523 U32 PhyInfo; /* 14h */
2524 U32 AttachedDeviceInfo; /* 18h */
2525 U16 OwnerDevHandle; /* 1Ch */
2526 U8 ChangeCount; /* 1Eh */
2527 U8 NegotiatedLinkRate; /* 1Fh */
2528 U8 PhyIdentifier; /* 20h */
2529 U8 AttachedPhyIdentifier; /* 21h */
2530 U8 NumTableEntriesProg; /* 22h */
2531 U8 DiscoveryInfo; /* 23h */
2532 U32 Reserved3; /* 24h */
2533 } CONFIG_PAGE_SAS_EXPANDER_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_EXPANDER_1,
2534 SasExpanderPage1_t, MPI_POINTER pSasExpanderPage1_t;
2535
2536 #define MPI_SASEXPANDER1_PAGEVERSION (0x01)
2537
2538 /* use MPI_SAS_PHY0_PRATE_ defines for ProgrammedLinkRate */
2539
2540 /* use MPI_SAS_PHY0_HWRATE_ defines for HwLinkRate */
2541
2542 /* use MPI_SAS_PHY0_PHYINFO_ defines for PhyInfo */
2543
2544 /* see mpi_sas.h for values for SAS Expander Page 1 AttachedDeviceInfo values */
2545
2546 /* values for SAS Expander Page 1 DiscoveryInfo field */
2547 #define MPI_SAS_EXPANDER1_DISCINFO_BAD_PHY DISABLED (0x04)
2548 #define MPI_SAS_EXPANDER1_DISCINFO_LINK_STATUS_CHANGE (0x02)
2549 #define MPI_SAS_EXPANDER1_DISCINFO_NO_ROUTING_ENTRIES (0x01)
2550
2551 /* values for SAS Expander Page 1 NegotiatedLinkRate field */
2552 #define MPI_SAS_EXPANDER1_NEG_RATE_UNKNOWN (0x00)
2553 #define MPI_SAS_EXPANDER1_NEG_RATE_PHY_DISABLED (0x01)
2554 #define MPI_SAS_EXPANDER1_NEG_RATE_FAILED_NEGOTIATION (0x02)
2555 #define MPI_SAS_EXPANDER1_NEG_RATE_SATA_OOB_COMPLETE (0x03)
2556 #define MPI_SAS_EXPANDER1_NEG_RATE_1_5 (0x08)
2557 #define MPI_SAS_EXPANDER1_NEG_RATE_3_0 (0x09)
2558
2559
2560 /****************************************************************************
2561 * SAS Device Config Pages
2562 ****************************************************************************/
2563
2564 typedef struct _CONFIG_PAGE_SAS_DEVICE_0
2565 {
2566 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2567 U16 Slot; /* 08h */
2568 U16 EnclosureHandle; /* 0Ah */
2569 U64 SASAddress; /* 0Ch */
2570 U16 ParentDevHandle; /* 14h */
2571 U8 PhyNum; /* 16h */
2572 U8 AccessStatus; /* 17h */
2573 U16 DevHandle; /* 18h */
2574 U8 TargetID; /* 1Ah */
2575 U8 Bus; /* 1Bh */
2576 U32 DeviceInfo; /* 1Ch */
2577 U16 Flags; /* 20h */
2578 U8 PhysicalPort; /* 22h */
2579 U8 Reserved2; /* 23h */
2580 } CONFIG_PAGE_SAS_DEVICE_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_0,
2581 SasDevicePage0_t, MPI_POINTER pSasDevicePage0_t;
2582
2583 #define MPI_SASDEVICE0_PAGEVERSION (0x04)
2584
2585 /* values for SAS Device Page 0 AccessStatus field */
2586 #define MPI_SAS_DEVICE0_ASTATUS_NO_ERRORS (0x00)
2587 #define MPI_SAS_DEVICE0_ASTATUS_SATA_INIT_FAILED (0x01)
2588 #define MPI_SAS_DEVICE0_ASTATUS_SATA_CAPABILITY_FAILED (0x02)
2589
2590 /* values for SAS Device Page 0 Flags field */
2591 #define MPI_SAS_DEVICE0_FLAGS_SATA_SW_PRESERVE (0x0200)
2592 #define MPI_SAS_DEVICE0_FLAGS_UNSUPPORTED_DEVICE (0x0100)
2593 #define MPI_SAS_DEVICE0_FLAGS_SATA_48BIT_LBA_SUPPORTED (0x0080)
2594 #define MPI_SAS_DEVICE0_FLAGS_SATA_SMART_SUPPORTED (0x0040)
2595 #define MPI_SAS_DEVICE0_FLAGS_SATA_NCQ_SUPPORTED (0x0020)
2596 #define MPI_SAS_DEVICE0_FLAGS_SATA_FUA_SUPPORTED (0x0010)
2597 #define MPI_SAS_DEVICE0_FLAGS_PORT_SELECTOR_ATTACH (0x0008)
2598 #define MPI_SAS_DEVICE0_FLAGS_MAPPING_PERSISTENT (0x0004)
2599 #define MPI_SAS_DEVICE0_FLAGS_DEVICE_MAPPED (0x0002)
2600 #define MPI_SAS_DEVICE0_FLAGS_DEVICE_PRESENT (0x0001)
2601
2602 /* see mpi_sas.h for values for SAS Device Page 0 DeviceInfo values */
2603
2604
2605 typedef struct _CONFIG_PAGE_SAS_DEVICE_1
2606 {
2607 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2608 U32 Reserved1; /* 08h */
2609 U64 SASAddress; /* 0Ch */
2610 U32 Reserved2; /* 14h */
2611 U16 DevHandle; /* 18h */
2612 U8 TargetID; /* 1Ah */
2613 U8 Bus; /* 1Bh */
2614 U8 InitialRegDeviceFIS[20];/* 1Ch */
2615 } CONFIG_PAGE_SAS_DEVICE_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_1,
2616 SasDevicePage1_t, MPI_POINTER pSasDevicePage1_t;
2617
2618 #define MPI_SASDEVICE1_PAGEVERSION (0x00)
2619
2620
2621 typedef struct _CONFIG_PAGE_SAS_DEVICE_2
2622 {
2623 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2624 U64 PhysicalIdentifier; /* 08h */
2625 U32 EnclosureMapping; /* 10h */
2626 } CONFIG_PAGE_SAS_DEVICE_2, MPI_POINTER PTR_CONFIG_PAGE_SAS_DEVICE_2,
2627 SasDevicePage2_t, MPI_POINTER pSasDevicePage2_t;
2628
2629 #define MPI_SASDEVICE2_PAGEVERSION (0x01)
2630
2631 /* defines for SAS Device Page 2 EnclosureMapping field */
2632 #define MPI_SASDEVICE2_ENC_MAP_MASK_MISSING_COUNT (0x0000000F)
2633 #define MPI_SASDEVICE2_ENC_MAP_SHIFT_MISSING_COUNT (0)
2634 #define MPI_SASDEVICE2_ENC_MAP_MASK_NUM_SLOTS (0x000007F0)
2635 #define MPI_SASDEVICE2_ENC_MAP_SHIFT_NUM_SLOTS (4)
2636 #define MPI_SASDEVICE2_ENC_MAP_MASK_START_INDEX (0x001FF800)
2637 #define MPI_SASDEVICE2_ENC_MAP_SHIFT_START_INDEX (11)
2638
2639
2640 /****************************************************************************
2641 * SAS PHY Config Pages
2642 ****************************************************************************/
2643
2644 typedef struct _CONFIG_PAGE_SAS_PHY_0
2645 {
2646 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2647 U16 OwnerDevHandle; /* 08h */
2648 U16 Reserved1; /* 0Ah */
2649 U64 SASAddress; /* 0Ch */
2650 U16 AttachedDevHandle; /* 14h */
2651 U8 AttachedPhyIdentifier; /* 16h */
2652 U8 Reserved2; /* 17h */
2653 U32 AttachedDeviceInfo; /* 18h */
2654 U8 ProgrammedLinkRate; /* 20h */
2655 U8 HwLinkRate; /* 21h */
2656 U8 ChangeCount; /* 22h */
2657 U8 Flags; /* 23h */
2658 U32 PhyInfo; /* 24h */
2659 } CONFIG_PAGE_SAS_PHY_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_PHY_0,
2660 SasPhyPage0_t, MPI_POINTER pSasPhyPage0_t;
2661
2662 #define MPI_SASPHY0_PAGEVERSION (0x01)
2663
2664 /* values for SAS PHY Page 0 ProgrammedLinkRate field */
2665 #define MPI_SAS_PHY0_PRATE_MAX_RATE_MASK (0xF0)
2666 #define MPI_SAS_PHY0_PRATE_MAX_RATE_NOT_PROGRAMMABLE (0x00)
2667 #define MPI_SAS_PHY0_PRATE_MAX_RATE_1_5 (0x80)
2668 #define MPI_SAS_PHY0_PRATE_MAX_RATE_3_0 (0x90)
2669 #define MPI_SAS_PHY0_PRATE_MIN_RATE_MASK (0x0F)
2670 #define MPI_SAS_PHY0_PRATE_MIN_RATE_NOT_PROGRAMMABLE (0x00)
2671 #define MPI_SAS_PHY0_PRATE_MIN_RATE_1_5 (0x08)
2672 #define MPI_SAS_PHY0_PRATE_MIN_RATE_3_0 (0x09)
2673
2674 /* values for SAS PHY Page 0 HwLinkRate field */
2675 #define MPI_SAS_PHY0_HWRATE_MAX_RATE_MASK (0xF0)
2676 #define MPI_SAS_PHY0_HWRATE_MAX_RATE_1_5 (0x80)
2677 #define MPI_SAS_PHY0_HWRATE_MAX_RATE_3_0 (0x90)
2678 #define MPI_SAS_PHY0_HWRATE_MIN_RATE_MASK (0x0F)
2679 #define MPI_SAS_PHY0_HWRATE_MIN_RATE_1_5 (0x08)
2680 #define MPI_SAS_PHY0_HWRATE_MIN_RATE_3_0 (0x09)
2681
2682 /* values for SAS PHY Page 0 Flags field */
2683 #define MPI_SAS_PHY0_FLAGS_SGPIO_DIRECT_ATTACH_ENC (0x01)
2684
2685 /* values for SAS PHY Page 0 PhyInfo field */
2686 #define MPI_SAS_PHY0_PHYINFO_SATA_PORT_ACTIVE (0x00004000)
2687 #define MPI_SAS_PHY0_PHYINFO_SATA_PORT_SELECTOR (0x00002000)
2688 #define MPI_SAS_PHY0_PHYINFO_VIRTUAL_PHY (0x00001000)
2689
2690 #define MPI_SAS_PHY0_PHYINFO_MASK_PARTIAL_PATHWAY_TIME (0x00000F00)
2691 #define MPI_SAS_PHY0_PHYINFO_SHIFT_PARTIAL_PATHWAY_TIME (8)
2692
2693 #define MPI_SAS_PHY0_PHYINFO_MASK_ROUTING_ATTRIBUTE (0x000000F0)
2694 #define MPI_SAS_PHY0_PHYINFO_DIRECT_ROUTING (0x00000000)
2695 #define MPI_SAS_PHY0_PHYINFO_SUBTRACTIVE_ROUTING (0x00000010)
2696 #define MPI_SAS_PHY0_PHYINFO_TABLE_ROUTING (0x00000020)
2697
2698 #define MPI_SAS_PHY0_PHYINFO_MASK_LINK_RATE (0x0000000F)
2699 #define MPI_SAS_PHY0_PHYINFO_UNKNOWN_LINK_RATE (0x00000000)
2700 #define MPI_SAS_PHY0_PHYINFO_PHY_DISABLED (0x00000001)
2701 #define MPI_SAS_PHY0_PHYINFO_NEGOTIATION_FAILED (0x00000002)
2702 #define MPI_SAS_PHY0_PHYINFO_SATA_OOB_COMPLETE (0x00000003)
2703 #define MPI_SAS_PHY0_PHYINFO_RATE_1_5 (0x00000008)
2704 #define MPI_SAS_PHY0_PHYINFO_RATE_3_0 (0x00000009)
2705
2706
2707 typedef struct _CONFIG_PAGE_SAS_PHY_1
2708 {
2709 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2710 U32 Reserved1; /* 08h */
2711 U32 InvalidDwordCount; /* 0Ch */
2712 U32 RunningDisparityErrorCount; /* 10h */
2713 U32 LossDwordSynchCount; /* 14h */
2714 U32 PhyResetProblemCount; /* 18h */
2715 } CONFIG_PAGE_SAS_PHY_1, MPI_POINTER PTR_CONFIG_PAGE_SAS_PHY_1,
2716 SasPhyPage1_t, MPI_POINTER pSasPhyPage1_t;
2717
2718 #define MPI_SASPHY1_PAGEVERSION (0x00)
2719
2720
2721 /****************************************************************************
2722 * SAS Enclosure Config Pages
2723 ****************************************************************************/
2724
2725 typedef struct _CONFIG_PAGE_SAS_ENCLOSURE_0
2726 {
2727 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2728 U32 Reserved1; /* 08h */
2729 U64 EnclosureLogicalID; /* 0Ch */
2730 U16 Flags; /* 14h */
2731 U16 EnclosureHandle; /* 16h */
2732 U16 NumSlots; /* 18h */
2733 U16 StartSlot; /* 1Ah */
2734 U8 StartTargetID; /* 1Ch */
2735 U8 StartBus; /* 1Dh */
2736 U8 SEPTargetID; /* 1Eh */
2737 U8 SEPBus; /* 1Fh */
2738 U32 Reserved2; /* 20h */
2739 U32 Reserved3; /* 24h */
2740 } CONFIG_PAGE_SAS_ENCLOSURE_0, MPI_POINTER PTR_CONFIG_PAGE_SAS_ENCLOSURE_0,
2741 SasEnclosurePage0_t, MPI_POINTER pSasEnclosurePage0_t;
2742
2743 #define MPI_SASENCLOSURE0_PAGEVERSION (0x01)
2744
2745 /* values for SAS Enclosure Page 0 Flags field */
2746 #define MPI_SAS_ENCLS0_FLAGS_SEP_BUS_ID_VALID (0x0020)
2747 #define MPI_SAS_ENCLS0_FLAGS_START_BUS_ID_VALID (0x0010)
2748
2749 #define MPI_SAS_ENCLS0_FLAGS_MNG_MASK (0x000F)
2750 #define MPI_SAS_ENCLS0_FLAGS_MNG_UNKNOWN (0x0000)
2751 #define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_SES (0x0001)
2752 #define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_SGPIO (0x0002)
2753 #define MPI_SAS_ENCLS0_FLAGS_MNG_EXP_SGPIO (0x0003)
2754 #define MPI_SAS_ENCLS0_FLAGS_MNG_SES_ENCLOSURE (0x0004)
2755 #define MPI_SAS_ENCLS0_FLAGS_MNG_IOC_GPIO (0x0005)
2756
2757
2758 /****************************************************************************
2759 * Log Config Pages
2760 ****************************************************************************/
2761 /*
2762 * Host code (drivers, BIOS, utilities, etc.) should leave this define set to
2763 * one and check NumLogEntries at runtime.
2764 */
2765 #ifndef MPI_LOG_0_NUM_LOG_ENTRIES
2766 #define MPI_LOG_0_NUM_LOG_ENTRIES (1)
2767 #endif
2768
2769 #define MPI_LOG_0_LOG_DATA_LENGTH (20)
2770
2771 typedef struct _MPI_LOG_0_ENTRY
2772 {
2773 U64 WWID; /* 00h */
2774 U32 TimeStamp; /* 08h */
2775 U32 Reserved1; /* 0Ch */
2776 U16 LogSequence; /* 10h */
2777 U16 LogEntryQualifier; /* 12h */
2778 U8 LogData[MPI_LOG_0_LOG_DATA_LENGTH]; /* 14h */
2779 } MPI_LOG_0_ENTRY, MPI_POINTER PTR_MPI_LOG_0_ENTRY,
2780 MpiLog0Entry_t, MPI_POINTER pMpiLog0Entry_t;
2781
2782 /* values for Log Page 0 LogEntry LogEntryQualifier field */
2783 #define MPI_LOG_0_ENTRY_QUAL_ENTRY_UNUSED (0x0000)
2784 #define MPI_LOG_0_ENTRY_QUAL_POWER_ON_RESET (0x0001)
2785
2786 typedef struct _CONFIG_PAGE_LOG_0
2787 {
2788 CONFIG_EXTENDED_PAGE_HEADER Header; /* 00h */
2789 U32 Reserved1; /* 08h */
2790 U32 Reserved2; /* 0Ch */
2791 U16 NumLogEntries; /* 10h */
2792 U16 Reserved3; /* 12h */
2793 MPI_LOG_0_ENTRY LogEntry[MPI_LOG_0_NUM_LOG_ENTRIES]; /* 14h */
2794 } CONFIG_PAGE_LOG_0, MPI_POINTER PTR_CONFIG_PAGE_LOG_0,
2795 LogPage0_t, MPI_POINTER pLogPage0_t;
2796
2797 #define MPI_LOG_0_PAGEVERSION (0x00)
2798
2799
2800 #endif
2801
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