drivers/mtd/nand/rtc_from4.c

   1 /*
   2  *  drivers/mtd/nand/rtc_from4.c
   3  *
   4  *  Copyright (C) 2004  Red Hat, Inc.
   5  *
   6  *  Derived from drivers/mtd/nand/spia.c
   7  *       Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
   8  *
   9  * $Id: rtc_from4.c,v 1.9 2005/01/24 20:40:11 dmarlin Exp $
  10  *
  11  * This program is free software; you can redistribute it and/or modify
  12  * it under the terms of the GNU General Public License version 2 as
  13  * published by the Free Software Foundation.
  14  *
  15  * Overview:
  16  *   This is a device driver for the AG-AND flash device found on the
  17  *   Renesas Technology Corp. Flash ROM 4-slot interface board (FROM_BOARD4),
  18  *   which utilizes the Renesas HN29V1G91T-30 part.
  19  *   This chip is a 1 GBibit (128MiB x 8 bits) AG-AND flash device.
  20  */
  21
  22 #include <linux/delay.h>
  23 #include <linux/kernel.h>
  24 #include <linux/init.h>
  25 #include <linux/slab.h>
  26 #include <linux/rslib.h>
  27 #include <linux/module.h>
  28 #include <linux/mtd/compatmac.h>
  29 #include <linux/mtd/mtd.h>
  30 #include <linux/mtd/nand.h>
  31 #include <linux/mtd/partitions.h>
  32 #include <asm/io.h>
  33
  34 /*
  35  * MTD structure for Renesas board
  36  */
  37 static struct mtd_info *rtc_from4_mtd = NULL;
  38
  39 #define RTC_FROM4_MAX_CHIPS     2
  40
  41 /* HS77x9 processor register defines */
  42 #define SH77X9_BCR1     ((volatile unsigned short *)(0xFFFFFF60))
  43 #define SH77X9_BCR2     ((volatile unsigned short *)(0xFFFFFF62))
  44 #define SH77X9_WCR1     ((volatile unsigned short *)(0xFFFFFF64))
  45 #define SH77X9_WCR2     ((volatile unsigned short *)(0xFFFFFF66))
  46 #define SH77X9_MCR      ((volatile unsigned short *)(0xFFFFFF68))
  47 #define SH77X9_PCR      ((volatile unsigned short *)(0xFFFFFF6C))
  48 #define SH77X9_FRQCR    ((volatile unsigned short *)(0xFFFFFF80))
  49
  50 /*
  51  * Values specific to the Renesas Technology Corp. FROM_BOARD4 (used with HS77x9 processor)
  52  */
  53 /* Address where flash is mapped */
  54 #define RTC_FROM4_FIO_BASE      0x14000000
  55
  56 /* CLE and ALE are tied to address lines 5 & 4, respectively */
  57 #define RTC_FROM4_CLE           (1 << 5)
  58 #define RTC_FROM4_ALE           (1 << 4)
  59
  60 /* address lines A24-A22 used for chip selection */
  61 #define RTC_FROM4_NAND_ADDR_SLOT3       (0x00800000)
  62 #define RTC_FROM4_NAND_ADDR_SLOT4       (0x00C00000)
  63 #define RTC_FROM4_NAND_ADDR_FPGA        (0x01000000)
  64 /* mask address lines A24-A22 used for chip selection */
  65 #define RTC_FROM4_NAND_ADDR_MASK        (RTC_FROM4_NAND_ADDR_SLOT3 | RTC_FROM4_NAND_ADDR_SLOT4 | RTC_FROM4_NAND_ADDR_FPGA)
  66
  67 /* FPGA status register for checking device ready (bit zero) */
  68 #define RTC_FROM4_FPGA_SR               (RTC_FROM4_NAND_ADDR_FPGA | 0x00000002)
  69 #define RTC_FROM4_DEVICE_READY          0x0001
  70
  71 /* FPGA Reed-Solomon ECC Control register */
  72
  73 #define RTC_FROM4_RS_ECC_CTL            (RTC_FROM4_NAND_ADDR_FPGA | 0x00000050)
  74 #define RTC_FROM4_RS_ECC_CTL_CLR        (1 << 7)
  75 #define RTC_FROM4_RS_ECC_CTL_GEN        (1 << 6)
  76 #define RTC_FROM4_RS_ECC_CTL_FD_E       (1 << 5)
  77
  78 /* FPGA Reed-Solomon ECC code base */
  79 #define RTC_FROM4_RS_ECC                (RTC_FROM4_NAND_ADDR_FPGA | 0x00000060)
  80 #define RTC_FROM4_RS_ECCN               (RTC_FROM4_NAND_ADDR_FPGA | 0x00000080)
  81
  82 /* FPGA Reed-Solomon ECC check register */
  83 #define RTC_FROM4_RS_ECC_CHK            (RTC_FROM4_NAND_ADDR_FPGA | 0x00000070)
  84 #define RTC_FROM4_RS_ECC_CHK_ERROR      (1 << 7)
  85
  86 #define ERR_STAT_ECC_AVAILABLE          0x20
  87
  88 /* Undefine for software ECC */
  89 #define RTC_FROM4_HWECC 1
  90
  91 /* Define as 1 for no virtual erase blocks (in JFFS2) */
  92 #define RTC_FROM4_NO_VIRTBLOCKS 0
  93
  94 /*
  95  * Module stuff
  96  */
  97 static void __iomem *rtc_from4_fio_base = (void *)P2SEGADDR(RTC_FROM4_FIO_BASE);
  98
  99 const static struct mtd_partition partition_info[] = {
 100         {
 101                 .name   = "Renesas flash partition 1",
 102                 .offset = 0,
 103                 .size   = MTDPART_SIZ_FULL
 104         },
 105 };
 106 #define NUM_PARTITIONS 1
 107
 108 /*
 109  *      hardware specific flash bbt decriptors
 110  *      Note: this is to allow debugging by disabling
 111  *              NAND_BBT_CREATE and/or NAND_BBT_WRITE
 112  *
 113  */
 114 static uint8_t bbt_pattern[] = {'B', 'b', 't', '0' };
 115 static uint8_t mirror_pattern[] = {'1', 't', 'b', 'B' };
 116
 117 static struct nand_bbt_descr rtc_from4_bbt_main_descr = {
 118         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
 119                 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
 120         .offs = 40,
 121         .len = 4,
 122         .veroffs = 44,
 123         .maxblocks = 4,
 124         .pattern = bbt_pattern
 125 };
 126
 127 static struct nand_bbt_descr rtc_from4_bbt_mirror_descr = {
 128         .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
 129                 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
 130         .offs = 40,
 131         .len = 4,
 132         .veroffs = 44,
 133         .maxblocks = 4,
 134         .pattern = mirror_pattern
 135 };
 136
 137
 138
 139 #ifdef RTC_FROM4_HWECC
 140
 141 /* the Reed Solomon control structure */
 142 static struct rs_control *rs_decoder;
 143
 144 /*
 145  *      hardware specific Out Of Band information
 146  */
 147 static struct nand_oobinfo rtc_from4_nand_oobinfo = {
 148         .useecc = MTD_NANDECC_AUTOPLACE,
 149         .eccbytes = 32,
 150         .eccpos = {
 151                  0,  1,  2,  3,  4,  5,  6,  7,
 152                  8,  9, 10, 11, 12, 13, 14, 15,
 153                 16, 17, 18, 19, 20, 21, 22, 23,
 154                 24, 25, 26, 27, 28, 29, 30, 31},
 155         .oobfree = { {32, 32} }
 156 };
 157
 158 /* Aargh. I missed the reversed bit order, when I
 159  * was talking to Renesas about the FPGA.
 160  *
 161  * The table is used for bit reordering and inversion
 162  * of the ecc byte which we get from the FPGA
 163  */
 164 static uint8_t revbits[256] = {
 165         0x00, 0x80, 0x40, 0xc0, 0x20, 0xa0, 0x60, 0xe0,
 166         0x10, 0x90, 0x50, 0xd0, 0x30, 0xb0, 0x70, 0xf0,
 167         0x08, 0x88, 0x48, 0xc8, 0x28, 0xa8, 0x68, 0xe8,
 168         0x18, 0x98, 0x58, 0xd8, 0x38, 0xb8, 0x78, 0xf8,
 169         0x04, 0x84, 0x44, 0xc4, 0x24, 0xa4, 0x64, 0xe4,
 170         0x14, 0x94, 0x54, 0xd4, 0x34, 0xb4, 0x74, 0xf4,
 171         0x0c, 0x8c, 0x4c, 0xcc, 0x2c, 0xac, 0x6c, 0xec,
 172         0x1c, 0x9c, 0x5c, 0xdc, 0x3c, 0xbc, 0x7c, 0xfc,
 173         0x02, 0x82, 0x42, 0xc2, 0x22, 0xa2, 0x62, 0xe2,
 174         0x12, 0x92, 0x52, 0xd2, 0x32, 0xb2, 0x72, 0xf2,
 175         0x0a, 0x8a, 0x4a, 0xca, 0x2a, 0xaa, 0x6a, 0xea,
 176         0x1a, 0x9a, 0x5a, 0xda, 0x3a, 0xba, 0x7a, 0xfa,
 177         0x06, 0x86, 0x46, 0xc6, 0x26, 0xa6, 0x66, 0xe6,
 178         0x16, 0x96, 0x56, 0xd6, 0x36, 0xb6, 0x76, 0xf6,
 179         0x0e, 0x8e, 0x4e, 0xce, 0x2e, 0xae, 0x6e, 0xee,
 180         0x1e, 0x9e, 0x5e, 0xde, 0x3e, 0xbe, 0x7e, 0xfe,
 181         0x01, 0x81, 0x41, 0xc1, 0x21, 0xa1, 0x61, 0xe1,
 182         0x11, 0x91, 0x51, 0xd1, 0x31, 0xb1, 0x71, 0xf1,
 183         0x09, 0x89, 0x49, 0xc9, 0x29, 0xa9, 0x69, 0xe9,
 184         0x19, 0x99, 0x59, 0xd9, 0x39, 0xb9, 0x79, 0xf9,
 185         0x05, 0x85, 0x45, 0xc5, 0x25, 0xa5, 0x65, 0xe5,
 186         0x15, 0x95, 0x55, 0xd5, 0x35, 0xb5, 0x75, 0xf5,
 187         0x0d, 0x8d, 0x4d, 0xcd, 0x2d, 0xad, 0x6d, 0xed,
 188         0x1d, 0x9d, 0x5d, 0xdd, 0x3d, 0xbd, 0x7d, 0xfd,
 189         0x03, 0x83, 0x43, 0xc3, 0x23, 0xa3, 0x63, 0xe3,
 190         0x13, 0x93, 0x53, 0xd3, 0x33, 0xb3, 0x73, 0xf3,
 191         0x0b, 0x8b, 0x4b, 0xcb, 0x2b, 0xab, 0x6b, 0xeb,
 192         0x1b, 0x9b, 0x5b, 0xdb, 0x3b, 0xbb, 0x7b, 0xfb,
 193         0x07, 0x87, 0x47, 0xc7, 0x27, 0xa7, 0x67, 0xe7,
 194         0x17, 0x97, 0x57, 0xd7, 0x37, 0xb7, 0x77, 0xf7,
 195         0x0f, 0x8f, 0x4f, 0xcf, 0x2f, 0xaf, 0x6f, 0xef,
 196         0x1f, 0x9f, 0x5f, 0xdf, 0x3f, 0xbf, 0x7f, 0xff,
 197 };
 198
 199 #endif
 200
 201
 202
 203 /*
 204  * rtc_from4_hwcontrol - hardware specific access to control-lines
 205  * @mtd:        MTD device structure
 206  * @cmd:        hardware control command
 207  *
 208  * Address lines (A5 and A4) are used to control Command and Address Latch
 209  * Enable on this board, so set the read/write address appropriately.
 210  *
 211  * Chip Enable is also controlled by the Chip Select (CS5) and
 212  * Address lines (A24-A22), so no action is required here.
 213  *
 214  */
 215 static void rtc_from4_hwcontrol(struct mtd_info *mtd, int cmd)
 216 {
 217         struct nand_chip* this = (struct nand_chip *) (mtd->priv);
 218
 219         switch(cmd) {
 220
 221         case NAND_CTL_SETCLE:
 222                 this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W | RTC_FROM4_CLE);
 223                 break;
 224         case NAND_CTL_CLRCLE:
 225                 this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W & ~RTC_FROM4_CLE);
 226                 break;
 227
 228         case NAND_CTL_SETALE:
 229                 this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W | RTC_FROM4_ALE);
 230                 break;
 231         case NAND_CTL_CLRALE:
 232                 this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W & ~RTC_FROM4_ALE);
 233                 break;
 234
 235         case NAND_CTL_SETNCE:
 236                 break;
 237         case NAND_CTL_CLRNCE:
 238                 break;
 239
 240         }
 241 }
 242
 243
 244 /*
 245  * rtc_from4_nand_select_chip - hardware specific chip select
 246  * @mtd:        MTD device structure
 247  * @chip:       Chip to select (0 == slot 3, 1 == slot 4)
 248  *
 249  * The chip select is based on address lines A24-A22.
 250  * This driver uses flash slots 3 and 4 (A23-A22).
 251  *
 252  */
 253 static void rtc_from4_nand_select_chip(struct mtd_info *mtd, int chip)
 254 {
 255         struct nand_chip *this = mtd->priv;
 256
 257         this->IO_ADDR_R = (void __iomem *)((unsigned long)this->IO_ADDR_R & ~RTC_FROM4_NAND_ADDR_MASK);
 258         this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W & ~RTC_FROM4_NAND_ADDR_MASK);
 259
 260         switch(chip) {
 261
 262         case 0:         /* select slot 3 chip */
 263                 this->IO_ADDR_R = (void __iomem *)((unsigned long)this->IO_ADDR_R | RTC_FROM4_NAND_ADDR_SLOT3);
 264                 this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W | RTC_FROM4_NAND_ADDR_SLOT3);
 265                 break;
 266         case 1:         /* select slot 4 chip */
 267                 this->IO_ADDR_R = (void __iomem *)((unsigned long)this->IO_ADDR_R | RTC_FROM4_NAND_ADDR_SLOT4);
 268                 this->IO_ADDR_W = (void __iomem *)((unsigned long)this->IO_ADDR_W | RTC_FROM4_NAND_ADDR_SLOT4);
 269                 break;
 270
 271         }
 272 }
 273
 274
 275 /*
 276  * rtc_from4_nand_device_ready - hardware specific ready/busy check
 277  * @mtd:        MTD device structure
 278  *
 279  * This board provides the Ready/Busy state in the status register
 280  * of the FPGA.  Bit zero indicates the RDY(1)/BSY(0) signal.
 281  *
 282  */
 283 static int rtc_from4_nand_device_ready(struct mtd_info *mtd)
 284 {
 285         unsigned short status;
 286
 287         status = *((volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_FPGA_SR));
 288
 289         return (status & RTC_FROM4_DEVICE_READY);
 290
 291 }
 292
 293
 294 /*
 295  * deplete - code to perform device recovery in case there was a power loss
 296  * @mtd:        MTD device structure
 297  * @chip:       Chip to select (0 == slot 3, 1 == slot 4)
 298  *
 299  * If there was a sudden loss of power during an erase operation, a
 300  * "device recovery" operation must be performed when power is restored
 301  * to ensure correct operation.  This routine performs the required steps
 302  * for the requested chip.
 303  *
 304  * See page 86 of the data sheet for details.
 305  *
 306  */
 307 static void deplete(struct mtd_info *mtd, int chip)
 308 {
 309         struct nand_chip *this = mtd->priv;
 310
 311         /* wait until device is ready */
 312         while (!this->dev_ready(mtd));
 313
 314         this->select_chip(mtd, chip);
 315
 316         /* Send the commands for device recovery, phase 1 */
 317         this->cmdfunc (mtd, NAND_CMD_DEPLETE1, 0x0000, 0x0000);
 318         this->cmdfunc (mtd, NAND_CMD_DEPLETE2, -1, -1);
 319
 320         /* Send the commands for device recovery, phase 2 */
 321         this->cmdfunc (mtd, NAND_CMD_DEPLETE1, 0x0000, 0x0004);
 322         this->cmdfunc (mtd, NAND_CMD_DEPLETE2, -1, -1);
 323
 324 }
 325
 326
 327 #ifdef RTC_FROM4_HWECC
 328 /*
 329  * rtc_from4_enable_hwecc - hardware specific hardware ECC enable function
 330  * @mtd:        MTD device structure
 331  * @mode:       I/O mode; read or write
 332  *
 333  * enable hardware ECC for data read or write
 334  *
 335  */
 336 static void rtc_from4_enable_hwecc(struct mtd_info *mtd, int mode)
 337 {
 338         volatile unsigned short * rs_ecc_ctl = (volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_RS_ECC_CTL);
 339         unsigned short status;
 340
 341         switch (mode) {
 342             case NAND_ECC_READ :
 343                 status =  RTC_FROM4_RS_ECC_CTL_CLR
 344                         | RTC_FROM4_RS_ECC_CTL_FD_E;
 345
 346                 *rs_ecc_ctl = status;
 347                 break;
 348
 349             case NAND_ECC_READSYN :
 350                 status =  0x00;
 351
 352                 *rs_ecc_ctl = status;
 353                 break;
 354
 355             case NAND_ECC_WRITE :
 356                 status =  RTC_FROM4_RS_ECC_CTL_CLR
 357                         | RTC_FROM4_RS_ECC_CTL_GEN
 358                         | RTC_FROM4_RS_ECC_CTL_FD_E;
 359
 360                 *rs_ecc_ctl = status;
 361                 break;
 362
 363             default:
 364                 BUG();
 365                 break;
 366         }
 367
 368 }
 369
 370
 371 /*
 372  * rtc_from4_calculate_ecc - hardware specific code to read ECC code
 373  * @mtd:        MTD device structure
 374  * @dat:        buffer containing the data to generate ECC codes
 375  * @ecc_code    ECC codes calculated
 376  *
 377  * The ECC code is calculated by the FPGA.  All we have to do is read the values
 378  * from the FPGA registers.
 379  *
 380  * Note: We read from the inverted registers, since data is inverted before
 381  * the code is calculated. So all 0xff data (blank page) results in all 0xff rs code
 382  *
 383  */
 384 static void rtc_from4_calculate_ecc(struct mtd_info *mtd, const u_char *dat, u_char *ecc_code)
 385 {
 386         volatile unsigned short * rs_eccn = (volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_RS_ECCN);
 387         unsigned short value;
 388         int i;
 389
 390         for (i = 0; i < 8; i++) {
 391                 value = *rs_eccn;
 392                 ecc_code[i] = (unsigned char)value;
 393                 rs_eccn++;
 394         }
 395         ecc_code[7] |= 0x0f;    /* set the last four bits (not used) */
 396 }
 397
 398
 399 /*
 400  * rtc_from4_correct_data - hardware specific code to correct data using ECC code
 401  * @mtd:        MTD device structure
 402  * @buf:        buffer containing the data to generate ECC codes
 403  * @ecc1        ECC codes read
 404  * @ecc2        ECC codes calculated
 405  *
 406  * The FPGA tells us fast, if there's an error or not. If no, we go back happy
 407  * else we read the ecc results from the fpga and call the rs library to decode
 408  * and hopefully correct the error.
 409  *
 410  */
 411 static int rtc_from4_correct_data(struct mtd_info *mtd, const u_char *buf, u_char *ecc1, u_char *ecc2)
 412 {
 413         int i, j, res;
 414         unsigned short status;
 415         uint16_t par[6], syn[6];
 416         uint8_t ecc[8];
 417         volatile unsigned short *rs_ecc;
 418
 419         status = *((volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_RS_ECC_CHK));
 420
 421         if (!(status & RTC_FROM4_RS_ECC_CHK_ERROR)) {
 422                 return 0;
 423         }
 424
 425         /* Read the syndrom pattern from the FPGA and correct the bitorder */
 426         rs_ecc = (volatile unsigned short *)(rtc_from4_fio_base + RTC_FROM4_RS_ECC);
 427         for (i = 0; i < 8; i++) {
 428                 ecc[i] = revbits[(*rs_ecc) & 0xFF];
 429                 rs_ecc++;
 430         }
 431
 432         /* convert into 6 10bit syndrome fields */
 433         par[5] = rs_decoder->index_of[(((uint16_t)ecc[0] >> 0) & 0x0ff) |
 434                                       (((uint16_t)ecc[1] << 8) & 0x300)];
 435         par[4] = rs_decoder->index_of[(((uint16_t)ecc[1] >> 2) & 0x03f) |
 436                                       (((uint16_t)ecc[2] << 6) & 0x3c0)];
 437         par[3] = rs_decoder->index_of[(((uint16_t)ecc[2] >> 4) & 0x00f) |
 438                                       (((uint16_t)ecc[3] << 4) & 0x3f0)];
 439         par[2] = rs_decoder->index_of[(((uint16_t)ecc[3] >> 6) & 0x003) |
 440                                       (((uint16_t)ecc[4] << 2) & 0x3fc)];
 441         par[1] = rs_decoder->index_of[(((uint16_t)ecc[5] >> 0) & 0x0ff) |
 442                                       (((uint16_t)ecc[6] << 8) & 0x300)];
 443         par[0] = (((uint16_t)ecc[6] >> 2) & 0x03f) | (((uint16_t)ecc[7] << 6) & 0x3c0);
 444
 445         /* Convert to computable syndrome */
 446         for (i = 0; i < 6; i++) {
 447                 syn[i] = par[0];
 448                 for (j = 1; j < 6; j++)
 449                         if (par[j] != rs_decoder->nn)
 450                                 syn[i] ^= rs_decoder->alpha_to[rs_modnn(rs_decoder, par[j] + i * j)];
 451
 452                 /* Convert to index form */
 453                 syn[i] = rs_decoder->index_of[syn[i]];
 454         }
 455
 456         /* Let the library code do its magic.*/
 457         res = decode_rs8(rs_decoder, (uint8_t *)buf, par, 512, syn, 0, NULL, 0xff, NULL);
 458         if (res > 0) {
 459                 DEBUG (MTD_DEBUG_LEVEL0, "rtc_from4_correct_data: "
 460                         "ECC corrected %d errors on read\n", res);
 461         }
 462         return res;
 463 }
 464
 465
 466 /**
 467  * rtc_from4_errstat - perform additional error status checks
 468  * @mtd:        MTD device structure
 469  * @this:       NAND chip structure
 470  * @state:      state or the operation
 471  * @status:     status code returned from read status
 472  * @page:       startpage inside the chip, must be called with (page & this->pagemask)
 473  *
 474  * Perform additional error status checks on erase and write failures
 475  * to determine if errors are correctable.  For this device, correctable
 476  * 1-bit errors on erase and write are considered acceptable.
 477  *
 478  * note: see pages 34..37 of data sheet for details.
 479  *
 480  */
 481 static int rtc_from4_errstat(struct mtd_info *mtd, struct nand_chip *this, int state, int status, int page)
 482 {
 483         int     er_stat=0;
 484         int     rtn, retlen;
 485         size_t  len;
 486         uint8_t *buf;
 487         int     i;
 488
 489         this->cmdfunc (mtd, NAND_CMD_STATUS_CLEAR, -1, -1);
 490
 491         if (state == FL_ERASING) {
 492                 for (i=0; i<4; i++) {
 493                         if (status & 1<<(i+1)) {
 494                                 this->cmdfunc (mtd, (NAND_CMD_STATUS_ERROR + i + 1), -1, -1);
 495                                 rtn = this->read_byte(mtd);
 496                                 this->cmdfunc (mtd, NAND_CMD_STATUS_RESET, -1, -1);
 497                                 if (!(rtn & ERR_STAT_ECC_AVAILABLE)) {
 498                                         er_stat |= 1<<(i+1);    /* err_ecc_not_avail */
 499                                 }
 500                         }
 501                 }
 502         } else if (state == FL_WRITING) {
 503                 /* single bank write logic */
 504                 this->cmdfunc (mtd, NAND_CMD_STATUS_ERROR, -1, -1);
 505                 rtn = this->read_byte(mtd);
 506                 this->cmdfunc (mtd, NAND_CMD_STATUS_RESET, -1, -1);
 507                 if (!(rtn & ERR_STAT_ECC_AVAILABLE)) {
 508                         er_stat |= 1<<1;        /* err_ecc_not_avail */
 509                 } else {
 510                         len = mtd->oobblock;
 511                         buf = kmalloc (len, GFP_KERNEL);
 512                         if (!buf) {
 513                                 printk (KERN_ERR "rtc_from4_errstat: Out of memory!\n");
 514                                 er_stat = 1;                    /* if we can't check, assume failed */
 515                         } else {
 516                                 /* recovery read */
 517                                 /* page read */
 518                                 rtn = nand_do_read_ecc (mtd, page, len, &retlen, buf, NULL, this->autooob, 1);
 519                                 if (rtn) {      /* if read failed or > 1-bit error corrected */
 520                                         er_stat |= 1<<1;        /* ECC read failed */
 521                                 }
 522                                 kfree(buf);
 523                         }
 524                 }
 525         }
 526
 527         rtn = status;
 528         if (er_stat == 0) {                             /* if ECC is available   */
 529                 rtn = (status & ~NAND_STATUS_FAIL);     /*   clear the error bit */
 530         }
 531
 532         return rtn;
 533 }
 534 #endif
 535
 536
 537 /*
 538  * Main initialization routine
 539  */
 540 int __init rtc_from4_init (void)
 541 {
 542         struct nand_chip *this;
 543         unsigned short bcr1, bcr2, wcr2;
 544         int i;
 545
 546         /* Allocate memory for MTD device structure and private data */
 547         rtc_from4_mtd = kmalloc(sizeof(struct mtd_info) + sizeof (struct nand_chip),
 548                                 GFP_KERNEL);
 549         if (!rtc_from4_mtd) {
 550                 printk ("Unable to allocate Renesas NAND MTD device structure.\n");
 551                 return -ENOMEM;
 552         }
 553
 554         /* Get pointer to private data */
 555         this = (struct nand_chip *) (&rtc_from4_mtd[1]);
 556
 557         /* Initialize structures */
 558         memset((char *) rtc_from4_mtd, 0, sizeof(struct mtd_info));
 559         memset((char *) this, 0, sizeof(struct nand_chip));
 560
 561         /* Link the private data with the MTD structure */
 562         rtc_from4_mtd->priv = this;
 563
 564         /* set area 5 as PCMCIA mode to clear the spec of tDH(Data hold time;9ns min) */
 565         bcr1 = *SH77X9_BCR1 & ~0x0002;
 566         bcr1 |= 0x0002;
 567         *SH77X9_BCR1 = bcr1;
 568
 569         /* set */
 570         bcr2 = *SH77X9_BCR2 & ~0x0c00;
 571         bcr2 |= 0x0800;
 572         *SH77X9_BCR2 = bcr2;
 573
 574         /* set area 5 wait states */
 575         wcr2 = *SH77X9_WCR2 & ~0x1c00;
 576         wcr2 |= 0x1c00;
 577         *SH77X9_WCR2 = wcr2;
 578
 579         /* Set address of NAND IO lines */
 580         this->IO_ADDR_R = rtc_from4_fio_base;
 581         this->IO_ADDR_W = rtc_from4_fio_base;
 582         /* Set address of hardware control function */
 583         this->hwcontrol = rtc_from4_hwcontrol;
 584         /* Set address of chip select function */
 585         this->select_chip = rtc_from4_nand_select_chip;
 586         /* command delay time (in us) */
 587         this->chip_delay = 100;
 588         /* return the status of the Ready/Busy line */
 589         this->dev_ready = rtc_from4_nand_device_ready;
 590
 591 #ifdef RTC_FROM4_HWECC
 592         printk(KERN_INFO "rtc_from4_init: using hardware ECC detection.\n");
 593
 594         this->eccmode = NAND_ECC_HW8_512;
 595         this->options |= NAND_HWECC_SYNDROME;
 596         /* return the status of extra status and ECC checks */
 597         this->errstat = rtc_from4_errstat;
 598         /* set the nand_oobinfo to support FPGA H/W error detection */
 599         this->autooob = &rtc_from4_nand_oobinfo;
 600         this->enable_hwecc = rtc_from4_enable_hwecc;
 601         this->calculate_ecc = rtc_from4_calculate_ecc;
 602         this->correct_data = rtc_from4_correct_data;
 603 #else
 604         printk(KERN_INFO "rtc_from4_init: using software ECC detection.\n");
 605
 606         this->eccmode = NAND_ECC_SOFT;
 607 #endif
 608
 609         /* set the bad block tables to support debugging */
 610         this->bbt_td = &rtc_from4_bbt_main_descr;
 611         this->bbt_md = &rtc_from4_bbt_mirror_descr;
 612
 613         /* Scan to find existence of the device */
 614         if (nand_scan(rtc_from4_mtd, RTC_FROM4_MAX_CHIPS)) {
 615                 kfree(rtc_from4_mtd);
 616                 return -ENXIO;
 617         }
 618
 619         /* Perform 'device recovery' for each chip in case there was a power loss. */
 620         for (i=0; i < this->numchips; i++) {
 621                 deplete(rtc_from4_mtd, i);
 622         }
 623
 624 #if RTC_FROM4_NO_VIRTBLOCKS
 625         /* use a smaller erase block to minimize wasted space when a block is bad */
 626         /* note: this uses eight times as much RAM as using the default and makes */
 627         /*       mounts take four times as long. */
 628         rtc_from4_mtd->flags |= MTD_NO_VIRTBLOCKS;
 629 #endif
 630
 631         /* Register the partitions */
 632         add_mtd_partitions(rtc_from4_mtd, partition_info, NUM_PARTITIONS);
 633
 634 #ifdef RTC_FROM4_HWECC
 635         /* We could create the decoder on demand, if memory is a concern.
 636          * This way we have it handy, if an error happens
 637          *
 638          * Symbolsize is 10 (bits)
 639          * Primitve polynomial is x^10+x^3+1
 640          * first consecutive root is 0
 641          * primitve element to generate roots = 1
 642          * generator polinomial degree = 6
 643          */
 644         rs_decoder = init_rs(10, 0x409, 0, 1, 6);
 645         if (!rs_decoder) {
 646                 printk (KERN_ERR "Could not create a RS decoder\n");
 647                 nand_release(rtc_from4_mtd);
 648                 kfree(rtc_from4_mtd);
 649                 return -ENOMEM;
 650         }
 651 #endif
 652         /* Return happy */
 653         return 0;
 654 }
 655 module_init(rtc_from4_init);
 656
 657
 658 /*
 659  * Clean up routine
 660  */
 661 #ifdef MODULE
 662 static void __exit rtc_from4_cleanup (void)
 663 {
 664         /* Release resource, unregister partitions */
 665         nand_release(rtc_from4_mtd);
 666
 667         /* Free the MTD device structure */
 668         kfree (rtc_from4_mtd);
 669
 670 #ifdef RTC_FROM4_HWECC
 671         /* Free the reed solomon resources */
 672         if (rs_decoder) {
 673                 free_rs(rs_decoder);
 674         }
 675 #endif
 676 }
 677 module_exit(rtc_from4_cleanup);
 678 #endif
 679
 680 MODULE_LICENSE("GPL");
 681 MODULE_AUTHOR("d.marlin <dmarlin@redhat.com");
 682 MODULE_DESCRIPTION("Board-specific glue layer for AG-AND flash on Renesas FROM_BOARD4");
 683