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[PATCH] W1: w1_netlink: New init/fini netlink callbacks.
[linux-2.6/verdex.git] / drivers / s390 / crypto / z90main.c
blob6aeef3bacc3345407c1fa0b061585feb003722b9
1 /*
2 * linux/drivers/s390/crypto/z90main.c
3 *
4 * z90crypt 1.3.2
5 *
6 * Copyright (C) 2001, 2004 IBM Corporation
7 * Author(s): Robert Burroughs (burrough@us.ibm.com)
8 * Eric Rossman (edrossma@us.ibm.com)
9 *
10 * Hotplug & misc device support: Jochen Roehrig (roehrig@de.ibm.com)
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2, or (at your option)
15 * any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 */
26
27 #include <asm/uaccess.h> // copy_(from|to)_user
28 #include <linux/compat.h>
29 #include <linux/compiler.h>
30 #include <linux/delay.h> // mdelay
31 #include <linux/init.h>
32 #include <linux/interrupt.h> // for tasklets
33 #include <linux/ioctl32.h>
34 #include <linux/miscdevice.h>
35 #include <linux/module.h>
36 #include <linux/moduleparam.h>
37 #include <linux/kobject_uevent.h>
38 #include <linux/proc_fs.h>
39 #include <linux/syscalls.h>
40 #include <linux/version.h>
41 #include "z90crypt.h"
42 #include "z90common.h"
43
44 #define VERSION_Z90MAIN_C "$Revision: 1.62 $"
45
46 static char z90main_version[] __initdata =
47 "z90main.o (" VERSION_Z90MAIN_C "/"
48 VERSION_Z90COMMON_H "/" VERSION_Z90CRYPT_H ")";
49
50 extern char z90hardware_version[];
51
52 /**
53 * Defaults that may be modified.
54 */
55
56 /**
57 * You can specify a different minor at compile time.
58 */
59 #ifndef Z90CRYPT_MINOR
60 #define Z90CRYPT_MINOR MISC_DYNAMIC_MINOR
61 #endif
62
63 /**
64 * You can specify a different domain at compile time or on the insmod
65 * command line.
66 */
67 #ifndef DOMAIN_INDEX
68 #define DOMAIN_INDEX -1
69 #endif
70
71 /**
72 * This is the name under which the device is registered in /proc/modules.
73 */
74 #define REG_NAME "z90crypt"
75
76 /**
77 * Cleanup should run every CLEANUPTIME seconds and should clean up requests
78 * older than CLEANUPTIME seconds in the past.
79 */
80 #ifndef CLEANUPTIME
81 #define CLEANUPTIME 15
82 #endif
83
84 /**
85 * Config should run every CONFIGTIME seconds
86 */
87 #ifndef CONFIGTIME
88 #define CONFIGTIME 30
89 #endif
90
91 /**
92 * The first execution of the config task should take place
93 * immediately after initialization
94 */
95 #ifndef INITIAL_CONFIGTIME
96 #define INITIAL_CONFIGTIME 1
97 #endif
98
99 /**
100 * Reader should run every READERTIME milliseconds
101 * With the 100Hz patch for s390, z90crypt can lock the system solid while
102 * under heavy load. We'll try to avoid that.
103 */
104 #ifndef READERTIME
105 #if HZ > 1000
106 #define READERTIME 2
107 #else
108 #define READERTIME 10
109 #endif
110 #endif
111
112 /**
113 * turn long device array index into device pointer
114 */
115 #define LONG2DEVPTR(ndx) (z90crypt.device_p[(ndx)])
116
117 /**
118 * turn short device array index into long device array index
119 */
120 #define SHRT2LONG(ndx) (z90crypt.overall_device_x.device_index[(ndx)])
121
122 /**
123 * turn short device array index into device pointer
124 */
125 #define SHRT2DEVPTR(ndx) LONG2DEVPTR(SHRT2LONG(ndx))
126
127 /**
128 * Status for a work-element
129 */
130 #define STAT_DEFAULT 0x00 // request has not been processed
131
132 #define STAT_ROUTED 0x80 // bit 7: requests get routed to specific device
133 // else, device is determined each write
134 #define STAT_FAILED 0x40 // bit 6: this bit is set if the request failed
135 // before being sent to the hardware.
136 #define STAT_WRITTEN 0x30 // bits 5-4: work to be done, not sent to device
137 // 0x20 // UNUSED state
138 #define STAT_READPEND 0x10 // bits 5-4: work done, we're returning data now
139 #define STAT_NOWORK 0x00 // bits off: no work on any queue
140 #define STAT_RDWRMASK 0x30 // mask for bits 5-4
141
142 /**
143 * Macros to check the status RDWRMASK
144 */
145 #define CHK_RDWRMASK(statbyte) ((statbyte) & STAT_RDWRMASK)
146 #define SET_RDWRMASK(statbyte, newval) \
147 {(statbyte) &= ~STAT_RDWRMASK; (statbyte) |= newval;}
148
149 /**
150 * Audit Trail. Progress of a Work element
151 * audit[0]: Unless noted otherwise, these bits are all set by the process
152 */
153 #define FP_COPYFROM 0x80 // Caller's buffer has been copied to work element
154 #define FP_BUFFREQ 0x40 // Low Level buffer requested
155 #define FP_BUFFGOT 0x20 // Low Level buffer obtained
156 #define FP_SENT 0x10 // Work element sent to a crypto device
157 // (may be set by process or by reader task)
158 #define FP_PENDING 0x08 // Work element placed on pending queue
159 // (may be set by process or by reader task)
160 #define FP_REQUEST 0x04 // Work element placed on request queue
161 #define FP_ASLEEP 0x02 // Work element about to sleep
162 #define FP_AWAKE 0x01 // Work element has been awakened
163
164 /**
165 * audit[1]: These bits are set by the reader task and/or the cleanup task
166 */
167 #define FP_NOTPENDING 0x80 // Work element removed from pending queue
168 #define FP_AWAKENING 0x40 // Caller about to be awakened
169 #define FP_TIMEDOUT 0x20 // Caller timed out
170 #define FP_RESPSIZESET 0x10 // Response size copied to work element
171 #define FP_RESPADDRCOPIED 0x08 // Response address copied to work element
172 #define FP_RESPBUFFCOPIED 0x04 // Response buffer copied to work element
173 #define FP_REMREQUEST 0x02 // Work element removed from request queue
174 #define FP_SIGNALED 0x01 // Work element was awakened by a signal
175
176 /**
177 * audit[2]: unused
178 */
179
180 /**
181 * state of the file handle in private_data.status
182 */
183 #define STAT_OPEN 0
184 #define STAT_CLOSED 1
185
186 /**
187 * PID() expands to the process ID of the current process
188 */
189 #define PID() (current->pid)
190
191 /**
192 * Selected Constants. The number of APs and the number of devices
193 */
194 #ifndef Z90CRYPT_NUM_APS
195 #define Z90CRYPT_NUM_APS 64
196 #endif
197 #ifndef Z90CRYPT_NUM_DEVS
198 #define Z90CRYPT_NUM_DEVS Z90CRYPT_NUM_APS
199 #endif
200
201 /**
202 * Buffer size for receiving responses. The maximum Response Size
203 * is actually the maximum request size, since in an error condition
204 * the request itself may be returned unchanged.
205 */
206 #define MAX_RESPONSE_SIZE 0x0000077C
207
208 /**
209 * A count and status-byte mask
210 */
211 struct status {
212 int st_count; // # of enabled devices
213 int disabled_count; // # of disabled devices
214 int user_disabled_count; // # of devices disabled via proc fs
215 unsigned char st_mask[Z90CRYPT_NUM_APS]; // current status mask
216 };
217
218 /**
219 * The array of device indexes is a mechanism for fast indexing into
220 * a long (and sparse) array. For instance, if APs 3, 9 and 47 are
221 * installed, z90CDeviceIndex[0] is 3, z90CDeviceIndex[1] is 9, and
222 * z90CDeviceIndex[2] is 47.
223 */
224 struct device_x {
225 int device_index[Z90CRYPT_NUM_DEVS];
226 };
227
228 /**
229 * All devices are arranged in a single array: 64 APs
230 */
231 struct device {
232 int dev_type; // PCICA, PCICC, PCIXCC_MCL2,
233 // PCIXCC_MCL3, CEX2C
234 enum devstat dev_stat; // current device status
235 int dev_self_x; // Index in array
236 int disabled; // Set when device is in error
237 int user_disabled; // Set when device is disabled by user
238 int dev_q_depth; // q depth
239 unsigned char * dev_resp_p; // Response buffer address
240 int dev_resp_l; // Response Buffer length
241 int dev_caller_count; // Number of callers
242 int dev_total_req_cnt; // # requests for device since load
243 struct list_head dev_caller_list; // List of callers
244 };
245
246 /**
247 * There's a struct status and a struct device_x for each device type.
248 */
249 struct hdware_block {
250 struct status hdware_mask;
251 struct status type_mask[Z90CRYPT_NUM_TYPES];
252 struct device_x type_x_addr[Z90CRYPT_NUM_TYPES];
253 unsigned char device_type_array[Z90CRYPT_NUM_APS];
254 };
255
256 /**
257 * z90crypt is the topmost data structure in the hierarchy.
258 */
259 struct z90crypt {
260 int max_count; // Nr of possible crypto devices
261 struct status mask;
262 int q_depth_array[Z90CRYPT_NUM_DEVS];
263 int dev_type_array[Z90CRYPT_NUM_DEVS];
264 struct device_x overall_device_x; // array device indexes
265 struct device * device_p[Z90CRYPT_NUM_DEVS];
266 int terminating;
267 int domain_established;// TRUE: domain has been found
268 int cdx; // Crypto Domain Index
269 int len; // Length of this data structure
270 struct hdware_block *hdware_info;
271 };
272
273 /**
274 * An array of these structures is pointed to from dev_caller
275 * The length of the array depends on the device type. For APs,
276 * there are 8.
277 *
278 * The caller buffer is allocated to the user at OPEN. At WRITE,
279 * it contains the request; at READ, the response. The function
280 * send_to_crypto_device converts the request to device-dependent
281 * form and use the caller's OPEN-allocated buffer for the response.
282 *
283 * For the contents of caller_dev_dep_req and caller_dev_dep_req_p
284 * because that points to it, see the discussion in z90hardware.c.
285 * Search for "extended request message block".
286 */
287 struct caller {
288 int caller_buf_l; // length of original request
289 unsigned char * caller_buf_p; // Original request on WRITE
290 int caller_dev_dep_req_l; // len device dependent request
291 unsigned char * caller_dev_dep_req_p; // Device dependent form
292 unsigned char caller_id[8]; // caller-supplied message id
293 struct list_head caller_liste;
294 unsigned char caller_dev_dep_req[MAX_RESPONSE_SIZE];
295 };
296
297 /**
298 * Function prototypes from z90hardware.c
299 */
300 enum hdstat query_online(int, int, int, int *, int *);
301 enum devstat reset_device(int, int, int);
302 enum devstat send_to_AP(int, int, int, unsigned char *);
303 enum devstat receive_from_AP(int, int, int, unsigned char *, unsigned char *);
304 int convert_request(unsigned char *, int, short, int, int, int *,
305 unsigned char *);
306 int convert_response(unsigned char *, unsigned char *, int *, unsigned char *);
307
308 /**
309 * Low level function prototypes
310 */
311 static int create_z90crypt(int *);
312 static int refresh_z90crypt(int *);
313 static int find_crypto_devices(struct status *);
314 static int create_crypto_device(int);
315 static int destroy_crypto_device(int);
316 static void destroy_z90crypt(void);
317 static int refresh_index_array(struct status *, struct device_x *);
318 static int probe_device_type(struct device *);
319 static int probe_PCIXCC_type(struct device *);
320
321 /**
322 * proc fs definitions
323 */
324 static struct proc_dir_entry *z90crypt_entry;
325
326 /**
327 * data structures
328 */
329
330 /**
331 * work_element.opener points back to this structure
332 */
333 struct priv_data {
334 pid_t opener_pid;
335 unsigned char status; // 0: open 1: closed
336 };
337
338 /**
339 * A work element is allocated for each request
340 */
341 struct work_element {
342 struct priv_data *priv_data;
343 pid_t pid;
344 int devindex; // index of device processing this w_e
345 // (If request did not specify device,
346 // -1 until placed onto a queue)
347 int devtype;
348 struct list_head liste; // used for requestq and pendingq
349 char buffer[128]; // local copy of user request
350 int buff_size; // size of the buffer for the request
351 char resp_buff[RESPBUFFSIZE];
352 int resp_buff_size;
353 char __user * resp_addr; // address of response in user space
354 unsigned int funccode; // function code of request
355 wait_queue_head_t waitq;
356 unsigned long requestsent; // time at which the request was sent
357 atomic_t alarmrung; // wake-up signal
358 unsigned char caller_id[8]; // pid + counter, for this w_e
359 unsigned char status[1]; // bits to mark status of the request
360 unsigned char audit[3]; // record of work element's progress
361 unsigned char * requestptr; // address of request buffer
362 int retcode; // return code of request
363 };
364
365 /**
366 * High level function prototypes
367 */
368 static int z90crypt_open(struct inode *, struct file *);
369 static int z90crypt_release(struct inode *, struct file *);
370 static ssize_t z90crypt_read(struct file *, char __user *, size_t, loff_t *);
371 static ssize_t z90crypt_write(struct file *, const char __user *,
372 size_t, loff_t *);
373 static long z90crypt_unlocked_ioctl(struct file *, unsigned int, unsigned long);
374 static long z90crypt_compat_ioctl(struct file *, unsigned int, unsigned long);
375
376 static void z90crypt_reader_task(unsigned long);
377 static void z90crypt_schedule_reader_task(unsigned long);
378 static void z90crypt_config_task(unsigned long);
379 static void z90crypt_cleanup_task(unsigned long);
380
381 static int z90crypt_status(char *, char **, off_t, int, int *, void *);
382 static int z90crypt_status_write(struct file *, const char __user *,
383 unsigned long, void *);
384
385 /**
386 * Storage allocated at initialization and used throughout the life of
387 * this insmod
388 */
389 static int domain = DOMAIN_INDEX;
390 static struct z90crypt z90crypt;
391 static int quiesce_z90crypt;
392 static spinlock_t queuespinlock;
393 static struct list_head request_list;
394 static int requestq_count;
395 static struct list_head pending_list;
396 static int pendingq_count;
397
398 static struct tasklet_struct reader_tasklet;
399 static struct timer_list reader_timer;
400 static struct timer_list config_timer;
401 static struct timer_list cleanup_timer;
402 static atomic_t total_open;
403 static atomic_t z90crypt_step;
404
405 static struct file_operations z90crypt_fops = {
406 .owner = THIS_MODULE,
407 .read = z90crypt_read,
408 .write = z90crypt_write,
409 .unlocked_ioctl = z90crypt_unlocked_ioctl,
410 #ifdef CONFIG_COMPAT
411 .compat_ioctl = z90crypt_compat_ioctl,
412 #endif
413 .open = z90crypt_open,
414 .release = z90crypt_release
415 };
416
417 static struct miscdevice z90crypt_misc_device = {
418 .minor = Z90CRYPT_MINOR,
419 .name = DEV_NAME,
420 .fops = &z90crypt_fops,
421 .devfs_name = DEV_NAME
422 };
423
424 /**
425 * Documentation values.
426 */
427 MODULE_AUTHOR("zSeries Linux Crypto Team: Robert H. Burroughs, Eric D. Rossman"
428 "and Jochen Roehrig");
429 MODULE_DESCRIPTION("zSeries Linux Cryptographic Coprocessor device driver, "
430 "Copyright 2001, 2004 IBM Corporation");
431 MODULE_LICENSE("GPL");
432 module_param(domain, int, 0);
433 MODULE_PARM_DESC(domain, "domain index for device");
434
435 #ifdef CONFIG_COMPAT
436 /**
437 * ioctl32 conversion routines
438 */
439 struct ica_rsa_modexpo_32 { // For 32-bit callers
440 compat_uptr_t inputdata;
441 unsigned int inputdatalength;
442 compat_uptr_t outputdata;
443 unsigned int outputdatalength;
444 compat_uptr_t b_key;
445 compat_uptr_t n_modulus;
446 };
447
448 static long
449 trans_modexpo32(struct file *filp, unsigned int cmd, unsigned long arg)
450 {
451 struct ica_rsa_modexpo_32 __user *mex32u = compat_ptr(arg);
452 struct ica_rsa_modexpo_32 mex32k;
453 struct ica_rsa_modexpo __user *mex64;
454 long ret = 0;
455 unsigned int i;
456
457 if (!access_ok(VERIFY_WRITE, mex32u, sizeof(struct ica_rsa_modexpo_32)))
458 return -EFAULT;
459 mex64 = compat_alloc_user_space(sizeof(struct ica_rsa_modexpo));
460 if (!access_ok(VERIFY_WRITE, mex64, sizeof(struct ica_rsa_modexpo)))
461 return -EFAULT;
462 if (copy_from_user(&mex32k, mex32u, sizeof(struct ica_rsa_modexpo_32)))
463 return -EFAULT;
464 if (__put_user(compat_ptr(mex32k.inputdata), &mex64->inputdata) ||
465 __put_user(mex32k.inputdatalength, &mex64->inputdatalength) ||
466 __put_user(compat_ptr(mex32k.outputdata), &mex64->outputdata) ||
467 __put_user(mex32k.outputdatalength, &mex64->outputdatalength) ||
468 __put_user(compat_ptr(mex32k.b_key), &mex64->b_key) ||
469 __put_user(compat_ptr(mex32k.n_modulus), &mex64->n_modulus))
470 return -EFAULT;
471 ret = z90crypt_unlocked_ioctl(filp, cmd, (unsigned long)mex64);
472 if (!ret)
473 if (__get_user(i, &mex64->outputdatalength) ||
474 __put_user(i, &mex32u->outputdatalength))
475 ret = -EFAULT;
476 return ret;
477 }
478
479 struct ica_rsa_modexpo_crt_32 { // For 32-bit callers
480 compat_uptr_t inputdata;
481 unsigned int inputdatalength;
482 compat_uptr_t outputdata;
483 unsigned int outputdatalength;
484 compat_uptr_t bp_key;
485 compat_uptr_t bq_key;
486 compat_uptr_t np_prime;
487 compat_uptr_t nq_prime;
488 compat_uptr_t u_mult_inv;
489 };
490
491 static long
492 trans_modexpo_crt32(struct file *filp, unsigned int cmd, unsigned long arg)
493 {
494 struct ica_rsa_modexpo_crt_32 __user *crt32u = compat_ptr(arg);
495 struct ica_rsa_modexpo_crt_32 crt32k;
496 struct ica_rsa_modexpo_crt __user *crt64;
497 long ret = 0;
498 unsigned int i;
499
500 if (!access_ok(VERIFY_WRITE, crt32u,
501 sizeof(struct ica_rsa_modexpo_crt_32)))
502 return -EFAULT;
503 crt64 = compat_alloc_user_space(sizeof(struct ica_rsa_modexpo_crt));
504 if (!access_ok(VERIFY_WRITE, crt64, sizeof(struct ica_rsa_modexpo_crt)))
505 return -EFAULT;
506 if (copy_from_user(&crt32k, crt32u,
507 sizeof(struct ica_rsa_modexpo_crt_32)))
508 return -EFAULT;
509 if (__put_user(compat_ptr(crt32k.inputdata), &crt64->inputdata) ||
510 __put_user(crt32k.inputdatalength, &crt64->inputdatalength) ||
511 __put_user(compat_ptr(crt32k.outputdata), &crt64->outputdata) ||
512 __put_user(crt32k.outputdatalength, &crt64->outputdatalength) ||
513 __put_user(compat_ptr(crt32k.bp_key), &crt64->bp_key) ||
514 __put_user(compat_ptr(crt32k.bq_key), &crt64->bq_key) ||
515 __put_user(compat_ptr(crt32k.np_prime), &crt64->np_prime) ||
516 __put_user(compat_ptr(crt32k.nq_prime), &crt64->nq_prime) ||
517 __put_user(compat_ptr(crt32k.u_mult_inv), &crt64->u_mult_inv))
518 return -EFAULT;
519 ret = z90crypt_unlocked_ioctl(filp, cmd, (unsigned long)crt64);
520 if (!ret)
521 if (__get_user(i, &crt64->outputdatalength) ||
522 __put_user(i, &crt32u->outputdatalength))
523 ret = -EFAULT;
524 return ret;
525 }
526
527 static long
528 z90crypt_compat_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
529 {
530 switch (cmd) {
531 case ICAZ90STATUS:
532 case Z90QUIESCE:
533 case Z90STAT_TOTALCOUNT:
534 case Z90STAT_PCICACOUNT:
535 case Z90STAT_PCICCCOUNT:
536 case Z90STAT_PCIXCCCOUNT:
537 case Z90STAT_PCIXCCMCL2COUNT:
538 case Z90STAT_PCIXCCMCL3COUNT:
539 case Z90STAT_CEX2CCOUNT:
540 case Z90STAT_REQUESTQ_COUNT:
541 case Z90STAT_PENDINGQ_COUNT:
542 case Z90STAT_TOTALOPEN_COUNT:
543 case Z90STAT_DOMAIN_INDEX:
544 case Z90STAT_STATUS_MASK:
545 case Z90STAT_QDEPTH_MASK:
546 case Z90STAT_PERDEV_REQCNT:
547 return z90crypt_unlocked_ioctl(filp, cmd, arg);
548 case ICARSAMODEXPO:
549 return trans_modexpo32(filp, cmd, arg);
550 case ICARSACRT:
551 return trans_modexpo_crt32(filp, cmd, arg);
552 default:
553 return -ENOIOCTLCMD;
554 }
555 }
556 #endif
557
558 /**
559 * The module initialization code.
560 */
561 static int __init
562 z90crypt_init_module(void)
563 {
564 int result, nresult;
565 struct proc_dir_entry *entry;
566
567 PDEBUG("PID %d\n", PID());
568
569 if ((domain < -1) || (domain > 15)) {
570 PRINTKW("Invalid param: domain = %d. Not loading.\n", domain);
571 return -EINVAL;
572 }
573
574 /* Register as misc device with given minor (or get a dynamic one). */
575 result = misc_register(&z90crypt_misc_device);
576 if (result < 0) {
577 PRINTKW(KERN_ERR "misc_register (minor %d) failed with %d\n",
578 z90crypt_misc_device.minor, result);
579 return result;
580 }
581
582 PDEBUG("Registered " DEV_NAME " with result %d\n", result);
583
584 result = create_z90crypt(&domain);
585 if (result != 0) {
586 PRINTKW("create_z90crypt (domain index %d) failed with %d.\n",
587 domain, result);
588 result = -ENOMEM;
589 goto init_module_cleanup;
590 }
591
592 if (result == 0) {
593 PRINTKN("Version %d.%d.%d loaded, built on %s %s\n",
594 z90crypt_VERSION, z90crypt_RELEASE, z90crypt_VARIANT,
595 __DATE__, __TIME__);
596 PRINTKN("%s\n", z90main_version);
597 PRINTKN("%s\n", z90hardware_version);
598 PDEBUG("create_z90crypt (domain index %d) successful.\n",
599 domain);
600 } else
601 PRINTK("No devices at startup\n");
602
603 /* Initialize globals. */
604 spin_lock_init(&queuespinlock);
605
606 INIT_LIST_HEAD(&pending_list);
607 pendingq_count = 0;
608
609 INIT_LIST_HEAD(&request_list);
610 requestq_count = 0;
611
612 quiesce_z90crypt = 0;
613
614 atomic_set(&total_open, 0);
615 atomic_set(&z90crypt_step, 0);
616
617 /* Set up the cleanup task. */
618 init_timer(&cleanup_timer);
619 cleanup_timer.function = z90crypt_cleanup_task;
620 cleanup_timer.data = 0;
621 cleanup_timer.expires = jiffies + (CLEANUPTIME * HZ);
622 add_timer(&cleanup_timer);
623
624 /* Set up the proc file system */
625 entry = create_proc_entry("driver/z90crypt", 0644, 0);
626 if (entry) {
627 entry->nlink = 1;
628 entry->data = 0;
629 entry->read_proc = z90crypt_status;
630 entry->write_proc = z90crypt_status_write;
631 }
632 else
633 PRINTK("Couldn't create z90crypt proc entry\n");
634 z90crypt_entry = entry;
635
636 /* Set up the configuration task. */
637 init_timer(&config_timer);
638 config_timer.function = z90crypt_config_task;
639 config_timer.data = 0;
640 config_timer.expires = jiffies + (INITIAL_CONFIGTIME * HZ);
641 add_timer(&config_timer);
642
643 /* Set up the reader task */
644 tasklet_init(&reader_tasklet, z90crypt_reader_task, 0);
645 init_timer(&reader_timer);
646 reader_timer.function = z90crypt_schedule_reader_task;
647 reader_timer.data = 0;
648 reader_timer.expires = jiffies + (READERTIME * HZ / 1000);
649 add_timer(&reader_timer);
650
651 return 0; // success
652
653 init_module_cleanup:
654 if ((nresult = misc_deregister(&z90crypt_misc_device)))
655 PRINTK("misc_deregister failed with %d.\n", nresult);
656 else
657 PDEBUG("misc_deregister successful.\n");
658
659 return result; // failure
660 }
661
662 /**
663 * The module termination code
664 */
665 static void __exit
666 z90crypt_cleanup_module(void)
667 {
668 int nresult;
669
670 PDEBUG("PID %d\n", PID());
671
672 remove_proc_entry("driver/z90crypt", 0);
673
674 if ((nresult = misc_deregister(&z90crypt_misc_device)))
675 PRINTK("misc_deregister failed with %d.\n", nresult);
676 else
677 PDEBUG("misc_deregister successful.\n");
678
679 /* Remove the tasks */
680 tasklet_kill(&reader_tasklet);
681 del_timer(&reader_timer);
682 del_timer(&config_timer);
683 del_timer(&cleanup_timer);
684
685 if (z90_device_work)
686 destroy_workqueue(z90_device_work);
687
688 destroy_z90crypt();
689
690 PRINTKN("Unloaded.\n");
691 }
692
693 /**
694 * Functions running under a process id
695 *
696 * The I/O functions:
697 * z90crypt_open
698 * z90crypt_release
699 * z90crypt_read
700 * z90crypt_write
701 * z90crypt_unlocked_ioctl
702 * z90crypt_status
703 * z90crypt_status_write
704 * disable_card
705 * enable_card
706 *
707 * Helper functions:
708 * z90crypt_rsa
709 * z90crypt_prepare
710 * z90crypt_send
711 * z90crypt_process_results
712 *
713 */
714 static int
715 z90crypt_open(struct inode *inode, struct file *filp)
716 {
717 struct priv_data *private_data_p;
718
719 if (quiesce_z90crypt)
720 return -EQUIESCE;
721
722 private_data_p = kmalloc(sizeof(struct priv_data), GFP_KERNEL);
723 if (!private_data_p) {
724 PRINTK("Memory allocate failed\n");
725 return -ENOMEM;
726 }
727
728 memset((void *)private_data_p, 0, sizeof(struct priv_data));
729 private_data_p->status = STAT_OPEN;
730 private_data_p->opener_pid = PID();
731 filp->private_data = private_data_p;
732 atomic_inc(&total_open);
733
734 return 0;
735 }
736
737 static int
738 z90crypt_release(struct inode *inode, struct file *filp)
739 {
740 struct priv_data *private_data_p = filp->private_data;
741
742 PDEBUG("PID %d (filp %p)\n", PID(), filp);
743
744 private_data_p->status = STAT_CLOSED;
745 memset(private_data_p, 0, sizeof(struct priv_data));
746 kfree(private_data_p);
747 atomic_dec(&total_open);
748
749 return 0;
750 }
751
752 /*
753 * there are two read functions, of which compile options will choose one
754 * without USE_GET_RANDOM_BYTES
755 * => read() always returns -EPERM;
756 * otherwise
757 * => read() uses get_random_bytes() kernel function
758 */
759 #ifndef USE_GET_RANDOM_BYTES
760 /**
761 * z90crypt_read will not be supported beyond z90crypt 1.3.1
762 */
763 static ssize_t
764 z90crypt_read(struct file *filp, char __user *buf, size_t count, loff_t *f_pos)
765 {
766 PDEBUG("filp %p (PID %d)\n", filp, PID());
767 return -EPERM;
768 }
769 #else // we want to use get_random_bytes
770 /**
771 * read() just returns a string of random bytes. Since we have no way
772 * to generate these cryptographically, we just execute get_random_bytes
773 * for the length specified.
774 */
775 #include <linux/random.h>
776 static ssize_t
777 z90crypt_read(struct file *filp, char __user *buf, size_t count, loff_t *f_pos)
778 {
779 unsigned char *temp_buff;
780
781 PDEBUG("filp %p (PID %d)\n", filp, PID());
782
783 if (quiesce_z90crypt)
784 return -EQUIESCE;
785 if (count < 0) {
786 PRINTK("Requested random byte count negative: %ld\n", count);
787 return -EINVAL;
788 }
789 if (count > RESPBUFFSIZE) {
790 PDEBUG("count[%d] > RESPBUFFSIZE", count);
791 return -EINVAL;
792 }
793 if (count == 0)
794 return 0;
795 temp_buff = kmalloc(RESPBUFFSIZE, GFP_KERNEL);
796 if (!temp_buff) {
797 PRINTK("Memory allocate failed\n");
798 return -ENOMEM;
799 }
800 get_random_bytes(temp_buff, count);
801
802 if (copy_to_user(buf, temp_buff, count) != 0) {
803 kfree(temp_buff);
804 return -EFAULT;
805 }
806 kfree(temp_buff);
807 return count;
808 }
809 #endif
810
811 /**
812 * Write is is not allowed
813 */
814 static ssize_t
815 z90crypt_write(struct file *filp, const char __user *buf, size_t count, loff_t *f_pos)
816 {
817 PDEBUG("filp %p (PID %d)\n", filp, PID());
818 return -EPERM;
819 }
820
821 /**
822 * New status functions
823 */
824 static inline int
825 get_status_totalcount(void)
826 {
827 return z90crypt.hdware_info->hdware_mask.st_count;
828 }
829
830 static inline int
831 get_status_PCICAcount(void)
832 {
833 return z90crypt.hdware_info->type_mask[PCICA].st_count;
834 }
835
836 static inline int
837 get_status_PCICCcount(void)
838 {
839 return z90crypt.hdware_info->type_mask[PCICC].st_count;
840 }
841
842 static inline int
843 get_status_PCIXCCcount(void)
844 {
845 return z90crypt.hdware_info->type_mask[PCIXCC_MCL2].st_count +
846 z90crypt.hdware_info->type_mask[PCIXCC_MCL3].st_count;
847 }
848
849 static inline int
850 get_status_PCIXCCMCL2count(void)
851 {
852 return z90crypt.hdware_info->type_mask[PCIXCC_MCL2].st_count;
853 }
854
855 static inline int
856 get_status_PCIXCCMCL3count(void)
857 {
858 return z90crypt.hdware_info->type_mask[PCIXCC_MCL3].st_count;
859 }
860
861 static inline int
862 get_status_CEX2Ccount(void)
863 {
864 return z90crypt.hdware_info->type_mask[CEX2C].st_count;
865 }
866
867 static inline int
868 get_status_requestq_count(void)
869 {
870 return requestq_count;
871 }
872
873 static inline int
874 get_status_pendingq_count(void)
875 {
876 return pendingq_count;
877 }
878
879 static inline int
880 get_status_totalopen_count(void)
881 {
882 return atomic_read(&total_open);
883 }
884
885 static inline int
886 get_status_domain_index(void)
887 {
888 return z90crypt.cdx;
889 }
890
891 static inline unsigned char *
892 get_status_status_mask(unsigned char status[Z90CRYPT_NUM_APS])
893 {
894 int i, ix;
895
896 memcpy(status, z90crypt.hdware_info->device_type_array,
897 Z90CRYPT_NUM_APS);
898
899 for (i = 0; i < get_status_totalcount(); i++) {
900 ix = SHRT2LONG(i);
901 if (LONG2DEVPTR(ix)->user_disabled)
902 status[ix] = 0x0d;
903 }
904
905 return status;
906 }
907
908 static inline unsigned char *
909 get_status_qdepth_mask(unsigned char qdepth[Z90CRYPT_NUM_APS])
910 {
911 int i, ix;
912
913 memset(qdepth, 0, Z90CRYPT_NUM_APS);
914
915 for (i = 0; i < get_status_totalcount(); i++) {
916 ix = SHRT2LONG(i);
917 qdepth[ix] = LONG2DEVPTR(ix)->dev_caller_count;
918 }
919
920 return qdepth;
921 }
922
923 static inline unsigned int *
924 get_status_perdevice_reqcnt(unsigned int reqcnt[Z90CRYPT_NUM_APS])
925 {
926 int i, ix;
927
928 memset(reqcnt, 0, Z90CRYPT_NUM_APS * sizeof(int));
929
930 for (i = 0; i < get_status_totalcount(); i++) {
931 ix = SHRT2LONG(i);
932 reqcnt[ix] = LONG2DEVPTR(ix)->dev_total_req_cnt;
933 }
934
935 return reqcnt;
936 }
937
938 static inline void
939 init_work_element(struct work_element *we_p,
940 struct priv_data *priv_data, pid_t pid)
941 {
942 int step;
943
944 we_p->requestptr = (unsigned char *)we_p + sizeof(struct work_element);
945 /* Come up with a unique id for this caller. */
946 step = atomic_inc_return(&z90crypt_step);
947 memcpy(we_p->caller_id+0, (void *) &pid, sizeof(pid));
948 memcpy(we_p->caller_id+4, (void *) &step, sizeof(step));
949 we_p->pid = pid;
950 we_p->priv_data = priv_data;
951 we_p->status[0] = STAT_DEFAULT;
952 we_p->audit[0] = 0x00;
953 we_p->audit[1] = 0x00;
954 we_p->audit[2] = 0x00;
955 we_p->resp_buff_size = 0;
956 we_p->retcode = 0;
957 we_p->devindex = -1;
958 we_p->devtype = -1;
959 atomic_set(&we_p->alarmrung, 0);
960 init_waitqueue_head(&we_p->waitq);
961 INIT_LIST_HEAD(&(we_p->liste));
962 }
963
964 static inline int
965 allocate_work_element(struct work_element **we_pp,
966 struct priv_data *priv_data_p, pid_t pid)
967 {
968 struct work_element *we_p;
969
970 we_p = (struct work_element *) get_zeroed_page(GFP_KERNEL);
971 if (!we_p)
972 return -ENOMEM;
973 init_work_element(we_p, priv_data_p, pid);
974 *we_pp = we_p;
975 return 0;
976 }
977
978 static inline void
979 remove_device(struct device *device_p)
980 {
981 if (!device_p || (device_p->disabled != 0))
982 return;
983 device_p->disabled = 1;
984 z90crypt.hdware_info->type_mask[device_p->dev_type].disabled_count++;
985 z90crypt.hdware_info->hdware_mask.disabled_count++;
986 }
987
988 /**
989 * Bitlength limits for each card
990 *
991 * There are new MCLs which allow more bitlengths. See the table for details.
992 * The MCL must be applied and the newer bitlengths enabled for these to work.
993 *
994 * Card Type Old limit New limit
995 * PCICA ??-2048 same (the lower limit is less than 128 bit...)
996 * PCICC 512-1024 512-2048
997 * PCIXCC_MCL2 512-2048 ----- (applying any GA LIC will make an MCL3 card)
998 * PCIXCC_MCL3 ----- 128-2048
999 * CEX2C 512-2048 128-2048
1000 *
1001 * ext_bitlens (extended bitlengths) is a global, since you should not apply an
1002 * MCL to just one card in a machine. We assume, at first, that all cards have
1003 * these capabilities.
1004 */
1005 int ext_bitlens = 1; // This is global
1006 #define PCIXCC_MIN_MOD_SIZE 16 // 128 bits
1007 #define OLD_PCIXCC_MIN_MOD_SIZE 64 // 512 bits
1008 #define PCICC_MIN_MOD_SIZE 64 // 512 bits
1009 #define OLD_PCICC_MAX_MOD_SIZE 128 // 1024 bits
1010 #define MAX_MOD_SIZE 256 // 2048 bits
1011
1012 static inline int
1013 select_device_type(int *dev_type_p, int bytelength)
1014 {
1015 static int count = 0;
1016 int PCICA_avail, PCIXCC_MCL3_avail, CEX2C_avail, index_to_use;
1017 struct status *stat;
1018 if ((*dev_type_p != PCICC) && (*dev_type_p != PCICA) &&
1019 (*dev_type_p != PCIXCC_MCL2) && (*dev_type_p != PCIXCC_MCL3) &&
1020 (*dev_type_p != CEX2C) && (*dev_type_p != ANYDEV))
1021 return -1;
1022 if (*dev_type_p != ANYDEV) {
1023 stat = &z90crypt.hdware_info->type_mask[*dev_type_p];
1024 if (stat->st_count >
1025 (stat->disabled_count + stat->user_disabled_count))
1026 return 0;
1027 return -1;
1028 }
1029
1030 /* Assumption: PCICA, PCIXCC_MCL3, and CEX2C are all similar in speed */
1031 stat = &z90crypt.hdware_info->type_mask[PCICA];
1032 PCICA_avail = stat->st_count -
1033 (stat->disabled_count + stat->user_disabled_count);
1034 stat = &z90crypt.hdware_info->type_mask[PCIXCC_MCL3];
1035 PCIXCC_MCL3_avail = stat->st_count -
1036 (stat->disabled_count + stat->user_disabled_count);
1037 stat = &z90crypt.hdware_info->type_mask[CEX2C];
1038 CEX2C_avail = stat->st_count -
1039 (stat->disabled_count + stat->user_disabled_count);
1040 if (PCICA_avail || PCIXCC_MCL3_avail || CEX2C_avail) {
1041 /**
1042 * bitlength is a factor, PCICA is the most capable, even with
1043 * the new MCL for PCIXCC.
1044 */
1045 if ((bytelength < PCIXCC_MIN_MOD_SIZE) ||
1046 (!ext_bitlens && (bytelength < OLD_PCIXCC_MIN_MOD_SIZE))) {
1047 if (!PCICA_avail)
1048 return -1;
1049 else {
1050 *dev_type_p = PCICA;
1051 return 0;
1052 }
1053 }
1054
1055 index_to_use = count % (PCICA_avail + PCIXCC_MCL3_avail +
1056 CEX2C_avail);
1057 if (index_to_use < PCICA_avail)
1058 *dev_type_p = PCICA;
1059 else if (index_to_use < (PCICA_avail + PCIXCC_MCL3_avail))
1060 *dev_type_p = PCIXCC_MCL3;
1061 else
1062 *dev_type_p = CEX2C;
1063 count++;
1064 return 0;
1065 }
1066
1067 /* Less than OLD_PCIXCC_MIN_MOD_SIZE cannot go to a PCIXCC_MCL2 */
1068 if (bytelength < OLD_PCIXCC_MIN_MOD_SIZE)
1069 return -1;
1070 stat = &z90crypt.hdware_info->type_mask[PCIXCC_MCL2];
1071 if (stat->st_count >
1072 (stat->disabled_count + stat->user_disabled_count)) {
1073 *dev_type_p = PCIXCC_MCL2;
1074 return 0;
1075 }
1076
1077 /**
1078 * Less than PCICC_MIN_MOD_SIZE or more than OLD_PCICC_MAX_MOD_SIZE
1079 * (if we don't have the MCL applied and the newer bitlengths enabled)
1080 * cannot go to a PCICC
1081 */
1082 if ((bytelength < PCICC_MIN_MOD_SIZE) ||
1083 (!ext_bitlens && (bytelength > OLD_PCICC_MAX_MOD_SIZE))) {
1084 return -1;
1085 }
1086 stat = &z90crypt.hdware_info->type_mask[PCICC];
1087 if (stat->st_count >
1088 (stat->disabled_count + stat->user_disabled_count)) {
1089 *dev_type_p = PCICC;
1090 return 0;
1091 }
1092
1093 return -1;
1094 }
1095
1096 /**
1097 * Try the selected number, then the selected type (can be ANYDEV)
1098 */
1099 static inline int
1100 select_device(int *dev_type_p, int *device_nr_p, int bytelength)
1101 {
1102 int i, indx, devTp, low_count, low_indx;
1103 struct device_x *index_p;
1104 struct device *dev_ptr;
1105
1106 PDEBUG("device type = %d, index = %d\n", *dev_type_p, *device_nr_p);
1107 if ((*device_nr_p >= 0) && (*device_nr_p < Z90CRYPT_NUM_DEVS)) {
1108 PDEBUG("trying index = %d\n", *device_nr_p);
1109 dev_ptr = z90crypt.device_p[*device_nr_p];
1110
1111 if (dev_ptr &&
1112 (dev_ptr->dev_stat != DEV_GONE) &&
1113 (dev_ptr->disabled == 0) &&
1114 (dev_ptr->user_disabled == 0)) {
1115 PDEBUG("selected by number, index = %d\n",
1116 *device_nr_p);
1117 *dev_type_p = dev_ptr->dev_type;
1118 return *device_nr_p;
1119 }
1120 }
1121 *device_nr_p = -1;
1122 PDEBUG("trying type = %d\n", *dev_type_p);
1123 devTp = *dev_type_p;
1124 if (select_device_type(&devTp, bytelength) == -1) {
1125 PDEBUG("failed to select by type\n");
1126 return -1;
1127 }
1128 PDEBUG("selected type = %d\n", devTp);
1129 index_p = &z90crypt.hdware_info->type_x_addr[devTp];
1130 low_count = 0x0000FFFF;
1131 low_indx = -1;
1132 for (i = 0; i < z90crypt.hdware_info->type_mask[devTp].st_count; i++) {
1133 indx = index_p->device_index[i];
1134 dev_ptr = z90crypt.device_p[indx];
1135 if (dev_ptr &&
1136 (dev_ptr->dev_stat != DEV_GONE) &&
1137 (dev_ptr->disabled == 0) &&
1138 (dev_ptr->user_disabled == 0) &&
1139 (devTp == dev_ptr->dev_type) &&
1140 (low_count > dev_ptr->dev_caller_count)) {
1141 low_count = dev_ptr->dev_caller_count;
1142 low_indx = indx;
1143 }
1144 }
1145 *device_nr_p = low_indx;
1146 return low_indx;
1147 }
1148
1149 static inline int
1150 send_to_crypto_device(struct work_element *we_p)
1151 {
1152 struct caller *caller_p;
1153 struct device *device_p;
1154 int dev_nr;
1155 int bytelen = ((struct ica_rsa_modexpo *)we_p->buffer)->inputdatalength;
1156
1157 if (!we_p->requestptr)
1158 return SEN_FATAL_ERROR;
1159 caller_p = (struct caller *)we_p->requestptr;
1160 dev_nr = we_p->devindex;
1161 if (select_device(&we_p->devtype, &dev_nr, bytelen) == -1) {
1162 if (z90crypt.hdware_info->hdware_mask.st_count != 0)
1163 return SEN_RETRY;
1164 else
1165 return SEN_NOT_AVAIL;
1166 }
1167 we_p->devindex = dev_nr;
1168 device_p = z90crypt.device_p[dev_nr];
1169 if (!device_p)
1170 return SEN_NOT_AVAIL;
1171 if (device_p->dev_type != we_p->devtype)
1172 return SEN_RETRY;
1173 if (device_p->dev_caller_count >= device_p->dev_q_depth)
1174 return SEN_QUEUE_FULL;
1175 PDEBUG("device number prior to send: %d\n", dev_nr);
1176 switch (send_to_AP(dev_nr, z90crypt.cdx,
1177 caller_p->caller_dev_dep_req_l,
1178 caller_p->caller_dev_dep_req_p)) {
1179 case DEV_SEN_EXCEPTION:
1180 PRINTKC("Exception during send to device %d\n", dev_nr);
1181 z90crypt.terminating = 1;
1182 return SEN_FATAL_ERROR;
1183 case DEV_GONE:
1184 PRINTK("Device %d not available\n", dev_nr);
1185 remove_device(device_p);
1186 return SEN_NOT_AVAIL;
1187 case DEV_EMPTY:
1188 return SEN_NOT_AVAIL;
1189 case DEV_NO_WORK:
1190 return SEN_FATAL_ERROR;
1191 case DEV_BAD_MESSAGE:
1192 return SEN_USER_ERROR;
1193 case DEV_QUEUE_FULL:
1194 return SEN_QUEUE_FULL;
1195 default:
1196 case DEV_ONLINE:
1197 break;
1198 }
1199 list_add_tail(&(caller_p->caller_liste), &(device_p->dev_caller_list));
1200 device_p->dev_caller_count++;
1201 return 0;
1202 }
1203
1204 /**
1205 * Send puts the user's work on one of two queues:
1206 * the pending queue if the send was successful
1207 * the request queue if the send failed because device full or busy
1208 */
1209 static inline int
1210 z90crypt_send(struct work_element *we_p, const char *buf)
1211 {
1212 int rv;
1213
1214 PDEBUG("PID %d\n", PID());
1215
1216 if (CHK_RDWRMASK(we_p->status[0]) != STAT_NOWORK) {
1217 PDEBUG("PID %d tried to send more work but has outstanding "
1218 "work.\n", PID());
1219 return -EWORKPEND;
1220 }
1221 we_p->devindex = -1; // Reset device number
1222 spin_lock_irq(&queuespinlock);
1223 rv = send_to_crypto_device(we_p);
1224 switch (rv) {
1225 case 0:
1226 we_p->requestsent = jiffies;
1227 we_p->audit[0] |= FP_SENT;
1228 list_add_tail(&we_p->liste, &pending_list);
1229 ++pendingq_count;
1230 we_p->audit[0] |= FP_PENDING;
1231 break;
1232 case SEN_BUSY:
1233 case SEN_QUEUE_FULL:
1234 rv = 0;
1235 we_p->devindex = -1; // any device will do
1236 we_p->requestsent = jiffies;
1237 list_add_tail(&we_p->liste, &request_list);
1238 ++requestq_count;
1239 we_p->audit[0] |= FP_REQUEST;
1240 break;
1241 case SEN_RETRY:
1242 rv = -ERESTARTSYS;
1243 break;
1244 case SEN_NOT_AVAIL:
1245 PRINTK("*** No devices available.\n");
1246 rv = we_p->retcode = -ENODEV;
1247 we_p->status[0] |= STAT_FAILED;
1248 break;
1249 case REC_OPERAND_INV:
1250 case REC_OPERAND_SIZE:
1251 case REC_EVEN_MOD:
1252 case REC_INVALID_PAD:
1253 rv = we_p->retcode = -EINVAL;
1254 we_p->status[0] |= STAT_FAILED;
1255 break;
1256 default:
1257 we_p->retcode = rv;
1258 we_p->status[0] |= STAT_FAILED;
1259 break;
1260 }
1261 if (rv != -ERESTARTSYS)
1262 SET_RDWRMASK(we_p->status[0], STAT_WRITTEN);
1263 spin_unlock_irq(&queuespinlock);
1264 if (rv == 0)
1265 tasklet_schedule(&reader_tasklet);
1266 return rv;
1267 }
1268
1269 /**
1270 * process_results copies the user's work from kernel space.
1271 */
1272 static inline int
1273 z90crypt_process_results(struct work_element *we_p, char __user *buf)
1274 {
1275 int rv;
1276
1277 PDEBUG("we_p %p (PID %d)\n", we_p, PID());
1278
1279 LONG2DEVPTR(we_p->devindex)->dev_total_req_cnt++;
1280 SET_RDWRMASK(we_p->status[0], STAT_READPEND);
1281
1282 rv = 0;
1283 if (!we_p->buffer) {
1284 PRINTK("we_p %p PID %d in STAT_READPEND: buffer NULL.\n",
1285 we_p, PID());
1286 rv = -ENOBUFF;
1287 }
1288
1289 if (!rv)
1290 if ((rv = copy_to_user(buf, we_p->buffer, we_p->buff_size))) {
1291 PDEBUG("copy_to_user failed: rv = %d\n", rv);
1292 rv = -EFAULT;
1293 }
1294
1295 if (!rv)
1296 rv = we_p->retcode;
1297 if (!rv)
1298 if (we_p->resp_buff_size
1299 && copy_to_user(we_p->resp_addr, we_p->resp_buff,
1300 we_p->resp_buff_size))
1301 rv = -EFAULT;
1302
1303 SET_RDWRMASK(we_p->status[0], STAT_NOWORK);
1304 return rv;
1305 }
1306
1307 static unsigned char NULL_psmid[8] =
1308 {0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00};
1309
1310 /**
1311 * Used in device configuration functions
1312 */
1313 #define MAX_RESET 90
1314
1315 /**
1316 * This is used only for PCICC support
1317 */
1318 static inline int
1319 is_PKCS11_padded(unsigned char *buffer, int length)
1320 {
1321 int i;
1322 if ((buffer[0] != 0x00) || (buffer[1] != 0x01))
1323 return 0;
1324 for (i = 2; i < length; i++)
1325 if (buffer[i] != 0xFF)
1326 break;
1327 if ((i < 10) || (i == length))
1328 return 0;
1329 if (buffer[i] != 0x00)
1330 return 0;
1331 return 1;
1332 }
1333
1334 /**
1335 * This is used only for PCICC support
1336 */
1337 static inline int
1338 is_PKCS12_padded(unsigned char *buffer, int length)
1339 {
1340 int i;
1341 if ((buffer[0] != 0x00) || (buffer[1] != 0x02))
1342 return 0;
1343 for (i = 2; i < length; i++)
1344 if (buffer[i] == 0x00)
1345 break;
1346 if ((i < 10) || (i == length))
1347 return 0;
1348 if (buffer[i] != 0x00)
1349 return 0;
1350 return 1;
1351 }
1352
1353 /**
1354 * builds struct caller and converts message from generic format to
1355 * device-dependent format
1356 * func is ICARSAMODEXPO or ICARSACRT
1357 * function is PCI_FUNC_KEY_ENCRYPT or PCI_FUNC_KEY_DECRYPT
1358 */
1359 static inline int
1360 build_caller(struct work_element *we_p, short function)
1361 {
1362 int rv;
1363 struct caller *caller_p = (struct caller *)we_p->requestptr;
1364
1365 if ((we_p->devtype != PCICC) && (we_p->devtype != PCICA) &&
1366 (we_p->devtype != PCIXCC_MCL2) && (we_p->devtype != PCIXCC_MCL3) &&
1367 (we_p->devtype != CEX2C))
1368 return SEN_NOT_AVAIL;
1369
1370 memcpy(caller_p->caller_id, we_p->caller_id,
1371 sizeof(caller_p->caller_id));
1372 caller_p->caller_dev_dep_req_p = caller_p->caller_dev_dep_req;
1373 caller_p->caller_dev_dep_req_l = MAX_RESPONSE_SIZE;
1374 caller_p->caller_buf_p = we_p->buffer;
1375 INIT_LIST_HEAD(&(caller_p->caller_liste));
1376
1377 rv = convert_request(we_p->buffer, we_p->funccode, function,
1378 z90crypt.cdx, we_p->devtype,
1379 &caller_p->caller_dev_dep_req_l,
1380 caller_p->caller_dev_dep_req_p);
1381 if (rv) {
1382 if (rv == SEN_NOT_AVAIL)
1383 PDEBUG("request can't be processed on hdwr avail\n");
1384 else
1385 PRINTK("Error from convert_request: %d\n", rv);
1386 }
1387 else
1388 memcpy(&(caller_p->caller_dev_dep_req_p[4]), we_p->caller_id,8);
1389 return rv;
1390 }
1391
1392 static inline void
1393 unbuild_caller(struct device *device_p, struct caller *caller_p)
1394 {
1395 if (!caller_p)
1396 return;
1397 if (caller_p->caller_liste.next && caller_p->caller_liste.prev)
1398 if (!list_empty(&caller_p->caller_liste)) {
1399 list_del_init(&caller_p->caller_liste);
1400 device_p->dev_caller_count--;
1401 }
1402 memset(caller_p->caller_id, 0, sizeof(caller_p->caller_id));
1403 }
1404
1405 static inline int
1406 get_crypto_request_buffer(struct work_element *we_p)
1407 {
1408 struct ica_rsa_modexpo *mex_p;
1409 struct ica_rsa_modexpo_crt *crt_p;
1410 unsigned char *temp_buffer;
1411 short function;
1412 int rv;
1413
1414 mex_p = (struct ica_rsa_modexpo *) we_p->buffer;
1415 crt_p = (struct ica_rsa_modexpo_crt *) we_p->buffer;
1416
1417 PDEBUG("device type input = %d\n", we_p->devtype);
1418
1419 if (z90crypt.terminating)
1420 return REC_NO_RESPONSE;
1421 if (memcmp(we_p->caller_id, NULL_psmid, 8) == 0) {
1422 PRINTK("psmid zeroes\n");
1423 return SEN_FATAL_ERROR;
1424 }
1425 if (!we_p->buffer) {
1426 PRINTK("buffer pointer NULL\n");
1427 return SEN_USER_ERROR;
1428 }
1429 if (!we_p->requestptr) {
1430 PRINTK("caller pointer NULL\n");
1431 return SEN_USER_ERROR;
1432 }
1433
1434 if ((we_p->devtype != PCICA) && (we_p->devtype != PCICC) &&
1435 (we_p->devtype != PCIXCC_MCL2) && (we_p->devtype != PCIXCC_MCL3) &&
1436 (we_p->devtype != CEX2C) && (we_p->devtype != ANYDEV)) {
1437 PRINTK("invalid device type\n");
1438 return SEN_USER_ERROR;
1439 }
1440
1441 if ((mex_p->inputdatalength < 1) ||
1442 (mex_p->inputdatalength > MAX_MOD_SIZE)) {
1443 PRINTK("inputdatalength[%d] is not valid\n",
1444 mex_p->inputdatalength);
1445 return SEN_USER_ERROR;
1446 }
1447
1448 if (mex_p->outputdatalength < mex_p->inputdatalength) {
1449 PRINTK("outputdatalength[%d] < inputdatalength[%d]\n",
1450 mex_p->outputdatalength, mex_p->inputdatalength);
1451 return SEN_USER_ERROR;
1452 }
1453
1454 if (!mex_p->inputdata || !mex_p->outputdata) {
1455 PRINTK("inputdata[%p] or outputdata[%p] is NULL\n",
1456 mex_p->outputdata, mex_p->inputdata);
1457 return SEN_USER_ERROR;
1458 }
1459
1460 /**
1461 * As long as outputdatalength is big enough, we can set the
1462 * outputdatalength equal to the inputdatalength, since that is the
1463 * number of bytes we will copy in any case
1464 */
1465 mex_p->outputdatalength = mex_p->inputdatalength;
1466
1467 rv = 0;
1468 switch (we_p->funccode) {
1469 case ICARSAMODEXPO:
1470 if (!mex_p->b_key || !mex_p->n_modulus)
1471 rv = SEN_USER_ERROR;
1472 break;
1473 case ICARSACRT:
1474 if (!IS_EVEN(crt_p->inputdatalength)) {
1475 PRINTK("inputdatalength[%d] is odd, CRT form\n",
1476 crt_p->inputdatalength);
1477 rv = SEN_USER_ERROR;
1478 break;
1479 }
1480 if (!crt_p->bp_key ||
1481 !crt_p->bq_key ||
1482 !crt_p->np_prime ||
1483 !crt_p->nq_prime ||
1484 !crt_p->u_mult_inv) {
1485 PRINTK("CRT form, bad data: %p/%p/%p/%p/%p\n",
1486 crt_p->bp_key, crt_p->bq_key,
1487 crt_p->np_prime, crt_p->nq_prime,
1488 crt_p->u_mult_inv);
1489 rv = SEN_USER_ERROR;
1490 }
1491 break;
1492 default:
1493 PRINTK("bad func = %d\n", we_p->funccode);
1494 rv = SEN_USER_ERROR;
1495 break;
1496 }
1497 if (rv != 0)
1498 return rv;
1499
1500 if (select_device_type(&we_p->devtype, mex_p->inputdatalength) < 0)
1501 return SEN_NOT_AVAIL;
1502
1503 temp_buffer = (unsigned char *)we_p + sizeof(struct work_element) +
1504 sizeof(struct caller);
1505 if (copy_from_user(temp_buffer, mex_p->inputdata,
1506 mex_p->inputdatalength) != 0)
1507 return SEN_RELEASED;
1508
1509 function = PCI_FUNC_KEY_ENCRYPT;
1510 switch (we_p->devtype) {
1511 /* PCICA does everything with a simple RSA mod-expo operation */
1512 case PCICA:
1513 function = PCI_FUNC_KEY_ENCRYPT;
1514 break;
1515 /**
1516 * PCIXCC_MCL2 does all Mod-Expo form with a simple RSA mod-expo
1517 * operation, and all CRT forms with a PKCS-1.2 format decrypt.
1518 * PCIXCC_MCL3 and CEX2C do all Mod-Expo and CRT forms with a simple RSA
1519 * mod-expo operation
1520 */
1521 case PCIXCC_MCL2:
1522 if (we_p->funccode == ICARSAMODEXPO)
1523 function = PCI_FUNC_KEY_ENCRYPT;
1524 else
1525 function = PCI_FUNC_KEY_DECRYPT;
1526 break;
1527 case PCIXCC_MCL3:
1528 case CEX2C:
1529 if (we_p->funccode == ICARSAMODEXPO)
1530 function = PCI_FUNC_KEY_ENCRYPT;
1531 else
1532 function = PCI_FUNC_KEY_DECRYPT;
1533 break;
1534 /**
1535 * PCICC does everything as a PKCS-1.2 format request
1536 */
1537 case PCICC:
1538 /* PCICC cannot handle input that is is PKCS#1.1 padded */
1539 if (is_PKCS11_padded(temp_buffer, mex_p->inputdatalength)) {
1540 return SEN_NOT_AVAIL;
1541 }
1542 if (we_p->funccode == ICARSAMODEXPO) {
1543 if (is_PKCS12_padded(temp_buffer,
1544 mex_p->inputdatalength))
1545 function = PCI_FUNC_KEY_ENCRYPT;
1546 else
1547 function = PCI_FUNC_KEY_DECRYPT;
1548 } else
1549 /* all CRT forms are decrypts */
1550 function = PCI_FUNC_KEY_DECRYPT;
1551 break;
1552 }
1553 PDEBUG("function: %04x\n", function);
1554 rv = build_caller(we_p, function);
1555 PDEBUG("rv from build_caller = %d\n", rv);
1556 return rv;
1557 }
1558
1559 static inline int
1560 z90crypt_prepare(struct work_element *we_p, unsigned int funccode,
1561 const char __user *buffer)
1562 {
1563 int rv;
1564
1565 we_p->devindex = -1;
1566 if (funccode == ICARSAMODEXPO)
1567 we_p->buff_size = sizeof(struct ica_rsa_modexpo);
1568 else
1569 we_p->buff_size = sizeof(struct ica_rsa_modexpo_crt);
1570
1571 if (copy_from_user(we_p->buffer, buffer, we_p->buff_size))
1572 return -EFAULT;
1573
1574 we_p->audit[0] |= FP_COPYFROM;
1575 SET_RDWRMASK(we_p->status[0], STAT_WRITTEN);
1576 we_p->funccode = funccode;
1577 we_p->devtype = -1;
1578 we_p->audit[0] |= FP_BUFFREQ;
1579 rv = get_crypto_request_buffer(we_p);
1580 switch (rv) {
1581 case 0:
1582 we_p->audit[0] |= FP_BUFFGOT;
1583 break;
1584 case SEN_USER_ERROR:
1585 rv = -EINVAL;
1586 break;
1587 case SEN_QUEUE_FULL:
1588 rv = 0;
1589 break;
1590 case SEN_RELEASED:
1591 rv = -EFAULT;
1592 break;
1593 case REC_NO_RESPONSE:
1594 rv = -ENODEV;
1595 break;
1596 case SEN_NOT_AVAIL:
1597 case EGETBUFF:
1598 rv = -EGETBUFF;
1599 break;
1600 default:
1601 PRINTK("rv = %d\n", rv);
1602 rv = -EGETBUFF;
1603 break;
1604 }
1605 if (CHK_RDWRMASK(we_p->status[0]) == STAT_WRITTEN)
1606 SET_RDWRMASK(we_p->status[0], STAT_DEFAULT);
1607 return rv;
1608 }
1609
1610 static inline void
1611 purge_work_element(struct work_element *we_p)
1612 {
1613 struct list_head *lptr;
1614
1615 spin_lock_irq(&queuespinlock);
1616 list_for_each(lptr, &request_list) {
1617 if (lptr == &we_p->liste) {
1618 list_del_init(lptr);
1619 requestq_count--;
1620 break;
1621 }
1622 }
1623 list_for_each(lptr, &pending_list) {
1624 if (lptr == &we_p->liste) {
1625 list_del_init(lptr);
1626 pendingq_count--;
1627 break;
1628 }
1629 }
1630 spin_unlock_irq(&queuespinlock);
1631 }
1632
1633 /**
1634 * Build the request and send it.
1635 */
1636 static inline int
1637 z90crypt_rsa(struct priv_data *private_data_p, pid_t pid,
1638 unsigned int cmd, unsigned long arg)
1639 {
1640 struct work_element *we_p;
1641 int rv;
1642
1643 if ((rv = allocate_work_element(&we_p, private_data_p, pid))) {
1644 PDEBUG("PID %d: allocate_work_element returned ENOMEM\n", pid);
1645 return rv;
1646 }
1647 if ((rv = z90crypt_prepare(we_p, cmd, (const char __user *)arg)))
1648 PDEBUG("PID %d: rv = %d from z90crypt_prepare\n", pid, rv);
1649 if (!rv)
1650 if ((rv = z90crypt_send(we_p, (const char *)arg)))
1651 PDEBUG("PID %d: rv %d from z90crypt_send.\n", pid, rv);
1652 if (!rv) {
1653 we_p->audit[0] |= FP_ASLEEP;
1654 wait_event(we_p->waitq, atomic_read(&we_p->alarmrung));
1655 we_p->audit[0] |= FP_AWAKE;
1656 rv = we_p->retcode;
1657 }
1658 if (!rv)
1659 rv = z90crypt_process_results(we_p, (char __user *)arg);
1660
1661 if ((we_p->status[0] & STAT_FAILED)) {
1662 switch (rv) {
1663 /**
1664 * EINVAL *after* receive is almost always a padding error or
1665 * length error issued by a coprocessor (not an accelerator).
1666 * We convert this return value to -EGETBUFF which should
1667 * trigger a fallback to software.
1668 */
1669 case -EINVAL:
1670 if (we_p->devtype != PCICA)
1671 rv = -EGETBUFF;
1672 break;
1673 case -ETIMEOUT:
1674 if (z90crypt.mask.st_count > 0)
1675 rv = -ERESTARTSYS; // retry with another
1676 else
1677 rv = -ENODEV; // no cards left
1678 /* fall through to clean up request queue */
1679 case -ERESTARTSYS:
1680 case -ERELEASED:
1681 switch (CHK_RDWRMASK(we_p->status[0])) {
1682 case STAT_WRITTEN:
1683 purge_work_element(we_p);
1684 break;
1685 case STAT_READPEND:
1686 case STAT_NOWORK:
1687 default:
1688 break;
1689 }
1690 break;
1691 default:
1692 we_p->status[0] ^= STAT_FAILED;
1693 break;
1694 }
1695 }
1696 free_page((long)we_p);
1697 return rv;
1698 }
1699
1700 /**
1701 * This function is a little long, but it's really just one large switch
1702 * statement.
1703 */
1704 static long
1705 z90crypt_unlocked_ioctl(struct file *filp, unsigned int cmd, unsigned long arg)
1706 {
1707 struct priv_data *private_data_p = filp->private_data;
1708 unsigned char *status;
1709 unsigned char *qdepth;
1710 unsigned int *reqcnt;
1711 struct ica_z90_status *pstat;
1712 int ret, i, loopLim, tempstat;
1713 static int deprecated_msg_count1 = 0;
1714 static int deprecated_msg_count2 = 0;
1715
1716 PDEBUG("filp %p (PID %d), cmd 0x%08X\n", filp, PID(), cmd);
1717 PDEBUG("cmd 0x%08X: dir %s, size 0x%04X, type 0x%02X, nr 0x%02X\n",
1718 cmd,
1719 !_IOC_DIR(cmd) ? "NO"
1720 : ((_IOC_DIR(cmd) == (_IOC_READ|_IOC_WRITE)) ? "RW"
1721 : ((_IOC_DIR(cmd) == _IOC_READ) ? "RD"
1722 : "WR")),
1723 _IOC_SIZE(cmd), _IOC_TYPE(cmd), _IOC_NR(cmd));
1724
1725 if (_IOC_TYPE(cmd) != Z90_IOCTL_MAGIC) {
1726 PRINTK("cmd 0x%08X contains bad magic\n", cmd);
1727 return -ENOTTY;
1728 }
1729
1730 ret = 0;
1731 switch (cmd) {
1732 case ICARSAMODEXPO:
1733 case ICARSACRT:
1734 if (quiesce_z90crypt) {
1735 ret = -EQUIESCE;
1736 break;
1737 }
1738 ret = -ENODEV; // Default if no devices
1739 loopLim = z90crypt.hdware_info->hdware_mask.st_count -
1740 (z90crypt.hdware_info->hdware_mask.disabled_count +
1741 z90crypt.hdware_info->hdware_mask.user_disabled_count);
1742 for (i = 0; i < loopLim; i++) {
1743 ret = z90crypt_rsa(private_data_p, PID(), cmd, arg);
1744 if (ret != -ERESTARTSYS)
1745 break;
1746 }
1747 if (ret == -ERESTARTSYS)
1748 ret = -ENODEV;
1749 break;
1750
1751 case Z90STAT_TOTALCOUNT:
1752 tempstat = get_status_totalcount();
1753 if (copy_to_user((int __user *)arg, &tempstat,sizeof(int)) != 0)
1754 ret = -EFAULT;
1755 break;
1756
1757 case Z90STAT_PCICACOUNT:
1758 tempstat = get_status_PCICAcount();
1759 if (copy_to_user((int __user *)arg, &tempstat, sizeof(int)) != 0)
1760 ret = -EFAULT;
1761 break;
1762
1763 case Z90STAT_PCICCCOUNT:
1764 tempstat = get_status_PCICCcount();
1765 if (copy_to_user((int __user *)arg, &tempstat, sizeof(int)) != 0)
1766 ret = -EFAULT;
1767 break;
1768
1769 case Z90STAT_PCIXCCMCL2COUNT:
1770 tempstat = get_status_PCIXCCMCL2count();
1771 if (copy_to_user((int __user *)arg, &tempstat, sizeof(int)) != 0)
1772 ret = -EFAULT;
1773 break;
1774
1775 case Z90STAT_PCIXCCMCL3COUNT:
1776 tempstat = get_status_PCIXCCMCL3count();
1777 if (copy_to_user((int __user *)arg, &tempstat, sizeof(int)) != 0)
1778 ret = -EFAULT;
1779 break;
1780
1781 case Z90STAT_CEX2CCOUNT:
1782 tempstat = get_status_CEX2Ccount();
1783 if (copy_to_user((int __user *)arg, &tempstat, sizeof(int)) != 0)
1784 ret = -EFAULT;
1785 break;
1786
1787 case Z90STAT_REQUESTQ_COUNT:
1788 tempstat = get_status_requestq_count();
1789 if (copy_to_user((int __user *)arg, &tempstat, sizeof(int)) != 0)
1790 ret = -EFAULT;
1791 break;
1792
1793 case Z90STAT_PENDINGQ_COUNT:
1794 tempstat = get_status_pendingq_count();
1795 if (copy_to_user((int __user *)arg, &tempstat, sizeof(int)) != 0)
1796 ret = -EFAULT;
1797 break;
1798
1799 case Z90STAT_TOTALOPEN_COUNT:
1800 tempstat = get_status_totalopen_count();
1801 if (copy_to_user((int __user *)arg, &tempstat, sizeof(int)) != 0)
1802 ret = -EFAULT;
1803 break;
1804
1805 case Z90STAT_DOMAIN_INDEX:
1806 tempstat = get_status_domain_index();
1807 if (copy_to_user((int __user *)arg, &tempstat, sizeof(int)) != 0)
1808 ret = -EFAULT;
1809 break;
1810
1811 case Z90STAT_STATUS_MASK:
1812 status = kmalloc(Z90CRYPT_NUM_APS, GFP_KERNEL);
1813 if (!status) {
1814 PRINTK("kmalloc for status failed!\n");
1815 ret = -ENOMEM;
1816 break;
1817 }
1818 get_status_status_mask(status);
1819 if (copy_to_user((char __user *) arg, status, Z90CRYPT_NUM_APS)
1820 != 0)
1821 ret = -EFAULT;
1822 kfree(status);
1823 break;
1824
1825 case Z90STAT_QDEPTH_MASK:
1826 qdepth = kmalloc(Z90CRYPT_NUM_APS, GFP_KERNEL);
1827 if (!qdepth) {
1828 PRINTK("kmalloc for qdepth failed!\n");
1829 ret = -ENOMEM;
1830 break;
1831 }
1832 get_status_qdepth_mask(qdepth);
1833 if (copy_to_user((char __user *) arg, qdepth, Z90CRYPT_NUM_APS) != 0)
1834 ret = -EFAULT;
1835 kfree(qdepth);
1836 break;
1837
1838 case Z90STAT_PERDEV_REQCNT:
1839 reqcnt = kmalloc(sizeof(int) * Z90CRYPT_NUM_APS, GFP_KERNEL);
1840 if (!reqcnt) {
1841 PRINTK("kmalloc for reqcnt failed!\n");
1842 ret = -ENOMEM;
1843 break;
1844 }
1845 get_status_perdevice_reqcnt(reqcnt);
1846 if (copy_to_user((char __user *) arg, reqcnt,
1847 Z90CRYPT_NUM_APS * sizeof(int)) != 0)
1848 ret = -EFAULT;
1849 kfree(reqcnt);
1850 break;
1851
1852 /* THIS IS DEPRECATED. USE THE NEW STATUS CALLS */
1853 case ICAZ90STATUS:
1854 if (deprecated_msg_count1 < 20) {
1855 PRINTK("deprecated call to ioctl (ICAZ90STATUS)!\n");
1856 deprecated_msg_count1++;
1857 if (deprecated_msg_count1 == 20)
1858 PRINTK("No longer issuing messages related to "
1859 "deprecated call to ICAZ90STATUS.\n");
1860 }
1861
1862 pstat = kmalloc(sizeof(struct ica_z90_status), GFP_KERNEL);
1863 if (!pstat) {
1864 PRINTK("kmalloc for pstat failed!\n");
1865 ret = -ENOMEM;
1866 break;
1867 }
1868
1869 pstat->totalcount = get_status_totalcount();
1870 pstat->leedslitecount = get_status_PCICAcount();
1871 pstat->leeds2count = get_status_PCICCcount();
1872 pstat->requestqWaitCount = get_status_requestq_count();
1873 pstat->pendingqWaitCount = get_status_pendingq_count();
1874 pstat->totalOpenCount = get_status_totalopen_count();
1875 pstat->cryptoDomain = get_status_domain_index();
1876 get_status_status_mask(pstat->status);
1877 get_status_qdepth_mask(pstat->qdepth);
1878
1879 if (copy_to_user((struct ica_z90_status __user *) arg, pstat,
1880 sizeof(struct ica_z90_status)) != 0)
1881 ret = -EFAULT;
1882 kfree(pstat);
1883 break;
1884
1885 /* THIS IS DEPRECATED. USE THE NEW STATUS CALLS */
1886 case Z90STAT_PCIXCCCOUNT:
1887 if (deprecated_msg_count2 < 20) {
1888 PRINTK("deprecated ioctl (Z90STAT_PCIXCCCOUNT)!\n");
1889 deprecated_msg_count2++;
1890 if (deprecated_msg_count2 == 20)
1891 PRINTK("No longer issuing messages about depre"
1892 "cated ioctl Z90STAT_PCIXCCCOUNT.\n");
1893 }
1894
1895 tempstat = get_status_PCIXCCcount();
1896 if (copy_to_user((int *)arg, &tempstat, sizeof(int)) != 0)
1897 ret = -EFAULT;
1898 break;
1899
1900 case Z90QUIESCE:
1901 if (current->euid != 0) {
1902 PRINTK("QUIESCE fails: euid %d\n",
1903 current->euid);
1904 ret = -EACCES;
1905 } else {
1906 PRINTK("QUIESCE device from PID %d\n", PID());
1907 quiesce_z90crypt = 1;
1908 }
1909 break;
1910
1911 default:
1912 /* user passed an invalid IOCTL number */
1913 PDEBUG("cmd 0x%08X contains invalid ioctl code\n", cmd);
1914 ret = -ENOTTY;
1915 break;
1916 }
1917
1918 return ret;
1919 }
1920
1921 static inline int
1922 sprintcl(unsigned char *outaddr, unsigned char *addr, unsigned int len)
1923 {
1924 int hl, i;
1925
1926 hl = 0;
1927 for (i = 0; i < len; i++)
1928 hl += sprintf(outaddr+hl, "%01x", (unsigned int) addr[i]);
1929 hl += sprintf(outaddr+hl, " ");
1930
1931 return hl;
1932 }
1933
1934 static inline int
1935 sprintrw(unsigned char *outaddr, unsigned char *addr, unsigned int len)
1936 {
1937 int hl, inl, c, cx;
1938
1939 hl = sprintf(outaddr, " ");
1940 inl = 0;
1941 for (c = 0; c < (len / 16); c++) {
1942 hl += sprintcl(outaddr+hl, addr+inl, 16);
1943 inl += 16;
1944 }
1945
1946 cx = len%16;
1947 if (cx) {
1948 hl += sprintcl(outaddr+hl, addr+inl, cx);
1949 inl += cx;
1950 }
1951
1952 hl += sprintf(outaddr+hl, "\n");
1953
1954 return hl;
1955 }
1956
1957 static inline int
1958 sprinthx(unsigned char *title, unsigned char *outaddr,
1959 unsigned char *addr, unsigned int len)
1960 {
1961 int hl, inl, r, rx;
1962
1963 hl = sprintf(outaddr, "\n%s\n", title);
1964 inl = 0;
1965 for (r = 0; r < (len / 64); r++) {
1966 hl += sprintrw(outaddr+hl, addr+inl, 64);
1967 inl += 64;
1968 }
1969 rx = len % 64;
1970 if (rx) {
1971 hl += sprintrw(outaddr+hl, addr+inl, rx);
1972 inl += rx;
1973 }
1974
1975 hl += sprintf(outaddr+hl, "\n");
1976
1977 return hl;
1978 }
1979
1980 static inline int
1981 sprinthx4(unsigned char *title, unsigned char *outaddr,
1982 unsigned int *array, unsigned int len)
1983 {
1984 int hl, r;
1985
1986 hl = sprintf(outaddr, "\n%s\n", title);
1987
1988 for (r = 0; r < len; r++) {
1989 if ((r % 8) == 0)
1990 hl += sprintf(outaddr+hl, " ");
1991 hl += sprintf(outaddr+hl, "%08X ", array[r]);
1992 if ((r % 8) == 7)
1993 hl += sprintf(outaddr+hl, "\n");
1994 }
1995
1996 hl += sprintf(outaddr+hl, "\n");
1997
1998 return hl;
1999 }
2000
2001 static int
2002 z90crypt_status(char *resp_buff, char **start, off_t offset,
2003 int count, int *eof, void *data)
2004 {
2005 unsigned char *workarea;
2006 int len;
2007
2008 /* resp_buff is a page. Use the right half for a work area */
2009 workarea = resp_buff+2000;
2010 len = 0;
2011 len += sprintf(resp_buff+len, "\nz90crypt version: %d.%d.%d\n",
2012 z90crypt_VERSION, z90crypt_RELEASE, z90crypt_VARIANT);
2013 len += sprintf(resp_buff+len, "Cryptographic domain: %d\n",
2014 get_status_domain_index());
2015 len += sprintf(resp_buff+len, "Total device count: %d\n",
2016 get_status_totalcount());
2017 len += sprintf(resp_buff+len, "PCICA count: %d\n",
2018 get_status_PCICAcount());
2019 len += sprintf(resp_buff+len, "PCICC count: %d\n",
2020 get_status_PCICCcount());
2021 len += sprintf(resp_buff+len, "PCIXCC MCL2 count: %d\n",
2022 get_status_PCIXCCMCL2count());
2023 len += sprintf(resp_buff+len, "PCIXCC MCL3 count: %d\n",
2024 get_status_PCIXCCMCL3count());
2025 len += sprintf(resp_buff+len, "CEX2C count: %d\n",
2026 get_status_CEX2Ccount());
2027 len += sprintf(resp_buff+len, "requestq count: %d\n",
2028 get_status_requestq_count());
2029 len += sprintf(resp_buff+len, "pendingq count: %d\n",
2030 get_status_pendingq_count());
2031 len += sprintf(resp_buff+len, "Total open handles: %d\n\n",
2032 get_status_totalopen_count());
2033 len += sprinthx(
2034 "Online devices: 1: PCICA, 2: PCICC, 3: PCIXCC (MCL2), "
2035 "4: PCIXCC (MCL3), 5: CEX2C",
2036 resp_buff+len,
2037 get_status_status_mask(workarea),
2038 Z90CRYPT_NUM_APS);
2039 len += sprinthx("Waiting work element counts",
2040 resp_buff+len,
2041 get_status_qdepth_mask(workarea),
2042 Z90CRYPT_NUM_APS);
2043 len += sprinthx4(
2044 "Per-device successfully completed request counts",
2045 resp_buff+len,
2046 get_status_perdevice_reqcnt((unsigned int *)workarea),
2047 Z90CRYPT_NUM_APS);
2048 *eof = 1;
2049 memset(workarea, 0, Z90CRYPT_NUM_APS * sizeof(unsigned int));
2050 return len;
2051 }
2052
2053 static inline void
2054 disable_card(int card_index)
2055 {
2056 struct device *devp;
2057
2058 devp = LONG2DEVPTR(card_index);
2059 if (!devp || devp->user_disabled)
2060 return;
2061 devp->user_disabled = 1;
2062 z90crypt.hdware_info->hdware_mask.user_disabled_count++;
2063 if (devp->dev_type == -1)
2064 return;
2065 z90crypt.hdware_info->type_mask[devp->dev_type].user_disabled_count++;
2066 }
2067
2068 static inline void
2069 enable_card(int card_index)
2070 {
2071 struct device *devp;
2072
2073 devp = LONG2DEVPTR(card_index);
2074 if (!devp || !devp->user_disabled)
2075 return;
2076 devp->user_disabled = 0;
2077 z90crypt.hdware_info->hdware_mask.user_disabled_count--;
2078 if (devp->dev_type == -1)
2079 return;
2080 z90crypt.hdware_info->type_mask[devp->dev_type].user_disabled_count--;
2081 }
2082
2083 static int
2084 z90crypt_status_write(struct file *file, const char __user *buffer,
2085 unsigned long count, void *data)
2086 {
2087 int j, eol;
2088 unsigned char *lbuf, *ptr;
2089 unsigned int local_count;
2090
2091 #define LBUFSIZE 1200
2092 lbuf = kmalloc(LBUFSIZE, GFP_KERNEL);
2093 if (!lbuf) {
2094 PRINTK("kmalloc failed!\n");
2095 return 0;
2096 }
2097
2098 if (count <= 0)
2099 return 0;
2100
2101 local_count = UMIN((unsigned int)count, LBUFSIZE-1);
2102
2103 if (copy_from_user(lbuf, buffer, local_count) != 0) {
2104 kfree(lbuf);
2105 return -EFAULT;
2106 }
2107
2108 lbuf[local_count] = '\0';
2109
2110 ptr = strstr(lbuf, "Online devices");
2111 if (ptr == 0) {
2112 PRINTK("Unable to parse data (missing \"Online devices\")\n");
2113 kfree(lbuf);
2114 return count;
2115 }
2116
2117 ptr = strstr(ptr, "\n");
2118 if (ptr == 0) {
2119 PRINTK("Unable to parse data (missing newline after \"Online devices\")\n");
2120 kfree(lbuf);
2121 return count;
2122 }
2123 ptr++;
2124
2125 if (strstr(ptr, "Waiting work element counts") == NULL) {
2126 PRINTK("Unable to parse data (missing \"Waiting work element counts\")\n");
2127 kfree(lbuf);
2128 return count;
2129 }
2130
2131 j = 0;
2132 eol = 0;
2133 while ((j < 64) && (*ptr != '\0')) {
2134 switch (*ptr) {
2135 case '\t':
2136 case ' ':
2137 break;
2138 case '\n':
2139 default:
2140 eol = 1;
2141 break;
2142 case '0': // no device
2143 case '1': // PCICA
2144 case '2': // PCICC
2145 case '3': // PCIXCC_MCL2
2146 case '4': // PCIXCC_MCL3
2147 case '5': // CEX2C
2148 j++;
2149 break;
2150 case 'd':
2151 case 'D':
2152 disable_card(j);
2153 j++;
2154 break;
2155 case 'e':
2156 case 'E':
2157 enable_card(j);
2158 j++;
2159 break;
2160 }
2161 if (eol)
2162 break;
2163 ptr++;
2164 }
2165
2166 kfree(lbuf);
2167 return count;
2168 }
2169
2170 /**
2171 * Functions that run under a timer, with no process id
2172 *
2173 * The task functions:
2174 * z90crypt_reader_task
2175 * helper_send_work
2176 * helper_handle_work_element
2177 * helper_receive_rc
2178 * z90crypt_config_task
2179 * z90crypt_cleanup_task
2180 *
2181 * Helper functions:
2182 * z90crypt_schedule_reader_timer
2183 * z90crypt_schedule_reader_task
2184 * z90crypt_schedule_config_task
2185 * z90crypt_schedule_cleanup_task
2186 */
2187 static inline int
2188 receive_from_crypto_device(int index, unsigned char *psmid, int *buff_len_p,
2189 unsigned char *buff, unsigned char __user **dest_p_p)
2190 {
2191 int dv, rv;
2192 struct device *dev_ptr;
2193 struct caller *caller_p;
2194 struct ica_rsa_modexpo *icaMsg_p;
2195 struct list_head *ptr, *tptr;
2196
2197 memcpy(psmid, NULL_psmid, sizeof(NULL_psmid));
2198
2199 if (z90crypt.terminating)
2200 return REC_FATAL_ERROR;
2201
2202 caller_p = 0;
2203 dev_ptr = z90crypt.device_p[index];
2204 rv = 0;
2205 do {
2206 if (!dev_ptr || dev_ptr->disabled) {
2207 rv = REC_NO_WORK; // a disabled device can't return work
2208 break;
2209 }
2210 if (dev_ptr->dev_self_x != index) {
2211 PRINTKC("Corrupt dev ptr\n");
2212 z90crypt.terminating = 1;
2213 rv = REC_FATAL_ERROR;
2214 break;
2215 }
2216 if (!dev_ptr->dev_resp_l || !dev_ptr->dev_resp_p) {
2217 dv = DEV_REC_EXCEPTION;
2218 PRINTK("dev_resp_l = %d, dev_resp_p = %p\n",
2219 dev_ptr->dev_resp_l, dev_ptr->dev_resp_p);
2220 } else {
2221 PDEBUG("Dequeue called for device %d\n", index);
2222 dv = receive_from_AP(index, z90crypt.cdx,
2223 dev_ptr->dev_resp_l,
2224 dev_ptr->dev_resp_p, psmid);
2225 }
2226 switch (dv) {
2227 case DEV_REC_EXCEPTION:
2228 rv = REC_FATAL_ERROR;
2229 z90crypt.terminating = 1;
2230 PRINTKC("Exception in receive from device %d\n",
2231 index);
2232 break;
2233 case DEV_ONLINE:
2234 rv = 0;
2235 break;
2236 case DEV_EMPTY:
2237 rv = REC_EMPTY;
2238 break;
2239 case DEV_NO_WORK:
2240 rv = REC_NO_WORK;
2241 break;
2242 case DEV_BAD_MESSAGE:
2243 case DEV_GONE:
2244 case REC_HARDWAR_ERR:
2245 default:
2246 rv = REC_NO_RESPONSE;
2247 break;
2248 }
2249 if (rv)
2250 break;
2251 if (dev_ptr->dev_caller_count <= 0) {
2252 rv = REC_USER_GONE;
2253 break;
2254 }
2255
2256 list_for_each_safe(ptr, tptr, &dev_ptr->dev_caller_list) {
2257 caller_p = list_entry(ptr, struct caller, caller_liste);
2258 if (!memcmp(caller_p->caller_id, psmid,
2259 sizeof(caller_p->caller_id))) {
2260 if (!list_empty(&caller_p->caller_liste)) {
2261 list_del_init(ptr);
2262 dev_ptr->dev_caller_count--;
2263 break;
2264 }
2265 }
2266 caller_p = 0;
2267 }
2268 if (!caller_p) {
2269 PRINTKW("Unable to locate PSMID %02X%02X%02X%02X%02X"
2270 "%02X%02X%02X in device list\n",
2271 psmid[0], psmid[1], psmid[2], psmid[3],
2272 psmid[4], psmid[5], psmid[6], psmid[7]);
2273 rv = REC_USER_GONE;
2274 break;
2275 }
2276
2277 PDEBUG("caller_p after successful receive: %p\n", caller_p);
2278 rv = convert_response(dev_ptr->dev_resp_p,
2279 caller_p->caller_buf_p, buff_len_p, buff);
2280 switch (rv) {
2281 case REC_USE_PCICA:
2282 break;
2283 case REC_OPERAND_INV:
2284 case REC_OPERAND_SIZE:
2285 case REC_EVEN_MOD:
2286 case REC_INVALID_PAD:
2287 PDEBUG("device %d: 'user error' %d\n", index, rv);
2288 break;
2289 case WRONG_DEVICE_TYPE:
2290 case REC_HARDWAR_ERR:
2291 case REC_BAD_MESSAGE:
2292 PRINTKW("device %d: hardware error %d\n", index, rv);
2293 rv = REC_NO_RESPONSE;
2294 break;
2295 default:
2296 PDEBUG("device %d: rv = %d\n", index, rv);
2297 break;
2298 }
2299 } while (0);
2300
2301 switch (rv) {
2302 case 0:
2303 PDEBUG("Successful receive from device %d\n", index);
2304 icaMsg_p = (struct ica_rsa_modexpo *)caller_p->caller_buf_p;
2305 *dest_p_p = icaMsg_p->outputdata;
2306 if (*buff_len_p == 0)
2307 PRINTK("Zero *buff_len_p\n");
2308 break;
2309 case REC_NO_RESPONSE:
2310 PRINTKW("Removing device %d from availability\n", index);
2311 remove_device(dev_ptr);
2312 break;
2313 }
2314
2315 if (caller_p)
2316 unbuild_caller(dev_ptr, caller_p);
2317
2318 return rv;
2319 }
2320
2321 static inline void
2322 helper_send_work(int index)
2323 {
2324 struct work_element *rq_p;
2325 int rv;
2326
2327 if (list_empty(&request_list))
2328 return;
2329 requestq_count--;
2330 rq_p = list_entry(request_list.next, struct work_element, liste);
2331 list_del_init(&rq_p->liste);
2332 rq_p->audit[1] |= FP_REMREQUEST;
2333 if (rq_p->devtype == SHRT2DEVPTR(index)->dev_type) {
2334 rq_p->devindex = SHRT2LONG(index);
2335 rv = send_to_crypto_device(rq_p);
2336 if (rv == 0) {
2337 rq_p->requestsent = jiffies;
2338 rq_p->audit[0] |= FP_SENT;
2339 list_add_tail(&rq_p->liste, &pending_list);
2340 ++pendingq_count;
2341 rq_p->audit[0] |= FP_PENDING;
2342 } else {
2343 switch (rv) {
2344 case REC_OPERAND_INV:
2345 case REC_OPERAND_SIZE:
2346 case REC_EVEN_MOD:
2347 case REC_INVALID_PAD:
2348 rq_p->retcode = -EINVAL;
2349 break;
2350 case SEN_NOT_AVAIL:
2351 case SEN_RETRY:
2352 case REC_NO_RESPONSE:
2353 default:
2354 if (z90crypt.mask.st_count > 1)
2355 rq_p->retcode =
2356 -ERESTARTSYS;
2357 else
2358 rq_p->retcode = -ENODEV;
2359 break;
2360 }
2361 rq_p->status[0] |= STAT_FAILED;
2362 rq_p->audit[1] |= FP_AWAKENING;
2363 atomic_set(&rq_p->alarmrung, 1);
2364 wake_up(&rq_p->waitq);
2365 }
2366 } else {
2367 if (z90crypt.mask.st_count > 1)
2368 rq_p->retcode = -ERESTARTSYS;
2369 else
2370 rq_p->retcode = -ENODEV;
2371 rq_p->status[0] |= STAT_FAILED;
2372 rq_p->audit[1] |= FP_AWAKENING;
2373 atomic_set(&rq_p->alarmrung, 1);
2374 wake_up(&rq_p->waitq);
2375 }
2376 }
2377
2378 static inline void
2379 helper_handle_work_element(int index, unsigned char psmid[8], int rc,
2380 int buff_len, unsigned char *buff,
2381 unsigned char __user *resp_addr)
2382 {
2383 struct work_element *pq_p;
2384 struct list_head *lptr, *tptr;
2385
2386 pq_p = 0;
2387 list_for_each_safe(lptr, tptr, &pending_list) {
2388 pq_p = list_entry(lptr, struct work_element, liste);
2389 if (!memcmp(pq_p->caller_id, psmid, sizeof(pq_p->caller_id))) {
2390 list_del_init(lptr);
2391 pendingq_count--;
2392 pq_p->audit[1] |= FP_NOTPENDING;
2393 break;
2394 }
2395 pq_p = 0;
2396 }
2397
2398 if (!pq_p) {
2399 PRINTK("device %d has work but no caller exists on pending Q\n",
2400 SHRT2LONG(index));
2401 return;
2402 }
2403
2404 switch (rc) {
2405 case 0:
2406 pq_p->resp_buff_size = buff_len;
2407 pq_p->audit[1] |= FP_RESPSIZESET;
2408 if (buff_len) {
2409 pq_p->resp_addr = resp_addr;
2410 pq_p->audit[1] |= FP_RESPADDRCOPIED;
2411 memcpy(pq_p->resp_buff, buff, buff_len);
2412 pq_p->audit[1] |= FP_RESPBUFFCOPIED;
2413 }
2414 break;
2415 case REC_OPERAND_INV:
2416 case REC_OPERAND_SIZE:
2417 case REC_EVEN_MOD:
2418 case REC_INVALID_PAD:
2419 PDEBUG("-EINVAL after application error %d\n", rc);
2420 pq_p->retcode = -EINVAL;
2421 pq_p->status[0] |= STAT_FAILED;
2422 break;
2423 case REC_USE_PCICA:
2424 pq_p->retcode = -ERESTARTSYS;
2425 pq_p->status[0] |= STAT_FAILED;
2426 break;
2427 case REC_NO_RESPONSE:
2428 default:
2429 if (z90crypt.mask.st_count > 1)
2430 pq_p->retcode = -ERESTARTSYS;
2431 else
2432 pq_p->retcode = -ENODEV;
2433 pq_p->status[0] |= STAT_FAILED;
2434 break;
2435 }
2436 if ((pq_p->status[0] != STAT_FAILED) || (pq_p->retcode != -ERELEASED)) {
2437 pq_p->audit[1] |= FP_AWAKENING;
2438 atomic_set(&pq_p->alarmrung, 1);
2439 wake_up(&pq_p->waitq);
2440 }
2441 }
2442
2443 /**
2444 * return TRUE if the work element should be removed from the queue
2445 */
2446 static inline int
2447 helper_receive_rc(int index, int *rc_p)
2448 {
2449 switch (*rc_p) {
2450 case 0:
2451 case REC_OPERAND_INV:
2452 case REC_OPERAND_SIZE:
2453 case REC_EVEN_MOD:
2454 case REC_INVALID_PAD:
2455 case REC_USE_PCICA:
2456 break;
2457
2458 case REC_BUSY:
2459 case REC_NO_WORK:
2460 case REC_EMPTY:
2461 case REC_RETRY_DEV:
2462 case REC_FATAL_ERROR:
2463 return 0;
2464
2465 case REC_NO_RESPONSE:
2466 break;
2467
2468 default:
2469 PRINTK("rc %d, device %d converted to REC_NO_RESPONSE\n",
2470 *rc_p, SHRT2LONG(index));
2471 *rc_p = REC_NO_RESPONSE;
2472 break;
2473 }
2474 return 1;
2475 }
2476
2477 static inline void
2478 z90crypt_schedule_reader_timer(void)
2479 {
2480 if (timer_pending(&reader_timer))
2481 return;
2482 if (mod_timer(&reader_timer, jiffies+(READERTIME*HZ/1000)) != 0)
2483 PRINTK("Timer pending while modifying reader timer\n");
2484 }
2485
2486 static void
2487 z90crypt_reader_task(unsigned long ptr)
2488 {
2489 int workavail, index, rc, buff_len;
2490 unsigned char psmid[8];
2491 unsigned char __user *resp_addr;
2492 static unsigned char buff[1024];
2493
2494 /**
2495 * we use workavail = 2 to ensure 2 passes with nothing dequeued before
2496 * exiting the loop. If (pendingq_count+requestq_count) == 0 after the
2497 * loop, there is no work remaining on the queues.
2498 */
2499 resp_addr = 0;
2500 workavail = 2;
2501 buff_len = 0;
2502 while (workavail) {
2503 workavail--;
2504 rc = 0;
2505 spin_lock_irq(&queuespinlock);
2506 memset(buff, 0x00, sizeof(buff));
2507
2508 /* Dequeue once from each device in round robin. */
2509 for (index = 0; index < z90crypt.mask.st_count; index++) {
2510 PDEBUG("About to receive.\n");
2511 rc = receive_from_crypto_device(SHRT2LONG(index),
2512 psmid,
2513 &buff_len,
2514 buff,
2515 &resp_addr);
2516 PDEBUG("Dequeued: rc = %d.\n", rc);
2517
2518 if (helper_receive_rc(index, &rc)) {
2519 if (rc != REC_NO_RESPONSE) {
2520 helper_send_work(index);
2521 workavail = 2;
2522 }
2523
2524 helper_handle_work_element(index, psmid, rc,
2525 buff_len, buff,
2526 resp_addr);
2527 }
2528
2529 if (rc == REC_FATAL_ERROR)
2530 PRINTKW("REC_FATAL_ERROR from device %d!\n",
2531 SHRT2LONG(index));
2532 }
2533 spin_unlock_irq(&queuespinlock);
2534 }
2535
2536 if (pendingq_count + requestq_count)
2537 z90crypt_schedule_reader_timer();
2538 }
2539
2540 static inline void
2541 z90crypt_schedule_config_task(unsigned int expiration)
2542 {
2543 if (timer_pending(&config_timer))
2544 return;
2545 if (mod_timer(&config_timer, jiffies+(expiration*HZ)) != 0)
2546 PRINTK("Timer pending while modifying config timer\n");
2547 }
2548
2549 static void
2550 z90crypt_config_task(unsigned long ptr)
2551 {
2552 int rc;
2553
2554 PDEBUG("jiffies %ld\n", jiffies);
2555
2556 if ((rc = refresh_z90crypt(&z90crypt.cdx)))
2557 PRINTK("Error %d detected in refresh_z90crypt.\n", rc);
2558 /* If return was fatal, don't bother reconfiguring */
2559 if ((rc != TSQ_FATAL_ERROR) && (rc != RSQ_FATAL_ERROR))
2560 z90crypt_schedule_config_task(CONFIGTIME);
2561 }
2562
2563 static inline void
2564 z90crypt_schedule_cleanup_task(void)
2565 {
2566 if (timer_pending(&cleanup_timer))
2567 return;
2568 if (mod_timer(&cleanup_timer, jiffies+(CLEANUPTIME*HZ)) != 0)
2569 PRINTK("Timer pending while modifying cleanup timer\n");
2570 }
2571
2572 static inline void
2573 helper_drain_queues(void)
2574 {
2575 struct work_element *pq_p;
2576 struct list_head *lptr, *tptr;
2577
2578 list_for_each_safe(lptr, tptr, &pending_list) {
2579 pq_p = list_entry(lptr, struct work_element, liste);
2580 pq_p->retcode = -ENODEV;
2581 pq_p->status[0] |= STAT_FAILED;
2582 unbuild_caller(LONG2DEVPTR(pq_p->devindex),
2583 (struct caller *)pq_p->requestptr);
2584 list_del_init(lptr);
2585 pendingq_count--;
2586 pq_p->audit[1] |= FP_NOTPENDING;
2587 pq_p->audit[1] |= FP_AWAKENING;
2588 atomic_set(&pq_p->alarmrung, 1);
2589 wake_up(&pq_p->waitq);
2590 }
2591
2592 list_for_each_safe(lptr, tptr, &request_list) {
2593 pq_p = list_entry(lptr, struct work_element, liste);
2594 pq_p->retcode = -ENODEV;
2595 pq_p->status[0] |= STAT_FAILED;
2596 list_del_init(lptr);
2597 requestq_count--;
2598 pq_p->audit[1] |= FP_REMREQUEST;
2599 pq_p->audit[1] |= FP_AWAKENING;
2600 atomic_set(&pq_p->alarmrung, 1);
2601 wake_up(&pq_p->waitq);
2602 }
2603 }
2604
2605 static inline void
2606 helper_timeout_requests(void)
2607 {
2608 struct work_element *pq_p;
2609 struct list_head *lptr, *tptr;
2610 long timelimit;
2611
2612 timelimit = jiffies - (CLEANUPTIME * HZ);
2613 /* The list is in strict chronological order */
2614 list_for_each_safe(lptr, tptr, &pending_list) {
2615 pq_p = list_entry(lptr, struct work_element, liste);
2616 if (pq_p->requestsent >= timelimit)
2617 break;
2618 PRINTKW("Purging(PQ) PSMID %02X%02X%02X%02X%02X%02X%02X%02X\n",
2619 ((struct caller *)pq_p->requestptr)->caller_id[0],
2620 ((struct caller *)pq_p->requestptr)->caller_id[1],
2621 ((struct caller *)pq_p->requestptr)->caller_id[2],
2622 ((struct caller *)pq_p->requestptr)->caller_id[3],
2623 ((struct caller *)pq_p->requestptr)->caller_id[4],
2624 ((struct caller *)pq_p->requestptr)->caller_id[5],
2625 ((struct caller *)pq_p->requestptr)->caller_id[6],
2626 ((struct caller *)pq_p->requestptr)->caller_id[7]);
2627 pq_p->retcode = -ETIMEOUT;
2628 pq_p->status[0] |= STAT_FAILED;
2629 /* get this off any caller queue it may be on */
2630 unbuild_caller(LONG2DEVPTR(pq_p->devindex),
2631 (struct caller *) pq_p->requestptr);
2632 list_del_init(lptr);
2633 pendingq_count--;
2634 pq_p->audit[1] |= FP_TIMEDOUT;
2635 pq_p->audit[1] |= FP_NOTPENDING;
2636 pq_p->audit[1] |= FP_AWAKENING;
2637 atomic_set(&pq_p->alarmrung, 1);
2638 wake_up(&pq_p->waitq);
2639 }
2640
2641 /**
2642 * If pending count is zero, items left on the request queue may
2643 * never be processed.
2644 */
2645 if (pendingq_count <= 0) {
2646 list_for_each_safe(lptr, tptr, &request_list) {
2647 pq_p = list_entry(lptr, struct work_element, liste);
2648 if (pq_p->requestsent >= timelimit)
2649 break;
2650 PRINTKW("Purging(RQ) PSMID %02X%02X%02X%02X%02X%02X%02X%02X\n",
2651 ((struct caller *)pq_p->requestptr)->caller_id[0],
2652 ((struct caller *)pq_p->requestptr)->caller_id[1],
2653 ((struct caller *)pq_p->requestptr)->caller_id[2],
2654 ((struct caller *)pq_p->requestptr)->caller_id[3],
2655 ((struct caller *)pq_p->requestptr)->caller_id[4],
2656 ((struct caller *)pq_p->requestptr)->caller_id[5],
2657 ((struct caller *)pq_p->requestptr)->caller_id[6],
2658 ((struct caller *)pq_p->requestptr)->caller_id[7]);
2659 pq_p->retcode = -ETIMEOUT;
2660 pq_p->status[0] |= STAT_FAILED;
2661 list_del_init(lptr);
2662 requestq_count--;
2663 pq_p->audit[1] |= FP_TIMEDOUT;
2664 pq_p->audit[1] |= FP_REMREQUEST;
2665 pq_p->audit[1] |= FP_AWAKENING;
2666 atomic_set(&pq_p->alarmrung, 1);
2667 wake_up(&pq_p->waitq);
2668 }
2669 }
2670 }
2671
2672 static void
2673 z90crypt_cleanup_task(unsigned long ptr)
2674 {
2675 PDEBUG("jiffies %ld\n", jiffies);
2676 spin_lock_irq(&queuespinlock);
2677 if (z90crypt.mask.st_count <= 0) // no devices!
2678 helper_drain_queues();
2679 else
2680 helper_timeout_requests();
2681 spin_unlock_irq(&queuespinlock);
2682 z90crypt_schedule_cleanup_task();
2683 }
2684
2685 static void
2686 z90crypt_schedule_reader_task(unsigned long ptr)
2687 {
2688 tasklet_schedule(&reader_tasklet);
2689 }
2690
2691 /**
2692 * Lowlevel Functions:
2693 *
2694 * create_z90crypt: creates and initializes basic data structures
2695 * refresh_z90crypt: re-initializes basic data structures
2696 * find_crypto_devices: returns a count and mask of hardware status
2697 * create_crypto_device: builds the descriptor for a device
2698 * destroy_crypto_device: unallocates the descriptor for a device
2699 * destroy_z90crypt: drains all work, unallocates structs
2700 */
2701
2702 /**
2703 * build the z90crypt root structure using the given domain index
2704 */
2705 static int
2706 create_z90crypt(int *cdx_p)
2707 {
2708 struct hdware_block *hdware_blk_p;
2709
2710 memset(&z90crypt, 0x00, sizeof(struct z90crypt));
2711 z90crypt.domain_established = 0;
2712 z90crypt.len = sizeof(struct z90crypt);
2713 z90crypt.max_count = Z90CRYPT_NUM_DEVS;
2714 z90crypt.cdx = *cdx_p;
2715
2716 hdware_blk_p = (struct hdware_block *)
2717 kmalloc(sizeof(struct hdware_block), GFP_ATOMIC);
2718 if (!hdware_blk_p) {
2719 PDEBUG("kmalloc for hardware block failed\n");
2720 return ENOMEM;
2721 }
2722 memset(hdware_blk_p, 0x00, sizeof(struct hdware_block));
2723 z90crypt.hdware_info = hdware_blk_p;
2724
2725 return 0;
2726 }
2727
2728 static inline int
2729 helper_scan_devices(int cdx_array[16], int *cdx_p, int *correct_cdx_found)
2730 {
2731 enum hdstat hd_stat;
2732 int q_depth, dev_type;
2733 int indx, chkdom, numdomains;
2734
2735 q_depth = dev_type = numdomains = 0;
2736 for (chkdom = 0; chkdom <= 15; cdx_array[chkdom++] = -1);
2737 for (indx = 0; indx < z90crypt.max_count; indx++) {
2738 hd_stat = HD_NOT_THERE;
2739 numdomains = 0;
2740 for (chkdom = 0; chkdom <= 15; chkdom++) {
2741 hd_stat = query_online(indx, chkdom, MAX_RESET,
2742 &q_depth, &dev_type);
2743 if (hd_stat == HD_TSQ_EXCEPTION) {
2744 z90crypt.terminating = 1;
2745 PRINTKC("exception taken!\n");
2746 break;
2747 }
2748 if (hd_stat == HD_ONLINE) {
2749 cdx_array[numdomains++] = chkdom;
2750 if (*cdx_p == chkdom) {
2751 *correct_cdx_found = 1;
2752 break;
2753 }
2754 }
2755 }
2756 if ((*correct_cdx_found == 1) || (numdomains != 0))
2757 break;
2758 if (z90crypt.terminating)
2759 break;
2760 }
2761 return numdomains;
2762 }
2763
2764 static inline int
2765 probe_crypto_domain(int *cdx_p)
2766 {
2767 int cdx_array[16];
2768 char cdx_array_text[53], temp[5];
2769 int correct_cdx_found, numdomains;
2770
2771 correct_cdx_found = 0;
2772 numdomains = helper_scan_devices(cdx_array, cdx_p, &correct_cdx_found);
2773
2774 if (z90crypt.terminating)
2775 return TSQ_FATAL_ERROR;
2776
2777 if (correct_cdx_found)
2778 return 0;
2779
2780 if (numdomains == 0) {
2781 PRINTKW("Unable to find crypto domain: No devices found\n");
2782 return Z90C_NO_DEVICES;
2783 }
2784
2785 if (numdomains == 1) {
2786 if (*cdx_p == -1) {
2787 *cdx_p = cdx_array[0];
2788 return 0;
2789 }
2790 PRINTKW("incorrect domain: specified = %d, found = %d\n",
2791 *cdx_p, cdx_array[0]);
2792 return Z90C_INCORRECT_DOMAIN;
2793 }
2794
2795 numdomains--;
2796 sprintf(cdx_array_text, "%d", cdx_array[numdomains]);
2797 while (numdomains) {
2798 numdomains--;
2799 sprintf(temp, ", %d", cdx_array[numdomains]);
2800 strcat(cdx_array_text, temp);
2801 }
2802
2803 PRINTKW("ambiguous domain detected: specified = %d, found array = %s\n",
2804 *cdx_p, cdx_array_text);
2805 return Z90C_AMBIGUOUS_DOMAIN;
2806 }
2807
2808 static int
2809 refresh_z90crypt(int *cdx_p)
2810 {
2811 int i, j, indx, rv;
2812 static struct status local_mask;
2813 struct device *devPtr;
2814 unsigned char oldStat, newStat;
2815 int return_unchanged;
2816
2817 if (z90crypt.len != sizeof(z90crypt))
2818 return ENOTINIT;
2819 if (z90crypt.terminating)
2820 return TSQ_FATAL_ERROR;
2821 rv = 0;
2822 if (!z90crypt.hdware_info->hdware_mask.st_count &&
2823 !z90crypt.domain_established) {
2824 rv = probe_crypto_domain(cdx_p);
2825 if (z90crypt.terminating)
2826 return TSQ_FATAL_ERROR;
2827 if (rv == Z90C_NO_DEVICES)
2828 return 0; // try later
2829 if (rv)
2830 return rv;
2831 z90crypt.cdx = *cdx_p;
2832 z90crypt.domain_established = 1;
2833 }
2834 rv = find_crypto_devices(&local_mask);
2835 if (rv) {
2836 PRINTK("find crypto devices returned %d\n", rv);
2837 return rv;
2838 }
2839 if (!memcmp(&local_mask, &z90crypt.hdware_info->hdware_mask,
2840 sizeof(struct status))) {
2841 return_unchanged = 1;
2842 for (i = 0; i < Z90CRYPT_NUM_TYPES; i++) {
2843 /**
2844 * Check for disabled cards. If any device is marked
2845 * disabled, destroy it.
2846 */
2847 for (j = 0;
2848 j < z90crypt.hdware_info->type_mask[i].st_count;
2849 j++) {
2850 indx = z90crypt.hdware_info->type_x_addr[i].
2851 device_index[j];
2852 devPtr = z90crypt.device_p[indx];
2853 if (devPtr && devPtr->disabled) {
2854 local_mask.st_mask[indx] = HD_NOT_THERE;
2855 return_unchanged = 0;
2856 }
2857 }
2858 }
2859 if (return_unchanged == 1)
2860 return 0;
2861 }
2862
2863 spin_lock_irq(&queuespinlock);
2864 for (i = 0; i < z90crypt.max_count; i++) {
2865 oldStat = z90crypt.hdware_info->hdware_mask.st_mask[i];
2866 newStat = local_mask.st_mask[i];
2867 if ((oldStat == HD_ONLINE) && (newStat != HD_ONLINE))
2868 destroy_crypto_device(i);
2869 else if ((oldStat != HD_ONLINE) && (newStat == HD_ONLINE)) {
2870 rv = create_crypto_device(i);
2871 if (rv >= REC_FATAL_ERROR)
2872 return rv;
2873 if (rv != 0) {
2874 local_mask.st_mask[i] = HD_NOT_THERE;
2875 local_mask.st_count--;
2876 }
2877 }
2878 }
2879 memcpy(z90crypt.hdware_info->hdware_mask.st_mask, local_mask.st_mask,
2880 sizeof(local_mask.st_mask));
2881 z90crypt.hdware_info->hdware_mask.st_count = local_mask.st_count;
2882 z90crypt.hdware_info->hdware_mask.disabled_count =
2883 local_mask.disabled_count;
2884 refresh_index_array(&z90crypt.mask, &z90crypt.overall_device_x);
2885 for (i = 0; i < Z90CRYPT_NUM_TYPES; i++)
2886 refresh_index_array(&(z90crypt.hdware_info->type_mask[i]),
2887 &(z90crypt.hdware_info->type_x_addr[i]));
2888 spin_unlock_irq(&queuespinlock);
2889
2890 return rv;
2891 }
2892
2893 static int
2894 find_crypto_devices(struct status *deviceMask)
2895 {
2896 int i, q_depth, dev_type;
2897 enum hdstat hd_stat;
2898
2899 deviceMask->st_count = 0;
2900 deviceMask->disabled_count = 0;
2901 deviceMask->user_disabled_count = 0;
2902
2903 for (i = 0; i < z90crypt.max_count; i++) {
2904 hd_stat = query_online(i, z90crypt.cdx, MAX_RESET, &q_depth,
2905 &dev_type);
2906 if (hd_stat == HD_TSQ_EXCEPTION) {
2907 z90crypt.terminating = 1;
2908 PRINTKC("Exception during probe for crypto devices\n");
2909 return TSQ_FATAL_ERROR;
2910 }
2911 deviceMask->st_mask[i] = hd_stat;
2912 if (hd_stat == HD_ONLINE) {
2913 PDEBUG("Got an online crypto!: %d\n", i);
2914 PDEBUG("Got a queue depth of %d\n", q_depth);
2915 PDEBUG("Got a device type of %d\n", dev_type);
2916 if (q_depth <= 0)
2917 return TSQ_FATAL_ERROR;
2918 deviceMask->st_count++;
2919 z90crypt.q_depth_array[i] = q_depth;
2920 z90crypt.dev_type_array[i] = dev_type;
2921 }
2922 }
2923
2924 return 0;
2925 }
2926
2927 static int
2928 refresh_index_array(struct status *status_str, struct device_x *index_array)
2929 {
2930 int i, count;
2931 enum devstat stat;
2932
2933 i = -1;
2934 count = 0;
2935 do {
2936 stat = status_str->st_mask[++i];
2937 if (stat == DEV_ONLINE)
2938 index_array->device_index[count++] = i;
2939 } while ((i < Z90CRYPT_NUM_DEVS) && (count < status_str->st_count));
2940
2941 return count;
2942 }
2943
2944 static int
2945 create_crypto_device(int index)
2946 {
2947 int rv, devstat, total_size;
2948 struct device *dev_ptr;
2949 struct status *type_str_p;
2950 int deviceType;
2951
2952 dev_ptr = z90crypt.device_p[index];
2953 if (!dev_ptr) {
2954 total_size = sizeof(struct device) +
2955 z90crypt.q_depth_array[index] * sizeof(int);
2956
2957 dev_ptr = (struct device *) kmalloc(total_size, GFP_ATOMIC);
2958 if (!dev_ptr) {
2959 PRINTK("kmalloc device %d failed\n", index);
2960 return ENOMEM;
2961 }
2962 memset(dev_ptr, 0, total_size);
2963 dev_ptr->dev_resp_p = kmalloc(MAX_RESPONSE_SIZE, GFP_ATOMIC);
2964 if (!dev_ptr->dev_resp_p) {
2965 kfree(dev_ptr);
2966 PRINTK("kmalloc device %d rec buffer failed\n", index);
2967 return ENOMEM;
2968 }
2969 dev_ptr->dev_resp_l = MAX_RESPONSE_SIZE;
2970 INIT_LIST_HEAD(&(dev_ptr->dev_caller_list));
2971 }
2972
2973 devstat = reset_device(index, z90crypt.cdx, MAX_RESET);
2974 if (devstat == DEV_RSQ_EXCEPTION) {
2975 PRINTK("exception during reset device %d\n", index);
2976 kfree(dev_ptr->dev_resp_p);
2977 kfree(dev_ptr);
2978 return RSQ_FATAL_ERROR;
2979 }
2980 if (devstat == DEV_ONLINE) {
2981 dev_ptr->dev_self_x = index;
2982 dev_ptr->dev_type = z90crypt.dev_type_array[index];
2983 if (dev_ptr->dev_type == NILDEV) {
2984 rv = probe_device_type(dev_ptr);
2985 if (rv) {
2986 PRINTK("rv = %d from probe_device_type %d\n",
2987 rv, index);
2988 kfree(dev_ptr->dev_resp_p);
2989 kfree(dev_ptr);
2990 return rv;
2991 }
2992 }
2993 if (dev_ptr->dev_type == PCIXCC_UNK) {
2994 rv = probe_PCIXCC_type(dev_ptr);
2995 if (rv) {
2996 PRINTK("rv = %d from probe_PCIXCC_type %d\n",
2997 rv, index);
2998 kfree(dev_ptr->dev_resp_p);
2999 kfree(dev_ptr);
3000 return rv;
3001 }
3002 }
3003 deviceType = dev_ptr->dev_type;
3004 z90crypt.dev_type_array[index] = deviceType;
3005 if (deviceType == PCICA)
3006 z90crypt.hdware_info->device_type_array[index] = 1;
3007 else if (deviceType == PCICC)
3008 z90crypt.hdware_info->device_type_array[index] = 2;
3009 else if (deviceType == PCIXCC_MCL2)
3010 z90crypt.hdware_info->device_type_array[index] = 3;
3011 else if (deviceType == PCIXCC_MCL3)
3012 z90crypt.hdware_info->device_type_array[index] = 4;
3013 else if (deviceType == CEX2C)
3014 z90crypt.hdware_info->device_type_array[index] = 5;
3015 else
3016 z90crypt.hdware_info->device_type_array[index] = -1;
3017 }
3018
3019 /**
3020 * 'q_depth' returned by the hardware is one less than
3021 * the actual depth
3022 */
3023 dev_ptr->dev_q_depth = z90crypt.q_depth_array[index];
3024 dev_ptr->dev_type = z90crypt.dev_type_array[index];
3025 dev_ptr->dev_stat = devstat;
3026 dev_ptr->disabled = 0;
3027 z90crypt.device_p[index] = dev_ptr;
3028
3029 if (devstat == DEV_ONLINE) {
3030 if (z90crypt.mask.st_mask[index] != DEV_ONLINE) {
3031 z90crypt.mask.st_mask[index] = DEV_ONLINE;
3032 z90crypt.mask.st_count++;
3033 }
3034 deviceType = dev_ptr->dev_type;
3035 type_str_p = &z90crypt.hdware_info->type_mask[deviceType];
3036 if (type_str_p->st_mask[index] != DEV_ONLINE) {
3037 type_str_p->st_mask[index] = DEV_ONLINE;
3038 type_str_p->st_count++;
3039 }
3040 }
3041
3042 return 0;
3043 }
3044
3045 static int
3046 destroy_crypto_device(int index)
3047 {
3048 struct device *dev_ptr;
3049 int t, disabledFlag;
3050
3051 dev_ptr = z90crypt.device_p[index];
3052
3053 /* remember device type; get rid of device struct */
3054 if (dev_ptr) {
3055 disabledFlag = dev_ptr->disabled;
3056 t = dev_ptr->dev_type;
3057 if (dev_ptr->dev_resp_p)
3058 kfree(dev_ptr->dev_resp_p);
3059 kfree(dev_ptr);
3060 } else {
3061 disabledFlag = 0;
3062 t = -1;
3063 }
3064 z90crypt.device_p[index] = 0;
3065
3066 /* if the type is valid, remove the device from the type_mask */
3067 if ((t != -1) && z90crypt.hdware_info->type_mask[t].st_mask[index]) {
3068 z90crypt.hdware_info->type_mask[t].st_mask[index] = 0x00;
3069 z90crypt.hdware_info->type_mask[t].st_count--;
3070 if (disabledFlag == 1)
3071 z90crypt.hdware_info->type_mask[t].disabled_count--;
3072 }
3073 if (z90crypt.mask.st_mask[index] != DEV_GONE) {
3074 z90crypt.mask.st_mask[index] = DEV_GONE;
3075 z90crypt.mask.st_count--;
3076 }
3077 z90crypt.hdware_info->device_type_array[index] = 0;
3078
3079 return 0;
3080 }
3081
3082 static void
3083 destroy_z90crypt(void)
3084 {
3085 int i;
3086 for (i = 0; i < z90crypt.max_count; i++)
3087 if (z90crypt.device_p[i])
3088 destroy_crypto_device(i);
3089 if (z90crypt.hdware_info)
3090 kfree((void *)z90crypt.hdware_info);
3091 memset((void *)&z90crypt, 0, sizeof(z90crypt));
3092 }
3093
3094 static unsigned char static_testmsg[384] = {
3095 0x00,0x00,0x00,0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x00,0x06,0x00,0x00,
3096 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x58,
3097 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x01,0x00,0x43,0x43,
3098 0x41,0x2d,0x41,0x50,0x50,0x4c,0x20,0x20,0x20,0x01,0x01,0x01,0x00,0x00,0x00,0x00,
3099 0x50,0x4b,0x00,0x00,0x00,0x00,0x01,0x1c,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3100 0x00,0x00,0x00,0x00,0x00,0x00,0x05,0xb8,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3101 0x00,0x00,0x00,0x00,0x70,0x00,0x41,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x54,0x32,
3102 0x01,0x00,0xa0,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3103 0xb8,0x05,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3104 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3105 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3106 0x00,0x00,0x00,0x00,0x00,0x00,0x0a,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3107 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x00,0x49,0x43,0x53,0x46,
3108 0x20,0x20,0x20,0x20,0x50,0x4b,0x0a,0x00,0x50,0x4b,0x43,0x53,0x2d,0x31,0x2e,0x32,
3109 0x37,0x00,0x11,0x22,0x33,0x44,0x55,0x66,0x77,0x88,0x99,0x00,0x11,0x22,0x33,0x44,
3110 0x55,0x66,0x77,0x88,0x99,0x00,0x11,0x22,0x33,0x44,0x55,0x66,0x77,0x88,0x99,0x00,
3111 0x11,0x22,0x33,0x44,0x55,0x66,0x77,0x88,0x99,0x00,0x11,0x22,0x33,0x44,0x55,0x66,
3112 0x77,0x88,0x99,0x00,0x11,0x22,0x33,0x5d,0x00,0x5b,0x00,0x77,0x88,0x1e,0x00,0x00,
3113 0x57,0x00,0x00,0x00,0x00,0x04,0x00,0x00,0x4f,0x00,0x00,0x00,0x03,0x02,0x00,0x00,
3114 0x40,0x01,0x00,0x01,0xce,0x02,0x68,0x2d,0x5f,0xa9,0xde,0x0c,0xf6,0xd2,0x7b,0x58,
3115 0x4b,0xf9,0x28,0x68,0x3d,0xb4,0xf4,0xef,0x78,0xd5,0xbe,0x66,0x63,0x42,0xef,0xf8,
3116 0xfd,0xa4,0xf8,0xb0,0x8e,0x29,0xc2,0xc9,0x2e,0xd8,0x45,0xb8,0x53,0x8c,0x6f,0x4e,
3117 0x72,0x8f,0x6c,0x04,0x9c,0x88,0xfc,0x1e,0xc5,0x83,0x55,0x57,0xf7,0xdd,0xfd,0x4f,
3118 0x11,0x36,0x95,0x5d,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00
3119 };
3120
3121 static int
3122 probe_device_type(struct device *devPtr)
3123 {
3124 int rv, dv, i, index, length;
3125 unsigned char psmid[8];
3126 static unsigned char loc_testmsg[sizeof(static_testmsg)];
3127
3128 index = devPtr->dev_self_x;
3129 rv = 0;
3130 do {
3131 memcpy(loc_testmsg, static_testmsg, sizeof(static_testmsg));
3132 length = sizeof(static_testmsg) - 24;
3133 /* the -24 allows for the header */
3134 dv = send_to_AP(index, z90crypt.cdx, length, loc_testmsg);
3135 if (dv) {
3136 PDEBUG("dv returned by send during probe: %d\n", dv);
3137 if (dv == DEV_SEN_EXCEPTION) {
3138 rv = SEN_FATAL_ERROR;
3139 PRINTKC("exception in send to AP %d\n", index);
3140 break;
3141 }
3142 PDEBUG("return value from send_to_AP: %d\n", rv);
3143 switch (dv) {
3144 case DEV_GONE:
3145 PDEBUG("dev %d not available\n", index);
3146 rv = SEN_NOT_AVAIL;
3147 break;
3148 case DEV_ONLINE:
3149 rv = 0;
3150 break;
3151 case DEV_EMPTY:
3152 rv = SEN_NOT_AVAIL;
3153 break;
3154 case DEV_NO_WORK:
3155 rv = SEN_FATAL_ERROR;
3156 break;
3157 case DEV_BAD_MESSAGE:
3158 rv = SEN_USER_ERROR;
3159 break;
3160 case DEV_QUEUE_FULL:
3161 rv = SEN_QUEUE_FULL;
3162 break;
3163 default:
3164 PRINTK("unknown dv=%d for dev %d\n", dv, index);
3165 rv = SEN_NOT_AVAIL;
3166 break;
3167 }
3168 }
3169
3170 if (rv)
3171 break;
3172
3173 for (i = 0; i < 6; i++) {
3174 mdelay(300);
3175 dv = receive_from_AP(index, z90crypt.cdx,
3176 devPtr->dev_resp_l,
3177 devPtr->dev_resp_p, psmid);
3178 PDEBUG("dv returned by DQ = %d\n", dv);
3179 if (dv == DEV_REC_EXCEPTION) {
3180 rv = REC_FATAL_ERROR;
3181 PRINTKC("exception in dequeue %d\n",
3182 index);
3183 break;
3184 }
3185 switch (dv) {
3186 case DEV_ONLINE:
3187 rv = 0;
3188 break;
3189 case DEV_EMPTY:
3190 rv = REC_EMPTY;
3191 break;
3192 case DEV_NO_WORK:
3193 rv = REC_NO_WORK;
3194 break;
3195 case DEV_BAD_MESSAGE:
3196 case DEV_GONE:
3197 default:
3198 rv = REC_NO_RESPONSE;
3199 break;
3200 }
3201 if ((rv != 0) && (rv != REC_NO_WORK))
3202 break;
3203 if (rv == 0)
3204 break;
3205 }
3206 if (rv)
3207 break;
3208 rv = (devPtr->dev_resp_p[0] == 0x00) &&
3209 (devPtr->dev_resp_p[1] == 0x86);
3210 if (rv)
3211 devPtr->dev_type = PCICC;
3212 else
3213 devPtr->dev_type = PCICA;
3214 rv = 0;
3215 } while (0);
3216 /* In a general error case, the card is not marked online */
3217 return rv;
3218 }
3219
3220 static unsigned char MCL3_testmsg[] = {
3221 0x00,0x00,0x00,0x00,0xEE,0xEE,0xEE,0xEE,0xEE,0xEE,0xEE,0xEE,
3222 0x00,0x06,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3223 0x00,0x00,0x00,0x58,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3224 0x43,0x41,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3225 0x00,0x00,0x00,0x00,0x50,0x4B,0x00,0x00,0x00,0x00,0x01,0xC4,0x00,0x00,0x00,0x00,
3226 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x24,0x00,0x00,0x00,0x00,
3227 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xDC,0x02,0x00,0x00,0x00,0x54,0x32,
3228 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0xE8,0x00,0x00,0x00,0x00,0x00,0x00,0x07,0x24,
3229 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3230 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3231 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3232 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3233 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3234 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3235 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3236 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3237 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3238 0x00,0x00,0x00,0x04,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3239 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3240 0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
3241 0x00,0x00,0x00,0x00,0x50,0x4B,0x00,0x0A,0x4D,0x52,0x50,0x20,0x20,0x20,0x20,0x20,
3242 0x00,0x42,0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,0x0A,0x0B,0x0C,0x0D,
3243 0x0E,0x0F,0x00,0x11,0x22,0x33,0x44,0x55,0x66,0x77,0x88,0x99,0xAA,0xBB,0xCC,0xDD,
3244 0xEE,0xFF,0xFF,0xEE,0xDD,0xCC,0xBB,0xAA,0x99,0x88,0x77,0x66,0x55,0x44,0x33,0x22,
3245 0x11,0x00,0x01,0x23,0x45,0x67,0x89,0xAB,0xCD,0xEF,0xFE,0xDC,0xBA,0x98,0x76,0x54,
3246 0x32,0x10,0x00,0x9A,0x00,0x98,0x00,0x00,0x1E,0x00,0x00,0x94,0x00,0x00,0x00,0x00,
3247 0x04,0x00,0x00,0x8C,0x00,0x00,0x00,0x40,0x02,0x00,0x00,0x40,0xBA,0xE8,0x23,0x3C,
3248 0x75,0xF3,0x91,0x61,0xD6,0x73,0x39,0xCF,0x7B,0x6D,0x8E,0x61,0x97,0x63,0x9E,0xD9,
3249 0x60,0x55,0xD6,0xC7,0xEF,0xF8,0x1E,0x63,0x95,0x17,0xCC,0x28,0x45,0x60,0x11,0xC5,
3250 0xC4,0x4E,0x66,0xC6,0xE6,0xC3,0xDE,0x8A,0x19,0x30,0xCF,0x0E,0xD7,0xAA,0xDB,0x01,
3251 0xD8,0x00,0xBB,0x8F,0x39,0x9F,0x64,0x28,0xF5,0x7A,0x77,0x49,0xCC,0x6B,0xA3,0x91,
3252 0x97,0x70,0xE7,0x60,0x1E,0x39,0xE1,0xE5,0x33,0xE1,0x15,0x63,0x69,0x08,0x80,0x4C,
3253 0x67,0xC4,0x41,0x8F,0x48,0xDF,0x26,0x98,0xF1,0xD5,0x8D,0x88,0xD9,0x6A,0xA4,0x96,
3254 0xC5,0x84,0xD9,0x30,0x49,0x67,0x7D,0x19,0xB1,0xB3,0x45,0x4D,0xB2,0x53,0x9A,0x47,
3255 0x3C,0x7C,0x55,0xBF,0xCC,0x85,0x00,0x36,0xF1,0x3D,0x93,0x53
3256 };
3257
3258 static int
3259 probe_PCIXCC_type(struct device *devPtr)
3260 {
3261 int rv, dv, i, index, length;
3262 unsigned char psmid[8];
3263 static unsigned char loc_testmsg[548];
3264 struct CPRBX *cprbx_p;
3265
3266 index = devPtr->dev_self_x;
3267 rv = 0;
3268 do {
3269 memcpy(loc_testmsg, MCL3_testmsg, sizeof(MCL3_testmsg));
3270 length = sizeof(MCL3_testmsg) - 0x0C;
3271 dv = send_to_AP(index, z90crypt.cdx, length, loc_testmsg);
3272 if (dv) {
3273 PDEBUG("dv returned = %d\n", dv);
3274 if (dv == DEV_SEN_EXCEPTION) {
3275 rv = SEN_FATAL_ERROR;
3276 PRINTKC("exception in send to AP %d\n", index);
3277 break;
3278 }
3279 PDEBUG("return value from send_to_AP: %d\n", rv);
3280 switch (dv) {
3281 case DEV_GONE:
3282 PDEBUG("dev %d not available\n", index);
3283 rv = SEN_NOT_AVAIL;
3284 break;
3285 case DEV_ONLINE:
3286 rv = 0;
3287 break;
3288 case DEV_EMPTY:
3289 rv = SEN_NOT_AVAIL;
3290 break;
3291 case DEV_NO_WORK:
3292 rv = SEN_FATAL_ERROR;
3293 break;
3294 case DEV_BAD_MESSAGE:
3295 rv = SEN_USER_ERROR;
3296 break;
3297 case DEV_QUEUE_FULL:
3298 rv = SEN_QUEUE_FULL;
3299 break;
3300 default:
3301 PRINTK("unknown dv=%d for dev %d\n", dv, index);
3302 rv = SEN_NOT_AVAIL;
3303 break;
3304 }
3305 }
3306
3307 if (rv)
3308 break;
3309
3310 for (i = 0; i < 6; i++) {
3311 mdelay(300);
3312 dv = receive_from_AP(index, z90crypt.cdx,
3313 devPtr->dev_resp_l,
3314 devPtr->dev_resp_p, psmid);
3315 PDEBUG("dv returned by DQ = %d\n", dv);
3316 if (dv == DEV_REC_EXCEPTION) {
3317 rv = REC_FATAL_ERROR;
3318 PRINTKC("exception in dequeue %d\n",
3319 index);
3320 break;
3321 }
3322 switch (dv) {
3323 case DEV_ONLINE:
3324 rv = 0;
3325 break;
3326 case DEV_EMPTY:
3327 rv = REC_EMPTY;
3328 break;
3329 case DEV_NO_WORK:
3330 rv = REC_NO_WORK;
3331 break;
3332 case DEV_BAD_MESSAGE:
3333 case DEV_GONE:
3334 default:
3335 rv = REC_NO_RESPONSE;
3336 break;
3337 }
3338 if ((rv != 0) && (rv != REC_NO_WORK))
3339 break;
3340 if (rv == 0)
3341 break;
3342 }
3343 if (rv)
3344 break;
3345 cprbx_p = (struct CPRBX *) (devPtr->dev_resp_p + 48);
3346 if ((cprbx_p->ccp_rtcode == 8) && (cprbx_p->ccp_rscode == 33)) {
3347 devPtr->dev_type = PCIXCC_MCL2;
3348 PDEBUG("device %d is MCL2\n", index);
3349 } else {
3350 devPtr->dev_type = PCIXCC_MCL3;
3351 PDEBUG("device %d is MCL3\n", index);
3352 }
3353 } while (0);
3354 /* In a general error case, the card is not marked online */
3355 return rv;
3356 }
3357
3358 module_init(z90crypt_init_module);
3359 module_exit(z90crypt_cleanup_module);
Verdex Pro support