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[PATCH] W1: w1_netlink: New init/fini netlink callbacks.
[linux-2.6/verdex.git] / drivers / sbus / char / bpp.c
blob87302fb1488545c94e8a5b58aa6822e7e668fb99
1 /*
2 * drivers/sbus/char/bpp.c
3 *
4 * Copyright (c) 1995 Picture Elements
5 * Stephen Williams (steve@icarus.com)
6 * Gus Baldauf (gbaldauf@ix.netcom.com)
7 *
8 * Linux/SPARC port by Peter Zaitcev.
9 * Integration into SPARC tree by Tom Dyas.
10 */
11
12
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/fs.h>
16 #include <linux/errno.h>
17 #include <linux/sched.h>
18 #include <linux/smp_lock.h>
19 #include <linux/spinlock.h>
20 #include <linux/timer.h>
21 #include <linux/ioport.h>
22 #include <linux/major.h>
23 #include <linux/devfs_fs_kernel.h>
24
25 #include <asm/uaccess.h>
26 #include <asm/io.h>
27
28 #if defined(__i386__)
29 # include <asm/system.h>
30 #endif
31
32 #if defined(__sparc__)
33 # include <linux/init.h>
34 # include <linux/delay.h> /* udelay() */
35
36 # include <asm/oplib.h> /* OpenProm Library */
37 # include <asm/sbus.h>
38 #endif
39
40 #include <asm/bpp.h>
41
42 #define BPP_PROBE_CODE 0x55
43 #define BPP_DELAY 100
44
45 static const unsigned BPP_MAJOR = LP_MAJOR;
46 static const char* dev_name = "bpp";
47
48 /* When switching from compatibility to a mode where I can read, try
49 the following mode first. */
50
51 /* const unsigned char DEFAULT_ECP = 0x10; */
52 static const unsigned char DEFAULT_ECP = 0x30;
53 static const unsigned char DEFAULT_NIBBLE = 0x00;
54
55 /*
56 * These are 1284 time constraints, in units of jiffies.
57 */
58
59 static const unsigned long TIME_PSetup = 1;
60 static const unsigned long TIME_PResponse = 6;
61 static const unsigned long TIME_IDLE_LIMIT = 2000;
62
63 /*
64 * One instance per supported subdevice...
65 */
66 # define BPP_NO 3
67
68 enum IEEE_Mode { COMPATIBILITY, NIBBLE, ECP, ECP_RLE, EPP };
69
70 struct inst {
71 unsigned present : 1; /* True if the hardware exists */
72 unsigned enhanced : 1; /* True if the hardware in "enhanced" */
73 unsigned opened : 1; /* True if the device is opened already */
74 unsigned run_flag : 1; /* True if waiting for a repeate byte */
75
76 unsigned char direction; /* 0 --> out, 0x20 --> IN */
77 unsigned char pp_state; /* State of host controlled pins. */
78 enum IEEE_Mode mode;
79
80 unsigned char run_length;
81 unsigned char repeat_byte;
82 };
83
84 static struct inst instances[BPP_NO];
85
86 #if defined(__i386__)
87
88 static const unsigned short base_addrs[BPP_NO] = { 0x278, 0x378, 0x3bc };
89
90 /*
91 * These are for data access.
92 * Control lines accesses are hidden in set_bits() and get_bits().
93 * The exception is the probe procedure, which is system-dependent.
94 */
95 #define bpp_outb_p(data, base) outb_p((data), (base))
96 #define bpp_inb(base) inb(base)
97 #define bpp_inb_p(base) inb_p(base)
98
99 /*
100 * This method takes the pin values mask and sets the hardware pins to
101 * the requested value: 1 == high voltage, 0 == low voltage. This
102 * burries the annoying PC bit inversion and preserves the direction
103 * flag.
104 */
105 static void set_pins(unsigned short pins, unsigned minor)
106 {
107 unsigned char bits = instances[minor].direction; /* == 0x20 */
108
109 if (! (pins & BPP_PP_nStrobe)) bits |= 1;
110 if (! (pins & BPP_PP_nAutoFd)) bits |= 2;
111 if ( pins & BPP_PP_nInit) bits |= 4;
112 if (! (pins & BPP_PP_nSelectIn)) bits |= 8;
113
114 instances[minor].pp_state = bits;
115
116 outb_p(bits, base_addrs[minor]+2);
117 }
118
119 static unsigned short get_pins(unsigned minor)
120 {
121 unsigned short bits = 0;
122
123 unsigned value = instances[minor].pp_state;
124 if (! (value & 0x01)) bits |= BPP_PP_nStrobe;
125 if (! (value & 0x02)) bits |= BPP_PP_nAutoFd;
126 if (value & 0x04) bits |= BPP_PP_nInit;
127 if (! (value & 0x08)) bits |= BPP_PP_nSelectIn;
128
129 value = inb_p(base_addrs[minor]+1);
130 if (value & 0x08) bits |= BPP_GP_nFault;
131 if (value & 0x10) bits |= BPP_GP_Select;
132 if (value & 0x20) bits |= BPP_GP_PError;
133 if (value & 0x40) bits |= BPP_GP_nAck;
134 if (! (value & 0x80)) bits |= BPP_GP_Busy;
135
136 return bits;
137 }
138
139 #endif /* __i386__ */
140
141 #if defined(__sparc__)
142
143 /*
144 * Register block
145 */
146 /* DMA registers */
147 #define BPP_CSR 0x00
148 #define BPP_ADDR 0x04
149 #define BPP_BCNT 0x08
150 #define BPP_TST_CSR 0x0C
151 /* Parallel Port registers */
152 #define BPP_HCR 0x10
153 #define BPP_OCR 0x12
154 #define BPP_DR 0x14
155 #define BPP_TCR 0x15
156 #define BPP_OR 0x16
157 #define BPP_IR 0x17
158 #define BPP_ICR 0x18
159 #define BPP_SIZE 0x1A
160
161 /* BPP_CSR. Bits of type RW1 are cleared with writting '1'. */
162 #define P_DEV_ID_MASK 0xf0000000 /* R */
163 #define P_DEV_ID_ZEBRA 0x40000000
164 #define P_DEV_ID_L64854 0xa0000000 /* == NCR 89C100+89C105. Pity. */
165 #define P_NA_LOADED 0x08000000 /* R NA wirtten but was not used */
166 #define P_A_LOADED 0x04000000 /* R */
167 #define P_DMA_ON 0x02000000 /* R DMA is not disabled */
168 #define P_EN_NEXT 0x01000000 /* RW */
169 #define P_TCI_DIS 0x00800000 /* RW TCI forbidden from interrupts */
170 #define P_DIAG 0x00100000 /* RW Disables draining and resetting
171 of P-FIFO on loading of P_ADDR*/
172 #define P_BURST_SIZE 0x000c0000 /* RW SBus burst size */
173 #define P_BURST_8 0x00000000
174 #define P_BURST_4 0x00040000
175 #define P_BURST_1 0x00080000 /* "No burst" write */
176 #define P_TC 0x00004000 /* RW1 Term Count, can be cleared when
177 P_EN_NEXT=1 */
178 #define P_EN_CNT 0x00002000 /* RW */
179 #define P_EN_DMA 0x00000200 /* RW */
180 #define P_WRITE 0x00000100 /* R DMA dir, 1=to ram, 0=to port */
181 #define P_RESET 0x00000080 /* RW */
182 #define P_SLAVE_ERR 0x00000040 /* RW1 Access size error */
183 #define P_INVALIDATE 0x00000020 /* W Drop P-FIFO */
184 #define P_INT_EN 0x00000010 /* RW OK to P_INT_PEND||P_ERR_PEND */
185 #define P_DRAINING 0x0000000c /* R P-FIFO is draining to memory */
186 #define P_ERR_PEND 0x00000002 /* R */
187 #define P_INT_PEND 0x00000001 /* R */
188
189 /* BPP_HCR. Time is in increments of SBus clock. */
190 #define P_HCR_TEST 0x8000 /* Allows buried counters to be read */
191 #define P_HCR_DSW 0x7f00 /* Data strobe width (in ticks) */
192 #define P_HCR_DDS 0x007f /* Data setup before strobe (in ticks) */
193
194 /* BPP_OCR. */
195 #define P_OCR_MEM_CLR 0x8000
196 #define P_OCR_DATA_SRC 0x4000 /* ) */
197 #define P_OCR_DS_DSEL 0x2000 /* ) Bidirectional */
198 #define P_OCR_BUSY_DSEL 0x1000 /* ) selects */
199 #define P_OCR_ACK_DSEL 0x0800 /* ) */
200 #define P_OCR_EN_DIAG 0x0400
201 #define P_OCR_BUSY_OP 0x0200 /* Busy operation */
202 #define P_OCR_ACK_OP 0x0100 /* Ack operation */
203 #define P_OCR_SRST 0x0080 /* Reset state machines. Not selfcleaning. */
204 #define P_OCR_IDLE 0x0008 /* PP data transfer state machine is idle */
205 #define P_OCR_V_ILCK 0x0002 /* Versatec faded. Zebra only. */
206 #define P_OCR_EN_VER 0x0001 /* Enable Versatec (0 - enable). Zebra only. */
207
208 /* BPP_TCR */
209 #define P_TCR_DIR 0x08
210 #define P_TCR_BUSY 0x04
211 #define P_TCR_ACK 0x02
212 #define P_TCR_DS 0x01 /* Strobe */
213
214 /* BPP_OR */
215 #define P_OR_V3 0x20 /* ) */
216 #define P_OR_V2 0x10 /* ) on Zebra only */
217 #define P_OR_V1 0x08 /* ) */
218 #define P_OR_INIT 0x04
219 #define P_OR_AFXN 0x02 /* Auto Feed */
220 #define P_OR_SLCT_IN 0x01
221
222 /* BPP_IR */
223 #define P_IR_PE 0x04
224 #define P_IR_SLCT 0x02
225 #define P_IR_ERR 0x01
226
227 /* BPP_ICR */
228 #define P_DS_IRQ 0x8000 /* RW1 */
229 #define P_ACK_IRQ 0x4000 /* RW1 */
230 #define P_BUSY_IRQ 0x2000 /* RW1 */
231 #define P_PE_IRQ 0x1000 /* RW1 */
232 #define P_SLCT_IRQ 0x0800 /* RW1 */
233 #define P_ERR_IRQ 0x0400 /* RW1 */
234 #define P_DS_IRQ_EN 0x0200 /* RW Always on rising edge */
235 #define P_ACK_IRQ_EN 0x0100 /* RW Always on rising edge */
236 #define P_BUSY_IRP 0x0080 /* RW 1= rising edge */
237 #define P_BUSY_IRQ_EN 0x0040 /* RW */
238 #define P_PE_IRP 0x0020 /* RW 1= rising edge */
239 #define P_PE_IRQ_EN 0x0010 /* RW */
240 #define P_SLCT_IRP 0x0008 /* RW 1= rising edge */
241 #define P_SLCT_IRQ_EN 0x0004 /* RW */
242 #define P_ERR_IRP 0x0002 /* RW1 1= rising edge */
243 #define P_ERR_IRQ_EN 0x0001 /* RW */
244
245 static void __iomem *base_addrs[BPP_NO];
246
247 #define bpp_outb_p(data, base) sbus_writeb(data, (base) + BPP_DR)
248 #define bpp_inb_p(base) sbus_readb((base) + BPP_DR)
249 #define bpp_inb(base) sbus_readb((base) + BPP_DR)
250
251 static void set_pins(unsigned short pins, unsigned minor)
252 {
253 void __iomem *base = base_addrs[minor];
254 unsigned char bits_tcr = 0, bits_or = 0;
255
256 if (instances[minor].direction & 0x20) bits_tcr |= P_TCR_DIR;
257 if ( pins & BPP_PP_nStrobe) bits_tcr |= P_TCR_DS;
258
259 if ( pins & BPP_PP_nAutoFd) bits_or |= P_OR_AFXN;
260 if (! (pins & BPP_PP_nInit)) bits_or |= P_OR_INIT;
261 if (! (pins & BPP_PP_nSelectIn)) bits_or |= P_OR_SLCT_IN;
262
263 sbus_writeb(bits_or, base + BPP_OR);
264 sbus_writeb(bits_tcr, base + BPP_TCR);
265 }
266
267 /*
268 * i386 people read output pins from a software image.
269 * We may get them back from hardware.
270 * Again, inversion of pins must he buried here.
271 */
272 static unsigned short get_pins(unsigned minor)
273 {
274 void __iomem *base = base_addrs[minor];
275 unsigned short bits = 0;
276 unsigned value_tcr = sbus_readb(base + BPP_TCR);
277 unsigned value_ir = sbus_readb(base + BPP_IR);
278 unsigned value_or = sbus_readb(base + BPP_OR);
279
280 if (value_tcr & P_TCR_DS) bits |= BPP_PP_nStrobe;
281 if (value_or & P_OR_AFXN) bits |= BPP_PP_nAutoFd;
282 if (! (value_or & P_OR_INIT)) bits |= BPP_PP_nInit;
283 if (! (value_or & P_OR_SLCT_IN)) bits |= BPP_PP_nSelectIn;
284
285 if (value_ir & P_IR_ERR) bits |= BPP_GP_nFault;
286 if (! (value_ir & P_IR_SLCT)) bits |= BPP_GP_Select;
287 if (! (value_ir & P_IR_PE)) bits |= BPP_GP_PError;
288 if (! (value_tcr & P_TCR_ACK)) bits |= BPP_GP_nAck;
289 if (value_tcr & P_TCR_BUSY) bits |= BPP_GP_Busy;
290
291 return bits;
292 }
293
294 #endif /* __sparc__ */
295
296 static void snooze(unsigned long snooze_time, unsigned minor)
297 {
298 set_current_state(TASK_UNINTERRUPTIBLE);
299 schedule_timeout(snooze_time + 1);
300 }
301
302 static int wait_for(unsigned short set, unsigned short clr,
303 unsigned long delay, unsigned minor)
304 {
305 unsigned short pins = get_pins(minor);
306
307 unsigned long extime = 0;
308
309 /*
310 * Try a real fast scan for the first jiffy, in case the device
311 * responds real good. The first while loop guesses an expire
312 * time accounting for possible wraparound of jiffies.
313 */
314 while (time_after_eq(jiffies, extime)) extime = jiffies + 1;
315 while ( (time_before(jiffies, extime))
316 && (((pins & set) != set) || ((pins & clr) != 0)) ) {
317 pins = get_pins(minor);
318 }
319
320 delay -= 1;
321
322 /*
323 * If my delay expired or the pins are still not where I want
324 * them, then resort to using the timer and greatly reduce my
325 * sample rate. If the peripheral is going to be slow, this will
326 * give the CPU up to some more worthy process.
327 */
328 while ( delay && (((pins & set) != set) || ((pins & clr) != 0)) ) {
329
330 snooze(1, minor);
331 pins = get_pins(minor);
332 delay -= 1;
333 }
334
335 if (delay == 0) return -1;
336 else return pins;
337 }
338
339 /*
340 * Return ZERO(0) If the negotiation succeeds, an errno otherwise. An
341 * errno means something broke, and I do not yet know how to fix it.
342 */
343 static int negotiate(unsigned char mode, unsigned minor)
344 {
345 int rc;
346 unsigned short pins = get_pins(minor);
347 if (pins & BPP_PP_nSelectIn) return -EIO;
348
349
350 /* Event 0: Write the mode to the data lines */
351 bpp_outb_p(mode, base_addrs[minor]);
352
353 snooze(TIME_PSetup, minor);
354
355 /* Event 1: Strobe the mode code into the peripheral */
356 set_pins(BPP_PP_nSelectIn|BPP_PP_nStrobe|BPP_PP_nInit, minor);
357
358 /* Wait for Event 2: Peripheral responds as a 1284 device. */
359 rc = wait_for(BPP_GP_PError|BPP_GP_Select|BPP_GP_nFault,
360 BPP_GP_nAck,
361 TIME_PResponse,
362 minor);
363
364 if (rc == -1) return -ETIMEDOUT;
365
366 /* Event 3: latch extensibility request */
367 set_pins(BPP_PP_nSelectIn|BPP_PP_nInit, minor);
368
369 /* ... quick nap while peripheral ponders the byte i'm sending...*/
370 snooze(1, minor);
371
372 /* Event 4: restore strobe, to ACK peripheral's response. */
373 set_pins(BPP_PP_nSelectIn|BPP_PP_nAutoFd|BPP_PP_nStrobe|BPP_PP_nInit, minor);
374
375 /* Wait for Event 6: Peripheral latches response bits */
376 rc = wait_for(BPP_GP_nAck, 0, TIME_PSetup+TIME_PResponse, minor);
377 if (rc == -1) return -EIO;
378
379 /* A 1284 device cannot refuse nibble mode */
380 if (mode == DEFAULT_NIBBLE) return 0;
381
382 if (pins & BPP_GP_Select) return 0;
383
384 return -EPROTONOSUPPORT;
385 }
386
387 static int terminate(unsigned minor)
388 {
389 int rc;
390
391 /* Event 22: Request termination of 1284 mode */
392 set_pins(BPP_PP_nAutoFd|BPP_PP_nStrobe|BPP_PP_nInit, minor);
393
394 /* Wait for Events 23 and 24: ACK termination request. */
395 rc = wait_for(BPP_GP_Busy|BPP_GP_nFault,
396 BPP_GP_nAck,
397 TIME_PSetup+TIME_PResponse,
398 minor);
399
400 instances[minor].direction = 0;
401 instances[minor].mode = COMPATIBILITY;
402
403 if (rc == -1) {
404 return -EIO;
405 }
406
407 /* Event 25: Handshake by lowering nAutoFd */
408 set_pins(BPP_PP_nStrobe|BPP_PP_nInit, minor);
409
410 /* Event 26: Peripheral wiggles lines... */
411
412 /* Event 27: Peripheral sets nAck HIGH to ack handshake */
413 rc = wait_for(BPP_GP_nAck, 0, TIME_PResponse, minor);
414 if (rc == -1) {
415 set_pins(BPP_PP_nAutoFd|BPP_PP_nStrobe|BPP_PP_nInit, minor);
416 return -EIO;
417 }
418
419 /* Event 28: Finish phase by raising nAutoFd */
420 set_pins(BPP_PP_nAutoFd|BPP_PP_nStrobe|BPP_PP_nInit, minor);
421
422 return 0;
423 }
424
425 static DEFINE_SPINLOCK(bpp_open_lock);
426
427 /*
428 * Allow only one process to open the device at a time.
429 */
430 static int bpp_open(struct inode *inode, struct file *f)
431 {
432 unsigned minor = iminor(inode);
433 int ret;
434
435 spin_lock(&bpp_open_lock);
436 ret = 0;
437 if (minor >= BPP_NO) {
438 ret = -ENODEV;
439 } else {
440 if (! instances[minor].present) {
441 ret = -ENODEV;
442 } else {
443 if (instances[minor].opened)
444 ret = -EBUSY;
445 else
446 instances[minor].opened = 1;
447 }
448 }
449 spin_unlock(&bpp_open_lock);
450
451 return ret;
452 }
453
454 /*
455 * When the process closes the device, this method is called to clean
456 * up and reset the hardware. Always leave the device in compatibility
457 * mode as this is a reasonable place to clean up from messes made by
458 * ioctls, or other mayhem.
459 */
460 static int bpp_release(struct inode *inode, struct file *f)
461 {
462 unsigned minor = iminor(inode);
463
464 spin_lock(&bpp_open_lock);
465 instances[minor].opened = 0;
466
467 if (instances[minor].mode != COMPATIBILITY)
468 terminate(minor);
469
470 spin_unlock(&bpp_open_lock);
471
472 return 0;
473 }
474
475 static long read_nibble(unsigned minor, char __user *c, unsigned long cnt)
476 {
477 unsigned long remaining = cnt;
478 long rc;
479
480 while (remaining > 0) {
481 unsigned char byte = 0;
482 int pins;
483
484 /* Event 7: request nibble */
485 set_pins(BPP_PP_nSelectIn|BPP_PP_nStrobe, minor);
486
487 /* Wait for event 9: Peripher strobes first nibble */
488 pins = wait_for(0, BPP_GP_nAck, TIME_IDLE_LIMIT, minor);
489 if (pins == -1) return -ETIMEDOUT;
490
491 /* Event 10: I handshake nibble */
492 set_pins(BPP_PP_nSelectIn|BPP_PP_nStrobe|BPP_PP_nAutoFd, minor);
493 if (pins & BPP_GP_nFault) byte |= 0x01;
494 if (pins & BPP_GP_Select) byte |= 0x02;
495 if (pins & BPP_GP_PError) byte |= 0x04;
496 if (pins & BPP_GP_Busy) byte |= 0x08;
497
498 /* Wait for event 11: Peripheral handshakes nibble */
499 rc = wait_for(BPP_GP_nAck, 0, TIME_PResponse, minor);
500
501 /* Event 7: request nibble */
502 set_pins(BPP_PP_nSelectIn|BPP_PP_nStrobe, minor);
503
504 /* Wait for event 9: Peripher strobes first nibble */
505 pins = wait_for(0, BPP_GP_nAck, TIME_PResponse, minor);
506 if (rc == -1) return -ETIMEDOUT;
507
508 /* Event 10: I handshake nibble */
509 set_pins(BPP_PP_nSelectIn|BPP_PP_nStrobe|BPP_PP_nAutoFd, minor);
510 if (pins & BPP_GP_nFault) byte |= 0x10;
511 if (pins & BPP_GP_Select) byte |= 0x20;
512 if (pins & BPP_GP_PError) byte |= 0x40;
513 if (pins & BPP_GP_Busy) byte |= 0x80;
514
515 if (put_user(byte, c))
516 return -EFAULT;
517 c += 1;
518 remaining -= 1;
519
520 /* Wait for event 11: Peripheral handshakes nibble */
521 rc = wait_for(BPP_GP_nAck, 0, TIME_PResponse, minor);
522 if (rc == -1) return -EIO;
523 }
524
525 return cnt - remaining;
526 }
527
528 static long read_ecp(unsigned minor, char __user *c, unsigned long cnt)
529 {
530 unsigned long remaining;
531 long rc;
532
533 /* Turn ECP mode from forward to reverse if needed. */
534 if (! instances[minor].direction) {
535 unsigned short pins = get_pins(minor);
536
537 /* Event 38: Turn the bus around */
538 instances[minor].direction = 0x20;
539 pins &= ~BPP_PP_nAutoFd;
540 set_pins(pins, minor);
541
542 /* Event 39: Set pins for reverse mode. */
543 snooze(TIME_PSetup, minor);
544 set_pins(BPP_PP_nStrobe|BPP_PP_nSelectIn, minor);
545
546 /* Wait for event 40: Peripheral ready to be strobed */
547 rc = wait_for(0, BPP_GP_PError, TIME_PResponse, minor);
548 if (rc == -1) return -ETIMEDOUT;
549 }
550
551 remaining = cnt;
552
553 while (remaining > 0) {
554
555 /* If there is a run length for a repeated byte, repeat */
556 /* that byte a few times. */
557 if (instances[minor].run_length && !instances[minor].run_flag) {
558
559 char buffer[128];
560 unsigned idx;
561 unsigned repeat = remaining < instances[minor].run_length
562 ? remaining
563 : instances[minor].run_length;
564
565 for (idx = 0 ; idx < repeat ; idx += 1)
566 buffer[idx] = instances[minor].repeat_byte;
567
568 if (copy_to_user(c, buffer, repeat))
569 return -EFAULT;
570 remaining -= repeat;
571 c += repeat;
572 instances[minor].run_length -= repeat;
573 }
574
575 if (remaining == 0) break;
576
577
578 /* Wait for Event 43: Data active on the bus. */
579 rc = wait_for(0, BPP_GP_nAck, TIME_IDLE_LIMIT, minor);
580 if (rc == -1) break;
581
582 if (rc & BPP_GP_Busy) {
583 /* OK, this is data. read it in. */
584 unsigned char byte = bpp_inb(base_addrs[minor]);
585 if (put_user(byte, c))
586 return -EFAULT;
587 c += 1;
588 remaining -= 1;
589
590 if (instances[minor].run_flag) {
591 instances[minor].repeat_byte = byte;
592 instances[minor].run_flag = 0;
593 }
594
595 } else {
596 unsigned char byte = bpp_inb(base_addrs[minor]);
597 if (byte & 0x80) {
598 printk("bpp%d: "
599 "Ignoring ECP channel %u from device.\n",
600 minor, byte & 0x7f);
601 } else {
602 instances[minor].run_length = byte;
603 instances[minor].run_flag = 1;
604 }
605 }
606
607 /* Event 44: I got it. */
608 set_pins(BPP_PP_nStrobe|BPP_PP_nAutoFd|BPP_PP_nSelectIn, minor);
609
610 /* Wait for event 45: peripheral handshake */
611 rc = wait_for(BPP_GP_nAck, 0, TIME_PResponse, minor);
612 if (rc == -1) return -ETIMEDOUT;
613
614 /* Event 46: Finish handshake */
615 set_pins(BPP_PP_nStrobe|BPP_PP_nSelectIn, minor);
616
617 }
618
619
620 return cnt - remaining;
621 }
622
623 static ssize_t bpp_read(struct file *f, char __user *c, size_t cnt, loff_t * ppos)
624 {
625 long rc;
626 unsigned minor = iminor(f->f_dentry->d_inode);
627 if (minor >= BPP_NO) return -ENODEV;
628 if (!instances[minor].present) return -ENODEV;
629
630 switch (instances[minor].mode) {
631
632 default:
633 if (instances[minor].mode != COMPATIBILITY)
634 terminate(minor);
635
636 if (instances[minor].enhanced) {
637 /* For now, do all reads with ECP-RLE mode */
638 unsigned short pins;
639
640 rc = negotiate(DEFAULT_ECP, minor);
641 if (rc < 0) break;
642
643 instances[minor].mode = ECP_RLE;
644
645 /* Event 30: set nAutoFd low to setup for ECP mode */
646 pins = get_pins(minor);
647 pins &= ~BPP_PP_nAutoFd;
648 set_pins(pins, minor);
649
650 /* Wait for Event 31: peripheral ready */
651 rc = wait_for(BPP_GP_PError, 0, TIME_PResponse, minor);
652 if (rc == -1) return -ETIMEDOUT;
653
654 rc = read_ecp(minor, c, cnt);
655
656 } else {
657 rc = negotiate(DEFAULT_NIBBLE, minor);
658 if (rc < 0) break;
659
660 instances[minor].mode = NIBBLE;
661
662 rc = read_nibble(minor, c, cnt);
663 }
664 break;
665
666 case NIBBLE:
667 rc = read_nibble(minor, c, cnt);
668 break;
669
670 case ECP:
671 case ECP_RLE:
672 rc = read_ecp(minor, c, cnt);
673 break;
674
675 }
676
677
678 return rc;
679 }
680
681 /*
682 * Compatibility mode handshaking is a matter of writing data,
683 * strobing it, and waiting for the printer to stop being busy.
684 */
685 static long write_compat(unsigned minor, const char __user *c, unsigned long cnt)
686 {
687 long rc;
688 unsigned short pins = get_pins(minor);
689
690 unsigned long remaining = cnt;
691
692
693 while (remaining > 0) {
694 unsigned char byte;
695
696 if (get_user(byte, c))
697 return -EFAULT;
698 c += 1;
699
700 rc = wait_for(BPP_GP_nAck, BPP_GP_Busy, TIME_IDLE_LIMIT, minor);
701 if (rc == -1) return -ETIMEDOUT;
702
703 bpp_outb_p(byte, base_addrs[minor]);
704 remaining -= 1;
705 /* snooze(1, minor); */
706
707 pins &= ~BPP_PP_nStrobe;
708 set_pins(pins, minor);
709
710 rc = wait_for(BPP_GP_Busy, 0, TIME_PResponse, minor);
711
712 pins |= BPP_PP_nStrobe;
713 set_pins(pins, minor);
714 }
715
716 return cnt - remaining;
717 }
718
719 /*
720 * Write data using ECP mode. Watch out that the port may be set up
721 * for reading. If so, turn the port around.
722 */
723 static long write_ecp(unsigned minor, const char __user *c, unsigned long cnt)
724 {
725 unsigned short pins = get_pins(minor);
726 unsigned long remaining = cnt;
727
728 if (instances[minor].direction) {
729 int rc;
730
731 /* Event 47 Request bus be turned around */
732 pins |= BPP_PP_nInit;
733 set_pins(pins, minor);
734
735 /* Wait for Event 49: Peripheral relinquished bus */
736 rc = wait_for(BPP_GP_PError, 0, TIME_PResponse, minor);
737
738 pins |= BPP_PP_nAutoFd;
739 instances[minor].direction = 0;
740 set_pins(pins, minor);
741 }
742
743 while (remaining > 0) {
744 unsigned char byte;
745 int rc;
746
747 if (get_user(byte, c))
748 return -EFAULT;
749
750 rc = wait_for(0, BPP_GP_Busy, TIME_PResponse, minor);
751 if (rc == -1) return -ETIMEDOUT;
752
753 c += 1;
754
755 bpp_outb_p(byte, base_addrs[minor]);
756
757 pins &= ~BPP_PP_nStrobe;
758 set_pins(pins, minor);
759
760 pins |= BPP_PP_nStrobe;
761 rc = wait_for(BPP_GP_Busy, 0, TIME_PResponse, minor);
762 if (rc == -1) return -EIO;
763
764 set_pins(pins, minor);
765 }
766
767 return cnt - remaining;
768 }
769
770 /*
771 * Write to the peripheral. Be sensitive of the current mode. If I'm
772 * in a mode that can be turned around (ECP) then just do
773 * that. Otherwise, terminate and do my writing in compat mode. This
774 * is the safest course as any device can handle it.
775 */
776 static ssize_t bpp_write(struct file *f, const char __user *c, size_t cnt, loff_t * ppos)
777 {
778 long errno = 0;
779 unsigned minor = iminor(f->f_dentry->d_inode);
780 if (minor >= BPP_NO) return -ENODEV;
781 if (!instances[minor].present) return -ENODEV;
782
783 switch (instances[minor].mode) {
784
785 case ECP:
786 case ECP_RLE:
787 errno = write_ecp(minor, c, cnt);
788 break;
789 case COMPATIBILITY:
790 errno = write_compat(minor, c, cnt);
791 break;
792 default:
793 terminate(minor);
794 errno = write_compat(minor, c, cnt);
795 }
796
797 return errno;
798 }
799
800 static int bpp_ioctl(struct inode *inode, struct file *f, unsigned int cmd,
801 unsigned long arg)
802 {
803 int errno = 0;
804
805 unsigned minor = iminor(inode);
806 if (minor >= BPP_NO) return -ENODEV;
807 if (!instances[minor].present) return -ENODEV;
808
809
810 switch (cmd) {
811
812 case BPP_PUT_PINS:
813 set_pins(arg, minor);
814 break;
815
816 case BPP_GET_PINS:
817 errno = get_pins(minor);
818 break;
819
820 case BPP_PUT_DATA:
821 bpp_outb_p(arg, base_addrs[minor]);
822 break;
823
824 case BPP_GET_DATA:
825 errno = bpp_inb_p(base_addrs[minor]);
826 break;
827
828 case BPP_SET_INPUT:
829 if (arg)
830 if (instances[minor].enhanced) {
831 unsigned short bits = get_pins(minor);
832 instances[minor].direction = 0x20;
833 set_pins(bits, minor);
834 } else {
835 errno = -ENOTTY;
836 }
837 else {
838 unsigned short bits = get_pins(minor);
839 instances[minor].direction = 0x00;
840 set_pins(bits, minor);
841 }
842 break;
843
844 default:
845 errno = -EINVAL;
846 }
847
848 return errno;
849 }
850
851 static struct file_operations bpp_fops = {
852 .owner = THIS_MODULE,
853 .read = bpp_read,
854 .write = bpp_write,
855 .ioctl = bpp_ioctl,
856 .open = bpp_open,
857 .release = bpp_release,
858 };
859
860 #if defined(__i386__)
861
862 #define collectLptPorts() {}
863
864 static void probeLptPort(unsigned idx)
865 {
866 unsigned int testvalue;
867 const unsigned short lpAddr = base_addrs[idx];
868
869 instances[idx].present = 0;
870 instances[idx].enhanced = 0;
871 instances[idx].direction = 0;
872 instances[idx].mode = COMPATIBILITY;
873 instances[idx].run_length = 0;
874 instances[idx].run_flag = 0;
875 if (!request_region(lpAddr,3, dev_name)) return;
876
877 /*
878 * First, make sure the instance exists. Do this by writing to
879 * the data latch and reading the value back. If the port *is*
880 * present, test to see if it supports extended-mode
881 * operation. This will be required for IEEE1284 reverse
882 * transfers.
883 */
884
885 outb_p(BPP_PROBE_CODE, lpAddr);
886 for (testvalue=0; testvalue<BPP_DELAY; testvalue++)
887 ;
888 testvalue = inb_p(lpAddr);
889 if (testvalue == BPP_PROBE_CODE) {
890 unsigned save;
891 instances[idx].present = 1;
892
893 save = inb_p(lpAddr+2);
894 for (testvalue=0; testvalue<BPP_DELAY; testvalue++)
895 ;
896 outb_p(save|0x20, lpAddr+2);
897 for (testvalue=0; testvalue<BPP_DELAY; testvalue++)
898 ;
899 outb_p(~BPP_PROBE_CODE, lpAddr);
900 for (testvalue=0; testvalue<BPP_DELAY; testvalue++)
901 ;
902 testvalue = inb_p(lpAddr);
903 if ((testvalue&0xff) == (0xff&~BPP_PROBE_CODE))
904 instances[idx].enhanced = 0;
905 else
906 instances[idx].enhanced = 1;
907 outb_p(save, lpAddr+2);
908 }
909 else {
910 release_region(lpAddr,3);
911 }
912 /*
913 * Leave the port in compat idle mode.
914 */
915 set_pins(BPP_PP_nAutoFd|BPP_PP_nStrobe|BPP_PP_nInit, idx);
916
917 printk("bpp%d: Port at 0x%03x: Enhanced mode %s\n", idx, base_addrs[idx],
918 instances[idx].enhanced? "SUPPORTED" : "UNAVAILABLE");
919 }
920
921 static inline void freeLptPort(int idx)
922 {
923 release_region(base_addrs[idx], 3);
924 }
925
926 #endif
927
928 #if defined(__sparc__)
929
930 static void __iomem *map_bpp(struct sbus_dev *dev, int idx)
931 {
932 return sbus_ioremap(&dev->resource[0], 0, BPP_SIZE, "bpp");
933 }
934
935 static int collectLptPorts(void)
936 {
937 struct sbus_bus *bus;
938 struct sbus_dev *dev;
939 int count;
940
941 count = 0;
942 for_all_sbusdev(dev, bus) {
943 if (strcmp(dev->prom_name, "SUNW,bpp") == 0) {
944 if (count >= BPP_NO) {
945 printk(KERN_NOTICE
946 "bpp: More than %d bpp ports,"
947 " rest is ignored\n", BPP_NO);
948 return count;
949 }
950 base_addrs[count] = map_bpp(dev, count);
951 count++;
952 }
953 }
954 return count;
955 }
956
957 static void probeLptPort(unsigned idx)
958 {
959 void __iomem *rp = base_addrs[idx];
960 __u32 csr;
961 char *brand;
962
963 instances[idx].present = 0;
964 instances[idx].enhanced = 0;
965 instances[idx].direction = 0;
966 instances[idx].mode = COMPATIBILITY;
967 instances[idx].run_length = 0;
968 instances[idx].run_flag = 0;
969
970 if (!rp) return;
971
972 instances[idx].present = 1;
973 instances[idx].enhanced = 1; /* Sure */
974
975 csr = sbus_readl(rp + BPP_CSR);
976 if ((csr & P_DRAINING) != 0 && (csr & P_ERR_PEND) == 0) {
977 udelay(20);
978 csr = sbus_readl(rp + BPP_CSR);
979 if ((csr & P_DRAINING) != 0 && (csr & P_ERR_PEND) == 0) {
980 printk("bpp%d: DRAINING still active (0x%08x)\n", idx, csr);
981 }
982 }
983 printk("bpp%d: reset with 0x%08x ..", idx, csr);
984 sbus_writel((csr | P_RESET) & ~P_INT_EN, rp + BPP_CSR);
985 udelay(500);
986 sbus_writel(sbus_readl(rp + BPP_CSR) & ~P_RESET, rp + BPP_CSR);
987 csr = sbus_readl(rp + BPP_CSR);
988 printk(" done with csr=0x%08x ocr=0x%04x\n",
989 csr, sbus_readw(rp + BPP_OCR));
990
991 switch (csr & P_DEV_ID_MASK) {
992 case P_DEV_ID_ZEBRA:
993 brand = "Zebra";
994 break;
995 case P_DEV_ID_L64854:
996 brand = "DMA2";
997 break;
998 default:
999 brand = "Unknown";
1000 }
1001 printk("bpp%d: %s at %p\n", idx, brand, rp);
1002
1003 /*
1004 * Leave the port in compat idle mode.
1005 */
1006 set_pins(BPP_PP_nAutoFd|BPP_PP_nStrobe|BPP_PP_nInit, idx);
1007
1008 return;
1009 }
1010
1011 static inline void freeLptPort(int idx)
1012 {
1013 sbus_iounmap(base_addrs[idx], BPP_SIZE);
1014 }
1015
1016 #endif
1017
1018 static int __init bpp_init(void)
1019 {
1020 int rc;
1021 unsigned idx;
1022
1023 rc = collectLptPorts();
1024 if (rc == 0)
1025 return -ENODEV;
1026
1027 rc = register_chrdev(BPP_MAJOR, dev_name, &bpp_fops);
1028 if (rc < 0)
1029 return rc;
1030
1031 for (idx = 0; idx < BPP_NO; idx++) {
1032 instances[idx].opened = 0;
1033 probeLptPort(idx);
1034 }
1035 devfs_mk_dir("bpp");
1036 for (idx = 0; idx < BPP_NO; idx++) {
1037 devfs_mk_cdev(MKDEV(BPP_MAJOR, idx),
1038 S_IFCHR | S_IRUSR | S_IWUSR, "bpp/%d", idx);
1039 }
1040
1041 return 0;
1042 }
1043
1044 static void __exit bpp_cleanup(void)
1045 {
1046 unsigned idx;
1047
1048 for (idx = 0; idx < BPP_NO; idx++)
1049 devfs_remove("bpp/%d", idx);
1050 devfs_remove("bpp");
1051 unregister_chrdev(BPP_MAJOR, dev_name);
1052
1053 for (idx = 0; idx < BPP_NO; idx++) {
1054 if (instances[idx].present)
1055 freeLptPort(idx);
1056 }
1057 }
1058
1059 module_init(bpp_init);
1060 module_exit(bpp_cleanup);
1061
1062 MODULE_LICENSE("GPL");
1063
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