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[PATCH] W1: w1_netlink: New init/fini netlink callbacks.
[linux-2.6/verdex.git] / drivers / scsi / ahci.c
blob320df6cd3defd6195ffd3eb759ac11906b377586
1 /*
2 * ahci.c - AHCI SATA support
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004-2005 Red Hat, Inc.
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * AHCI hardware documentation:
30 * http://www.intel.com/technology/serialata/pdf/rev1_0.pdf
31 * http://www.intel.com/technology/serialata/pdf/rev1_1.pdf
32 *
33 */
34
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/sched.h>
43 #include <linux/dma-mapping.h>
44 #include "scsi.h"
45 #include <scsi/scsi_host.h>
46 #include <linux/libata.h>
47 #include <asm/io.h>
48
49 #define DRV_NAME "ahci"
50 #define DRV_VERSION "1.01"
51
52
53 enum {
54 AHCI_PCI_BAR = 5,
55 AHCI_MAX_SG = 168, /* hardware max is 64K */
56 AHCI_DMA_BOUNDARY = 0xffffffff,
57 AHCI_USE_CLUSTERING = 0,
58 AHCI_CMD_SLOT_SZ = 32 * 32,
59 AHCI_RX_FIS_SZ = 256,
60 AHCI_CMD_TBL_HDR = 0x80,
61 AHCI_CMD_TBL_CDB = 0x40,
62 AHCI_CMD_TBL_SZ = AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16),
63 AHCI_PORT_PRIV_DMA_SZ = AHCI_CMD_SLOT_SZ + AHCI_CMD_TBL_SZ +
64 AHCI_RX_FIS_SZ,
65 AHCI_IRQ_ON_SG = (1 << 31),
66 AHCI_CMD_ATAPI = (1 << 5),
67 AHCI_CMD_WRITE = (1 << 6),
68
69 RX_FIS_D2H_REG = 0x40, /* offset of D2H Register FIS data */
70
71 board_ahci = 0,
72
73 /* global controller registers */
74 HOST_CAP = 0x00, /* host capabilities */
75 HOST_CTL = 0x04, /* global host control */
76 HOST_IRQ_STAT = 0x08, /* interrupt status */
77 HOST_PORTS_IMPL = 0x0c, /* bitmap of implemented ports */
78 HOST_VERSION = 0x10, /* AHCI spec. version compliancy */
79
80 /* HOST_CTL bits */
81 HOST_RESET = (1 << 0), /* reset controller; self-clear */
82 HOST_IRQ_EN = (1 << 1), /* global IRQ enable */
83 HOST_AHCI_EN = (1 << 31), /* AHCI enabled */
84
85 /* HOST_CAP bits */
86 HOST_CAP_64 = (1 << 31), /* PCI DAC (64-bit DMA) support */
87
88 /* registers for each SATA port */
89 PORT_LST_ADDR = 0x00, /* command list DMA addr */
90 PORT_LST_ADDR_HI = 0x04, /* command list DMA addr hi */
91 PORT_FIS_ADDR = 0x08, /* FIS rx buf addr */
92 PORT_FIS_ADDR_HI = 0x0c, /* FIS rx buf addr hi */
93 PORT_IRQ_STAT = 0x10, /* interrupt status */
94 PORT_IRQ_MASK = 0x14, /* interrupt enable/disable mask */
95 PORT_CMD = 0x18, /* port command */
96 PORT_TFDATA = 0x20, /* taskfile data */
97 PORT_SIG = 0x24, /* device TF signature */
98 PORT_CMD_ISSUE = 0x38, /* command issue */
99 PORT_SCR = 0x28, /* SATA phy register block */
100 PORT_SCR_STAT = 0x28, /* SATA phy register: SStatus */
101 PORT_SCR_CTL = 0x2c, /* SATA phy register: SControl */
102 PORT_SCR_ERR = 0x30, /* SATA phy register: SError */
103 PORT_SCR_ACT = 0x34, /* SATA phy register: SActive */
104
105 /* PORT_IRQ_{STAT,MASK} bits */
106 PORT_IRQ_COLD_PRES = (1 << 31), /* cold presence detect */
107 PORT_IRQ_TF_ERR = (1 << 30), /* task file error */
108 PORT_IRQ_HBUS_ERR = (1 << 29), /* host bus fatal error */
109 PORT_IRQ_HBUS_DATA_ERR = (1 << 28), /* host bus data error */
110 PORT_IRQ_IF_ERR = (1 << 27), /* interface fatal error */
111 PORT_IRQ_IF_NONFATAL = (1 << 26), /* interface non-fatal error */
112 PORT_IRQ_OVERFLOW = (1 << 24), /* xfer exhausted available S/G */
113 PORT_IRQ_BAD_PMP = (1 << 23), /* incorrect port multiplier */
114
115 PORT_IRQ_PHYRDY = (1 << 22), /* PhyRdy changed */
116 PORT_IRQ_DEV_ILCK = (1 << 7), /* device interlock */
117 PORT_IRQ_CONNECT = (1 << 6), /* port connect change status */
118 PORT_IRQ_SG_DONE = (1 << 5), /* descriptor processed */
119 PORT_IRQ_UNK_FIS = (1 << 4), /* unknown FIS rx'd */
120 PORT_IRQ_SDB_FIS = (1 << 3), /* Set Device Bits FIS rx'd */
121 PORT_IRQ_DMAS_FIS = (1 << 2), /* DMA Setup FIS rx'd */
122 PORT_IRQ_PIOS_FIS = (1 << 1), /* PIO Setup FIS rx'd */
123 PORT_IRQ_D2H_REG_FIS = (1 << 0), /* D2H Register FIS rx'd */
124
125 PORT_IRQ_FATAL = PORT_IRQ_TF_ERR |
126 PORT_IRQ_HBUS_ERR |
127 PORT_IRQ_HBUS_DATA_ERR |
128 PORT_IRQ_IF_ERR,
129 DEF_PORT_IRQ = PORT_IRQ_FATAL | PORT_IRQ_PHYRDY |
130 PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE |
131 PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS |
132 PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS |
133 PORT_IRQ_D2H_REG_FIS,
134
135 /* PORT_CMD bits */
136 PORT_CMD_LIST_ON = (1 << 15), /* cmd list DMA engine running */
137 PORT_CMD_FIS_ON = (1 << 14), /* FIS DMA engine running */
138 PORT_CMD_FIS_RX = (1 << 4), /* Enable FIS receive DMA engine */
139 PORT_CMD_POWER_ON = (1 << 2), /* Power up device */
140 PORT_CMD_SPIN_UP = (1 << 1), /* Spin up device */
141 PORT_CMD_START = (1 << 0), /* Enable port DMA engine */
142
143 PORT_CMD_ICC_ACTIVE = (0x1 << 28), /* Put i/f in active state */
144 PORT_CMD_ICC_PARTIAL = (0x2 << 28), /* Put i/f in partial state */
145 PORT_CMD_ICC_SLUMBER = (0x6 << 28), /* Put i/f in slumber state */
146
147 /* hpriv->flags bits */
148 AHCI_FLAG_MSI = (1 << 0),
149 };
150
151 struct ahci_cmd_hdr {
152 u32 opts;
153 u32 status;
154 u32 tbl_addr;
155 u32 tbl_addr_hi;
156 u32 reserved[4];
157 };
158
159 struct ahci_sg {
160 u32 addr;
161 u32 addr_hi;
162 u32 reserved;
163 u32 flags_size;
164 };
165
166 struct ahci_host_priv {
167 unsigned long flags;
168 u32 cap; /* cache of HOST_CAP register */
169 u32 port_map; /* cache of HOST_PORTS_IMPL reg */
170 };
171
172 struct ahci_port_priv {
173 struct ahci_cmd_hdr *cmd_slot;
174 dma_addr_t cmd_slot_dma;
175 void *cmd_tbl;
176 dma_addr_t cmd_tbl_dma;
177 struct ahci_sg *cmd_tbl_sg;
178 void *rx_fis;
179 dma_addr_t rx_fis_dma;
180 };
181
182 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg);
183 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
184 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
185 static int ahci_qc_issue(struct ata_queued_cmd *qc);
186 static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs);
187 static void ahci_phy_reset(struct ata_port *ap);
188 static void ahci_irq_clear(struct ata_port *ap);
189 static void ahci_eng_timeout(struct ata_port *ap);
190 static int ahci_port_start(struct ata_port *ap);
191 static void ahci_port_stop(struct ata_port *ap);
192 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf);
193 static void ahci_qc_prep(struct ata_queued_cmd *qc);
194 static u8 ahci_check_status(struct ata_port *ap);
195 static u8 ahci_check_err(struct ata_port *ap);
196 static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc);
197 static void ahci_remove_one (struct pci_dev *pdev);
198
199 static Scsi_Host_Template ahci_sht = {
200 .module = THIS_MODULE,
201 .name = DRV_NAME,
202 .ioctl = ata_scsi_ioctl,
203 .queuecommand = ata_scsi_queuecmd,
204 .eh_strategy_handler = ata_scsi_error,
205 .can_queue = ATA_DEF_QUEUE,
206 .this_id = ATA_SHT_THIS_ID,
207 .sg_tablesize = AHCI_MAX_SG,
208 .max_sectors = ATA_MAX_SECTORS,
209 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
210 .emulated = ATA_SHT_EMULATED,
211 .use_clustering = AHCI_USE_CLUSTERING,
212 .proc_name = DRV_NAME,
213 .dma_boundary = AHCI_DMA_BOUNDARY,
214 .slave_configure = ata_scsi_slave_config,
215 .bios_param = ata_std_bios_param,
216 .ordered_flush = 1,
217 };
218
219 static struct ata_port_operations ahci_ops = {
220 .port_disable = ata_port_disable,
221
222 .check_status = ahci_check_status,
223 .check_altstatus = ahci_check_status,
224 .check_err = ahci_check_err,
225 .dev_select = ata_noop_dev_select,
226
227 .tf_read = ahci_tf_read,
228
229 .phy_reset = ahci_phy_reset,
230
231 .qc_prep = ahci_qc_prep,
232 .qc_issue = ahci_qc_issue,
233
234 .eng_timeout = ahci_eng_timeout,
235
236 .irq_handler = ahci_interrupt,
237 .irq_clear = ahci_irq_clear,
238
239 .scr_read = ahci_scr_read,
240 .scr_write = ahci_scr_write,
241
242 .port_start = ahci_port_start,
243 .port_stop = ahci_port_stop,
244 };
245
246 static struct ata_port_info ahci_port_info[] = {
247 /* board_ahci */
248 {
249 .sht = &ahci_sht,
250 .host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
251 ATA_FLAG_SATA_RESET | ATA_FLAG_MMIO |
252 ATA_FLAG_PIO_DMA,
253 .pio_mask = 0x1f, /* pio0-4 */
254 .udma_mask = 0x7f, /* udma0-6 ; FIXME */
255 .port_ops = &ahci_ops,
256 },
257 };
258
259 static struct pci_device_id ahci_pci_tbl[] = {
260 { PCI_VENDOR_ID_INTEL, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
261 board_ahci }, /* ICH6 */
262 { PCI_VENDOR_ID_INTEL, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
263 board_ahci }, /* ICH6M */
264 { PCI_VENDOR_ID_INTEL, 0x27c1, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
265 board_ahci }, /* ICH7 */
266 { PCI_VENDOR_ID_INTEL, 0x27c5, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
267 board_ahci }, /* ICH7M */
268 { PCI_VENDOR_ID_INTEL, 0x27c3, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
269 board_ahci }, /* ICH7R */
270 { PCI_VENDOR_ID_AL, 0x5288, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
271 board_ahci }, /* ULi M5288 */
272 { PCI_VENDOR_ID_INTEL, 0x2681, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
273 board_ahci }, /* ESB2 */
274 { PCI_VENDOR_ID_INTEL, 0x2682, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
275 board_ahci }, /* ESB2 */
276 { PCI_VENDOR_ID_INTEL, 0x2683, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
277 board_ahci }, /* ESB2 */
278 { PCI_VENDOR_ID_INTEL, 0x27c6, PCI_ANY_ID, PCI_ANY_ID, 0, 0,
279 board_ahci }, /* ICH7-M DH */
280 { } /* terminate list */
281 };
282
283
284 static struct pci_driver ahci_pci_driver = {
285 .name = DRV_NAME,
286 .id_table = ahci_pci_tbl,
287 .probe = ahci_init_one,
288 .remove = ahci_remove_one,
289 };
290
291
292 static inline unsigned long ahci_port_base_ul (unsigned long base, unsigned int port)
293 {
294 return base + 0x100 + (port * 0x80);
295 }
296
297 static inline void __iomem *ahci_port_base (void __iomem *base, unsigned int port)
298 {
299 return (void __iomem *) ahci_port_base_ul((unsigned long)base, port);
300 }
301
302 static int ahci_port_start(struct ata_port *ap)
303 {
304 struct device *dev = ap->host_set->dev;
305 struct ahci_host_priv *hpriv = ap->host_set->private_data;
306 struct ahci_port_priv *pp;
307 void __iomem *mmio = ap->host_set->mmio_base;
308 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
309 void *mem;
310 dma_addr_t mem_dma;
311
312 pp = kmalloc(sizeof(*pp), GFP_KERNEL);
313 if (!pp)
314 return -ENOMEM;
315 memset(pp, 0, sizeof(*pp));
316
317 mem = dma_alloc_coherent(dev, AHCI_PORT_PRIV_DMA_SZ, &mem_dma, GFP_KERNEL);
318 if (!mem) {
319 kfree(pp);
320 return -ENOMEM;
321 }
322 memset(mem, 0, AHCI_PORT_PRIV_DMA_SZ);
323
324 /*
325 * First item in chunk of DMA memory: 32-slot command table,
326 * 32 bytes each in size
327 */
328 pp->cmd_slot = mem;
329 pp->cmd_slot_dma = mem_dma;
330
331 mem += AHCI_CMD_SLOT_SZ;
332 mem_dma += AHCI_CMD_SLOT_SZ;
333
334 /*
335 * Second item: Received-FIS area
336 */
337 pp->rx_fis = mem;
338 pp->rx_fis_dma = mem_dma;
339
340 mem += AHCI_RX_FIS_SZ;
341 mem_dma += AHCI_RX_FIS_SZ;
342
343 /*
344 * Third item: data area for storing a single command
345 * and its scatter-gather table
346 */
347 pp->cmd_tbl = mem;
348 pp->cmd_tbl_dma = mem_dma;
349
350 pp->cmd_tbl_sg = mem + AHCI_CMD_TBL_HDR;
351
352 ap->private_data = pp;
353
354 if (hpriv->cap & HOST_CAP_64)
355 writel((pp->cmd_slot_dma >> 16) >> 16, port_mmio + PORT_LST_ADDR_HI);
356 writel(pp->cmd_slot_dma & 0xffffffff, port_mmio + PORT_LST_ADDR);
357 readl(port_mmio + PORT_LST_ADDR); /* flush */
358
359 if (hpriv->cap & HOST_CAP_64)
360 writel((pp->rx_fis_dma >> 16) >> 16, port_mmio + PORT_FIS_ADDR_HI);
361 writel(pp->rx_fis_dma & 0xffffffff, port_mmio + PORT_FIS_ADDR);
362 readl(port_mmio + PORT_FIS_ADDR); /* flush */
363
364 writel(PORT_CMD_ICC_ACTIVE | PORT_CMD_FIS_RX |
365 PORT_CMD_POWER_ON | PORT_CMD_SPIN_UP |
366 PORT_CMD_START, port_mmio + PORT_CMD);
367 readl(port_mmio + PORT_CMD); /* flush */
368
369 return 0;
370 }
371
372
373 static void ahci_port_stop(struct ata_port *ap)
374 {
375 struct device *dev = ap->host_set->dev;
376 struct ahci_port_priv *pp = ap->private_data;
377 void __iomem *mmio = ap->host_set->mmio_base;
378 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
379 u32 tmp;
380
381 tmp = readl(port_mmio + PORT_CMD);
382 tmp &= ~(PORT_CMD_START | PORT_CMD_FIS_RX);
383 writel(tmp, port_mmio + PORT_CMD);
384 readl(port_mmio + PORT_CMD); /* flush */
385
386 /* spec says 500 msecs for each PORT_CMD_{START,FIS_RX} bit, so
387 * this is slightly incorrect.
388 */
389 msleep(500);
390
391 ap->private_data = NULL;
392 dma_free_coherent(dev, AHCI_PORT_PRIV_DMA_SZ,
393 pp->cmd_slot, pp->cmd_slot_dma);
394 kfree(pp);
395 }
396
397 static u32 ahci_scr_read (struct ata_port *ap, unsigned int sc_reg_in)
398 {
399 unsigned int sc_reg;
400
401 switch (sc_reg_in) {
402 case SCR_STATUS: sc_reg = 0; break;
403 case SCR_CONTROL: sc_reg = 1; break;
404 case SCR_ERROR: sc_reg = 2; break;
405 case SCR_ACTIVE: sc_reg = 3; break;
406 default:
407 return 0xffffffffU;
408 }
409
410 return readl((void *) ap->ioaddr.scr_addr + (sc_reg * 4));
411 }
412
413
414 static void ahci_scr_write (struct ata_port *ap, unsigned int sc_reg_in,
415 u32 val)
416 {
417 unsigned int sc_reg;
418
419 switch (sc_reg_in) {
420 case SCR_STATUS: sc_reg = 0; break;
421 case SCR_CONTROL: sc_reg = 1; break;
422 case SCR_ERROR: sc_reg = 2; break;
423 case SCR_ACTIVE: sc_reg = 3; break;
424 default:
425 return;
426 }
427
428 writel(val, (void *) ap->ioaddr.scr_addr + (sc_reg * 4));
429 }
430
431 static void ahci_phy_reset(struct ata_port *ap)
432 {
433 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
434 struct ata_taskfile tf;
435 struct ata_device *dev = &ap->device[0];
436 u32 tmp;
437
438 __sata_phy_reset(ap);
439
440 if (ap->flags & ATA_FLAG_PORT_DISABLED)
441 return;
442
443 tmp = readl(port_mmio + PORT_SIG);
444 tf.lbah = (tmp >> 24) & 0xff;
445 tf.lbam = (tmp >> 16) & 0xff;
446 tf.lbal = (tmp >> 8) & 0xff;
447 tf.nsect = (tmp) & 0xff;
448
449 dev->class = ata_dev_classify(&tf);
450 if (!ata_dev_present(dev))
451 ata_port_disable(ap);
452 }
453
454 static u8 ahci_check_status(struct ata_port *ap)
455 {
456 void *mmio = (void *) ap->ioaddr.cmd_addr;
457
458 return readl(mmio + PORT_TFDATA) & 0xFF;
459 }
460
461 static u8 ahci_check_err(struct ata_port *ap)
462 {
463 void *mmio = (void *) ap->ioaddr.cmd_addr;
464
465 return (readl(mmio + PORT_TFDATA) >> 8) & 0xFF;
466 }
467
468 static void ahci_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
469 {
470 struct ahci_port_priv *pp = ap->private_data;
471 u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
472
473 ata_tf_from_fis(d2h_fis, tf);
474 }
475
476 static void ahci_fill_sg(struct ata_queued_cmd *qc)
477 {
478 struct ahci_port_priv *pp = qc->ap->private_data;
479 unsigned int i;
480
481 VPRINTK("ENTER\n");
482
483 /*
484 * Next, the S/G list.
485 */
486 for (i = 0; i < qc->n_elem; i++) {
487 u32 sg_len;
488 dma_addr_t addr;
489
490 addr = sg_dma_address(&qc->sg[i]);
491 sg_len = sg_dma_len(&qc->sg[i]);
492
493 pp->cmd_tbl_sg[i].addr = cpu_to_le32(addr & 0xffffffff);
494 pp->cmd_tbl_sg[i].addr_hi = cpu_to_le32((addr >> 16) >> 16);
495 pp->cmd_tbl_sg[i].flags_size = cpu_to_le32(sg_len - 1);
496 }
497 }
498
499 static void ahci_qc_prep(struct ata_queued_cmd *qc)
500 {
501 struct ata_port *ap = qc->ap;
502 struct ahci_port_priv *pp = ap->private_data;
503 u32 opts;
504 const u32 cmd_fis_len = 5; /* five dwords */
505
506 /*
507 * Fill in command slot information (currently only one slot,
508 * slot 0, is currently since we don't do queueing)
509 */
510
511 opts = (qc->n_elem << 16) | cmd_fis_len;
512 if (qc->tf.flags & ATA_TFLAG_WRITE)
513 opts |= AHCI_CMD_WRITE;
514 if (is_atapi_taskfile(&qc->tf))
515 opts |= AHCI_CMD_ATAPI;
516
517 pp->cmd_slot[0].opts = cpu_to_le32(opts);
518 pp->cmd_slot[0].status = 0;
519 pp->cmd_slot[0].tbl_addr = cpu_to_le32(pp->cmd_tbl_dma & 0xffffffff);
520 pp->cmd_slot[0].tbl_addr_hi = cpu_to_le32((pp->cmd_tbl_dma >> 16) >> 16);
521
522 /*
523 * Fill in command table information. First, the header,
524 * a SATA Register - Host to Device command FIS.
525 */
526 ata_tf_to_fis(&qc->tf, pp->cmd_tbl, 0);
527 if (opts & AHCI_CMD_ATAPI) {
528 memset(pp->cmd_tbl + AHCI_CMD_TBL_CDB, 0, 32);
529 memcpy(pp->cmd_tbl + AHCI_CMD_TBL_CDB, qc->cdb, ap->cdb_len);
530 }
531
532 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
533 return;
534
535 ahci_fill_sg(qc);
536 }
537
538 static void ahci_intr_error(struct ata_port *ap, u32 irq_stat)
539 {
540 void __iomem *mmio = ap->host_set->mmio_base;
541 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
542 u32 tmp;
543 int work;
544
545 /* stop DMA */
546 tmp = readl(port_mmio + PORT_CMD);
547 tmp &= ~PORT_CMD_START;
548 writel(tmp, port_mmio + PORT_CMD);
549
550 /* wait for engine to stop. TODO: this could be
551 * as long as 500 msec
552 */
553 work = 1000;
554 while (work-- > 0) {
555 tmp = readl(port_mmio + PORT_CMD);
556 if ((tmp & PORT_CMD_LIST_ON) == 0)
557 break;
558 udelay(10);
559 }
560
561 /* clear SATA phy error, if any */
562 tmp = readl(port_mmio + PORT_SCR_ERR);
563 writel(tmp, port_mmio + PORT_SCR_ERR);
564
565 /* if DRQ/BSY is set, device needs to be reset.
566 * if so, issue COMRESET
567 */
568 tmp = readl(port_mmio + PORT_TFDATA);
569 if (tmp & (ATA_BUSY | ATA_DRQ)) {
570 writel(0x301, port_mmio + PORT_SCR_CTL);
571 readl(port_mmio + PORT_SCR_CTL); /* flush */
572 udelay(10);
573 writel(0x300, port_mmio + PORT_SCR_CTL);
574 readl(port_mmio + PORT_SCR_CTL); /* flush */
575 }
576
577 /* re-start DMA */
578 tmp = readl(port_mmio + PORT_CMD);
579 tmp |= PORT_CMD_START;
580 writel(tmp, port_mmio + PORT_CMD);
581 readl(port_mmio + PORT_CMD); /* flush */
582
583 printk(KERN_WARNING "ata%u: error occurred, port reset\n", ap->id);
584 }
585
586 static void ahci_eng_timeout(struct ata_port *ap)
587 {
588 struct ata_host_set *host_set = ap->host_set;
589 void __iomem *mmio = host_set->mmio_base;
590 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
591 struct ata_queued_cmd *qc;
592 unsigned long flags;
593
594 DPRINTK("ENTER\n");
595
596 spin_lock_irqsave(&host_set->lock, flags);
597
598 ahci_intr_error(ap, readl(port_mmio + PORT_IRQ_STAT));
599
600 qc = ata_qc_from_tag(ap, ap->active_tag);
601 if (!qc) {
602 printk(KERN_ERR "ata%u: BUG: timeout without command\n",
603 ap->id);
604 } else {
605 /* hack alert! We cannot use the supplied completion
606 * function from inside the ->eh_strategy_handler() thread.
607 * libata is the only user of ->eh_strategy_handler() in
608 * any kernel, so the default scsi_done() assumes it is
609 * not being called from the SCSI EH.
610 */
611 qc->scsidone = scsi_finish_command;
612 ata_qc_complete(qc, ATA_ERR);
613 }
614
615 spin_unlock_irqrestore(&host_set->lock, flags);
616 }
617
618 static inline int ahci_host_intr(struct ata_port *ap, struct ata_queued_cmd *qc)
619 {
620 void __iomem *mmio = ap->host_set->mmio_base;
621 void __iomem *port_mmio = ahci_port_base(mmio, ap->port_no);
622 u32 status, serr, ci;
623
624 serr = readl(port_mmio + PORT_SCR_ERR);
625 writel(serr, port_mmio + PORT_SCR_ERR);
626
627 status = readl(port_mmio + PORT_IRQ_STAT);
628 writel(status, port_mmio + PORT_IRQ_STAT);
629
630 ci = readl(port_mmio + PORT_CMD_ISSUE);
631 if (likely((ci & 0x1) == 0)) {
632 if (qc) {
633 ata_qc_complete(qc, 0);
634 qc = NULL;
635 }
636 }
637
638 if (status & PORT_IRQ_FATAL) {
639 ahci_intr_error(ap, status);
640 if (qc)
641 ata_qc_complete(qc, ATA_ERR);
642 }
643
644 return 1;
645 }
646
647 static void ahci_irq_clear(struct ata_port *ap)
648 {
649 /* TODO */
650 }
651
652 static irqreturn_t ahci_interrupt (int irq, void *dev_instance, struct pt_regs *regs)
653 {
654 struct ata_host_set *host_set = dev_instance;
655 struct ahci_host_priv *hpriv;
656 unsigned int i, handled = 0;
657 void __iomem *mmio;
658 u32 irq_stat, irq_ack = 0;
659
660 VPRINTK("ENTER\n");
661
662 hpriv = host_set->private_data;
663 mmio = host_set->mmio_base;
664
665 /* sigh. 0xffffffff is a valid return from h/w */
666 irq_stat = readl(mmio + HOST_IRQ_STAT);
667 irq_stat &= hpriv->port_map;
668 if (!irq_stat)
669 return IRQ_NONE;
670
671 spin_lock(&host_set->lock);
672
673 for (i = 0; i < host_set->n_ports; i++) {
674 struct ata_port *ap;
675 u32 tmp;
676
677 VPRINTK("port %u\n", i);
678 ap = host_set->ports[i];
679 tmp = irq_stat & (1 << i);
680 if (tmp && ap) {
681 struct ata_queued_cmd *qc;
682 qc = ata_qc_from_tag(ap, ap->active_tag);
683 if (ahci_host_intr(ap, qc))
684 irq_ack |= (1 << i);
685 }
686 }
687
688 if (irq_ack) {
689 writel(irq_ack, mmio + HOST_IRQ_STAT);
690 handled = 1;
691 }
692
693 spin_unlock(&host_set->lock);
694
695 VPRINTK("EXIT\n");
696
697 return IRQ_RETVAL(handled);
698 }
699
700 static int ahci_qc_issue(struct ata_queued_cmd *qc)
701 {
702 struct ata_port *ap = qc->ap;
703 void __iomem *port_mmio = (void __iomem *) ap->ioaddr.cmd_addr;
704
705 writel(1, port_mmio + PORT_CMD_ISSUE);
706 readl(port_mmio + PORT_CMD_ISSUE); /* flush */
707
708 return 0;
709 }
710
711 static void ahci_setup_port(struct ata_ioports *port, unsigned long base,
712 unsigned int port_idx)
713 {
714 VPRINTK("ENTER, base==0x%lx, port_idx %u\n", base, port_idx);
715 base = ahci_port_base_ul(base, port_idx);
716 VPRINTK("base now==0x%lx\n", base);
717
718 port->cmd_addr = base;
719 port->scr_addr = base + PORT_SCR;
720
721 VPRINTK("EXIT\n");
722 }
723
724 static int ahci_host_init(struct ata_probe_ent *probe_ent)
725 {
726 struct ahci_host_priv *hpriv = probe_ent->private_data;
727 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
728 void __iomem *mmio = probe_ent->mmio_base;
729 u32 tmp, cap_save;
730 u16 tmp16;
731 unsigned int i, j, using_dac;
732 int rc;
733 void __iomem *port_mmio;
734
735 cap_save = readl(mmio + HOST_CAP);
736 cap_save &= ( (1<<28) | (1<<17) );
737 cap_save |= (1 << 27);
738
739 /* global controller reset */
740 tmp = readl(mmio + HOST_CTL);
741 if ((tmp & HOST_RESET) == 0) {
742 writel(tmp | HOST_RESET, mmio + HOST_CTL);
743 readl(mmio + HOST_CTL); /* flush */
744 }
745
746 /* reset must complete within 1 second, or
747 * the hardware should be considered fried.
748 */
749 ssleep(1);
750
751 tmp = readl(mmio + HOST_CTL);
752 if (tmp & HOST_RESET) {
753 printk(KERN_ERR DRV_NAME "(%s): controller reset failed (0x%x)\n",
754 pci_name(pdev), tmp);
755 return -EIO;
756 }
757
758 writel(HOST_AHCI_EN, mmio + HOST_CTL);
759 (void) readl(mmio + HOST_CTL); /* flush */
760 writel(cap_save, mmio + HOST_CAP);
761 writel(0xf, mmio + HOST_PORTS_IMPL);
762 (void) readl(mmio + HOST_PORTS_IMPL); /* flush */
763
764 pci_read_config_word(pdev, 0x92, &tmp16);
765 tmp16 |= 0xf;
766 pci_write_config_word(pdev, 0x92, tmp16);
767
768 hpriv->cap = readl(mmio + HOST_CAP);
769 hpriv->port_map = readl(mmio + HOST_PORTS_IMPL);
770 probe_ent->n_ports = (hpriv->cap & 0x1f) + 1;
771
772 VPRINTK("cap 0x%x port_map 0x%x n_ports %d\n",
773 hpriv->cap, hpriv->port_map, probe_ent->n_ports);
774
775 using_dac = hpriv->cap & HOST_CAP_64;
776 if (using_dac &&
777 !pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
778 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
779 if (rc) {
780 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
781 if (rc) {
782 printk(KERN_ERR DRV_NAME "(%s): 64-bit DMA enable failed\n",
783 pci_name(pdev));
784 return rc;
785 }
786 }
787 } else {
788 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
789 if (rc) {
790 printk(KERN_ERR DRV_NAME "(%s): 32-bit DMA enable failed\n",
791 pci_name(pdev));
792 return rc;
793 }
794 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
795 if (rc) {
796 printk(KERN_ERR DRV_NAME "(%s): 32-bit consistent DMA enable failed\n",
797 pci_name(pdev));
798 return rc;
799 }
800 }
801
802 for (i = 0; i < probe_ent->n_ports; i++) {
803 #if 0 /* BIOSen initialize this incorrectly */
804 if (!(hpriv->port_map & (1 << i)))
805 continue;
806 #endif
807
808 port_mmio = ahci_port_base(mmio, i);
809 VPRINTK("mmio %p port_mmio %p\n", mmio, port_mmio);
810
811 ahci_setup_port(&probe_ent->port[i],
812 (unsigned long) mmio, i);
813
814 /* make sure port is not active */
815 tmp = readl(port_mmio + PORT_CMD);
816 VPRINTK("PORT_CMD 0x%x\n", tmp);
817 if (tmp & (PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
818 PORT_CMD_FIS_RX | PORT_CMD_START)) {
819 tmp &= ~(PORT_CMD_LIST_ON | PORT_CMD_FIS_ON |
820 PORT_CMD_FIS_RX | PORT_CMD_START);
821 writel(tmp, port_mmio + PORT_CMD);
822 readl(port_mmio + PORT_CMD); /* flush */
823
824 /* spec says 500 msecs for each bit, so
825 * this is slightly incorrect.
826 */
827 msleep(500);
828 }
829
830 writel(PORT_CMD_SPIN_UP, port_mmio + PORT_CMD);
831
832 j = 0;
833 while (j < 100) {
834 msleep(10);
835 tmp = readl(port_mmio + PORT_SCR_STAT);
836 if ((tmp & 0xf) == 0x3)
837 break;
838 j++;
839 }
840
841 tmp = readl(port_mmio + PORT_SCR_ERR);
842 VPRINTK("PORT_SCR_ERR 0x%x\n", tmp);
843 writel(tmp, port_mmio + PORT_SCR_ERR);
844
845 /* ack any pending irq events for this port */
846 tmp = readl(port_mmio + PORT_IRQ_STAT);
847 VPRINTK("PORT_IRQ_STAT 0x%x\n", tmp);
848 if (tmp)
849 writel(tmp, port_mmio + PORT_IRQ_STAT);
850
851 writel(1 << i, mmio + HOST_IRQ_STAT);
852
853 /* set irq mask (enables interrupts) */
854 writel(DEF_PORT_IRQ, port_mmio + PORT_IRQ_MASK);
855 }
856
857 tmp = readl(mmio + HOST_CTL);
858 VPRINTK("HOST_CTL 0x%x\n", tmp);
859 writel(tmp | HOST_IRQ_EN, mmio + HOST_CTL);
860 tmp = readl(mmio + HOST_CTL);
861 VPRINTK("HOST_CTL 0x%x\n", tmp);
862
863 pci_set_master(pdev);
864
865 return 0;
866 }
867
868 /* move to PCI layer, integrate w/ MSI stuff */
869 static void pci_intx(struct pci_dev *pdev, int enable)
870 {
871 u16 pci_command, new;
872
873 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
874
875 if (enable)
876 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
877 else
878 new = pci_command | PCI_COMMAND_INTX_DISABLE;
879
880 if (new != pci_command)
881 pci_write_config_word(pdev, PCI_COMMAND, pci_command);
882 }
883
884 static void ahci_print_info(struct ata_probe_ent *probe_ent)
885 {
886 struct ahci_host_priv *hpriv = probe_ent->private_data;
887 struct pci_dev *pdev = to_pci_dev(probe_ent->dev);
888 void __iomem *mmio = probe_ent->mmio_base;
889 u32 vers, cap, impl, speed;
890 const char *speed_s;
891 u16 cc;
892 const char *scc_s;
893
894 vers = readl(mmio + HOST_VERSION);
895 cap = hpriv->cap;
896 impl = hpriv->port_map;
897
898 speed = (cap >> 20) & 0xf;
899 if (speed == 1)
900 speed_s = "1.5";
901 else if (speed == 2)
902 speed_s = "3";
903 else
904 speed_s = "?";
905
906 pci_read_config_word(pdev, 0x0a, &cc);
907 if (cc == 0x0101)
908 scc_s = "IDE";
909 else if (cc == 0x0106)
910 scc_s = "SATA";
911 else if (cc == 0x0104)
912 scc_s = "RAID";
913 else
914 scc_s = "unknown";
915
916 printk(KERN_INFO DRV_NAME "(%s) AHCI %02x%02x.%02x%02x "
917 "%u slots %u ports %s Gbps 0x%x impl %s mode\n"
918 ,
919 pci_name(pdev),
920
921 (vers >> 24) & 0xff,
922 (vers >> 16) & 0xff,
923 (vers >> 8) & 0xff,
924 vers & 0xff,
925
926 ((cap >> 8) & 0x1f) + 1,
927 (cap & 0x1f) + 1,
928 speed_s,
929 impl,
930 scc_s);
931
932 printk(KERN_INFO DRV_NAME "(%s) flags: "
933 "%s%s%s%s%s%s"
934 "%s%s%s%s%s%s%s\n"
935 ,
936 pci_name(pdev),
937
938 cap & (1 << 31) ? "64bit " : "",
939 cap & (1 << 30) ? "ncq " : "",
940 cap & (1 << 28) ? "ilck " : "",
941 cap & (1 << 27) ? "stag " : "",
942 cap & (1 << 26) ? "pm " : "",
943 cap & (1 << 25) ? "led " : "",
944
945 cap & (1 << 24) ? "clo " : "",
946 cap & (1 << 19) ? "nz " : "",
947 cap & (1 << 18) ? "only " : "",
948 cap & (1 << 17) ? "pmp " : "",
949 cap & (1 << 15) ? "pio " : "",
950 cap & (1 << 14) ? "slum " : "",
951 cap & (1 << 13) ? "part " : ""
952 );
953 }
954
955 static int ahci_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
956 {
957 static int printed_version;
958 struct ata_probe_ent *probe_ent = NULL;
959 struct ahci_host_priv *hpriv;
960 unsigned long base;
961 void __iomem *mmio_base;
962 unsigned int board_idx = (unsigned int) ent->driver_data;
963 int have_msi, pci_dev_busy = 0;
964 int rc;
965
966 VPRINTK("ENTER\n");
967
968 if (!printed_version++)
969 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
970
971 rc = pci_enable_device(pdev);
972 if (rc)
973 return rc;
974
975 rc = pci_request_regions(pdev, DRV_NAME);
976 if (rc) {
977 pci_dev_busy = 1;
978 goto err_out;
979 }
980
981 if (pci_enable_msi(pdev) == 0)
982 have_msi = 1;
983 else {
984 pci_intx(pdev, 1);
985 have_msi = 0;
986 }
987
988 probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
989 if (probe_ent == NULL) {
990 rc = -ENOMEM;
991 goto err_out_msi;
992 }
993
994 memset(probe_ent, 0, sizeof(*probe_ent));
995 probe_ent->dev = pci_dev_to_dev(pdev);
996 INIT_LIST_HEAD(&probe_ent->node);
997
998 mmio_base = pci_iomap(pdev, AHCI_PCI_BAR, 0);
999 if (mmio_base == NULL) {
1000 rc = -ENOMEM;
1001 goto err_out_free_ent;
1002 }
1003 base = (unsigned long) mmio_base;
1004
1005 hpriv = kmalloc(sizeof(*hpriv), GFP_KERNEL);
1006 if (!hpriv) {
1007 rc = -ENOMEM;
1008 goto err_out_iounmap;
1009 }
1010 memset(hpriv, 0, sizeof(*hpriv));
1011
1012 probe_ent->sht = ahci_port_info[board_idx].sht;
1013 probe_ent->host_flags = ahci_port_info[board_idx].host_flags;
1014 probe_ent->pio_mask = ahci_port_info[board_idx].pio_mask;
1015 probe_ent->udma_mask = ahci_port_info[board_idx].udma_mask;
1016 probe_ent->port_ops = ahci_port_info[board_idx].port_ops;
1017
1018 probe_ent->irq = pdev->irq;
1019 probe_ent->irq_flags = SA_SHIRQ;
1020 probe_ent->mmio_base = mmio_base;
1021 probe_ent->private_data = hpriv;
1022
1023 if (have_msi)
1024 hpriv->flags |= AHCI_FLAG_MSI;
1025
1026 /* initialize adapter */
1027 rc = ahci_host_init(probe_ent);
1028 if (rc)
1029 goto err_out_hpriv;
1030
1031 ahci_print_info(probe_ent);
1032
1033 /* FIXME: check ata_device_add return value */
1034 ata_device_add(probe_ent);
1035 kfree(probe_ent);
1036
1037 return 0;
1038
1039 err_out_hpriv:
1040 kfree(hpriv);
1041 err_out_iounmap:
1042 pci_iounmap(pdev, mmio_base);
1043 err_out_free_ent:
1044 kfree(probe_ent);
1045 err_out_msi:
1046 if (have_msi)
1047 pci_disable_msi(pdev);
1048 else
1049 pci_intx(pdev, 0);
1050 pci_release_regions(pdev);
1051 err_out:
1052 if (!pci_dev_busy)
1053 pci_disable_device(pdev);
1054 return rc;
1055 }
1056
1057 static void ahci_remove_one (struct pci_dev *pdev)
1058 {
1059 struct device *dev = pci_dev_to_dev(pdev);
1060 struct ata_host_set *host_set = dev_get_drvdata(dev);
1061 struct ahci_host_priv *hpriv = host_set->private_data;
1062 struct ata_port *ap;
1063 unsigned int i;
1064 int have_msi;
1065
1066 for (i = 0; i < host_set->n_ports; i++) {
1067 ap = host_set->ports[i];
1068
1069 scsi_remove_host(ap->host);
1070 }
1071
1072 have_msi = hpriv->flags & AHCI_FLAG_MSI;
1073 free_irq(host_set->irq, host_set);
1074
1075 for (i = 0; i < host_set->n_ports; i++) {
1076 ap = host_set->ports[i];
1077
1078 ata_scsi_release(ap->host);
1079 scsi_host_put(ap->host);
1080 }
1081
1082 kfree(hpriv);
1083 pci_iounmap(pdev, host_set->mmio_base);
1084 kfree(host_set);
1085
1086 if (have_msi)
1087 pci_disable_msi(pdev);
1088 else
1089 pci_intx(pdev, 0);
1090 pci_release_regions(pdev);
1091 pci_disable_device(pdev);
1092 dev_set_drvdata(dev, NULL);
1093 }
1094
1095 static int __init ahci_init(void)
1096 {
1097 return pci_module_init(&ahci_pci_driver);
1098 }
1099
1100 static void __exit ahci_exit(void)
1101 {
1102 pci_unregister_driver(&ahci_pci_driver);
1103 }
1104
1105
1106 MODULE_AUTHOR("Jeff Garzik");
1107 MODULE_DESCRIPTION("AHCI SATA low-level driver");
1108 MODULE_LICENSE("GPL");
1109 MODULE_DEVICE_TABLE(pci, ahci_pci_tbl);
1110 MODULE_VERSION(DRV_VERSION);
1111
1112 module_init(ahci_init);
1113 module_exit(ahci_exit);
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