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[PATCH] W1: w1_netlink: New init/fini netlink callbacks.
[linux-2.6/verdex.git] / drivers / scsi / aic7xxx / aic7xxx_core.c
blob58ac46103eb66d3db45242f5c06c5ef78fcbb40b
1 /*
2 * Core routines and tables shareable across OS platforms.
3 *
4 * Copyright (c) 1994-2002 Justin T. Gibbs.
5 * Copyright (c) 2000-2002 Adaptec Inc.
6 * All rights reserved.
7 *
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
10 * are met:
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * substantially similar to the "NO WARRANTY" disclaimer below
16 * ("Disclaimer") and any redistribution must be conditioned upon
17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
22 *
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
26 *
27 * NO WARRANTY
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGES.
39 *
40 * $Id: //depot/aic7xxx/aic7xxx/aic7xxx.c#155 $
41 */
42
43 #ifdef __linux__
44 #include "aic7xxx_osm.h"
45 #include "aic7xxx_inline.h"
46 #include "aicasm/aicasm_insformat.h"
47 #else
48 #include <dev/aic7xxx/aic7xxx_osm.h>
49 #include <dev/aic7xxx/aic7xxx_inline.h>
50 #include <dev/aic7xxx/aicasm/aicasm_insformat.h>
51 #endif
52
53 /***************************** Lookup Tables **********************************/
54 char *ahc_chip_names[] =
55 {
56 "NONE",
57 "aic7770",
58 "aic7850",
59 "aic7855",
60 "aic7859",
61 "aic7860",
62 "aic7870",
63 "aic7880",
64 "aic7895",
65 "aic7895C",
66 "aic7890/91",
67 "aic7896/97",
68 "aic7892",
69 "aic7899"
70 };
71 static const u_int num_chip_names = NUM_ELEMENTS(ahc_chip_names);
72
73 /*
74 * Hardware error codes.
75 */
76 struct ahc_hard_error_entry {
77 uint8_t errno;
78 char *errmesg;
79 };
80
81 static struct ahc_hard_error_entry ahc_hard_errors[] = {
82 { ILLHADDR, "Illegal Host Access" },
83 { ILLSADDR, "Illegal Sequencer Address referrenced" },
84 { ILLOPCODE, "Illegal Opcode in sequencer program" },
85 { SQPARERR, "Sequencer Parity Error" },
86 { DPARERR, "Data-path Parity Error" },
87 { MPARERR, "Scratch or SCB Memory Parity Error" },
88 { PCIERRSTAT, "PCI Error detected" },
89 { CIOPARERR, "CIOBUS Parity Error" },
90 };
91 static const u_int num_errors = NUM_ELEMENTS(ahc_hard_errors);
92
93 static struct ahc_phase_table_entry ahc_phase_table[] =
94 {
95 { P_DATAOUT, MSG_NOOP, "in Data-out phase" },
96 { P_DATAIN, MSG_INITIATOR_DET_ERR, "in Data-in phase" },
97 { P_DATAOUT_DT, MSG_NOOP, "in DT Data-out phase" },
98 { P_DATAIN_DT, MSG_INITIATOR_DET_ERR, "in DT Data-in phase" },
99 { P_COMMAND, MSG_NOOP, "in Command phase" },
100 { P_MESGOUT, MSG_NOOP, "in Message-out phase" },
101 { P_STATUS, MSG_INITIATOR_DET_ERR, "in Status phase" },
102 { P_MESGIN, MSG_PARITY_ERROR, "in Message-in phase" },
103 { P_BUSFREE, MSG_NOOP, "while idle" },
104 { 0, MSG_NOOP, "in unknown phase" }
105 };
106
107 /*
108 * In most cases we only wish to itterate over real phases, so
109 * exclude the last element from the count.
110 */
111 static const u_int num_phases = NUM_ELEMENTS(ahc_phase_table) - 1;
112
113 /*
114 * Valid SCSIRATE values. (p. 3-17)
115 * Provides a mapping of tranfer periods in ns to the proper value to
116 * stick in the scsixfer reg.
117 */
118 static struct ahc_syncrate ahc_syncrates[] =
119 {
120 /* ultra2 fast/ultra period rate */
121 { 0x42, 0x000, 9, "80.0" },
122 { 0x03, 0x000, 10, "40.0" },
123 { 0x04, 0x000, 11, "33.0" },
124 { 0x05, 0x100, 12, "20.0" },
125 { 0x06, 0x110, 15, "16.0" },
126 { 0x07, 0x120, 18, "13.4" },
127 { 0x08, 0x000, 25, "10.0" },
128 { 0x19, 0x010, 31, "8.0" },
129 { 0x1a, 0x020, 37, "6.67" },
130 { 0x1b, 0x030, 43, "5.7" },
131 { 0x1c, 0x040, 50, "5.0" },
132 { 0x00, 0x050, 56, "4.4" },
133 { 0x00, 0x060, 62, "4.0" },
134 { 0x00, 0x070, 68, "3.6" },
135 { 0x00, 0x000, 0, NULL }
136 };
137
138 /* Our Sequencer Program */
139 #include "aic7xxx_seq.h"
140
141 /**************************** Function Declarations ***************************/
142 static void ahc_force_renegotiation(struct ahc_softc *ahc,
143 struct ahc_devinfo *devinfo);
144 static struct ahc_tmode_tstate*
145 ahc_alloc_tstate(struct ahc_softc *ahc,
146 u_int scsi_id, char channel);
147 #ifdef AHC_TARGET_MODE
148 static void ahc_free_tstate(struct ahc_softc *ahc,
149 u_int scsi_id, char channel, int force);
150 #endif
151 static struct ahc_syncrate*
152 ahc_devlimited_syncrate(struct ahc_softc *ahc,
153 struct ahc_initiator_tinfo *,
154 u_int *period,
155 u_int *ppr_options,
156 role_t role);
157 static void ahc_update_pending_scbs(struct ahc_softc *ahc);
158 static void ahc_fetch_devinfo(struct ahc_softc *ahc,
159 struct ahc_devinfo *devinfo);
160 static void ahc_scb_devinfo(struct ahc_softc *ahc,
161 struct ahc_devinfo *devinfo,
162 struct scb *scb);
163 static void ahc_assert_atn(struct ahc_softc *ahc);
164 static void ahc_setup_initiator_msgout(struct ahc_softc *ahc,
165 struct ahc_devinfo *devinfo,
166 struct scb *scb);
167 static void ahc_build_transfer_msg(struct ahc_softc *ahc,
168 struct ahc_devinfo *devinfo);
169 static void ahc_construct_sdtr(struct ahc_softc *ahc,
170 struct ahc_devinfo *devinfo,
171 u_int period, u_int offset);
172 static void ahc_construct_wdtr(struct ahc_softc *ahc,
173 struct ahc_devinfo *devinfo,
174 u_int bus_width);
175 static void ahc_construct_ppr(struct ahc_softc *ahc,
176 struct ahc_devinfo *devinfo,
177 u_int period, u_int offset,
178 u_int bus_width, u_int ppr_options);
179 static void ahc_clear_msg_state(struct ahc_softc *ahc);
180 static void ahc_handle_proto_violation(struct ahc_softc *ahc);
181 static void ahc_handle_message_phase(struct ahc_softc *ahc);
182 typedef enum {
183 AHCMSG_1B,
184 AHCMSG_2B,
185 AHCMSG_EXT
186 } ahc_msgtype;
187 static int ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type,
188 u_int msgval, int full);
189 static int ahc_parse_msg(struct ahc_softc *ahc,
190 struct ahc_devinfo *devinfo);
191 static int ahc_handle_msg_reject(struct ahc_softc *ahc,
192 struct ahc_devinfo *devinfo);
193 static void ahc_handle_ign_wide_residue(struct ahc_softc *ahc,
194 struct ahc_devinfo *devinfo);
195 static void ahc_reinitialize_dataptrs(struct ahc_softc *ahc);
196 static void ahc_handle_devreset(struct ahc_softc *ahc,
197 struct ahc_devinfo *devinfo,
198 cam_status status, char *message,
199 int verbose_level);
200 #ifdef AHC_TARGET_MODE
201 static void ahc_setup_target_msgin(struct ahc_softc *ahc,
202 struct ahc_devinfo *devinfo,
203 struct scb *scb);
204 #endif
205
206 static bus_dmamap_callback_t ahc_dmamap_cb;
207 static void ahc_build_free_scb_list(struct ahc_softc *ahc);
208 static int ahc_init_scbdata(struct ahc_softc *ahc);
209 static void ahc_fini_scbdata(struct ahc_softc *ahc);
210 static void ahc_qinfifo_requeue(struct ahc_softc *ahc,
211 struct scb *prev_scb,
212 struct scb *scb);
213 static int ahc_qinfifo_count(struct ahc_softc *ahc);
214 static u_int ahc_rem_scb_from_disc_list(struct ahc_softc *ahc,
215 u_int prev, u_int scbptr);
216 static void ahc_add_curscb_to_free_list(struct ahc_softc *ahc);
217 static u_int ahc_rem_wscb(struct ahc_softc *ahc,
218 u_int scbpos, u_int prev);
219 static void ahc_reset_current_bus(struct ahc_softc *ahc);
220 #ifdef AHC_DUMP_SEQ
221 static void ahc_dumpseq(struct ahc_softc *ahc);
222 #endif
223 static int ahc_loadseq(struct ahc_softc *ahc);
224 static int ahc_check_patch(struct ahc_softc *ahc,
225 struct patch **start_patch,
226 u_int start_instr, u_int *skip_addr);
227 static void ahc_download_instr(struct ahc_softc *ahc,
228 u_int instrptr, uint8_t *dconsts);
229 #ifdef AHC_TARGET_MODE
230 static void ahc_queue_lstate_event(struct ahc_softc *ahc,
231 struct ahc_tmode_lstate *lstate,
232 u_int initiator_id,
233 u_int event_type,
234 u_int event_arg);
235 static void ahc_update_scsiid(struct ahc_softc *ahc,
236 u_int targid_mask);
237 static int ahc_handle_target_cmd(struct ahc_softc *ahc,
238 struct target_cmd *cmd);
239 #endif
240 /************************* Sequencer Execution Control ************************/
241 /*
242 * Restart the sequencer program from address zero
243 */
244 void
245 ahc_restart(struct ahc_softc *ahc)
246 {
247
248 ahc_pause(ahc);
249
250 /* No more pending messages. */
251 ahc_clear_msg_state(ahc);
252
253 ahc_outb(ahc, SCSISIGO, 0); /* De-assert BSY */
254 ahc_outb(ahc, MSG_OUT, MSG_NOOP); /* No message to send */
255 ahc_outb(ahc, SXFRCTL1, ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
256 ahc_outb(ahc, LASTPHASE, P_BUSFREE);
257 ahc_outb(ahc, SAVED_SCSIID, 0xFF);
258 ahc_outb(ahc, SAVED_LUN, 0xFF);
259
260 /*
261 * Ensure that the sequencer's idea of TQINPOS
262 * matches our own. The sequencer increments TQINPOS
263 * only after it sees a DMA complete and a reset could
264 * occur before the increment leaving the kernel to believe
265 * the command arrived but the sequencer to not.
266 */
267 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
268
269 /* Always allow reselection */
270 ahc_outb(ahc, SCSISEQ,
271 ahc_inb(ahc, SCSISEQ_TEMPLATE) & (ENSELI|ENRSELI|ENAUTOATNP));
272 if ((ahc->features & AHC_CMD_CHAN) != 0) {
273 /* Ensure that no DMA operations are in progress */
274 ahc_outb(ahc, CCSCBCNT, 0);
275 ahc_outb(ahc, CCSGCTL, 0);
276 ahc_outb(ahc, CCSCBCTL, 0);
277 }
278 /*
279 * If we were in the process of DMA'ing SCB data into
280 * an SCB, replace that SCB on the free list. This prevents
281 * an SCB leak.
282 */
283 if ((ahc_inb(ahc, SEQ_FLAGS2) & SCB_DMA) != 0) {
284 ahc_add_curscb_to_free_list(ahc);
285 ahc_outb(ahc, SEQ_FLAGS2,
286 ahc_inb(ahc, SEQ_FLAGS2) & ~SCB_DMA);
287 }
288
289 /*
290 * Clear any pending sequencer interrupt. It is no
291 * longer relevant since we're resetting the Program
292 * Counter.
293 */
294 ahc_outb(ahc, CLRINT, CLRSEQINT);
295
296 ahc_outb(ahc, MWI_RESIDUAL, 0);
297 ahc_outb(ahc, SEQCTL, ahc->seqctl);
298 ahc_outb(ahc, SEQADDR0, 0);
299 ahc_outb(ahc, SEQADDR1, 0);
300
301 ahc_unpause(ahc);
302 }
303
304 /************************* Input/Output Queues ********************************/
305 void
306 ahc_run_qoutfifo(struct ahc_softc *ahc)
307 {
308 struct scb *scb;
309 u_int scb_index;
310
311 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD);
312 while (ahc->qoutfifo[ahc->qoutfifonext] != SCB_LIST_NULL) {
313
314 scb_index = ahc->qoutfifo[ahc->qoutfifonext];
315 if ((ahc->qoutfifonext & 0x03) == 0x03) {
316 u_int modnext;
317
318 /*
319 * Clear 32bits of QOUTFIFO at a time
320 * so that we don't clobber an incoming
321 * byte DMA to the array on architectures
322 * that only support 32bit load and store
323 * operations.
324 */
325 modnext = ahc->qoutfifonext & ~0x3;
326 *((uint32_t *)(&ahc->qoutfifo[modnext])) = 0xFFFFFFFFUL;
327 ahc_dmamap_sync(ahc, ahc->shared_data_dmat,
328 ahc->shared_data_dmamap,
329 /*offset*/modnext, /*len*/4,
330 BUS_DMASYNC_PREREAD);
331 }
332 ahc->qoutfifonext++;
333
334 scb = ahc_lookup_scb(ahc, scb_index);
335 if (scb == NULL) {
336 printf("%s: WARNING no command for scb %d "
337 "(cmdcmplt)\nQOUTPOS = %d\n",
338 ahc_name(ahc), scb_index,
339 (ahc->qoutfifonext - 1) & 0xFF);
340 continue;
341 }
342
343 /*
344 * Save off the residual
345 * if there is one.
346 */
347 ahc_update_residual(ahc, scb);
348 ahc_done(ahc, scb);
349 }
350 }
351
352 void
353 ahc_run_untagged_queues(struct ahc_softc *ahc)
354 {
355 int i;
356
357 for (i = 0; i < 16; i++)
358 ahc_run_untagged_queue(ahc, &ahc->untagged_queues[i]);
359 }
360
361 void
362 ahc_run_untagged_queue(struct ahc_softc *ahc, struct scb_tailq *queue)
363 {
364 struct scb *scb;
365
366 if (ahc->untagged_queue_lock != 0)
367 return;
368
369 if ((scb = TAILQ_FIRST(queue)) != NULL
370 && (scb->flags & SCB_ACTIVE) == 0) {
371 scb->flags |= SCB_ACTIVE;
372 ahc_queue_scb(ahc, scb);
373 }
374 }
375
376 /************************* Interrupt Handling *********************************/
377 void
378 ahc_handle_brkadrint(struct ahc_softc *ahc)
379 {
380 /*
381 * We upset the sequencer :-(
382 * Lookup the error message
383 */
384 int i;
385 int error;
386
387 error = ahc_inb(ahc, ERROR);
388 for (i = 0; error != 1 && i < num_errors; i++)
389 error >>= 1;
390 printf("%s: brkadrint, %s at seqaddr = 0x%x\n",
391 ahc_name(ahc), ahc_hard_errors[i].errmesg,
392 ahc_inb(ahc, SEQADDR0) |
393 (ahc_inb(ahc, SEQADDR1) << 8));
394
395 ahc_dump_card_state(ahc);
396
397 /* Tell everyone that this HBA is no longer available */
398 ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, ALL_CHANNELS,
399 CAM_LUN_WILDCARD, SCB_LIST_NULL, ROLE_UNKNOWN,
400 CAM_NO_HBA);
401
402 /* Disable all interrupt sources by resetting the controller */
403 ahc_shutdown(ahc);
404 }
405
406 void
407 ahc_handle_seqint(struct ahc_softc *ahc, u_int intstat)
408 {
409 struct scb *scb;
410 struct ahc_devinfo devinfo;
411
412 ahc_fetch_devinfo(ahc, &devinfo);
413
414 /*
415 * Clear the upper byte that holds SEQINT status
416 * codes and clear the SEQINT bit. We will unpause
417 * the sequencer, if appropriate, after servicing
418 * the request.
419 */
420 ahc_outb(ahc, CLRINT, CLRSEQINT);
421 switch (intstat & SEQINT_MASK) {
422 case BAD_STATUS:
423 {
424 u_int scb_index;
425 struct hardware_scb *hscb;
426
427 /*
428 * Set the default return value to 0 (don't
429 * send sense). The sense code will change
430 * this if needed.
431 */
432 ahc_outb(ahc, RETURN_1, 0);
433
434 /*
435 * The sequencer will notify us when a command
436 * has an error that would be of interest to
437 * the kernel. This allows us to leave the sequencer
438 * running in the common case of command completes
439 * without error. The sequencer will already have
440 * dma'd the SCB back up to us, so we can reference
441 * the in kernel copy directly.
442 */
443 scb_index = ahc_inb(ahc, SCB_TAG);
444 scb = ahc_lookup_scb(ahc, scb_index);
445 if (scb == NULL) {
446 ahc_print_devinfo(ahc, &devinfo);
447 printf("ahc_intr - referenced scb "
448 "not valid during seqint 0x%x scb(%d)\n",
449 intstat, scb_index);
450 ahc_dump_card_state(ahc);
451 panic("for safety");
452 goto unpause;
453 }
454
455 hscb = scb->hscb;
456
457 /* Don't want to clobber the original sense code */
458 if ((scb->flags & SCB_SENSE) != 0) {
459 /*
460 * Clear the SCB_SENSE Flag and have
461 * the sequencer do a normal command
462 * complete.
463 */
464 scb->flags &= ~SCB_SENSE;
465 ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
466 break;
467 }
468 ahc_set_transaction_status(scb, CAM_SCSI_STATUS_ERROR);
469 /* Freeze the queue until the client sees the error. */
470 ahc_freeze_devq(ahc, scb);
471 ahc_freeze_scb(scb);
472 ahc_set_scsi_status(scb, hscb->shared_data.status.scsi_status);
473 switch (hscb->shared_data.status.scsi_status) {
474 case SCSI_STATUS_OK:
475 printf("%s: Interrupted for staus of 0???\n",
476 ahc_name(ahc));
477 break;
478 case SCSI_STATUS_CMD_TERMINATED:
479 case SCSI_STATUS_CHECK_COND:
480 {
481 struct ahc_dma_seg *sg;
482 struct scsi_sense *sc;
483 struct ahc_initiator_tinfo *targ_info;
484 struct ahc_tmode_tstate *tstate;
485 struct ahc_transinfo *tinfo;
486 #ifdef AHC_DEBUG
487 if (ahc_debug & AHC_SHOW_SENSE) {
488 ahc_print_path(ahc, scb);
489 printf("SCB %d: requests Check Status\n",
490 scb->hscb->tag);
491 }
492 #endif
493
494 if (ahc_perform_autosense(scb) == 0)
495 break;
496
497 targ_info = ahc_fetch_transinfo(ahc,
498 devinfo.channel,
499 devinfo.our_scsiid,
500 devinfo.target,
501 &tstate);
502 tinfo = &targ_info->curr;
503 sg = scb->sg_list;
504 sc = (struct scsi_sense *)(&hscb->shared_data.cdb);
505 /*
506 * Save off the residual if there is one.
507 */
508 ahc_update_residual(ahc, scb);
509 #ifdef AHC_DEBUG
510 if (ahc_debug & AHC_SHOW_SENSE) {
511 ahc_print_path(ahc, scb);
512 printf("Sending Sense\n");
513 }
514 #endif
515 sg->addr = ahc_get_sense_bufaddr(ahc, scb);
516 sg->len = ahc_get_sense_bufsize(ahc, scb);
517 sg->len |= AHC_DMA_LAST_SEG;
518
519 /* Fixup byte order */
520 sg->addr = ahc_htole32(sg->addr);
521 sg->len = ahc_htole32(sg->len);
522
523 sc->opcode = REQUEST_SENSE;
524 sc->byte2 = 0;
525 if (tinfo->protocol_version <= SCSI_REV_2
526 && SCB_GET_LUN(scb) < 8)
527 sc->byte2 = SCB_GET_LUN(scb) << 5;
528 sc->unused[0] = 0;
529 sc->unused[1] = 0;
530 sc->length = sg->len;
531 sc->control = 0;
532
533 /*
534 * We can't allow the target to disconnect.
535 * This will be an untagged transaction and
536 * having the target disconnect will make this
537 * transaction indestinguishable from outstanding
538 * tagged transactions.
539 */
540 hscb->control = 0;
541
542 /*
543 * This request sense could be because the
544 * the device lost power or in some other
545 * way has lost our transfer negotiations.
546 * Renegotiate if appropriate. Unit attention
547 * errors will be reported before any data
548 * phases occur.
549 */
550 if (ahc_get_residual(scb)
551 == ahc_get_transfer_length(scb)) {
552 ahc_update_neg_request(ahc, &devinfo,
553 tstate, targ_info,
554 AHC_NEG_IF_NON_ASYNC);
555 }
556 if (tstate->auto_negotiate & devinfo.target_mask) {
557 hscb->control |= MK_MESSAGE;
558 scb->flags &= ~SCB_NEGOTIATE;
559 scb->flags |= SCB_AUTO_NEGOTIATE;
560 }
561 hscb->cdb_len = sizeof(*sc);
562 hscb->dataptr = sg->addr;
563 hscb->datacnt = sg->len;
564 hscb->sgptr = scb->sg_list_phys | SG_FULL_RESID;
565 hscb->sgptr = ahc_htole32(hscb->sgptr);
566 scb->sg_count = 1;
567 scb->flags |= SCB_SENSE;
568 ahc_qinfifo_requeue_tail(ahc, scb);
569 ahc_outb(ahc, RETURN_1, SEND_SENSE);
570 /*
571 * Ensure we have enough time to actually
572 * retrieve the sense.
573 */
574 ahc_scb_timer_reset(scb, 5 * 1000000);
575 break;
576 }
577 default:
578 break;
579 }
580 break;
581 }
582 case NO_MATCH:
583 {
584 /* Ensure we don't leave the selection hardware on */
585 ahc_outb(ahc, SCSISEQ,
586 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
587
588 printf("%s:%c:%d: no active SCB for reconnecting "
589 "target - issuing BUS DEVICE RESET\n",
590 ahc_name(ahc), devinfo.channel, devinfo.target);
591 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
592 "ARG_1 == 0x%x ACCUM = 0x%x\n",
593 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
594 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
595 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
596 "SINDEX == 0x%x\n",
597 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
598 ahc_index_busy_tcl(ahc,
599 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
600 ahc_inb(ahc, SAVED_LUN))),
601 ahc_inb(ahc, SINDEX));
602 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
603 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
604 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
605 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
606 ahc_inb(ahc, SCB_CONTROL));
607 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
608 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
609 printf("SXFRCTL0 == 0x%x\n", ahc_inb(ahc, SXFRCTL0));
610 printf("SEQCTL == 0x%x\n", ahc_inb(ahc, SEQCTL));
611 ahc_dump_card_state(ahc);
612 ahc->msgout_buf[0] = MSG_BUS_DEV_RESET;
613 ahc->msgout_len = 1;
614 ahc->msgout_index = 0;
615 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
616 ahc_outb(ahc, MSG_OUT, HOST_MSG);
617 ahc_assert_atn(ahc);
618 break;
619 }
620 case SEND_REJECT:
621 {
622 u_int rejbyte = ahc_inb(ahc, ACCUM);
623 printf("%s:%c:%d: Warning - unknown message received from "
624 "target (0x%x). Rejecting\n",
625 ahc_name(ahc), devinfo.channel, devinfo.target, rejbyte);
626 break;
627 }
628 case PROTO_VIOLATION:
629 {
630 ahc_handle_proto_violation(ahc);
631 break;
632 }
633 case IGN_WIDE_RES:
634 ahc_handle_ign_wide_residue(ahc, &devinfo);
635 break;
636 case PDATA_REINIT:
637 ahc_reinitialize_dataptrs(ahc);
638 break;
639 case BAD_PHASE:
640 {
641 u_int lastphase;
642
643 lastphase = ahc_inb(ahc, LASTPHASE);
644 printf("%s:%c:%d: unknown scsi bus phase %x, "
645 "lastphase = 0x%x. Attempting to continue\n",
646 ahc_name(ahc), devinfo.channel, devinfo.target,
647 lastphase, ahc_inb(ahc, SCSISIGI));
648 break;
649 }
650 case MISSED_BUSFREE:
651 {
652 u_int lastphase;
653
654 lastphase = ahc_inb(ahc, LASTPHASE);
655 printf("%s:%c:%d: Missed busfree. "
656 "Lastphase = 0x%x, Curphase = 0x%x\n",
657 ahc_name(ahc), devinfo.channel, devinfo.target,
658 lastphase, ahc_inb(ahc, SCSISIGI));
659 ahc_restart(ahc);
660 return;
661 }
662 case HOST_MSG_LOOP:
663 {
664 /*
665 * The sequencer has encountered a message phase
666 * that requires host assistance for completion.
667 * While handling the message phase(s), we will be
668 * notified by the sequencer after each byte is
669 * transfered so we can track bus phase changes.
670 *
671 * If this is the first time we've seen a HOST_MSG_LOOP
672 * interrupt, initialize the state of the host message
673 * loop.
674 */
675 if (ahc->msg_type == MSG_TYPE_NONE) {
676 struct scb *scb;
677 u_int scb_index;
678 u_int bus_phase;
679
680 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
681 if (bus_phase != P_MESGIN
682 && bus_phase != P_MESGOUT) {
683 printf("ahc_intr: HOST_MSG_LOOP bad "
684 "phase 0x%x\n",
685 bus_phase);
686 /*
687 * Probably transitioned to bus free before
688 * we got here. Just punt the message.
689 */
690 ahc_clear_intstat(ahc);
691 ahc_restart(ahc);
692 return;
693 }
694
695 scb_index = ahc_inb(ahc, SCB_TAG);
696 scb = ahc_lookup_scb(ahc, scb_index);
697 if (devinfo.role == ROLE_INITIATOR) {
698 if (scb == NULL)
699 panic("HOST_MSG_LOOP with "
700 "invalid SCB %x\n", scb_index);
701
702 if (bus_phase == P_MESGOUT)
703 ahc_setup_initiator_msgout(ahc,
704 &devinfo,
705 scb);
706 else {
707 ahc->msg_type =
708 MSG_TYPE_INITIATOR_MSGIN;
709 ahc->msgin_index = 0;
710 }
711 }
712 #ifdef AHC_TARGET_MODE
713 else {
714 if (bus_phase == P_MESGOUT) {
715 ahc->msg_type =
716 MSG_TYPE_TARGET_MSGOUT;
717 ahc->msgin_index = 0;
718 }
719 else
720 ahc_setup_target_msgin(ahc,
721 &devinfo,
722 scb);
723 }
724 #endif
725 }
726
727 ahc_handle_message_phase(ahc);
728 break;
729 }
730 case PERR_DETECTED:
731 {
732 /*
733 * If we've cleared the parity error interrupt
734 * but the sequencer still believes that SCSIPERR
735 * is true, it must be that the parity error is
736 * for the currently presented byte on the bus,
737 * and we are not in a phase (data-in) where we will
738 * eventually ack this byte. Ack the byte and
739 * throw it away in the hope that the target will
740 * take us to message out to deliver the appropriate
741 * error message.
742 */
743 if ((intstat & SCSIINT) == 0
744 && (ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0) {
745
746 if ((ahc->features & AHC_DT) == 0) {
747 u_int curphase;
748
749 /*
750 * The hardware will only let you ack bytes
751 * if the expected phase in SCSISIGO matches
752 * the current phase. Make sure this is
753 * currently the case.
754 */
755 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
756 ahc_outb(ahc, LASTPHASE, curphase);
757 ahc_outb(ahc, SCSISIGO, curphase);
758 }
759 if ((ahc_inb(ahc, SCSISIGI) & (CDI|MSGI)) == 0) {
760 int wait;
761
762 /*
763 * In a data phase. Faster to bitbucket
764 * the data than to individually ack each
765 * byte. This is also the only strategy
766 * that will work with AUTOACK enabled.
767 */
768 ahc_outb(ahc, SXFRCTL1,
769 ahc_inb(ahc, SXFRCTL1) | BITBUCKET);
770 wait = 5000;
771 while (--wait != 0) {
772 if ((ahc_inb(ahc, SCSISIGI)
773 & (CDI|MSGI)) != 0)
774 break;
775 ahc_delay(100);
776 }
777 ahc_outb(ahc, SXFRCTL1,
778 ahc_inb(ahc, SXFRCTL1) & ~BITBUCKET);
779 if (wait == 0) {
780 struct scb *scb;
781 u_int scb_index;
782
783 ahc_print_devinfo(ahc, &devinfo);
784 printf("Unable to clear parity error. "
785 "Resetting bus.\n");
786 scb_index = ahc_inb(ahc, SCB_TAG);
787 scb = ahc_lookup_scb(ahc, scb_index);
788 if (scb != NULL)
789 ahc_set_transaction_status(scb,
790 CAM_UNCOR_PARITY);
791 ahc_reset_channel(ahc, devinfo.channel,
792 /*init reset*/TRUE);
793 }
794 } else {
795 ahc_inb(ahc, SCSIDATL);
796 }
797 }
798 break;
799 }
800 case DATA_OVERRUN:
801 {
802 /*
803 * When the sequencer detects an overrun, it
804 * places the controller in "BITBUCKET" mode
805 * and allows the target to complete its transfer.
806 * Unfortunately, none of the counters get updated
807 * when the controller is in this mode, so we have
808 * no way of knowing how large the overrun was.
809 */
810 u_int scbindex = ahc_inb(ahc, SCB_TAG);
811 u_int lastphase = ahc_inb(ahc, LASTPHASE);
812 u_int i;
813
814 scb = ahc_lookup_scb(ahc, scbindex);
815 for (i = 0; i < num_phases; i++) {
816 if (lastphase == ahc_phase_table[i].phase)
817 break;
818 }
819 ahc_print_path(ahc, scb);
820 printf("data overrun detected %s."
821 " Tag == 0x%x.\n",
822 ahc_phase_table[i].phasemsg,
823 scb->hscb->tag);
824 ahc_print_path(ahc, scb);
825 printf("%s seen Data Phase. Length = %ld. NumSGs = %d.\n",
826 ahc_inb(ahc, SEQ_FLAGS) & DPHASE ? "Have" : "Haven't",
827 ahc_get_transfer_length(scb), scb->sg_count);
828 if (scb->sg_count > 0) {
829 for (i = 0; i < scb->sg_count; i++) {
830
831 printf("sg[%d] - Addr 0x%x%x : Length %d\n",
832 i,
833 (ahc_le32toh(scb->sg_list[i].len) >> 24
834 & SG_HIGH_ADDR_BITS),
835 ahc_le32toh(scb->sg_list[i].addr),
836 ahc_le32toh(scb->sg_list[i].len)
837 & AHC_SG_LEN_MASK);
838 }
839 }
840 /*
841 * Set this and it will take effect when the
842 * target does a command complete.
843 */
844 ahc_freeze_devq(ahc, scb);
845 if ((scb->flags & SCB_SENSE) == 0) {
846 ahc_set_transaction_status(scb, CAM_DATA_RUN_ERR);
847 } else {
848 scb->flags &= ~SCB_SENSE;
849 ahc_set_transaction_status(scb, CAM_AUTOSENSE_FAIL);
850 }
851 ahc_freeze_scb(scb);
852
853 if ((ahc->features & AHC_ULTRA2) != 0) {
854 /*
855 * Clear the channel in case we return
856 * to data phase later.
857 */
858 ahc_outb(ahc, SXFRCTL0,
859 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
860 ahc_outb(ahc, SXFRCTL0,
861 ahc_inb(ahc, SXFRCTL0) | CLRSTCNT|CLRCHN);
862 }
863 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
864 u_int dscommand1;
865
866 /* Ensure HHADDR is 0 for future DMA operations. */
867 dscommand1 = ahc_inb(ahc, DSCOMMAND1);
868 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
869 ahc_outb(ahc, HADDR, 0);
870 ahc_outb(ahc, DSCOMMAND1, dscommand1);
871 }
872 break;
873 }
874 case MKMSG_FAILED:
875 {
876 u_int scbindex;
877
878 printf("%s:%c:%d:%d: Attempt to issue message failed\n",
879 ahc_name(ahc), devinfo.channel, devinfo.target,
880 devinfo.lun);
881 scbindex = ahc_inb(ahc, SCB_TAG);
882 scb = ahc_lookup_scb(ahc, scbindex);
883 if (scb != NULL
884 && (scb->flags & SCB_RECOVERY_SCB) != 0)
885 /*
886 * Ensure that we didn't put a second instance of this
887 * SCB into the QINFIFO.
888 */
889 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
890 SCB_GET_CHANNEL(ahc, scb),
891 SCB_GET_LUN(scb), scb->hscb->tag,
892 ROLE_INITIATOR, /*status*/0,
893 SEARCH_REMOVE);
894 break;
895 }
896 case NO_FREE_SCB:
897 {
898 printf("%s: No free or disconnected SCBs\n", ahc_name(ahc));
899 ahc_dump_card_state(ahc);
900 panic("for safety");
901 break;
902 }
903 case SCB_MISMATCH:
904 {
905 u_int scbptr;
906
907 scbptr = ahc_inb(ahc, SCBPTR);
908 printf("Bogus TAG after DMA. SCBPTR %d, tag %d, our tag %d\n",
909 scbptr, ahc_inb(ahc, ARG_1),
910 ahc->scb_data->hscbs[scbptr].tag);
911 ahc_dump_card_state(ahc);
912 panic("for saftey");
913 break;
914 }
915 case OUT_OF_RANGE:
916 {
917 printf("%s: BTT calculation out of range\n", ahc_name(ahc));
918 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
919 "ARG_1 == 0x%x ACCUM = 0x%x\n",
920 ahc_inb(ahc, SAVED_SCSIID), ahc_inb(ahc, SAVED_LUN),
921 ahc_inb(ahc, ARG_1), ahc_inb(ahc, ACCUM));
922 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
923 "SINDEX == 0x%x\n, A == 0x%x\n",
924 ahc_inb(ahc, SEQ_FLAGS), ahc_inb(ahc, SCBPTR),
925 ahc_index_busy_tcl(ahc,
926 BUILD_TCL(ahc_inb(ahc, SAVED_SCSIID),
927 ahc_inb(ahc, SAVED_LUN))),
928 ahc_inb(ahc, SINDEX),
929 ahc_inb(ahc, ACCUM));
930 printf("SCSIID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
931 "SCB_TAG == 0x%x, SCB_CONTROL == 0x%x\n",
932 ahc_inb(ahc, SCSIID), ahc_inb(ahc, SCB_SCSIID),
933 ahc_inb(ahc, SCB_LUN), ahc_inb(ahc, SCB_TAG),
934 ahc_inb(ahc, SCB_CONTROL));
935 printf("SCSIBUSL == 0x%x, SCSISIGI == 0x%x\n",
936 ahc_inb(ahc, SCSIBUSL), ahc_inb(ahc, SCSISIGI));
937 ahc_dump_card_state(ahc);
938 panic("for safety");
939 break;
940 }
941 default:
942 printf("ahc_intr: seqint, "
943 "intstat == 0x%x, scsisigi = 0x%x\n",
944 intstat, ahc_inb(ahc, SCSISIGI));
945 break;
946 }
947 unpause:
948 /*
949 * The sequencer is paused immediately on
950 * a SEQINT, so we should restart it when
951 * we're done.
952 */
953 ahc_unpause(ahc);
954 }
955
956 void
957 ahc_handle_scsiint(struct ahc_softc *ahc, u_int intstat)
958 {
959 u_int scb_index;
960 u_int status0;
961 u_int status;
962 struct scb *scb;
963 char cur_channel;
964 char intr_channel;
965
966 if ((ahc->features & AHC_TWIN) != 0
967 && ((ahc_inb(ahc, SBLKCTL) & SELBUSB) != 0))
968 cur_channel = 'B';
969 else
970 cur_channel = 'A';
971 intr_channel = cur_channel;
972
973 if ((ahc->features & AHC_ULTRA2) != 0)
974 status0 = ahc_inb(ahc, SSTAT0) & IOERR;
975 else
976 status0 = 0;
977 status = ahc_inb(ahc, SSTAT1) & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
978 if (status == 0 && status0 == 0) {
979 if ((ahc->features & AHC_TWIN) != 0) {
980 /* Try the other channel */
981 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
982 status = ahc_inb(ahc, SSTAT1)
983 & (SELTO|SCSIRSTI|BUSFREE|SCSIPERR);
984 intr_channel = (cur_channel == 'A') ? 'B' : 'A';
985 }
986 if (status == 0) {
987 printf("%s: Spurious SCSI interrupt\n", ahc_name(ahc));
988 ahc_outb(ahc, CLRINT, CLRSCSIINT);
989 ahc_unpause(ahc);
990 return;
991 }
992 }
993
994 /* Make sure the sequencer is in a safe location. */
995 ahc_clear_critical_section(ahc);
996
997 scb_index = ahc_inb(ahc, SCB_TAG);
998 scb = ahc_lookup_scb(ahc, scb_index);
999 if (scb != NULL
1000 && (ahc_inb(ahc, SEQ_FLAGS) & NOT_IDENTIFIED) != 0)
1001 scb = NULL;
1002
1003 if ((ahc->features & AHC_ULTRA2) != 0
1004 && (status0 & IOERR) != 0) {
1005 int now_lvd;
1006
1007 now_lvd = ahc_inb(ahc, SBLKCTL) & ENAB40;
1008 printf("%s: Transceiver State Has Changed to %s mode\n",
1009 ahc_name(ahc), now_lvd ? "LVD" : "SE");
1010 ahc_outb(ahc, CLRSINT0, CLRIOERR);
1011 /*
1012 * When transitioning to SE mode, the reset line
1013 * glitches, triggering an arbitration bug in some
1014 * Ultra2 controllers. This bug is cleared when we
1015 * assert the reset line. Since a reset glitch has
1016 * already occurred with this transition and a
1017 * transceiver state change is handled just like
1018 * a bus reset anyway, asserting the reset line
1019 * ourselves is safe.
1020 */
1021 ahc_reset_channel(ahc, intr_channel,
1022 /*Initiate Reset*/now_lvd == 0);
1023 } else if ((status & SCSIRSTI) != 0) {
1024 printf("%s: Someone reset channel %c\n",
1025 ahc_name(ahc), intr_channel);
1026 if (intr_channel != cur_channel)
1027 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) ^ SELBUSB);
1028 ahc_reset_channel(ahc, intr_channel, /*Initiate Reset*/FALSE);
1029 } else if ((status & SCSIPERR) != 0) {
1030 /*
1031 * Determine the bus phase and queue an appropriate message.
1032 * SCSIPERR is latched true as soon as a parity error
1033 * occurs. If the sequencer acked the transfer that
1034 * caused the parity error and the currently presented
1035 * transfer on the bus has correct parity, SCSIPERR will
1036 * be cleared by CLRSCSIPERR. Use this to determine if
1037 * we should look at the last phase the sequencer recorded,
1038 * or the current phase presented on the bus.
1039 */
1040 struct ahc_devinfo devinfo;
1041 u_int mesg_out;
1042 u_int curphase;
1043 u_int errorphase;
1044 u_int lastphase;
1045 u_int scsirate;
1046 u_int i;
1047 u_int sstat2;
1048 int silent;
1049
1050 lastphase = ahc_inb(ahc, LASTPHASE);
1051 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
1052 sstat2 = ahc_inb(ahc, SSTAT2);
1053 ahc_outb(ahc, CLRSINT1, CLRSCSIPERR);
1054 /*
1055 * For all phases save DATA, the sequencer won't
1056 * automatically ack a byte that has a parity error
1057 * in it. So the only way that the current phase
1058 * could be 'data-in' is if the parity error is for
1059 * an already acked byte in the data phase. During
1060 * synchronous data-in transfers, we may actually
1061 * ack bytes before latching the current phase in
1062 * LASTPHASE, leading to the discrepancy between
1063 * curphase and lastphase.
1064 */
1065 if ((ahc_inb(ahc, SSTAT1) & SCSIPERR) != 0
1066 || curphase == P_DATAIN || curphase == P_DATAIN_DT)
1067 errorphase = curphase;
1068 else
1069 errorphase = lastphase;
1070
1071 for (i = 0; i < num_phases; i++) {
1072 if (errorphase == ahc_phase_table[i].phase)
1073 break;
1074 }
1075 mesg_out = ahc_phase_table[i].mesg_out;
1076 silent = FALSE;
1077 if (scb != NULL) {
1078 if (SCB_IS_SILENT(scb))
1079 silent = TRUE;
1080 else
1081 ahc_print_path(ahc, scb);
1082 scb->flags |= SCB_TRANSMISSION_ERROR;
1083 } else
1084 printf("%s:%c:%d: ", ahc_name(ahc), intr_channel,
1085 SCSIID_TARGET(ahc, ahc_inb(ahc, SAVED_SCSIID)));
1086 scsirate = ahc_inb(ahc, SCSIRATE);
1087 if (silent == FALSE) {
1088 printf("parity error detected %s. "
1089 "SEQADDR(0x%x) SCSIRATE(0x%x)\n",
1090 ahc_phase_table[i].phasemsg,
1091 ahc_inw(ahc, SEQADDR0),
1092 scsirate);
1093 if ((ahc->features & AHC_DT) != 0) {
1094 if ((sstat2 & CRCVALERR) != 0)
1095 printf("\tCRC Value Mismatch\n");
1096 if ((sstat2 & CRCENDERR) != 0)
1097 printf("\tNo terminal CRC packet "
1098 "recevied\n");
1099 if ((sstat2 & CRCREQERR) != 0)
1100 printf("\tIllegal CRC packet "
1101 "request\n");
1102 if ((sstat2 & DUAL_EDGE_ERR) != 0)
1103 printf("\tUnexpected %sDT Data Phase\n",
1104 (scsirate & SINGLE_EDGE)
1105 ? "" : "non-");
1106 }
1107 }
1108
1109 if ((ahc->features & AHC_DT) != 0
1110 && (sstat2 & DUAL_EDGE_ERR) != 0) {
1111 /*
1112 * This error applies regardless of
1113 * data direction, so ignore the value
1114 * in the phase table.
1115 */
1116 mesg_out = MSG_INITIATOR_DET_ERR;
1117 }
1118
1119 /*
1120 * We've set the hardware to assert ATN if we
1121 * get a parity error on "in" phases, so all we
1122 * need to do is stuff the message buffer with
1123 * the appropriate message. "In" phases have set
1124 * mesg_out to something other than MSG_NOP.
1125 */
1126 if (mesg_out != MSG_NOOP) {
1127 if (ahc->msg_type != MSG_TYPE_NONE)
1128 ahc->send_msg_perror = TRUE;
1129 else
1130 ahc_outb(ahc, MSG_OUT, mesg_out);
1131 }
1132 /*
1133 * Force a renegotiation with this target just in
1134 * case we are out of sync for some external reason
1135 * unknown (or unreported) by the target.
1136 */
1137 ahc_fetch_devinfo(ahc, &devinfo);
1138 ahc_force_renegotiation(ahc, &devinfo);
1139
1140 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1141 ahc_unpause(ahc);
1142 } else if ((status & SELTO) != 0) {
1143 u_int scbptr;
1144
1145 /* Stop the selection */
1146 ahc_outb(ahc, SCSISEQ, 0);
1147
1148 /* No more pending messages */
1149 ahc_clear_msg_state(ahc);
1150
1151 /* Clear interrupt state */
1152 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
1153 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRBUSFREE|CLRSCSIPERR);
1154
1155 /*
1156 * Although the driver does not care about the
1157 * 'Selection in Progress' status bit, the busy
1158 * LED does. SELINGO is only cleared by a sucessfull
1159 * selection, so we must manually clear it to insure
1160 * the LED turns off just incase no future successful
1161 * selections occur (e.g. no devices on the bus).
1162 */
1163 ahc_outb(ahc, CLRSINT0, CLRSELINGO);
1164
1165 scbptr = ahc_inb(ahc, WAITING_SCBH);
1166 ahc_outb(ahc, SCBPTR, scbptr);
1167 scb_index = ahc_inb(ahc, SCB_TAG);
1168
1169 scb = ahc_lookup_scb(ahc, scb_index);
1170 if (scb == NULL) {
1171 printf("%s: ahc_intr - referenced scb not "
1172 "valid during SELTO scb(%d, %d)\n",
1173 ahc_name(ahc), scbptr, scb_index);
1174 ahc_dump_card_state(ahc);
1175 } else {
1176 struct ahc_devinfo devinfo;
1177 #ifdef AHC_DEBUG
1178 if ((ahc_debug & AHC_SHOW_SELTO) != 0) {
1179 ahc_print_path(ahc, scb);
1180 printf("Saw Selection Timeout for SCB 0x%x\n",
1181 scb_index);
1182 }
1183 #endif
1184 ahc_scb_devinfo(ahc, &devinfo, scb);
1185 ahc_set_transaction_status(scb, CAM_SEL_TIMEOUT);
1186 ahc_freeze_devq(ahc, scb);
1187
1188 /*
1189 * Cancel any pending transactions on the device
1190 * now that it seems to be missing. This will
1191 * also revert us to async/narrow transfers until
1192 * we can renegotiate with the device.
1193 */
1194 ahc_handle_devreset(ahc, &devinfo,
1195 CAM_SEL_TIMEOUT,
1196 "Selection Timeout",
1197 /*verbose_level*/1);
1198 }
1199 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1200 ahc_restart(ahc);
1201 } else if ((status & BUSFREE) != 0
1202 && (ahc_inb(ahc, SIMODE1) & ENBUSFREE) != 0) {
1203 struct ahc_devinfo devinfo;
1204 u_int lastphase;
1205 u_int saved_scsiid;
1206 u_int saved_lun;
1207 u_int target;
1208 u_int initiator_role_id;
1209 char channel;
1210 int printerror;
1211
1212 /*
1213 * Clear our selection hardware as soon as possible.
1214 * We may have an entry in the waiting Q for this target,
1215 * that is affected by this busfree and we don't want to
1216 * go about selecting the target while we handle the event.
1217 */
1218 ahc_outb(ahc, SCSISEQ,
1219 ahc_inb(ahc, SCSISEQ) & (ENSELI|ENRSELI|ENAUTOATNP));
1220
1221 /*
1222 * Disable busfree interrupts and clear the busfree
1223 * interrupt status. We do this here so that several
1224 * bus transactions occur prior to clearing the SCSIINT
1225 * latch. It can take a bit for the clearing to take effect.
1226 */
1227 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENBUSFREE);
1228 ahc_outb(ahc, CLRSINT1, CLRBUSFREE|CLRSCSIPERR);
1229
1230 /*
1231 * Look at what phase we were last in.
1232 * If its message out, chances are pretty good
1233 * that the busfree was in response to one of
1234 * our abort requests.
1235 */
1236 lastphase = ahc_inb(ahc, LASTPHASE);
1237 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
1238 saved_lun = ahc_inb(ahc, SAVED_LUN);
1239 target = SCSIID_TARGET(ahc, saved_scsiid);
1240 initiator_role_id = SCSIID_OUR_ID(saved_scsiid);
1241 channel = SCSIID_CHANNEL(ahc, saved_scsiid);
1242 ahc_compile_devinfo(&devinfo, initiator_role_id,
1243 target, saved_lun, channel, ROLE_INITIATOR);
1244 printerror = 1;
1245
1246 if (lastphase == P_MESGOUT) {
1247 u_int tag;
1248
1249 tag = SCB_LIST_NULL;
1250 if (ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT_TAG, TRUE)
1251 || ahc_sent_msg(ahc, AHCMSG_1B, MSG_ABORT, TRUE)) {
1252 if (ahc->msgout_buf[ahc->msgout_index - 1]
1253 == MSG_ABORT_TAG)
1254 tag = scb->hscb->tag;
1255 ahc_print_path(ahc, scb);
1256 printf("SCB %d - Abort%s Completed.\n",
1257 scb->hscb->tag, tag == SCB_LIST_NULL ?
1258 "" : " Tag");
1259 ahc_abort_scbs(ahc, target, channel,
1260 saved_lun, tag,
1261 ROLE_INITIATOR,
1262 CAM_REQ_ABORTED);
1263 printerror = 0;
1264 } else if (ahc_sent_msg(ahc, AHCMSG_1B,
1265 MSG_BUS_DEV_RESET, TRUE)) {
1266 #ifdef __FreeBSD__
1267 /*
1268 * Don't mark the user's request for this BDR
1269 * as completing with CAM_BDR_SENT. CAM3
1270 * specifies CAM_REQ_CMP.
1271 */
1272 if (scb != NULL
1273 && scb->io_ctx->ccb_h.func_code== XPT_RESET_DEV
1274 && ahc_match_scb(ahc, scb, target, channel,
1275 CAM_LUN_WILDCARD,
1276 SCB_LIST_NULL,
1277 ROLE_INITIATOR)) {
1278 ahc_set_transaction_status(scb, CAM_REQ_CMP);
1279 }
1280 #endif
1281 ahc_compile_devinfo(&devinfo,
1282 initiator_role_id,
1283 target,
1284 CAM_LUN_WILDCARD,
1285 channel,
1286 ROLE_INITIATOR);
1287 ahc_handle_devreset(ahc, &devinfo,
1288 CAM_BDR_SENT,
1289 "Bus Device Reset",
1290 /*verbose_level*/0);
1291 printerror = 0;
1292 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1293 MSG_EXT_PPR, FALSE)) {
1294 struct ahc_initiator_tinfo *tinfo;
1295 struct ahc_tmode_tstate *tstate;
1296
1297 /*
1298 * PPR Rejected. Try non-ppr negotiation
1299 * and retry command.
1300 */
1301 tinfo = ahc_fetch_transinfo(ahc,
1302 devinfo.channel,
1303 devinfo.our_scsiid,
1304 devinfo.target,
1305 &tstate);
1306 tinfo->curr.transport_version = 2;
1307 tinfo->goal.transport_version = 2;
1308 tinfo->goal.ppr_options = 0;
1309 ahc_qinfifo_requeue_tail(ahc, scb);
1310 printerror = 0;
1311 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1312 MSG_EXT_WDTR, FALSE)) {
1313 /*
1314 * Negotiation Rejected. Go-narrow and
1315 * retry command.
1316 */
1317 ahc_set_width(ahc, &devinfo,
1318 MSG_EXT_WDTR_BUS_8_BIT,
1319 AHC_TRANS_CUR|AHC_TRANS_GOAL,
1320 /*paused*/TRUE);
1321 ahc_qinfifo_requeue_tail(ahc, scb);
1322 printerror = 0;
1323 } else if (ahc_sent_msg(ahc, AHCMSG_EXT,
1324 MSG_EXT_SDTR, FALSE)) {
1325 /*
1326 * Negotiation Rejected. Go-async and
1327 * retry command.
1328 */
1329 ahc_set_syncrate(ahc, &devinfo,
1330 /*syncrate*/NULL,
1331 /*period*/0, /*offset*/0,
1332 /*ppr_options*/0,
1333 AHC_TRANS_CUR|AHC_TRANS_GOAL,
1334 /*paused*/TRUE);
1335 ahc_qinfifo_requeue_tail(ahc, scb);
1336 printerror = 0;
1337 }
1338 }
1339 if (printerror != 0) {
1340 u_int i;
1341
1342 if (scb != NULL) {
1343 u_int tag;
1344
1345 if ((scb->hscb->control & TAG_ENB) != 0)
1346 tag = scb->hscb->tag;
1347 else
1348 tag = SCB_LIST_NULL;
1349 ahc_print_path(ahc, scb);
1350 ahc_abort_scbs(ahc, target, channel,
1351 SCB_GET_LUN(scb), tag,
1352 ROLE_INITIATOR,
1353 CAM_UNEXP_BUSFREE);
1354 } else {
1355 /*
1356 * We had not fully identified this connection,
1357 * so we cannot abort anything.
1358 */
1359 printf("%s: ", ahc_name(ahc));
1360 }
1361 for (i = 0; i < num_phases; i++) {
1362 if (lastphase == ahc_phase_table[i].phase)
1363 break;
1364 }
1365 if (lastphase != P_BUSFREE) {
1366 /*
1367 * Renegotiate with this device at the
1368 * next oportunity just in case this busfree
1369 * is due to a negotiation mismatch with the
1370 * device.
1371 */
1372 ahc_force_renegotiation(ahc, &devinfo);
1373 }
1374 printf("Unexpected busfree %s\n"
1375 "SEQADDR == 0x%x\n",
1376 ahc_phase_table[i].phasemsg,
1377 ahc_inb(ahc, SEQADDR0)
1378 | (ahc_inb(ahc, SEQADDR1) << 8));
1379 }
1380 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1381 ahc_restart(ahc);
1382 } else {
1383 printf("%s: Missing case in ahc_handle_scsiint. status = %x\n",
1384 ahc_name(ahc), status);
1385 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1386 }
1387 }
1388
1389 /*
1390 * Force renegotiation to occur the next time we initiate
1391 * a command to the current device.
1392 */
1393 static void
1394 ahc_force_renegotiation(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
1395 {
1396 struct ahc_initiator_tinfo *targ_info;
1397 struct ahc_tmode_tstate *tstate;
1398
1399 targ_info = ahc_fetch_transinfo(ahc,
1400 devinfo->channel,
1401 devinfo->our_scsiid,
1402 devinfo->target,
1403 &tstate);
1404 ahc_update_neg_request(ahc, devinfo, tstate,
1405 targ_info, AHC_NEG_IF_NON_ASYNC);
1406 }
1407
1408 #define AHC_MAX_STEPS 2000
1409 void
1410 ahc_clear_critical_section(struct ahc_softc *ahc)
1411 {
1412 int stepping;
1413 int steps;
1414 u_int simode0;
1415 u_int simode1;
1416
1417 if (ahc->num_critical_sections == 0)
1418 return;
1419
1420 stepping = FALSE;
1421 steps = 0;
1422 simode0 = 0;
1423 simode1 = 0;
1424 for (;;) {
1425 struct cs *cs;
1426 u_int seqaddr;
1427 u_int i;
1428
1429 seqaddr = ahc_inb(ahc, SEQADDR0)
1430 | (ahc_inb(ahc, SEQADDR1) << 8);
1431
1432 /*
1433 * Seqaddr represents the next instruction to execute,
1434 * so we are really executing the instruction just
1435 * before it.
1436 */
1437 if (seqaddr != 0)
1438 seqaddr -= 1;
1439 cs = ahc->critical_sections;
1440 for (i = 0; i < ahc->num_critical_sections; i++, cs++) {
1441
1442 if (cs->begin < seqaddr && cs->end >= seqaddr)
1443 break;
1444 }
1445
1446 if (i == ahc->num_critical_sections)
1447 break;
1448
1449 if (steps > AHC_MAX_STEPS) {
1450 printf("%s: Infinite loop in critical section\n",
1451 ahc_name(ahc));
1452 ahc_dump_card_state(ahc);
1453 panic("critical section loop");
1454 }
1455
1456 steps++;
1457 if (stepping == FALSE) {
1458
1459 /*
1460 * Disable all interrupt sources so that the
1461 * sequencer will not be stuck by a pausing
1462 * interrupt condition while we attempt to
1463 * leave a critical section.
1464 */
1465 simode0 = ahc_inb(ahc, SIMODE0);
1466 ahc_outb(ahc, SIMODE0, 0);
1467 simode1 = ahc_inb(ahc, SIMODE1);
1468 if ((ahc->features & AHC_DT) != 0)
1469 /*
1470 * On DT class controllers, we
1471 * use the enhanced busfree logic.
1472 * Unfortunately we cannot re-enable
1473 * busfree detection within the
1474 * current connection, so we must
1475 * leave it on while single stepping.
1476 */
1477 ahc_outb(ahc, SIMODE1, simode1 & ENBUSFREE);
1478 else
1479 ahc_outb(ahc, SIMODE1, 0);
1480 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1481 ahc_outb(ahc, SEQCTL, ahc->seqctl | STEP);
1482 stepping = TRUE;
1483 }
1484 if ((ahc->features & AHC_DT) != 0) {
1485 ahc_outb(ahc, CLRSINT1, CLRBUSFREE);
1486 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1487 }
1488 ahc_outb(ahc, HCNTRL, ahc->unpause);
1489 while (!ahc_is_paused(ahc))
1490 ahc_delay(200);
1491 }
1492 if (stepping) {
1493 ahc_outb(ahc, SIMODE0, simode0);
1494 ahc_outb(ahc, SIMODE1, simode1);
1495 ahc_outb(ahc, SEQCTL, ahc->seqctl);
1496 }
1497 }
1498
1499 /*
1500 * Clear any pending interrupt status.
1501 */
1502 void
1503 ahc_clear_intstat(struct ahc_softc *ahc)
1504 {
1505 /* Clear any interrupt conditions this may have caused */
1506 ahc_outb(ahc, CLRSINT1, CLRSELTIMEO|CLRATNO|CLRSCSIRSTI
1507 |CLRBUSFREE|CLRSCSIPERR|CLRPHASECHG|
1508 CLRREQINIT);
1509 ahc_flush_device_writes(ahc);
1510 ahc_outb(ahc, CLRSINT0, CLRSELDO|CLRSELDI|CLRSELINGO);
1511 ahc_flush_device_writes(ahc);
1512 ahc_outb(ahc, CLRINT, CLRSCSIINT);
1513 ahc_flush_device_writes(ahc);
1514 }
1515
1516 /**************************** Debugging Routines ******************************/
1517 #ifdef AHC_DEBUG
1518 uint32_t ahc_debug = AHC_DEBUG_OPTS;
1519 #endif
1520
1521 void
1522 ahc_print_scb(struct scb *scb)
1523 {
1524 int i;
1525
1526 struct hardware_scb *hscb = scb->hscb;
1527
1528 printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n",
1529 (void *)scb,
1530 hscb->control,
1531 hscb->scsiid,
1532 hscb->lun,
1533 hscb->cdb_len);
1534 printf("Shared Data: ");
1535 for (i = 0; i < sizeof(hscb->shared_data.cdb); i++)
1536 printf("%#02x", hscb->shared_data.cdb[i]);
1537 printf(" dataptr:%#x datacnt:%#x sgptr:%#x tag:%#x\n",
1538 ahc_le32toh(hscb->dataptr),
1539 ahc_le32toh(hscb->datacnt),
1540 ahc_le32toh(hscb->sgptr),
1541 hscb->tag);
1542 if (scb->sg_count > 0) {
1543 for (i = 0; i < scb->sg_count; i++) {
1544 printf("sg[%d] - Addr 0x%x%x : Length %d\n",
1545 i,
1546 (ahc_le32toh(scb->sg_list[i].len) >> 24
1547 & SG_HIGH_ADDR_BITS),
1548 ahc_le32toh(scb->sg_list[i].addr),
1549 ahc_le32toh(scb->sg_list[i].len));
1550 }
1551 }
1552 }
1553
1554 /************************* Transfer Negotiation *******************************/
1555 /*
1556 * Allocate per target mode instance (ID we respond to as a target)
1557 * transfer negotiation data structures.
1558 */
1559 static struct ahc_tmode_tstate *
1560 ahc_alloc_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel)
1561 {
1562 struct ahc_tmode_tstate *master_tstate;
1563 struct ahc_tmode_tstate *tstate;
1564 int i;
1565
1566 master_tstate = ahc->enabled_targets[ahc->our_id];
1567 if (channel == 'B') {
1568 scsi_id += 8;
1569 master_tstate = ahc->enabled_targets[ahc->our_id_b + 8];
1570 }
1571 if (ahc->enabled_targets[scsi_id] != NULL
1572 && ahc->enabled_targets[scsi_id] != master_tstate)
1573 panic("%s: ahc_alloc_tstate - Target already allocated",
1574 ahc_name(ahc));
1575 tstate = (struct ahc_tmode_tstate*)malloc(sizeof(*tstate),
1576 M_DEVBUF, M_NOWAIT);
1577 if (tstate == NULL)
1578 return (NULL);
1579
1580 /*
1581 * If we have allocated a master tstate, copy user settings from
1582 * the master tstate (taken from SRAM or the EEPROM) for this
1583 * channel, but reset our current and goal settings to async/narrow
1584 * until an initiator talks to us.
1585 */
1586 if (master_tstate != NULL) {
1587 memcpy(tstate, master_tstate, sizeof(*tstate));
1588 memset(tstate->enabled_luns, 0, sizeof(tstate->enabled_luns));
1589 tstate->ultraenb = 0;
1590 for (i = 0; i < AHC_NUM_TARGETS; i++) {
1591 memset(&tstate->transinfo[i].curr, 0,
1592 sizeof(tstate->transinfo[i].curr));
1593 memset(&tstate->transinfo[i].goal, 0,
1594 sizeof(tstate->transinfo[i].goal));
1595 }
1596 } else
1597 memset(tstate, 0, sizeof(*tstate));
1598 ahc->enabled_targets[scsi_id] = tstate;
1599 return (tstate);
1600 }
1601
1602 #ifdef AHC_TARGET_MODE
1603 /*
1604 * Free per target mode instance (ID we respond to as a target)
1605 * transfer negotiation data structures.
1606 */
1607 static void
1608 ahc_free_tstate(struct ahc_softc *ahc, u_int scsi_id, char channel, int force)
1609 {
1610 struct ahc_tmode_tstate *tstate;
1611
1612 /*
1613 * Don't clean up our "master" tstate.
1614 * It has our default user settings.
1615 */
1616 if (((channel == 'B' && scsi_id == ahc->our_id_b)
1617 || (channel == 'A' && scsi_id == ahc->our_id))
1618 && force == FALSE)
1619 return;
1620
1621 if (channel == 'B')
1622 scsi_id += 8;
1623 tstate = ahc->enabled_targets[scsi_id];
1624 if (tstate != NULL)
1625 free(tstate, M_DEVBUF);
1626 ahc->enabled_targets[scsi_id] = NULL;
1627 }
1628 #endif
1629
1630 /*
1631 * Called when we have an active connection to a target on the bus,
1632 * this function finds the nearest syncrate to the input period limited
1633 * by the capabilities of the bus connectivity of and sync settings for
1634 * the target.
1635 */
1636 struct ahc_syncrate *
1637 ahc_devlimited_syncrate(struct ahc_softc *ahc,
1638 struct ahc_initiator_tinfo *tinfo,
1639 u_int *period, u_int *ppr_options, role_t role)
1640 {
1641 struct ahc_transinfo *transinfo;
1642 u_int maxsync;
1643
1644 if ((ahc->features & AHC_ULTRA2) != 0) {
1645 if ((ahc_inb(ahc, SBLKCTL) & ENAB40) != 0
1646 && (ahc_inb(ahc, SSTAT2) & EXP_ACTIVE) == 0) {
1647 maxsync = AHC_SYNCRATE_DT;
1648 } else {
1649 maxsync = AHC_SYNCRATE_ULTRA;
1650 /* Can't do DT on an SE bus */
1651 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1652 }
1653 } else if ((ahc->features & AHC_ULTRA) != 0) {
1654 maxsync = AHC_SYNCRATE_ULTRA;
1655 } else {
1656 maxsync = AHC_SYNCRATE_FAST;
1657 }
1658 /*
1659 * Never allow a value higher than our current goal
1660 * period otherwise we may allow a target initiated
1661 * negotiation to go above the limit as set by the
1662 * user. In the case of an initiator initiated
1663 * sync negotiation, we limit based on the user
1664 * setting. This allows the system to still accept
1665 * incoming negotiations even if target initiated
1666 * negotiation is not performed.
1667 */
1668 if (role == ROLE_TARGET)
1669 transinfo = &tinfo->user;
1670 else
1671 transinfo = &tinfo->goal;
1672 *ppr_options &= transinfo->ppr_options;
1673 if (transinfo->width == MSG_EXT_WDTR_BUS_8_BIT) {
1674 maxsync = MAX(maxsync, AHC_SYNCRATE_ULTRA2);
1675 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1676 }
1677 if (transinfo->period == 0) {
1678 *period = 0;
1679 *ppr_options = 0;
1680 return (NULL);
1681 }
1682 *period = MAX(*period, transinfo->period);
1683 return (ahc_find_syncrate(ahc, period, ppr_options, maxsync));
1684 }
1685
1686 /*
1687 * Look up the valid period to SCSIRATE conversion in our table.
1688 * Return the period and offset that should be sent to the target
1689 * if this was the beginning of an SDTR.
1690 */
1691 struct ahc_syncrate *
1692 ahc_find_syncrate(struct ahc_softc *ahc, u_int *period,
1693 u_int *ppr_options, u_int maxsync)
1694 {
1695 struct ahc_syncrate *syncrate;
1696
1697 if ((ahc->features & AHC_DT) == 0)
1698 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1699
1700 /* Skip all DT only entries if DT is not available */
1701 if ((*ppr_options & MSG_EXT_PPR_DT_REQ) == 0
1702 && maxsync < AHC_SYNCRATE_ULTRA2)
1703 maxsync = AHC_SYNCRATE_ULTRA2;
1704
1705 for (syncrate = &ahc_syncrates[maxsync];
1706 syncrate->rate != NULL;
1707 syncrate++) {
1708
1709 /*
1710 * The Ultra2 table doesn't go as low
1711 * as for the Fast/Ultra cards.
1712 */
1713 if ((ahc->features & AHC_ULTRA2) != 0
1714 && (syncrate->sxfr_u2 == 0))
1715 break;
1716
1717 if (*period <= syncrate->period) {
1718 /*
1719 * When responding to a target that requests
1720 * sync, the requested rate may fall between
1721 * two rates that we can output, but still be
1722 * a rate that we can receive. Because of this,
1723 * we want to respond to the target with
1724 * the same rate that it sent to us even
1725 * if the period we use to send data to it
1726 * is lower. Only lower the response period
1727 * if we must.
1728 */
1729 if (syncrate == &ahc_syncrates[maxsync])
1730 *period = syncrate->period;
1731
1732 /*
1733 * At some speeds, we only support
1734 * ST transfers.
1735 */
1736 if ((syncrate->sxfr_u2 & ST_SXFR) != 0)
1737 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1738 break;
1739 }
1740 }
1741
1742 if ((*period == 0)
1743 || (syncrate->rate == NULL)
1744 || ((ahc->features & AHC_ULTRA2) != 0
1745 && (syncrate->sxfr_u2 == 0))) {
1746 /* Use asynchronous transfers. */
1747 *period = 0;
1748 syncrate = NULL;
1749 *ppr_options &= ~MSG_EXT_PPR_DT_REQ;
1750 }
1751 return (syncrate);
1752 }
1753
1754 /*
1755 * Convert from an entry in our syncrate table to the SCSI equivalent
1756 * sync "period" factor.
1757 */
1758 u_int
1759 ahc_find_period(struct ahc_softc *ahc, u_int scsirate, u_int maxsync)
1760 {
1761 struct ahc_syncrate *syncrate;
1762
1763 if ((ahc->features & AHC_ULTRA2) != 0)
1764 scsirate &= SXFR_ULTRA2;
1765 else
1766 scsirate &= SXFR;
1767
1768 syncrate = &ahc_syncrates[maxsync];
1769 while (syncrate->rate != NULL) {
1770
1771 if ((ahc->features & AHC_ULTRA2) != 0) {
1772 if (syncrate->sxfr_u2 == 0)
1773 break;
1774 else if (scsirate == (syncrate->sxfr_u2 & SXFR_ULTRA2))
1775 return (syncrate->period);
1776 } else if (scsirate == (syncrate->sxfr & SXFR)) {
1777 return (syncrate->period);
1778 }
1779 syncrate++;
1780 }
1781 return (0); /* async */
1782 }
1783
1784 /*
1785 * Truncate the given synchronous offset to a value the
1786 * current adapter type and syncrate are capable of.
1787 */
1788 void
1789 ahc_validate_offset(struct ahc_softc *ahc,
1790 struct ahc_initiator_tinfo *tinfo,
1791 struct ahc_syncrate *syncrate,
1792 u_int *offset, int wide, role_t role)
1793 {
1794 u_int maxoffset;
1795
1796 /* Limit offset to what we can do */
1797 if (syncrate == NULL) {
1798 maxoffset = 0;
1799 } else if ((ahc->features & AHC_ULTRA2) != 0) {
1800 maxoffset = MAX_OFFSET_ULTRA2;
1801 } else {
1802 if (wide)
1803 maxoffset = MAX_OFFSET_16BIT;
1804 else
1805 maxoffset = MAX_OFFSET_8BIT;
1806 }
1807 *offset = MIN(*offset, maxoffset);
1808 if (tinfo != NULL) {
1809 if (role == ROLE_TARGET)
1810 *offset = MIN(*offset, tinfo->user.offset);
1811 else
1812 *offset = MIN(*offset, tinfo->goal.offset);
1813 }
1814 }
1815
1816 /*
1817 * Truncate the given transfer width parameter to a value the
1818 * current adapter type is capable of.
1819 */
1820 void
1821 ahc_validate_width(struct ahc_softc *ahc, struct ahc_initiator_tinfo *tinfo,
1822 u_int *bus_width, role_t role)
1823 {
1824 switch (*bus_width) {
1825 default:
1826 if (ahc->features & AHC_WIDE) {
1827 /* Respond Wide */
1828 *bus_width = MSG_EXT_WDTR_BUS_16_BIT;
1829 break;
1830 }
1831 /* FALLTHROUGH */
1832 case MSG_EXT_WDTR_BUS_8_BIT:
1833 *bus_width = MSG_EXT_WDTR_BUS_8_BIT;
1834 break;
1835 }
1836 if (tinfo != NULL) {
1837 if (role == ROLE_TARGET)
1838 *bus_width = MIN(tinfo->user.width, *bus_width);
1839 else
1840 *bus_width = MIN(tinfo->goal.width, *bus_width);
1841 }
1842 }
1843
1844 /*
1845 * Update the bitmask of targets for which the controller should
1846 * negotiate with at the next convenient oportunity. This currently
1847 * means the next time we send the initial identify messages for
1848 * a new transaction.
1849 */
1850 int
1851 ahc_update_neg_request(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
1852 struct ahc_tmode_tstate *tstate,
1853 struct ahc_initiator_tinfo *tinfo, ahc_neg_type neg_type)
1854 {
1855 u_int auto_negotiate_orig;
1856
1857 auto_negotiate_orig = tstate->auto_negotiate;
1858 if (neg_type == AHC_NEG_ALWAYS) {
1859 /*
1860 * Force our "current" settings to be
1861 * unknown so that unless a bus reset
1862 * occurs the need to renegotiate is
1863 * recorded persistently.
1864 */
1865 if ((ahc->features & AHC_WIDE) != 0)
1866 tinfo->curr.width = AHC_WIDTH_UNKNOWN;
1867 tinfo->curr.period = AHC_PERIOD_UNKNOWN;
1868 tinfo->curr.offset = AHC_OFFSET_UNKNOWN;
1869 }
1870 if (tinfo->curr.period != tinfo->goal.period
1871 || tinfo->curr.width != tinfo->goal.width
1872 || tinfo->curr.offset != tinfo->goal.offset
1873 || tinfo->curr.ppr_options != tinfo->goal.ppr_options
1874 || (neg_type == AHC_NEG_IF_NON_ASYNC
1875 && (tinfo->goal.offset != 0
1876 || tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT
1877 || tinfo->goal.ppr_options != 0)))
1878 tstate->auto_negotiate |= devinfo->target_mask;
1879 else
1880 tstate->auto_negotiate &= ~devinfo->target_mask;
1881
1882 return (auto_negotiate_orig != tstate->auto_negotiate);
1883 }
1884
1885 /*
1886 * Update the user/goal/curr tables of synchronous negotiation
1887 * parameters as well as, in the case of a current or active update,
1888 * any data structures on the host controller. In the case of an
1889 * active update, the specified target is currently talking to us on
1890 * the bus, so the transfer parameter update must take effect
1891 * immediately.
1892 */
1893 void
1894 ahc_set_syncrate(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
1895 struct ahc_syncrate *syncrate, u_int period,
1896 u_int offset, u_int ppr_options, u_int type, int paused)
1897 {
1898 struct ahc_initiator_tinfo *tinfo;
1899 struct ahc_tmode_tstate *tstate;
1900 u_int old_period;
1901 u_int old_offset;
1902 u_int old_ppr;
1903 int active;
1904 int update_needed;
1905
1906 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
1907 update_needed = 0;
1908
1909 if (syncrate == NULL) {
1910 period = 0;
1911 offset = 0;
1912 }
1913
1914 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
1915 devinfo->target, &tstate);
1916
1917 if ((type & AHC_TRANS_USER) != 0) {
1918 tinfo->user.period = period;
1919 tinfo->user.offset = offset;
1920 tinfo->user.ppr_options = ppr_options;
1921 }
1922
1923 if ((type & AHC_TRANS_GOAL) != 0) {
1924 tinfo->goal.period = period;
1925 tinfo->goal.offset = offset;
1926 tinfo->goal.ppr_options = ppr_options;
1927 }
1928
1929 old_period = tinfo->curr.period;
1930 old_offset = tinfo->curr.offset;
1931 old_ppr = tinfo->curr.ppr_options;
1932
1933 if ((type & AHC_TRANS_CUR) != 0
1934 && (old_period != period
1935 || old_offset != offset
1936 || old_ppr != ppr_options)) {
1937 u_int scsirate;
1938
1939 update_needed++;
1940 scsirate = tinfo->scsirate;
1941 if ((ahc->features & AHC_ULTRA2) != 0) {
1942
1943 scsirate &= ~(SXFR_ULTRA2|SINGLE_EDGE|ENABLE_CRC);
1944 if (syncrate != NULL) {
1945 scsirate |= syncrate->sxfr_u2;
1946 if ((ppr_options & MSG_EXT_PPR_DT_REQ) != 0)
1947 scsirate |= ENABLE_CRC;
1948 else
1949 scsirate |= SINGLE_EDGE;
1950 }
1951 } else {
1952
1953 scsirate &= ~(SXFR|SOFS);
1954 /*
1955 * Ensure Ultra mode is set properly for
1956 * this target.
1957 */
1958 tstate->ultraenb &= ~devinfo->target_mask;
1959 if (syncrate != NULL) {
1960 if (syncrate->sxfr & ULTRA_SXFR) {
1961 tstate->ultraenb |=
1962 devinfo->target_mask;
1963 }
1964 scsirate |= syncrate->sxfr & SXFR;
1965 scsirate |= offset & SOFS;
1966 }
1967 if (active) {
1968 u_int sxfrctl0;
1969
1970 sxfrctl0 = ahc_inb(ahc, SXFRCTL0);
1971 sxfrctl0 &= ~FAST20;
1972 if (tstate->ultraenb & devinfo->target_mask)
1973 sxfrctl0 |= FAST20;
1974 ahc_outb(ahc, SXFRCTL0, sxfrctl0);
1975 }
1976 }
1977 if (active) {
1978 ahc_outb(ahc, SCSIRATE, scsirate);
1979 if ((ahc->features & AHC_ULTRA2) != 0)
1980 ahc_outb(ahc, SCSIOFFSET, offset);
1981 }
1982
1983 tinfo->scsirate = scsirate;
1984 tinfo->curr.period = period;
1985 tinfo->curr.offset = offset;
1986 tinfo->curr.ppr_options = ppr_options;
1987
1988 ahc_send_async(ahc, devinfo->channel, devinfo->target,
1989 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
1990 if (bootverbose) {
1991 if (offset != 0) {
1992 printf("%s: target %d synchronous at %sMHz%s, "
1993 "offset = 0x%x\n", ahc_name(ahc),
1994 devinfo->target, syncrate->rate,
1995 (ppr_options & MSG_EXT_PPR_DT_REQ)
1996 ? " DT" : "", offset);
1997 } else {
1998 printf("%s: target %d using "
1999 "asynchronous transfers\n",
2000 ahc_name(ahc), devinfo->target);
2001 }
2002 }
2003 }
2004
2005 update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
2006 tinfo, AHC_NEG_TO_GOAL);
2007
2008 if (update_needed)
2009 ahc_update_pending_scbs(ahc);
2010 }
2011
2012 /*
2013 * Update the user/goal/curr tables of wide negotiation
2014 * parameters as well as, in the case of a current or active update,
2015 * any data structures on the host controller. In the case of an
2016 * active update, the specified target is currently talking to us on
2017 * the bus, so the transfer parameter update must take effect
2018 * immediately.
2019 */
2020 void
2021 ahc_set_width(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2022 u_int width, u_int type, int paused)
2023 {
2024 struct ahc_initiator_tinfo *tinfo;
2025 struct ahc_tmode_tstate *tstate;
2026 u_int oldwidth;
2027 int active;
2028 int update_needed;
2029
2030 active = (type & AHC_TRANS_ACTIVE) == AHC_TRANS_ACTIVE;
2031 update_needed = 0;
2032 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2033 devinfo->target, &tstate);
2034
2035 if ((type & AHC_TRANS_USER) != 0)
2036 tinfo->user.width = width;
2037
2038 if ((type & AHC_TRANS_GOAL) != 0)
2039 tinfo->goal.width = width;
2040
2041 oldwidth = tinfo->curr.width;
2042 if ((type & AHC_TRANS_CUR) != 0 && oldwidth != width) {
2043 u_int scsirate;
2044
2045 update_needed++;
2046 scsirate = tinfo->scsirate;
2047 scsirate &= ~WIDEXFER;
2048 if (width == MSG_EXT_WDTR_BUS_16_BIT)
2049 scsirate |= WIDEXFER;
2050
2051 tinfo->scsirate = scsirate;
2052
2053 if (active)
2054 ahc_outb(ahc, SCSIRATE, scsirate);
2055
2056 tinfo->curr.width = width;
2057
2058 ahc_send_async(ahc, devinfo->channel, devinfo->target,
2059 CAM_LUN_WILDCARD, AC_TRANSFER_NEG, NULL);
2060 if (bootverbose) {
2061 printf("%s: target %d using %dbit transfers\n",
2062 ahc_name(ahc), devinfo->target,
2063 8 * (0x01 << width));
2064 }
2065 }
2066
2067 update_needed += ahc_update_neg_request(ahc, devinfo, tstate,
2068 tinfo, AHC_NEG_TO_GOAL);
2069 if (update_needed)
2070 ahc_update_pending_scbs(ahc);
2071 }
2072
2073 /*
2074 * Update the current state of tagged queuing for a given target.
2075 */
2076 void
2077 ahc_set_tags(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2078 ahc_queue_alg alg)
2079 {
2080 ahc_platform_set_tags(ahc, devinfo, alg);
2081 ahc_send_async(ahc, devinfo->channel, devinfo->target,
2082 devinfo->lun, AC_TRANSFER_NEG, &alg);
2083 }
2084
2085 /*
2086 * When the transfer settings for a connection change, update any
2087 * in-transit SCBs to contain the new data so the hardware will
2088 * be set correctly during future (re)selections.
2089 */
2090 static void
2091 ahc_update_pending_scbs(struct ahc_softc *ahc)
2092 {
2093 struct scb *pending_scb;
2094 int pending_scb_count;
2095 int i;
2096 int paused;
2097 u_int saved_scbptr;
2098
2099 /*
2100 * Traverse the pending SCB list and ensure that all of the
2101 * SCBs there have the proper settings.
2102 */
2103 pending_scb_count = 0;
2104 LIST_FOREACH(pending_scb, &ahc->pending_scbs, pending_links) {
2105 struct ahc_devinfo devinfo;
2106 struct hardware_scb *pending_hscb;
2107 struct ahc_initiator_tinfo *tinfo;
2108 struct ahc_tmode_tstate *tstate;
2109
2110 ahc_scb_devinfo(ahc, &devinfo, pending_scb);
2111 tinfo = ahc_fetch_transinfo(ahc, devinfo.channel,
2112 devinfo.our_scsiid,
2113 devinfo.target, &tstate);
2114 pending_hscb = pending_scb->hscb;
2115 pending_hscb->control &= ~ULTRAENB;
2116 if ((tstate->ultraenb & devinfo.target_mask) != 0)
2117 pending_hscb->control |= ULTRAENB;
2118 pending_hscb->scsirate = tinfo->scsirate;
2119 pending_hscb->scsioffset = tinfo->curr.offset;
2120 if ((tstate->auto_negotiate & devinfo.target_mask) == 0
2121 && (pending_scb->flags & SCB_AUTO_NEGOTIATE) != 0) {
2122 pending_scb->flags &= ~SCB_AUTO_NEGOTIATE;
2123 pending_hscb->control &= ~MK_MESSAGE;
2124 }
2125 ahc_sync_scb(ahc, pending_scb,
2126 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
2127 pending_scb_count++;
2128 }
2129
2130 if (pending_scb_count == 0)
2131 return;
2132
2133 if (ahc_is_paused(ahc)) {
2134 paused = 1;
2135 } else {
2136 paused = 0;
2137 ahc_pause(ahc);
2138 }
2139
2140 saved_scbptr = ahc_inb(ahc, SCBPTR);
2141 /* Ensure that the hscbs down on the card match the new information */
2142 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
2143 struct hardware_scb *pending_hscb;
2144 u_int control;
2145 u_int scb_tag;
2146
2147 ahc_outb(ahc, SCBPTR, i);
2148 scb_tag = ahc_inb(ahc, SCB_TAG);
2149 pending_scb = ahc_lookup_scb(ahc, scb_tag);
2150 if (pending_scb == NULL)
2151 continue;
2152
2153 pending_hscb = pending_scb->hscb;
2154 control = ahc_inb(ahc, SCB_CONTROL);
2155 control &= ~(ULTRAENB|MK_MESSAGE);
2156 control |= pending_hscb->control & (ULTRAENB|MK_MESSAGE);
2157 ahc_outb(ahc, SCB_CONTROL, control);
2158 ahc_outb(ahc, SCB_SCSIRATE, pending_hscb->scsirate);
2159 ahc_outb(ahc, SCB_SCSIOFFSET, pending_hscb->scsioffset);
2160 }
2161 ahc_outb(ahc, SCBPTR, saved_scbptr);
2162
2163 if (paused == 0)
2164 ahc_unpause(ahc);
2165 }
2166
2167 /**************************** Pathing Information *****************************/
2168 static void
2169 ahc_fetch_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2170 {
2171 u_int saved_scsiid;
2172 role_t role;
2173 int our_id;
2174
2175 if (ahc_inb(ahc, SSTAT0) & TARGET)
2176 role = ROLE_TARGET;
2177 else
2178 role = ROLE_INITIATOR;
2179
2180 if (role == ROLE_TARGET
2181 && (ahc->features & AHC_MULTI_TID) != 0
2182 && (ahc_inb(ahc, SEQ_FLAGS)
2183 & (CMDPHASE_PENDING|TARG_CMD_PENDING|NO_DISCONNECT)) != 0) {
2184 /* We were selected, so pull our id from TARGIDIN */
2185 our_id = ahc_inb(ahc, TARGIDIN) & OID;
2186 } else if ((ahc->features & AHC_ULTRA2) != 0)
2187 our_id = ahc_inb(ahc, SCSIID_ULTRA2) & OID;
2188 else
2189 our_id = ahc_inb(ahc, SCSIID) & OID;
2190
2191 saved_scsiid = ahc_inb(ahc, SAVED_SCSIID);
2192 ahc_compile_devinfo(devinfo,
2193 our_id,
2194 SCSIID_TARGET(ahc, saved_scsiid),
2195 ahc_inb(ahc, SAVED_LUN),
2196 SCSIID_CHANNEL(ahc, saved_scsiid),
2197 role);
2198 }
2199
2200 struct ahc_phase_table_entry*
2201 ahc_lookup_phase_entry(int phase)
2202 {
2203 struct ahc_phase_table_entry *entry;
2204 struct ahc_phase_table_entry *last_entry;
2205
2206 /*
2207 * num_phases doesn't include the default entry which
2208 * will be returned if the phase doesn't match.
2209 */
2210 last_entry = &ahc_phase_table[num_phases];
2211 for (entry = ahc_phase_table; entry < last_entry; entry++) {
2212 if (phase == entry->phase)
2213 break;
2214 }
2215 return (entry);
2216 }
2217
2218 void
2219 ahc_compile_devinfo(struct ahc_devinfo *devinfo, u_int our_id, u_int target,
2220 u_int lun, char channel, role_t role)
2221 {
2222 devinfo->our_scsiid = our_id;
2223 devinfo->target = target;
2224 devinfo->lun = lun;
2225 devinfo->target_offset = target;
2226 devinfo->channel = channel;
2227 devinfo->role = role;
2228 if (channel == 'B')
2229 devinfo->target_offset += 8;
2230 devinfo->target_mask = (0x01 << devinfo->target_offset);
2231 }
2232
2233 void
2234 ahc_print_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2235 {
2236 printf("%s:%c:%d:%d: ", ahc_name(ahc), devinfo->channel,
2237 devinfo->target, devinfo->lun);
2238 }
2239
2240 static void
2241 ahc_scb_devinfo(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2242 struct scb *scb)
2243 {
2244 role_t role;
2245 int our_id;
2246
2247 our_id = SCSIID_OUR_ID(scb->hscb->scsiid);
2248 role = ROLE_INITIATOR;
2249 if ((scb->flags & SCB_TARGET_SCB) != 0)
2250 role = ROLE_TARGET;
2251 ahc_compile_devinfo(devinfo, our_id, SCB_GET_TARGET(ahc, scb),
2252 SCB_GET_LUN(scb), SCB_GET_CHANNEL(ahc, scb), role);
2253 }
2254
2255
2256 /************************ Message Phase Processing ****************************/
2257 static void
2258 ahc_assert_atn(struct ahc_softc *ahc)
2259 {
2260 u_int scsisigo;
2261
2262 scsisigo = ATNO;
2263 if ((ahc->features & AHC_DT) == 0)
2264 scsisigo |= ahc_inb(ahc, SCSISIGI);
2265 ahc_outb(ahc, SCSISIGO, scsisigo);
2266 }
2267
2268 /*
2269 * When an initiator transaction with the MK_MESSAGE flag either reconnects
2270 * or enters the initial message out phase, we are interrupted. Fill our
2271 * outgoing message buffer with the appropriate message and beging handing
2272 * the message phase(s) manually.
2273 */
2274 static void
2275 ahc_setup_initiator_msgout(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2276 struct scb *scb)
2277 {
2278 /*
2279 * To facilitate adding multiple messages together,
2280 * each routine should increment the index and len
2281 * variables instead of setting them explicitly.
2282 */
2283 ahc->msgout_index = 0;
2284 ahc->msgout_len = 0;
2285
2286 if ((scb->flags & SCB_DEVICE_RESET) == 0
2287 && ahc_inb(ahc, MSG_OUT) == MSG_IDENTIFYFLAG) {
2288 u_int identify_msg;
2289
2290 identify_msg = MSG_IDENTIFYFLAG | SCB_GET_LUN(scb);
2291 if ((scb->hscb->control & DISCENB) != 0)
2292 identify_msg |= MSG_IDENTIFY_DISCFLAG;
2293 ahc->msgout_buf[ahc->msgout_index++] = identify_msg;
2294 ahc->msgout_len++;
2295
2296 if ((scb->hscb->control & TAG_ENB) != 0) {
2297 ahc->msgout_buf[ahc->msgout_index++] =
2298 scb->hscb->control & (TAG_ENB|SCB_TAG_TYPE);
2299 ahc->msgout_buf[ahc->msgout_index++] = scb->hscb->tag;
2300 ahc->msgout_len += 2;
2301 }
2302 }
2303
2304 if (scb->flags & SCB_DEVICE_RESET) {
2305 ahc->msgout_buf[ahc->msgout_index++] = MSG_BUS_DEV_RESET;
2306 ahc->msgout_len++;
2307 ahc_print_path(ahc, scb);
2308 printf("Bus Device Reset Message Sent\n");
2309 /*
2310 * Clear our selection hardware in advance of
2311 * the busfree. We may have an entry in the waiting
2312 * Q for this target, and we don't want to go about
2313 * selecting while we handle the busfree and blow it
2314 * away.
2315 */
2316 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
2317 } else if ((scb->flags & SCB_ABORT) != 0) {
2318 if ((scb->hscb->control & TAG_ENB) != 0)
2319 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT_TAG;
2320 else
2321 ahc->msgout_buf[ahc->msgout_index++] = MSG_ABORT;
2322 ahc->msgout_len++;
2323 ahc_print_path(ahc, scb);
2324 printf("Abort%s Message Sent\n",
2325 (scb->hscb->control & TAG_ENB) != 0 ? " Tag" : "");
2326 /*
2327 * Clear our selection hardware in advance of
2328 * the busfree. We may have an entry in the waiting
2329 * Q for this target, and we don't want to go about
2330 * selecting while we handle the busfree and blow it
2331 * away.
2332 */
2333 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
2334 } else if ((scb->flags & (SCB_AUTO_NEGOTIATE|SCB_NEGOTIATE)) != 0) {
2335 ahc_build_transfer_msg(ahc, devinfo);
2336 } else {
2337 printf("ahc_intr: AWAITING_MSG for an SCB that "
2338 "does not have a waiting message\n");
2339 printf("SCSIID = %x, target_mask = %x\n", scb->hscb->scsiid,
2340 devinfo->target_mask);
2341 panic("SCB = %d, SCB Control = %x, MSG_OUT = %x "
2342 "SCB flags = %x", scb->hscb->tag, scb->hscb->control,
2343 ahc_inb(ahc, MSG_OUT), scb->flags);
2344 }
2345
2346 /*
2347 * Clear the MK_MESSAGE flag from the SCB so we aren't
2348 * asked to send this message again.
2349 */
2350 ahc_outb(ahc, SCB_CONTROL, ahc_inb(ahc, SCB_CONTROL) & ~MK_MESSAGE);
2351 scb->hscb->control &= ~MK_MESSAGE;
2352 ahc->msgout_index = 0;
2353 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2354 }
2355
2356 /*
2357 * Build an appropriate transfer negotiation message for the
2358 * currently active target.
2359 */
2360 static void
2361 ahc_build_transfer_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2362 {
2363 /*
2364 * We need to initiate transfer negotiations.
2365 * If our current and goal settings are identical,
2366 * we want to renegotiate due to a check condition.
2367 */
2368 struct ahc_initiator_tinfo *tinfo;
2369 struct ahc_tmode_tstate *tstate;
2370 struct ahc_syncrate *rate;
2371 int dowide;
2372 int dosync;
2373 int doppr;
2374 u_int period;
2375 u_int ppr_options;
2376 u_int offset;
2377
2378 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
2379 devinfo->target, &tstate);
2380 /*
2381 * Filter our period based on the current connection.
2382 * If we can't perform DT transfers on this segment (not in LVD
2383 * mode for instance), then our decision to issue a PPR message
2384 * may change.
2385 */
2386 period = tinfo->goal.period;
2387 offset = tinfo->goal.offset;
2388 ppr_options = tinfo->goal.ppr_options;
2389 /* Target initiated PPR is not allowed in the SCSI spec */
2390 if (devinfo->role == ROLE_TARGET)
2391 ppr_options = 0;
2392 rate = ahc_devlimited_syncrate(ahc, tinfo, &period,
2393 &ppr_options, devinfo->role);
2394 dowide = tinfo->curr.width != tinfo->goal.width;
2395 dosync = tinfo->curr.offset != offset || tinfo->curr.period != period;
2396 /*
2397 * Only use PPR if we have options that need it, even if the device
2398 * claims to support it. There might be an expander in the way
2399 * that doesn't.
2400 */
2401 doppr = ppr_options != 0;
2402
2403 if (!dowide && !dosync && !doppr) {
2404 dowide = tinfo->goal.width != MSG_EXT_WDTR_BUS_8_BIT;
2405 dosync = tinfo->goal.offset != 0;
2406 }
2407
2408 if (!dowide && !dosync && !doppr) {
2409 /*
2410 * Force async with a WDTR message if we have a wide bus,
2411 * or just issue an SDTR with a 0 offset.
2412 */
2413 if ((ahc->features & AHC_WIDE) != 0)
2414 dowide = 1;
2415 else
2416 dosync = 1;
2417
2418 if (bootverbose) {
2419 ahc_print_devinfo(ahc, devinfo);
2420 printf("Ensuring async\n");
2421 }
2422 }
2423
2424 /* Target initiated PPR is not allowed in the SCSI spec */
2425 if (devinfo->role == ROLE_TARGET)
2426 doppr = 0;
2427
2428 /*
2429 * Both the PPR message and SDTR message require the
2430 * goal syncrate to be limited to what the target device
2431 * is capable of handling (based on whether an LVD->SE
2432 * expander is on the bus), so combine these two cases.
2433 * Regardless, guarantee that if we are using WDTR and SDTR
2434 * messages that WDTR comes first.
2435 */
2436 if (doppr || (dosync && !dowide)) {
2437
2438 offset = tinfo->goal.offset;
2439 ahc_validate_offset(ahc, tinfo, rate, &offset,
2440 doppr ? tinfo->goal.width
2441 : tinfo->curr.width,
2442 devinfo->role);
2443 if (doppr) {
2444 ahc_construct_ppr(ahc, devinfo, period, offset,
2445 tinfo->goal.width, ppr_options);
2446 } else {
2447 ahc_construct_sdtr(ahc, devinfo, period, offset);
2448 }
2449 } else {
2450 ahc_construct_wdtr(ahc, devinfo, tinfo->goal.width);
2451 }
2452 }
2453
2454 /*
2455 * Build a synchronous negotiation message in our message
2456 * buffer based on the input parameters.
2457 */
2458 static void
2459 ahc_construct_sdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2460 u_int period, u_int offset)
2461 {
2462 if (offset == 0)
2463 period = AHC_ASYNC_XFER_PERIOD;
2464 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
2465 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR_LEN;
2466 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_SDTR;
2467 ahc->msgout_buf[ahc->msgout_index++] = period;
2468 ahc->msgout_buf[ahc->msgout_index++] = offset;
2469 ahc->msgout_len += 5;
2470 if (bootverbose) {
2471 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n",
2472 ahc_name(ahc), devinfo->channel, devinfo->target,
2473 devinfo->lun, period, offset);
2474 }
2475 }
2476
2477 /*
2478 * Build a wide negotiation message in our message
2479 * buffer based on the input parameters.
2480 */
2481 static void
2482 ahc_construct_wdtr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2483 u_int bus_width)
2484 {
2485 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
2486 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR_LEN;
2487 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_WDTR;
2488 ahc->msgout_buf[ahc->msgout_index++] = bus_width;
2489 ahc->msgout_len += 4;
2490 if (bootverbose) {
2491 printf("(%s:%c:%d:%d): Sending WDTR %x\n",
2492 ahc_name(ahc), devinfo->channel, devinfo->target,
2493 devinfo->lun, bus_width);
2494 }
2495 }
2496
2497 /*
2498 * Build a parallel protocol request message in our message
2499 * buffer based on the input parameters.
2500 */
2501 static void
2502 ahc_construct_ppr(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
2503 u_int period, u_int offset, u_int bus_width,
2504 u_int ppr_options)
2505 {
2506 if (offset == 0)
2507 period = AHC_ASYNC_XFER_PERIOD;
2508 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXTENDED;
2509 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR_LEN;
2510 ahc->msgout_buf[ahc->msgout_index++] = MSG_EXT_PPR;
2511 ahc->msgout_buf[ahc->msgout_index++] = period;
2512 ahc->msgout_buf[ahc->msgout_index++] = 0;
2513 ahc->msgout_buf[ahc->msgout_index++] = offset;
2514 ahc->msgout_buf[ahc->msgout_index++] = bus_width;
2515 ahc->msgout_buf[ahc->msgout_index++] = ppr_options;
2516 ahc->msgout_len += 8;
2517 if (bootverbose) {
2518 printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, "
2519 "offset %x, ppr_options %x\n", ahc_name(ahc),
2520 devinfo->channel, devinfo->target, devinfo->lun,
2521 bus_width, period, offset, ppr_options);
2522 }
2523 }
2524
2525 /*
2526 * Clear any active message state.
2527 */
2528 static void
2529 ahc_clear_msg_state(struct ahc_softc *ahc)
2530 {
2531 ahc->msgout_len = 0;
2532 ahc->msgin_index = 0;
2533 ahc->msg_type = MSG_TYPE_NONE;
2534 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0) {
2535 /*
2536 * The target didn't care to respond to our
2537 * message request, so clear ATN.
2538 */
2539 ahc_outb(ahc, CLRSINT1, CLRATNO);
2540 }
2541 ahc_outb(ahc, MSG_OUT, MSG_NOOP);
2542 ahc_outb(ahc, SEQ_FLAGS2,
2543 ahc_inb(ahc, SEQ_FLAGS2) & ~TARGET_MSG_PENDING);
2544 }
2545
2546 static void
2547 ahc_handle_proto_violation(struct ahc_softc *ahc)
2548 {
2549 struct ahc_devinfo devinfo;
2550 struct scb *scb;
2551 u_int scbid;
2552 u_int seq_flags;
2553 u_int curphase;
2554 u_int lastphase;
2555 int found;
2556
2557 ahc_fetch_devinfo(ahc, &devinfo);
2558 scbid = ahc_inb(ahc, SCB_TAG);
2559 scb = ahc_lookup_scb(ahc, scbid);
2560 seq_flags = ahc_inb(ahc, SEQ_FLAGS);
2561 curphase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
2562 lastphase = ahc_inb(ahc, LASTPHASE);
2563 if ((seq_flags & NOT_IDENTIFIED) != 0) {
2564
2565 /*
2566 * The reconnecting target either did not send an
2567 * identify message, or did, but we didn't find an SCB
2568 * to match.
2569 */
2570 ahc_print_devinfo(ahc, &devinfo);
2571 printf("Target did not send an IDENTIFY message. "
2572 "LASTPHASE = 0x%x.\n", lastphase);
2573 scb = NULL;
2574 } else if (scb == NULL) {
2575 /*
2576 * We don't seem to have an SCB active for this
2577 * transaction. Print an error and reset the bus.
2578 */
2579 ahc_print_devinfo(ahc, &devinfo);
2580 printf("No SCB found during protocol violation\n");
2581 goto proto_violation_reset;
2582 } else {
2583 ahc_set_transaction_status(scb, CAM_SEQUENCE_FAIL);
2584 if ((seq_flags & NO_CDB_SENT) != 0) {
2585 ahc_print_path(ahc, scb);
2586 printf("No or incomplete CDB sent to device.\n");
2587 } else if ((ahc_inb(ahc, SCB_CONTROL) & STATUS_RCVD) == 0) {
2588 /*
2589 * The target never bothered to provide status to
2590 * us prior to completing the command. Since we don't
2591 * know the disposition of this command, we must attempt
2592 * to abort it. Assert ATN and prepare to send an abort
2593 * message.
2594 */
2595 ahc_print_path(ahc, scb);
2596 printf("Completed command without status.\n");
2597 } else {
2598 ahc_print_path(ahc, scb);
2599 printf("Unknown protocol violation.\n");
2600 ahc_dump_card_state(ahc);
2601 }
2602 }
2603 if ((lastphase & ~P_DATAIN_DT) == 0
2604 || lastphase == P_COMMAND) {
2605 proto_violation_reset:
2606 /*
2607 * Target either went directly to data/command
2608 * phase or didn't respond to our ATN.
2609 * The only safe thing to do is to blow
2610 * it away with a bus reset.
2611 */
2612 found = ahc_reset_channel(ahc, 'A', TRUE);
2613 printf("%s: Issued Channel %c Bus Reset. "
2614 "%d SCBs aborted\n", ahc_name(ahc), 'A', found);
2615 } else {
2616 /*
2617 * Leave the selection hardware off in case
2618 * this abort attempt will affect yet to
2619 * be sent commands.
2620 */
2621 ahc_outb(ahc, SCSISEQ,
2622 ahc_inb(ahc, SCSISEQ) & ~ENSELO);
2623 ahc_assert_atn(ahc);
2624 ahc_outb(ahc, MSG_OUT, HOST_MSG);
2625 if (scb == NULL) {
2626 ahc_print_devinfo(ahc, &devinfo);
2627 ahc->msgout_buf[0] = MSG_ABORT_TASK;
2628 ahc->msgout_len = 1;
2629 ahc->msgout_index = 0;
2630 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2631 } else {
2632 ahc_print_path(ahc, scb);
2633 scb->flags |= SCB_ABORT;
2634 }
2635 printf("Protocol violation %s. Attempting to abort.\n",
2636 ahc_lookup_phase_entry(curphase)->phasemsg);
2637 }
2638 }
2639
2640 /*
2641 * Manual message loop handler.
2642 */
2643 static void
2644 ahc_handle_message_phase(struct ahc_softc *ahc)
2645 {
2646 struct ahc_devinfo devinfo;
2647 u_int bus_phase;
2648 int end_session;
2649
2650 ahc_fetch_devinfo(ahc, &devinfo);
2651 end_session = FALSE;
2652 bus_phase = ahc_inb(ahc, SCSISIGI) & PHASE_MASK;
2653
2654 reswitch:
2655 switch (ahc->msg_type) {
2656 case MSG_TYPE_INITIATOR_MSGOUT:
2657 {
2658 int lastbyte;
2659 int phasemis;
2660 int msgdone;
2661
2662 if (ahc->msgout_len == 0)
2663 panic("HOST_MSG_LOOP interrupt with no active message");
2664
2665 #ifdef AHC_DEBUG
2666 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2667 ahc_print_devinfo(ahc, &devinfo);
2668 printf("INITIATOR_MSG_OUT");
2669 }
2670 #endif
2671 phasemis = bus_phase != P_MESGOUT;
2672 if (phasemis) {
2673 #ifdef AHC_DEBUG
2674 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2675 printf(" PHASEMIS %s\n",
2676 ahc_lookup_phase_entry(bus_phase)
2677 ->phasemsg);
2678 }
2679 #endif
2680 if (bus_phase == P_MESGIN) {
2681 /*
2682 * Change gears and see if
2683 * this messages is of interest to
2684 * us or should be passed back to
2685 * the sequencer.
2686 */
2687 ahc_outb(ahc, CLRSINT1, CLRATNO);
2688 ahc->send_msg_perror = FALSE;
2689 ahc->msg_type = MSG_TYPE_INITIATOR_MSGIN;
2690 ahc->msgin_index = 0;
2691 goto reswitch;
2692 }
2693 end_session = TRUE;
2694 break;
2695 }
2696
2697 if (ahc->send_msg_perror) {
2698 ahc_outb(ahc, CLRSINT1, CLRATNO);
2699 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2700 #ifdef AHC_DEBUG
2701 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2702 printf(" byte 0x%x\n", ahc->send_msg_perror);
2703 #endif
2704 ahc_outb(ahc, SCSIDATL, MSG_PARITY_ERROR);
2705 break;
2706 }
2707
2708 msgdone = ahc->msgout_index == ahc->msgout_len;
2709 if (msgdone) {
2710 /*
2711 * The target has requested a retry.
2712 * Re-assert ATN, reset our message index to
2713 * 0, and try again.
2714 */
2715 ahc->msgout_index = 0;
2716 ahc_assert_atn(ahc);
2717 }
2718
2719 lastbyte = ahc->msgout_index == (ahc->msgout_len - 1);
2720 if (lastbyte) {
2721 /* Last byte is signified by dropping ATN */
2722 ahc_outb(ahc, CLRSINT1, CLRATNO);
2723 }
2724
2725 /*
2726 * Clear our interrupt status and present
2727 * the next byte on the bus.
2728 */
2729 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2730 #ifdef AHC_DEBUG
2731 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2732 printf(" byte 0x%x\n",
2733 ahc->msgout_buf[ahc->msgout_index]);
2734 #endif
2735 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
2736 break;
2737 }
2738 case MSG_TYPE_INITIATOR_MSGIN:
2739 {
2740 int phasemis;
2741 int message_done;
2742
2743 #ifdef AHC_DEBUG
2744 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2745 ahc_print_devinfo(ahc, &devinfo);
2746 printf("INITIATOR_MSG_IN");
2747 }
2748 #endif
2749 phasemis = bus_phase != P_MESGIN;
2750 if (phasemis) {
2751 #ifdef AHC_DEBUG
2752 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2753 printf(" PHASEMIS %s\n",
2754 ahc_lookup_phase_entry(bus_phase)
2755 ->phasemsg);
2756 }
2757 #endif
2758 ahc->msgin_index = 0;
2759 if (bus_phase == P_MESGOUT
2760 && (ahc->send_msg_perror == TRUE
2761 || (ahc->msgout_len != 0
2762 && ahc->msgout_index == 0))) {
2763 ahc->msg_type = MSG_TYPE_INITIATOR_MSGOUT;
2764 goto reswitch;
2765 }
2766 end_session = TRUE;
2767 break;
2768 }
2769
2770 /* Pull the byte in without acking it */
2771 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIBUSL);
2772 #ifdef AHC_DEBUG
2773 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0)
2774 printf(" byte 0x%x\n",
2775 ahc->msgin_buf[ahc->msgin_index]);
2776 #endif
2777
2778 message_done = ahc_parse_msg(ahc, &devinfo);
2779
2780 if (message_done) {
2781 /*
2782 * Clear our incoming message buffer in case there
2783 * is another message following this one.
2784 */
2785 ahc->msgin_index = 0;
2786
2787 /*
2788 * If this message illicited a response,
2789 * assert ATN so the target takes us to the
2790 * message out phase.
2791 */
2792 if (ahc->msgout_len != 0) {
2793 #ifdef AHC_DEBUG
2794 if ((ahc_debug & AHC_SHOW_MESSAGES) != 0) {
2795 ahc_print_devinfo(ahc, &devinfo);
2796 printf("Asserting ATN for response\n");
2797 }
2798 #endif
2799 ahc_assert_atn(ahc);
2800 }
2801 } else
2802 ahc->msgin_index++;
2803
2804 if (message_done == MSGLOOP_TERMINATED) {
2805 end_session = TRUE;
2806 } else {
2807 /* Ack the byte */
2808 ahc_outb(ahc, CLRSINT1, CLRREQINIT);
2809 ahc_inb(ahc, SCSIDATL);
2810 }
2811 break;
2812 }
2813 case MSG_TYPE_TARGET_MSGIN:
2814 {
2815 int msgdone;
2816 int msgout_request;
2817
2818 if (ahc->msgout_len == 0)
2819 panic("Target MSGIN with no active message");
2820
2821 /*
2822 * If we interrupted a mesgout session, the initiator
2823 * will not know this until our first REQ. So, we
2824 * only honor mesgout requests after we've sent our
2825 * first byte.
2826 */
2827 if ((ahc_inb(ahc, SCSISIGI) & ATNI) != 0
2828 && ahc->msgout_index > 0)
2829 msgout_request = TRUE;
2830 else
2831 msgout_request = FALSE;
2832
2833 if (msgout_request) {
2834
2835 /*
2836 * Change gears and see if
2837 * this messages is of interest to
2838 * us or should be passed back to
2839 * the sequencer.
2840 */
2841 ahc->msg_type = MSG_TYPE_TARGET_MSGOUT;
2842 ahc_outb(ahc, SCSISIGO, P_MESGOUT | BSYO);
2843 ahc->msgin_index = 0;
2844 /* Dummy read to REQ for first byte */
2845 ahc_inb(ahc, SCSIDATL);
2846 ahc_outb(ahc, SXFRCTL0,
2847 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2848 break;
2849 }
2850
2851 msgdone = ahc->msgout_index == ahc->msgout_len;
2852 if (msgdone) {
2853 ahc_outb(ahc, SXFRCTL0,
2854 ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
2855 end_session = TRUE;
2856 break;
2857 }
2858
2859 /*
2860 * Present the next byte on the bus.
2861 */
2862 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2863 ahc_outb(ahc, SCSIDATL, ahc->msgout_buf[ahc->msgout_index++]);
2864 break;
2865 }
2866 case MSG_TYPE_TARGET_MSGOUT:
2867 {
2868 int lastbyte;
2869 int msgdone;
2870
2871 /*
2872 * The initiator signals that this is
2873 * the last byte by dropping ATN.
2874 */
2875 lastbyte = (ahc_inb(ahc, SCSISIGI) & ATNI) == 0;
2876
2877 /*
2878 * Read the latched byte, but turn off SPIOEN first
2879 * so that we don't inadvertently cause a REQ for the
2880 * next byte.
2881 */
2882 ahc_outb(ahc, SXFRCTL0, ahc_inb(ahc, SXFRCTL0) & ~SPIOEN);
2883 ahc->msgin_buf[ahc->msgin_index] = ahc_inb(ahc, SCSIDATL);
2884 msgdone = ahc_parse_msg(ahc, &devinfo);
2885 if (msgdone == MSGLOOP_TERMINATED) {
2886 /*
2887 * The message is *really* done in that it caused
2888 * us to go to bus free. The sequencer has already
2889 * been reset at this point, so pull the ejection
2890 * handle.
2891 */
2892 return;
2893 }
2894
2895 ahc->msgin_index++;
2896
2897 /*
2898 * XXX Read spec about initiator dropping ATN too soon
2899 * and use msgdone to detect it.
2900 */
2901 if (msgdone == MSGLOOP_MSGCOMPLETE) {
2902 ahc->msgin_index = 0;
2903
2904 /*
2905 * If this message illicited a response, transition
2906 * to the Message in phase and send it.
2907 */
2908 if (ahc->msgout_len != 0) {
2909 ahc_outb(ahc, SCSISIGO, P_MESGIN | BSYO);
2910 ahc_outb(ahc, SXFRCTL0,
2911 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2912 ahc->msg_type = MSG_TYPE_TARGET_MSGIN;
2913 ahc->msgin_index = 0;
2914 break;
2915 }
2916 }
2917
2918 if (lastbyte)
2919 end_session = TRUE;
2920 else {
2921 /* Ask for the next byte. */
2922 ahc_outb(ahc, SXFRCTL0,
2923 ahc_inb(ahc, SXFRCTL0) | SPIOEN);
2924 }
2925
2926 break;
2927 }
2928 default:
2929 panic("Unknown REQINIT message type");
2930 }
2931
2932 if (end_session) {
2933 ahc_clear_msg_state(ahc);
2934 ahc_outb(ahc, RETURN_1, EXIT_MSG_LOOP);
2935 } else
2936 ahc_outb(ahc, RETURN_1, CONT_MSG_LOOP);
2937 }
2938
2939 /*
2940 * See if we sent a particular extended message to the target.
2941 * If "full" is true, return true only if the target saw the full
2942 * message. If "full" is false, return true if the target saw at
2943 * least the first byte of the message.
2944 */
2945 static int
2946 ahc_sent_msg(struct ahc_softc *ahc, ahc_msgtype type, u_int msgval, int full)
2947 {
2948 int found;
2949 u_int index;
2950
2951 found = FALSE;
2952 index = 0;
2953
2954 while (index < ahc->msgout_len) {
2955 if (ahc->msgout_buf[index] == MSG_EXTENDED) {
2956 u_int end_index;
2957
2958 end_index = index + 1 + ahc->msgout_buf[index + 1];
2959 if (ahc->msgout_buf[index+2] == msgval
2960 && type == AHCMSG_EXT) {
2961
2962 if (full) {
2963 if (ahc->msgout_index > end_index)
2964 found = TRUE;
2965 } else if (ahc->msgout_index > index)
2966 found = TRUE;
2967 }
2968 index = end_index;
2969 } else if (ahc->msgout_buf[index] >= MSG_SIMPLE_TASK
2970 && ahc->msgout_buf[index] <= MSG_IGN_WIDE_RESIDUE) {
2971
2972 /* Skip tag type and tag id or residue param*/
2973 index += 2;
2974 } else {
2975 /* Single byte message */
2976 if (type == AHCMSG_1B
2977 && ahc->msgout_buf[index] == msgval
2978 && ahc->msgout_index > index)
2979 found = TRUE;
2980 index++;
2981 }
2982
2983 if (found)
2984 break;
2985 }
2986 return (found);
2987 }
2988
2989 /*
2990 * Wait for a complete incoming message, parse it, and respond accordingly.
2991 */
2992 static int
2993 ahc_parse_msg(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
2994 {
2995 struct ahc_initiator_tinfo *tinfo;
2996 struct ahc_tmode_tstate *tstate;
2997 int reject;
2998 int done;
2999 int response;
3000 u_int targ_scsirate;
3001
3002 done = MSGLOOP_IN_PROG;
3003 response = FALSE;
3004 reject = FALSE;
3005 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel, devinfo->our_scsiid,
3006 devinfo->target, &tstate);
3007 targ_scsirate = tinfo->scsirate;
3008
3009 /*
3010 * Parse as much of the message as is available,
3011 * rejecting it if we don't support it. When
3012 * the entire message is available and has been
3013 * handled, return MSGLOOP_MSGCOMPLETE, indicating
3014 * that we have parsed an entire message.
3015 *
3016 * In the case of extended messages, we accept the length
3017 * byte outright and perform more checking once we know the
3018 * extended message type.
3019 */
3020 switch (ahc->msgin_buf[0]) {
3021 case MSG_DISCONNECT:
3022 case MSG_SAVEDATAPOINTER:
3023 case MSG_CMDCOMPLETE:
3024 case MSG_RESTOREPOINTERS:
3025 case MSG_IGN_WIDE_RESIDUE:
3026 /*
3027 * End our message loop as these are messages
3028 * the sequencer handles on its own.
3029 */
3030 done = MSGLOOP_TERMINATED;
3031 break;
3032 case MSG_MESSAGE_REJECT:
3033 response = ahc_handle_msg_reject(ahc, devinfo);
3034 /* FALLTHROUGH */
3035 case MSG_NOOP:
3036 done = MSGLOOP_MSGCOMPLETE;
3037 break;
3038 case MSG_EXTENDED:
3039 {
3040 /* Wait for enough of the message to begin validation */
3041 if (ahc->msgin_index < 2)
3042 break;
3043 switch (ahc->msgin_buf[2]) {
3044 case MSG_EXT_SDTR:
3045 {
3046 struct ahc_syncrate *syncrate;
3047 u_int period;
3048 u_int ppr_options;
3049 u_int offset;
3050 u_int saved_offset;
3051
3052 if (ahc->msgin_buf[1] != MSG_EXT_SDTR_LEN) {
3053 reject = TRUE;
3054 break;
3055 }
3056
3057 /*
3058 * Wait until we have both args before validating
3059 * and acting on this message.
3060 *
3061 * Add one to MSG_EXT_SDTR_LEN to account for
3062 * the extended message preamble.
3063 */
3064 if (ahc->msgin_index < (MSG_EXT_SDTR_LEN + 1))
3065 break;
3066
3067 period = ahc->msgin_buf[3];
3068 ppr_options = 0;
3069 saved_offset = offset = ahc->msgin_buf[4];
3070 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period,
3071 &ppr_options,
3072 devinfo->role);
3073 ahc_validate_offset(ahc, tinfo, syncrate, &offset,
3074 targ_scsirate & WIDEXFER,
3075 devinfo->role);
3076 if (bootverbose) {
3077 printf("(%s:%c:%d:%d): Received "
3078 "SDTR period %x, offset %x\n\t"
3079 "Filtered to period %x, offset %x\n",
3080 ahc_name(ahc), devinfo->channel,
3081 devinfo->target, devinfo->lun,
3082 ahc->msgin_buf[3], saved_offset,
3083 period, offset);
3084 }
3085 ahc_set_syncrate(ahc, devinfo,
3086 syncrate, period,
3087 offset, ppr_options,
3088 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3089 /*paused*/TRUE);
3090
3091 /*
3092 * See if we initiated Sync Negotiation
3093 * and didn't have to fall down to async
3094 * transfers.
3095 */
3096 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, TRUE)) {
3097 /* We started it */
3098 if (saved_offset != offset) {
3099 /* Went too low - force async */
3100 reject = TRUE;
3101 }
3102 } else {
3103 /*
3104 * Send our own SDTR in reply
3105 */
3106 if (bootverbose
3107 && devinfo->role == ROLE_INITIATOR) {
3108 printf("(%s:%c:%d:%d): Target "
3109 "Initiated SDTR\n",
3110 ahc_name(ahc), devinfo->channel,
3111 devinfo->target, devinfo->lun);
3112 }
3113 ahc->msgout_index = 0;
3114 ahc->msgout_len = 0;
3115 ahc_construct_sdtr(ahc, devinfo,
3116 period, offset);
3117 ahc->msgout_index = 0;
3118 response = TRUE;
3119 }
3120 done = MSGLOOP_MSGCOMPLETE;
3121 break;
3122 }
3123 case MSG_EXT_WDTR:
3124 {
3125 u_int bus_width;
3126 u_int saved_width;
3127 u_int sending_reply;
3128
3129 sending_reply = FALSE;
3130 if (ahc->msgin_buf[1] != MSG_EXT_WDTR_LEN) {
3131 reject = TRUE;
3132 break;
3133 }
3134
3135 /*
3136 * Wait until we have our arg before validating
3137 * and acting on this message.
3138 *
3139 * Add one to MSG_EXT_WDTR_LEN to account for
3140 * the extended message preamble.
3141 */
3142 if (ahc->msgin_index < (MSG_EXT_WDTR_LEN + 1))
3143 break;
3144
3145 bus_width = ahc->msgin_buf[3];
3146 saved_width = bus_width;
3147 ahc_validate_width(ahc, tinfo, &bus_width,
3148 devinfo->role);
3149 if (bootverbose) {
3150 printf("(%s:%c:%d:%d): Received WDTR "
3151 "%x filtered to %x\n",
3152 ahc_name(ahc), devinfo->channel,
3153 devinfo->target, devinfo->lun,
3154 saved_width, bus_width);
3155 }
3156
3157 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, TRUE)) {
3158 /*
3159 * Don't send a WDTR back to the
3160 * target, since we asked first.
3161 * If the width went higher than our
3162 * request, reject it.
3163 */
3164 if (saved_width > bus_width) {
3165 reject = TRUE;
3166 printf("(%s:%c:%d:%d): requested %dBit "
3167 "transfers. Rejecting...\n",
3168 ahc_name(ahc), devinfo->channel,
3169 devinfo->target, devinfo->lun,
3170 8 * (0x01 << bus_width));
3171 bus_width = 0;
3172 }
3173 } else {
3174 /*
3175 * Send our own WDTR in reply
3176 */
3177 if (bootverbose
3178 && devinfo->role == ROLE_INITIATOR) {
3179 printf("(%s:%c:%d:%d): Target "
3180 "Initiated WDTR\n",
3181 ahc_name(ahc), devinfo->channel,
3182 devinfo->target, devinfo->lun);
3183 }
3184 ahc->msgout_index = 0;
3185 ahc->msgout_len = 0;
3186 ahc_construct_wdtr(ahc, devinfo, bus_width);
3187 ahc->msgout_index = 0;
3188 response = TRUE;
3189 sending_reply = TRUE;
3190 }
3191 /*
3192 * After a wide message, we are async, but
3193 * some devices don't seem to honor this portion
3194 * of the spec. Force a renegotiation of the
3195 * sync component of our transfer agreement even
3196 * if our goal is async. By updating our width
3197 * after forcing the negotiation, we avoid
3198 * renegotiating for width.
3199 */
3200 ahc_update_neg_request(ahc, devinfo, tstate,
3201 tinfo, AHC_NEG_ALWAYS);
3202 ahc_set_width(ahc, devinfo, bus_width,
3203 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3204 /*paused*/TRUE);
3205 if (sending_reply == FALSE && reject == FALSE) {
3206
3207 /*
3208 * We will always have an SDTR to send.
3209 */
3210 ahc->msgout_index = 0;
3211 ahc->msgout_len = 0;
3212 ahc_build_transfer_msg(ahc, devinfo);
3213 ahc->msgout_index = 0;
3214 response = TRUE;
3215 }
3216 done = MSGLOOP_MSGCOMPLETE;
3217 break;
3218 }
3219 case MSG_EXT_PPR:
3220 {
3221 struct ahc_syncrate *syncrate;
3222 u_int period;
3223 u_int offset;
3224 u_int bus_width;
3225 u_int ppr_options;
3226 u_int saved_width;
3227 u_int saved_offset;
3228 u_int saved_ppr_options;
3229
3230 if (ahc->msgin_buf[1] != MSG_EXT_PPR_LEN) {
3231 reject = TRUE;
3232 break;
3233 }
3234
3235 /*
3236 * Wait until we have all args before validating
3237 * and acting on this message.
3238 *
3239 * Add one to MSG_EXT_PPR_LEN to account for
3240 * the extended message preamble.
3241 */
3242 if (ahc->msgin_index < (MSG_EXT_PPR_LEN + 1))
3243 break;
3244
3245 period = ahc->msgin_buf[3];
3246 offset = ahc->msgin_buf[5];
3247 bus_width = ahc->msgin_buf[6];
3248 saved_width = bus_width;
3249 ppr_options = ahc->msgin_buf[7];
3250 /*
3251 * According to the spec, a DT only
3252 * period factor with no DT option
3253 * set implies async.
3254 */
3255 if ((ppr_options & MSG_EXT_PPR_DT_REQ) == 0
3256 && period == 9)
3257 offset = 0;
3258 saved_ppr_options = ppr_options;
3259 saved_offset = offset;
3260
3261 /*
3262 * Mask out any options we don't support
3263 * on any controller. Transfer options are
3264 * only available if we are negotiating wide.
3265 */
3266 ppr_options &= MSG_EXT_PPR_DT_REQ;
3267 if (bus_width == 0)
3268 ppr_options = 0;
3269
3270 ahc_validate_width(ahc, tinfo, &bus_width,
3271 devinfo->role);
3272 syncrate = ahc_devlimited_syncrate(ahc, tinfo, &period,
3273 &ppr_options,
3274 devinfo->role);
3275 ahc_validate_offset(ahc, tinfo, syncrate,
3276 &offset, bus_width,
3277 devinfo->role);
3278
3279 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, TRUE)) {
3280 /*
3281 * If we are unable to do any of the
3282 * requested options (we went too low),
3283 * then we'll have to reject the message.
3284 */
3285 if (saved_width > bus_width
3286 || saved_offset != offset
3287 || saved_ppr_options != ppr_options) {
3288 reject = TRUE;
3289 period = 0;
3290 offset = 0;
3291 bus_width = 0;
3292 ppr_options = 0;
3293 syncrate = NULL;
3294 }
3295 } else {
3296 if (devinfo->role != ROLE_TARGET)
3297 printf("(%s:%c:%d:%d): Target "
3298 "Initiated PPR\n",
3299 ahc_name(ahc), devinfo->channel,
3300 devinfo->target, devinfo->lun);
3301 else
3302 printf("(%s:%c:%d:%d): Initiator "
3303 "Initiated PPR\n",
3304 ahc_name(ahc), devinfo->channel,
3305 devinfo->target, devinfo->lun);
3306 ahc->msgout_index = 0;
3307 ahc->msgout_len = 0;
3308 ahc_construct_ppr(ahc, devinfo, period, offset,
3309 bus_width, ppr_options);
3310 ahc->msgout_index = 0;
3311 response = TRUE;
3312 }
3313 if (bootverbose) {
3314 printf("(%s:%c:%d:%d): Received PPR width %x, "
3315 "period %x, offset %x,options %x\n"
3316 "\tFiltered to width %x, period %x, "
3317 "offset %x, options %x\n",
3318 ahc_name(ahc), devinfo->channel,
3319 devinfo->target, devinfo->lun,
3320 saved_width, ahc->msgin_buf[3],
3321 saved_offset, saved_ppr_options,
3322 bus_width, period, offset, ppr_options);
3323 }
3324 ahc_set_width(ahc, devinfo, bus_width,
3325 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3326 /*paused*/TRUE);
3327 ahc_set_syncrate(ahc, devinfo,
3328 syncrate, period,
3329 offset, ppr_options,
3330 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3331 /*paused*/TRUE);
3332 done = MSGLOOP_MSGCOMPLETE;
3333 break;
3334 }
3335 default:
3336 /* Unknown extended message. Reject it. */
3337 reject = TRUE;
3338 break;
3339 }
3340 break;
3341 }
3342 #ifdef AHC_TARGET_MODE
3343 case MSG_BUS_DEV_RESET:
3344 ahc_handle_devreset(ahc, devinfo,
3345 CAM_BDR_SENT,
3346 "Bus Device Reset Received",
3347 /*verbose_level*/0);
3348 ahc_restart(ahc);
3349 done = MSGLOOP_TERMINATED;
3350 break;
3351 case MSG_ABORT_TAG:
3352 case MSG_ABORT:
3353 case MSG_CLEAR_QUEUE:
3354 {
3355 int tag;
3356
3357 /* Target mode messages */
3358 if (devinfo->role != ROLE_TARGET) {
3359 reject = TRUE;
3360 break;
3361 }
3362 tag = SCB_LIST_NULL;
3363 if (ahc->msgin_buf[0] == MSG_ABORT_TAG)
3364 tag = ahc_inb(ahc, INITIATOR_TAG);
3365 ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
3366 devinfo->lun, tag, ROLE_TARGET,
3367 CAM_REQ_ABORTED);
3368
3369 tstate = ahc->enabled_targets[devinfo->our_scsiid];
3370 if (tstate != NULL) {
3371 struct ahc_tmode_lstate* lstate;
3372
3373 lstate = tstate->enabled_luns[devinfo->lun];
3374 if (lstate != NULL) {
3375 ahc_queue_lstate_event(ahc, lstate,
3376 devinfo->our_scsiid,
3377 ahc->msgin_buf[0],
3378 /*arg*/tag);
3379 ahc_send_lstate_events(ahc, lstate);
3380 }
3381 }
3382 ahc_restart(ahc);
3383 done = MSGLOOP_TERMINATED;
3384 break;
3385 }
3386 #endif
3387 case MSG_TERM_IO_PROC:
3388 default:
3389 reject = TRUE;
3390 break;
3391 }
3392
3393 if (reject) {
3394 /*
3395 * Setup to reject the message.
3396 */
3397 ahc->msgout_index = 0;
3398 ahc->msgout_len = 1;
3399 ahc->msgout_buf[0] = MSG_MESSAGE_REJECT;
3400 done = MSGLOOP_MSGCOMPLETE;
3401 response = TRUE;
3402 }
3403
3404 if (done != MSGLOOP_IN_PROG && !response)
3405 /* Clear the outgoing message buffer */
3406 ahc->msgout_len = 0;
3407
3408 return (done);
3409 }
3410
3411 /*
3412 * Process a message reject message.
3413 */
3414 static int
3415 ahc_handle_msg_reject(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3416 {
3417 /*
3418 * What we care about here is if we had an
3419 * outstanding SDTR or WDTR message for this
3420 * target. If we did, this is a signal that
3421 * the target is refusing negotiation.
3422 */
3423 struct scb *scb;
3424 struct ahc_initiator_tinfo *tinfo;
3425 struct ahc_tmode_tstate *tstate;
3426 u_int scb_index;
3427 u_int last_msg;
3428 int response = 0;
3429
3430 scb_index = ahc_inb(ahc, SCB_TAG);
3431 scb = ahc_lookup_scb(ahc, scb_index);
3432 tinfo = ahc_fetch_transinfo(ahc, devinfo->channel,
3433 devinfo->our_scsiid,
3434 devinfo->target, &tstate);
3435 /* Might be necessary */
3436 last_msg = ahc_inb(ahc, LAST_MSG);
3437
3438 if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_PPR, /*full*/FALSE)) {
3439 /*
3440 * Target does not support the PPR message.
3441 * Attempt to negotiate SPI-2 style.
3442 */
3443 if (bootverbose) {
3444 printf("(%s:%c:%d:%d): PPR Rejected. "
3445 "Trying WDTR/SDTR\n",
3446 ahc_name(ahc), devinfo->channel,
3447 devinfo->target, devinfo->lun);
3448 }
3449 tinfo->goal.ppr_options = 0;
3450 tinfo->curr.transport_version = 2;
3451 tinfo->goal.transport_version = 2;
3452 ahc->msgout_index = 0;
3453 ahc->msgout_len = 0;
3454 ahc_build_transfer_msg(ahc, devinfo);
3455 ahc->msgout_index = 0;
3456 response = 1;
3457 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_WDTR, /*full*/FALSE)) {
3458
3459 /* note 8bit xfers */
3460 printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using "
3461 "8bit transfers\n", ahc_name(ahc),
3462 devinfo->channel, devinfo->target, devinfo->lun);
3463 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
3464 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3465 /*paused*/TRUE);
3466 /*
3467 * No need to clear the sync rate. If the target
3468 * did not accept the command, our syncrate is
3469 * unaffected. If the target started the negotiation,
3470 * but rejected our response, we already cleared the
3471 * sync rate before sending our WDTR.
3472 */
3473 if (tinfo->goal.offset != tinfo->curr.offset) {
3474
3475 /* Start the sync negotiation */
3476 ahc->msgout_index = 0;
3477 ahc->msgout_len = 0;
3478 ahc_build_transfer_msg(ahc, devinfo);
3479 ahc->msgout_index = 0;
3480 response = 1;
3481 }
3482 } else if (ahc_sent_msg(ahc, AHCMSG_EXT, MSG_EXT_SDTR, /*full*/FALSE)) {
3483 /* note asynch xfers and clear flag */
3484 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL, /*period*/0,
3485 /*offset*/0, /*ppr_options*/0,
3486 AHC_TRANS_ACTIVE|AHC_TRANS_GOAL,
3487 /*paused*/TRUE);
3488 printf("(%s:%c:%d:%d): refuses synchronous negotiation. "
3489 "Using asynchronous transfers\n",
3490 ahc_name(ahc), devinfo->channel,
3491 devinfo->target, devinfo->lun);
3492 } else if ((scb->hscb->control & MSG_SIMPLE_TASK) != 0) {
3493 int tag_type;
3494 int mask;
3495
3496 tag_type = (scb->hscb->control & MSG_SIMPLE_TASK);
3497
3498 if (tag_type == MSG_SIMPLE_TASK) {
3499 printf("(%s:%c:%d:%d): refuses tagged commands. "
3500 "Performing non-tagged I/O\n", ahc_name(ahc),
3501 devinfo->channel, devinfo->target, devinfo->lun);
3502 ahc_set_tags(ahc, devinfo, AHC_QUEUE_NONE);
3503 mask = ~0x23;
3504 } else {
3505 printf("(%s:%c:%d:%d): refuses %s tagged commands. "
3506 "Performing simple queue tagged I/O only\n",
3507 ahc_name(ahc), devinfo->channel, devinfo->target,
3508 devinfo->lun, tag_type == MSG_ORDERED_TASK
3509 ? "ordered" : "head of queue");
3510 ahc_set_tags(ahc, devinfo, AHC_QUEUE_BASIC);
3511 mask = ~0x03;
3512 }
3513
3514 /*
3515 * Resend the identify for this CCB as the target
3516 * may believe that the selection is invalid otherwise.
3517 */
3518 ahc_outb(ahc, SCB_CONTROL,
3519 ahc_inb(ahc, SCB_CONTROL) & mask);
3520 scb->hscb->control &= mask;
3521 ahc_set_transaction_tag(scb, /*enabled*/FALSE,
3522 /*type*/MSG_SIMPLE_TASK);
3523 ahc_outb(ahc, MSG_OUT, MSG_IDENTIFYFLAG);
3524 ahc_assert_atn(ahc);
3525
3526 /*
3527 * This transaction is now at the head of
3528 * the untagged queue for this target.
3529 */
3530 if ((ahc->flags & AHC_SCB_BTT) == 0) {
3531 struct scb_tailq *untagged_q;
3532
3533 untagged_q =
3534 &(ahc->untagged_queues[devinfo->target_offset]);
3535 TAILQ_INSERT_HEAD(untagged_q, scb, links.tqe);
3536 scb->flags |= SCB_UNTAGGEDQ;
3537 }
3538 ahc_busy_tcl(ahc, BUILD_TCL(scb->hscb->scsiid, devinfo->lun),
3539 scb->hscb->tag);
3540
3541 /*
3542 * Requeue all tagged commands for this target
3543 * currently in our posession so they can be
3544 * converted to untagged commands.
3545 */
3546 ahc_search_qinfifo(ahc, SCB_GET_TARGET(ahc, scb),
3547 SCB_GET_CHANNEL(ahc, scb),
3548 SCB_GET_LUN(scb), /*tag*/SCB_LIST_NULL,
3549 ROLE_INITIATOR, CAM_REQUEUE_REQ,
3550 SEARCH_COMPLETE);
3551 } else {
3552 /*
3553 * Otherwise, we ignore it.
3554 */
3555 printf("%s:%c:%d: Message reject for %x -- ignored\n",
3556 ahc_name(ahc), devinfo->channel, devinfo->target,
3557 last_msg);
3558 }
3559 return (response);
3560 }
3561
3562 /*
3563 * Process an ingnore wide residue message.
3564 */
3565 static void
3566 ahc_handle_ign_wide_residue(struct ahc_softc *ahc, struct ahc_devinfo *devinfo)
3567 {
3568 u_int scb_index;
3569 struct scb *scb;
3570
3571 scb_index = ahc_inb(ahc, SCB_TAG);
3572 scb = ahc_lookup_scb(ahc, scb_index);
3573 /*
3574 * XXX Actually check data direction in the sequencer?
3575 * Perhaps add datadir to some spare bits in the hscb?
3576 */
3577 if ((ahc_inb(ahc, SEQ_FLAGS) & DPHASE) == 0
3578 || ahc_get_transfer_dir(scb) != CAM_DIR_IN) {
3579 /*
3580 * Ignore the message if we haven't
3581 * seen an appropriate data phase yet.
3582 */
3583 } else {
3584 /*
3585 * If the residual occurred on the last
3586 * transfer and the transfer request was
3587 * expected to end on an odd count, do
3588 * nothing. Otherwise, subtract a byte
3589 * and update the residual count accordingly.
3590 */
3591 uint32_t sgptr;
3592
3593 sgptr = ahc_inb(ahc, SCB_RESIDUAL_SGPTR);
3594 if ((sgptr & SG_LIST_NULL) != 0
3595 && (ahc_inb(ahc, SCB_LUN) & SCB_XFERLEN_ODD) != 0) {
3596 /*
3597 * If the residual occurred on the last
3598 * transfer and the transfer request was
3599 * expected to end on an odd count, do
3600 * nothing.
3601 */
3602 } else {
3603 struct ahc_dma_seg *sg;
3604 uint32_t data_cnt;
3605 uint32_t data_addr;
3606 uint32_t sglen;
3607
3608 /* Pull in all of the sgptr */
3609 sgptr = ahc_inl(ahc, SCB_RESIDUAL_SGPTR);
3610 data_cnt = ahc_inl(ahc, SCB_RESIDUAL_DATACNT);
3611
3612 if ((sgptr & SG_LIST_NULL) != 0) {
3613 /*
3614 * The residual data count is not updated
3615 * for the command run to completion case.
3616 * Explicitly zero the count.
3617 */
3618 data_cnt &= ~AHC_SG_LEN_MASK;
3619 }
3620
3621 data_addr = ahc_inl(ahc, SHADDR);
3622
3623 data_cnt += 1;
3624 data_addr -= 1;
3625 sgptr &= SG_PTR_MASK;
3626
3627 sg = ahc_sg_bus_to_virt(scb, sgptr);
3628
3629 /*
3630 * The residual sg ptr points to the next S/G
3631 * to load so we must go back one.
3632 */
3633 sg--;
3634 sglen = ahc_le32toh(sg->len) & AHC_SG_LEN_MASK;
3635 if (sg != scb->sg_list
3636 && sglen < (data_cnt & AHC_SG_LEN_MASK)) {
3637
3638 sg--;
3639 sglen = ahc_le32toh(sg->len);
3640 /*
3641 * Preserve High Address and SG_LIST bits
3642 * while setting the count to 1.
3643 */
3644 data_cnt = 1 | (sglen & (~AHC_SG_LEN_MASK));
3645 data_addr = ahc_le32toh(sg->addr)
3646 + (sglen & AHC_SG_LEN_MASK) - 1;
3647
3648 /*
3649 * Increment sg so it points to the
3650 * "next" sg.
3651 */
3652 sg++;
3653 sgptr = ahc_sg_virt_to_bus(scb, sg);
3654 }
3655 ahc_outl(ahc, SCB_RESIDUAL_SGPTR, sgptr);
3656 ahc_outl(ahc, SCB_RESIDUAL_DATACNT, data_cnt);
3657 /*
3658 * Toggle the "oddness" of the transfer length
3659 * to handle this mid-transfer ignore wide
3660 * residue. This ensures that the oddness is
3661 * correct for subsequent data transfers.
3662 */
3663 ahc_outb(ahc, SCB_LUN,
3664 ahc_inb(ahc, SCB_LUN) ^ SCB_XFERLEN_ODD);
3665 }
3666 }
3667 }
3668
3669
3670 /*
3671 * Reinitialize the data pointers for the active transfer
3672 * based on its current residual.
3673 */
3674 static void
3675 ahc_reinitialize_dataptrs(struct ahc_softc *ahc)
3676 {
3677 struct scb *scb;
3678 struct ahc_dma_seg *sg;
3679 u_int scb_index;
3680 uint32_t sgptr;
3681 uint32_t resid;
3682 uint32_t dataptr;
3683
3684 scb_index = ahc_inb(ahc, SCB_TAG);
3685 scb = ahc_lookup_scb(ahc, scb_index);
3686 sgptr = (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 3) << 24)
3687 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 2) << 16)
3688 | (ahc_inb(ahc, SCB_RESIDUAL_SGPTR + 1) << 8)
3689 | ahc_inb(ahc, SCB_RESIDUAL_SGPTR);
3690
3691 sgptr &= SG_PTR_MASK;
3692 sg = ahc_sg_bus_to_virt(scb, sgptr);
3693
3694 /* The residual sg_ptr always points to the next sg */
3695 sg--;
3696
3697 resid = (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 2) << 16)
3698 | (ahc_inb(ahc, SCB_RESIDUAL_DATACNT + 1) << 8)
3699 | ahc_inb(ahc, SCB_RESIDUAL_DATACNT);
3700
3701 dataptr = ahc_le32toh(sg->addr)
3702 + (ahc_le32toh(sg->len) & AHC_SG_LEN_MASK)
3703 - resid;
3704 if ((ahc->flags & AHC_39BIT_ADDRESSING) != 0) {
3705 u_int dscommand1;
3706
3707 dscommand1 = ahc_inb(ahc, DSCOMMAND1);
3708 ahc_outb(ahc, DSCOMMAND1, dscommand1 | HADDLDSEL0);
3709 ahc_outb(ahc, HADDR,
3710 (ahc_le32toh(sg->len) >> 24) & SG_HIGH_ADDR_BITS);
3711 ahc_outb(ahc, DSCOMMAND1, dscommand1);
3712 }
3713 ahc_outb(ahc, HADDR + 3, dataptr >> 24);
3714 ahc_outb(ahc, HADDR + 2, dataptr >> 16);
3715 ahc_outb(ahc, HADDR + 1, dataptr >> 8);
3716 ahc_outb(ahc, HADDR, dataptr);
3717 ahc_outb(ahc, HCNT + 2, resid >> 16);
3718 ahc_outb(ahc, HCNT + 1, resid >> 8);
3719 ahc_outb(ahc, HCNT, resid);
3720 if ((ahc->features & AHC_ULTRA2) == 0) {
3721 ahc_outb(ahc, STCNT + 2, resid >> 16);
3722 ahc_outb(ahc, STCNT + 1, resid >> 8);
3723 ahc_outb(ahc, STCNT, resid);
3724 }
3725 }
3726
3727 /*
3728 * Handle the effects of issuing a bus device reset message.
3729 */
3730 static void
3731 ahc_handle_devreset(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
3732 cam_status status, char *message, int verbose_level)
3733 {
3734 #ifdef AHC_TARGET_MODE
3735 struct ahc_tmode_tstate* tstate;
3736 u_int lun;
3737 #endif
3738 int found;
3739
3740 found = ahc_abort_scbs(ahc, devinfo->target, devinfo->channel,
3741 CAM_LUN_WILDCARD, SCB_LIST_NULL, devinfo->role,
3742 status);
3743
3744 #ifdef AHC_TARGET_MODE
3745 /*
3746 * Send an immediate notify ccb to all target mord peripheral
3747 * drivers affected by this action.
3748 */
3749 tstate = ahc->enabled_targets[devinfo->our_scsiid];
3750 if (tstate != NULL) {
3751 for (lun = 0; lun < AHC_NUM_LUNS; lun++) {
3752 struct ahc_tmode_lstate* lstate;
3753
3754 lstate = tstate->enabled_luns[lun];
3755 if (lstate == NULL)
3756 continue;
3757
3758 ahc_queue_lstate_event(ahc, lstate, devinfo->our_scsiid,
3759 MSG_BUS_DEV_RESET, /*arg*/0);
3760 ahc_send_lstate_events(ahc, lstate);
3761 }
3762 }
3763 #endif
3764
3765 /*
3766 * Go back to async/narrow transfers and renegotiate.
3767 */
3768 ahc_set_width(ahc, devinfo, MSG_EXT_WDTR_BUS_8_BIT,
3769 AHC_TRANS_CUR, /*paused*/TRUE);
3770 ahc_set_syncrate(ahc, devinfo, /*syncrate*/NULL,
3771 /*period*/0, /*offset*/0, /*ppr_options*/0,
3772 AHC_TRANS_CUR, /*paused*/TRUE);
3773
3774 if (status != CAM_SEL_TIMEOUT)
3775 ahc_send_async(ahc, devinfo->channel, devinfo->target,
3776 CAM_LUN_WILDCARD, AC_SENT_BDR, NULL);
3777
3778 if (message != NULL
3779 && (verbose_level <= bootverbose))
3780 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahc_name(ahc),
3781 message, devinfo->channel, devinfo->target, found);
3782 }
3783
3784 #ifdef AHC_TARGET_MODE
3785 static void
3786 ahc_setup_target_msgin(struct ahc_softc *ahc, struct ahc_devinfo *devinfo,
3787 struct scb *scb)
3788 {
3789
3790 /*
3791 * To facilitate adding multiple messages together,
3792 * each routine should increment the index and len
3793 * variables instead of setting them explicitly.
3794 */
3795 ahc->msgout_index = 0;
3796 ahc->msgout_len = 0;
3797
3798 if (scb != NULL && (scb->flags & SCB_AUTO_NEGOTIATE) != 0)
3799 ahc_build_transfer_msg(ahc, devinfo);
3800 else
3801 panic("ahc_intr: AWAITING target message with no message");
3802
3803 ahc->msgout_index = 0;
3804 ahc->msg_type = MSG_TYPE_TARGET_MSGIN;
3805 }
3806 #endif
3807 /**************************** Initialization **********************************/
3808 /*
3809 * Allocate a controller structure for a new device
3810 * and perform initial initializion.
3811 */
3812 struct ahc_softc *
3813 ahc_alloc(void *platform_arg, char *name)
3814 {
3815 struct ahc_softc *ahc;
3816 int i;
3817
3818 #ifndef __FreeBSD__
3819 ahc = malloc(sizeof(*ahc), M_DEVBUF, M_NOWAIT);
3820 if (!ahc) {
3821 printf("aic7xxx: cannot malloc softc!\n");
3822 free(name, M_DEVBUF);
3823 return NULL;
3824 }
3825 #else
3826 ahc = device_get_softc((device_t)platform_arg);
3827 #endif
3828 memset(ahc, 0, sizeof(*ahc));
3829 ahc->seep_config = malloc(sizeof(*ahc->seep_config),
3830 M_DEVBUF, M_NOWAIT);
3831 if (ahc->seep_config == NULL) {
3832 #ifndef __FreeBSD__
3833 free(ahc, M_DEVBUF);
3834 #endif
3835 free(name, M_DEVBUF);
3836 return (NULL);
3837 }
3838 LIST_INIT(&ahc->pending_scbs);
3839 /* We don't know our unit number until the OSM sets it */
3840 ahc->name = name;
3841 ahc->unit = -1;
3842 ahc->description = NULL;
3843 ahc->channel = 'A';
3844 ahc->channel_b = 'B';
3845 ahc->chip = AHC_NONE;
3846 ahc->features = AHC_FENONE;
3847 ahc->bugs = AHC_BUGNONE;
3848 ahc->flags = AHC_FNONE;
3849 /*
3850 * Default to all error reporting enabled with the
3851 * sequencer operating at its fastest speed.
3852 * The bus attach code may modify this.
3853 */
3854 ahc->seqctl = FASTMODE;
3855
3856 for (i = 0; i < AHC_NUM_TARGETS; i++)
3857 TAILQ_INIT(&ahc->untagged_queues[i]);
3858 if (ahc_platform_alloc(ahc, platform_arg) != 0) {
3859 ahc_free(ahc);
3860 ahc = NULL;
3861 }
3862 return (ahc);
3863 }
3864
3865 int
3866 ahc_softc_init(struct ahc_softc *ahc)
3867 {
3868
3869 /* The IRQMS bit is only valid on VL and EISA chips */
3870 if ((ahc->chip & AHC_PCI) == 0)
3871 ahc->unpause = ahc_inb(ahc, HCNTRL) & IRQMS;
3872 else
3873 ahc->unpause = 0;
3874 ahc->pause = ahc->unpause | PAUSE;
3875 /* XXX The shared scb data stuff should be deprecated */
3876 if (ahc->scb_data == NULL) {
3877 ahc->scb_data = malloc(sizeof(*ahc->scb_data),
3878 M_DEVBUF, M_NOWAIT);
3879 if (ahc->scb_data == NULL)
3880 return (ENOMEM);
3881 memset(ahc->scb_data, 0, sizeof(*ahc->scb_data));
3882 }
3883
3884 return (0);
3885 }
3886
3887 void
3888 ahc_set_unit(struct ahc_softc *ahc, int unit)
3889 {
3890 ahc->unit = unit;
3891 }
3892
3893 void
3894 ahc_set_name(struct ahc_softc *ahc, char *name)
3895 {
3896 if (ahc->name != NULL)
3897 free(ahc->name, M_DEVBUF);
3898 ahc->name = name;
3899 }
3900
3901 void
3902 ahc_free(struct ahc_softc *ahc)
3903 {
3904 int i;
3905
3906 switch (ahc->init_level) {
3907 default:
3908 case 5:
3909 ahc_shutdown(ahc);
3910 /* FALLTHROUGH */
3911 case 4:
3912 ahc_dmamap_unload(ahc, ahc->shared_data_dmat,
3913 ahc->shared_data_dmamap);
3914 /* FALLTHROUGH */
3915 case 3:
3916 ahc_dmamem_free(ahc, ahc->shared_data_dmat, ahc->qoutfifo,
3917 ahc->shared_data_dmamap);
3918 ahc_dmamap_destroy(ahc, ahc->shared_data_dmat,
3919 ahc->shared_data_dmamap);
3920 /* FALLTHROUGH */
3921 case 2:
3922 ahc_dma_tag_destroy(ahc, ahc->shared_data_dmat);
3923 case 1:
3924 #ifndef __linux__
3925 ahc_dma_tag_destroy(ahc, ahc->buffer_dmat);
3926 #endif
3927 break;
3928 case 0:
3929 break;
3930 }
3931
3932 #ifndef __linux__
3933 ahc_dma_tag_destroy(ahc, ahc->parent_dmat);
3934 #endif
3935 ahc_platform_free(ahc);
3936 ahc_fini_scbdata(ahc);
3937 for (i = 0; i < AHC_NUM_TARGETS; i++) {
3938 struct ahc_tmode_tstate *tstate;
3939
3940 tstate = ahc->enabled_targets[i];
3941 if (tstate != NULL) {
3942 #ifdef AHC_TARGET_MODE
3943 int j;
3944
3945 for (j = 0; j < AHC_NUM_LUNS; j++) {
3946 struct ahc_tmode_lstate *lstate;
3947
3948 lstate = tstate->enabled_luns[j];
3949 if (lstate != NULL) {
3950 xpt_free_path(lstate->path);
3951 free(lstate, M_DEVBUF);
3952 }
3953 }
3954 #endif
3955 free(tstate, M_DEVBUF);
3956 }
3957 }
3958 #ifdef AHC_TARGET_MODE
3959 if (ahc->black_hole != NULL) {
3960 xpt_free_path(ahc->black_hole->path);
3961 free(ahc->black_hole, M_DEVBUF);
3962 }
3963 #endif
3964 if (ahc->name != NULL)
3965 free(ahc->name, M_DEVBUF);
3966 if (ahc->seep_config != NULL)
3967 free(ahc->seep_config, M_DEVBUF);
3968 #ifndef __FreeBSD__
3969 free(ahc, M_DEVBUF);
3970 #endif
3971 return;
3972 }
3973
3974 void
3975 ahc_shutdown(void *arg)
3976 {
3977 struct ahc_softc *ahc;
3978 int i;
3979
3980 ahc = (struct ahc_softc *)arg;
3981
3982 /* This will reset most registers to 0, but not all */
3983 ahc_reset(ahc, /*reinit*/FALSE);
3984 ahc_outb(ahc, SCSISEQ, 0);
3985 ahc_outb(ahc, SXFRCTL0, 0);
3986 ahc_outb(ahc, DSPCISTATUS, 0);
3987
3988 for (i = TARG_SCSIRATE; i < SCSICONF; i++)
3989 ahc_outb(ahc, i, 0);
3990 }
3991
3992 /*
3993 * Reset the controller and record some information about it
3994 * that is only available just after a reset. If "reinit" is
3995 * non-zero, this reset occured after initial configuration
3996 * and the caller requests that the chip be fully reinitialized
3997 * to a runable state. Chip interrupts are *not* enabled after
3998 * a reinitialization. The caller must enable interrupts via
3999 * ahc_intr_enable().
4000 */
4001 int
4002 ahc_reset(struct ahc_softc *ahc, int reinit)
4003 {
4004 u_int sblkctl;
4005 u_int sxfrctl1_a, sxfrctl1_b;
4006 int error;
4007 int wait;
4008
4009 /*
4010 * Preserve the value of the SXFRCTL1 register for all channels.
4011 * It contains settings that affect termination and we don't want
4012 * to disturb the integrity of the bus.
4013 */
4014 ahc_pause(ahc);
4015 sxfrctl1_b = 0;
4016 if ((ahc->chip & AHC_CHIPID_MASK) == AHC_AIC7770) {
4017 u_int sblkctl;
4018
4019 /*
4020 * Save channel B's settings in case this chip
4021 * is setup for TWIN channel operation.
4022 */
4023 sblkctl = ahc_inb(ahc, SBLKCTL);
4024 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB);
4025 sxfrctl1_b = ahc_inb(ahc, SXFRCTL1);
4026 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB);
4027 }
4028 sxfrctl1_a = ahc_inb(ahc, SXFRCTL1);
4029
4030 ahc_outb(ahc, HCNTRL, CHIPRST | ahc->pause);
4031
4032 /*
4033 * Ensure that the reset has finished. We delay 1000us
4034 * prior to reading the register to make sure the chip
4035 * has sufficiently completed its reset to handle register
4036 * accesses.
4037 */
4038 wait = 1000;
4039 do {
4040 ahc_delay(1000);
4041 } while (--wait && !(ahc_inb(ahc, HCNTRL) & CHIPRSTACK));
4042
4043 if (wait == 0) {
4044 printf("%s: WARNING - Failed chip reset! "
4045 "Trying to initialize anyway.\n", ahc_name(ahc));
4046 }
4047 ahc_outb(ahc, HCNTRL, ahc->pause);
4048
4049 /* Determine channel configuration */
4050 sblkctl = ahc_inb(ahc, SBLKCTL) & (SELBUSB|SELWIDE);
4051 /* No Twin Channel PCI cards */
4052 if ((ahc->chip & AHC_PCI) != 0)
4053 sblkctl &= ~SELBUSB;
4054 switch (sblkctl) {
4055 case 0:
4056 /* Single Narrow Channel */
4057 break;
4058 case 2:
4059 /* Wide Channel */
4060 ahc->features |= AHC_WIDE;
4061 break;
4062 case 8:
4063 /* Twin Channel */
4064 ahc->features |= AHC_TWIN;
4065 break;
4066 default:
4067 printf(" Unsupported adapter type. Ignoring\n");
4068 return(-1);
4069 }
4070
4071 /*
4072 * Reload sxfrctl1.
4073 *
4074 * We must always initialize STPWEN to 1 before we
4075 * restore the saved values. STPWEN is initialized
4076 * to a tri-state condition which can only be cleared
4077 * by turning it on.
4078 */
4079 if ((ahc->features & AHC_TWIN) != 0) {
4080 u_int sblkctl;
4081
4082 sblkctl = ahc_inb(ahc, SBLKCTL);
4083 ahc_outb(ahc, SBLKCTL, sblkctl | SELBUSB);
4084 ahc_outb(ahc, SXFRCTL1, sxfrctl1_b);
4085 ahc_outb(ahc, SBLKCTL, sblkctl & ~SELBUSB);
4086 }
4087 ahc_outb(ahc, SXFRCTL1, sxfrctl1_a);
4088
4089 error = 0;
4090 if (reinit != 0)
4091 /*
4092 * If a recovery action has forced a chip reset,
4093 * re-initialize the chip to our liking.
4094 */
4095 error = ahc->bus_chip_init(ahc);
4096 #ifdef AHC_DUMP_SEQ
4097 else
4098 ahc_dumpseq(ahc);
4099 #endif
4100
4101 return (error);
4102 }
4103
4104 /*
4105 * Determine the number of SCBs available on the controller
4106 */
4107 int
4108 ahc_probe_scbs(struct ahc_softc *ahc) {
4109 int i;
4110
4111 for (i = 0; i < AHC_SCB_MAX; i++) {
4112
4113 ahc_outb(ahc, SCBPTR, i);
4114 ahc_outb(ahc, SCB_BASE, i);
4115 if (ahc_inb(ahc, SCB_BASE) != i)
4116 break;
4117 ahc_outb(ahc, SCBPTR, 0);
4118 if (ahc_inb(ahc, SCB_BASE) != 0)
4119 break;
4120 }
4121 return (i);
4122 }
4123
4124 static void
4125 ahc_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
4126 {
4127 dma_addr_t *baddr;
4128
4129 baddr = (dma_addr_t *)arg;
4130 *baddr = segs->ds_addr;
4131 }
4132
4133 static void
4134 ahc_build_free_scb_list(struct ahc_softc *ahc)
4135 {
4136 int scbsize;
4137 int i;
4138
4139 scbsize = 32;
4140 if ((ahc->flags & AHC_LSCBS_ENABLED) != 0)
4141 scbsize = 64;
4142
4143 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
4144 int j;
4145
4146 ahc_outb(ahc, SCBPTR, i);
4147
4148 /*
4149 * Touch all SCB bytes to avoid parity errors
4150 * should one of our debugging routines read
4151 * an otherwise uninitiatlized byte.
4152 */
4153 for (j = 0; j < scbsize; j++)
4154 ahc_outb(ahc, SCB_BASE+j, 0xFF);
4155
4156 /* Clear the control byte. */
4157 ahc_outb(ahc, SCB_CONTROL, 0);
4158
4159 /* Set the next pointer */
4160 if ((ahc->flags & AHC_PAGESCBS) != 0)
4161 ahc_outb(ahc, SCB_NEXT, i+1);
4162 else
4163 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL);
4164
4165 /* Make the tag number, SCSIID, and lun invalid */
4166 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL);
4167 ahc_outb(ahc, SCB_SCSIID, 0xFF);
4168 ahc_outb(ahc, SCB_LUN, 0xFF);
4169 }
4170
4171 if ((ahc->flags & AHC_PAGESCBS) != 0) {
4172 /* SCB 0 heads the free list. */
4173 ahc_outb(ahc, FREE_SCBH, 0);
4174 } else {
4175 /* No free list. */
4176 ahc_outb(ahc, FREE_SCBH, SCB_LIST_NULL);
4177 }
4178
4179 /* Make sure that the last SCB terminates the free list */
4180 ahc_outb(ahc, SCBPTR, i-1);
4181 ahc_outb(ahc, SCB_NEXT, SCB_LIST_NULL);
4182 }
4183
4184 static int
4185 ahc_init_scbdata(struct ahc_softc *ahc)
4186 {
4187 struct scb_data *scb_data;
4188
4189 scb_data = ahc->scb_data;
4190 SLIST_INIT(&scb_data->free_scbs);
4191 SLIST_INIT(&scb_data->sg_maps);
4192
4193 /* Allocate SCB resources */
4194 scb_data->scbarray =
4195 (struct scb *)malloc(sizeof(struct scb) * AHC_SCB_MAX_ALLOC,
4196 M_DEVBUF, M_NOWAIT);
4197 if (scb_data->scbarray == NULL)
4198 return (ENOMEM);
4199 memset(scb_data->scbarray, 0, sizeof(struct scb) * AHC_SCB_MAX_ALLOC);
4200
4201 /* Determine the number of hardware SCBs and initialize them */
4202
4203 scb_data->maxhscbs = ahc_probe_scbs(ahc);
4204 if (ahc->scb_data->maxhscbs == 0) {
4205 printf("%s: No SCB space found\n", ahc_name(ahc));
4206 return (ENXIO);
4207 }
4208
4209 /*
4210 * Create our DMA tags. These tags define the kinds of device
4211 * accessible memory allocations and memory mappings we will
4212 * need to perform during normal operation.
4213 *
4214 * Unless we need to further restrict the allocation, we rely
4215 * on the restrictions of the parent dmat, hence the common
4216 * use of MAXADDR and MAXSIZE.
4217 */
4218
4219 /* DMA tag for our hardware scb structures */
4220 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4221 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4222 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4223 /*highaddr*/BUS_SPACE_MAXADDR,
4224 /*filter*/NULL, /*filterarg*/NULL,
4225 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb),
4226 /*nsegments*/1,
4227 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4228 /*flags*/0, &scb_data->hscb_dmat) != 0) {
4229 goto error_exit;
4230 }
4231
4232 scb_data->init_level++;
4233
4234 /* Allocation for our hscbs */
4235 if (ahc_dmamem_alloc(ahc, scb_data->hscb_dmat,
4236 (void **)&scb_data->hscbs,
4237 BUS_DMA_NOWAIT, &scb_data->hscb_dmamap) != 0) {
4238 goto error_exit;
4239 }
4240
4241 scb_data->init_level++;
4242
4243 /* And permanently map them */
4244 ahc_dmamap_load(ahc, scb_data->hscb_dmat, scb_data->hscb_dmamap,
4245 scb_data->hscbs,
4246 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb),
4247 ahc_dmamap_cb, &scb_data->hscb_busaddr, /*flags*/0);
4248
4249 scb_data->init_level++;
4250
4251 /* DMA tag for our sense buffers */
4252 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4253 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4254 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4255 /*highaddr*/BUS_SPACE_MAXADDR,
4256 /*filter*/NULL, /*filterarg*/NULL,
4257 AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data),
4258 /*nsegments*/1,
4259 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4260 /*flags*/0, &scb_data->sense_dmat) != 0) {
4261 goto error_exit;
4262 }
4263
4264 scb_data->init_level++;
4265
4266 /* Allocate them */
4267 if (ahc_dmamem_alloc(ahc, scb_data->sense_dmat,
4268 (void **)&scb_data->sense,
4269 BUS_DMA_NOWAIT, &scb_data->sense_dmamap) != 0) {
4270 goto error_exit;
4271 }
4272
4273 scb_data->init_level++;
4274
4275 /* And permanently map them */
4276 ahc_dmamap_load(ahc, scb_data->sense_dmat, scb_data->sense_dmamap,
4277 scb_data->sense,
4278 AHC_SCB_MAX_ALLOC * sizeof(struct scsi_sense_data),
4279 ahc_dmamap_cb, &scb_data->sense_busaddr, /*flags*/0);
4280
4281 scb_data->init_level++;
4282
4283 /* DMA tag for our S/G structures. We allocate in page sized chunks */
4284 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/8,
4285 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4286 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4287 /*highaddr*/BUS_SPACE_MAXADDR,
4288 /*filter*/NULL, /*filterarg*/NULL,
4289 PAGE_SIZE, /*nsegments*/1,
4290 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4291 /*flags*/0, &scb_data->sg_dmat) != 0) {
4292 goto error_exit;
4293 }
4294
4295 scb_data->init_level++;
4296
4297 /* Perform initial CCB allocation */
4298 memset(scb_data->hscbs, 0,
4299 AHC_SCB_MAX_ALLOC * sizeof(struct hardware_scb));
4300 ahc_alloc_scbs(ahc);
4301
4302 if (scb_data->numscbs == 0) {
4303 printf("%s: ahc_init_scbdata - "
4304 "Unable to allocate initial scbs\n",
4305 ahc_name(ahc));
4306 goto error_exit;
4307 }
4308
4309 /*
4310 * Reserve the next queued SCB.
4311 */
4312 ahc->next_queued_scb = ahc_get_scb(ahc);
4313
4314 /*
4315 * Note that we were successfull
4316 */
4317 return (0);
4318
4319 error_exit:
4320
4321 return (ENOMEM);
4322 }
4323
4324 static void
4325 ahc_fini_scbdata(struct ahc_softc *ahc)
4326 {
4327 struct scb_data *scb_data;
4328
4329 scb_data = ahc->scb_data;
4330 if (scb_data == NULL)
4331 return;
4332
4333 switch (scb_data->init_level) {
4334 default:
4335 case 7:
4336 {
4337 struct sg_map_node *sg_map;
4338
4339 while ((sg_map = SLIST_FIRST(&scb_data->sg_maps))!= NULL) {
4340 SLIST_REMOVE_HEAD(&scb_data->sg_maps, links);
4341 ahc_dmamap_unload(ahc, scb_data->sg_dmat,
4342 sg_map->sg_dmamap);
4343 ahc_dmamem_free(ahc, scb_data->sg_dmat,
4344 sg_map->sg_vaddr,
4345 sg_map->sg_dmamap);
4346 free(sg_map, M_DEVBUF);
4347 }
4348 ahc_dma_tag_destroy(ahc, scb_data->sg_dmat);
4349 }
4350 case 6:
4351 ahc_dmamap_unload(ahc, scb_data->sense_dmat,
4352 scb_data->sense_dmamap);
4353 case 5:
4354 ahc_dmamem_free(ahc, scb_data->sense_dmat, scb_data->sense,
4355 scb_data->sense_dmamap);
4356 ahc_dmamap_destroy(ahc, scb_data->sense_dmat,
4357 scb_data->sense_dmamap);
4358 case 4:
4359 ahc_dma_tag_destroy(ahc, scb_data->sense_dmat);
4360 case 3:
4361 ahc_dmamap_unload(ahc, scb_data->hscb_dmat,
4362 scb_data->hscb_dmamap);
4363 case 2:
4364 ahc_dmamem_free(ahc, scb_data->hscb_dmat, scb_data->hscbs,
4365 scb_data->hscb_dmamap);
4366 ahc_dmamap_destroy(ahc, scb_data->hscb_dmat,
4367 scb_data->hscb_dmamap);
4368 case 1:
4369 ahc_dma_tag_destroy(ahc, scb_data->hscb_dmat);
4370 break;
4371 case 0:
4372 break;
4373 }
4374 if (scb_data->scbarray != NULL)
4375 free(scb_data->scbarray, M_DEVBUF);
4376 }
4377
4378 void
4379 ahc_alloc_scbs(struct ahc_softc *ahc)
4380 {
4381 struct scb_data *scb_data;
4382 struct scb *next_scb;
4383 struct sg_map_node *sg_map;
4384 dma_addr_t physaddr;
4385 struct ahc_dma_seg *segs;
4386 int newcount;
4387 int i;
4388
4389 scb_data = ahc->scb_data;
4390 if (scb_data->numscbs >= AHC_SCB_MAX_ALLOC)
4391 /* Can't allocate any more */
4392 return;
4393
4394 next_scb = &scb_data->scbarray[scb_data->numscbs];
4395
4396 sg_map = malloc(sizeof(*sg_map), M_DEVBUF, M_NOWAIT);
4397
4398 if (sg_map == NULL)
4399 return;
4400
4401 /* Allocate S/G space for the next batch of SCBS */
4402 if (ahc_dmamem_alloc(ahc, scb_data->sg_dmat,
4403 (void **)&sg_map->sg_vaddr,
4404 BUS_DMA_NOWAIT, &sg_map->sg_dmamap) != 0) {
4405 free(sg_map, M_DEVBUF);
4406 return;
4407 }
4408
4409 SLIST_INSERT_HEAD(&scb_data->sg_maps, sg_map, links);
4410
4411 ahc_dmamap_load(ahc, scb_data->sg_dmat, sg_map->sg_dmamap,
4412 sg_map->sg_vaddr, PAGE_SIZE, ahc_dmamap_cb,
4413 &sg_map->sg_physaddr, /*flags*/0);
4414
4415 segs = sg_map->sg_vaddr;
4416 physaddr = sg_map->sg_physaddr;
4417
4418 newcount = (PAGE_SIZE / (AHC_NSEG * sizeof(struct ahc_dma_seg)));
4419 newcount = MIN(newcount, (AHC_SCB_MAX_ALLOC - scb_data->numscbs));
4420 for (i = 0; i < newcount; i++) {
4421 struct scb_platform_data *pdata;
4422 #ifndef __linux__
4423 int error;
4424 #endif
4425 pdata = (struct scb_platform_data *)malloc(sizeof(*pdata),
4426 M_DEVBUF, M_NOWAIT);
4427 if (pdata == NULL)
4428 break;
4429 next_scb->platform_data = pdata;
4430 next_scb->sg_map = sg_map;
4431 next_scb->sg_list = segs;
4432 /*
4433 * The sequencer always starts with the second entry.
4434 * The first entry is embedded in the scb.
4435 */
4436 next_scb->sg_list_phys = physaddr + sizeof(struct ahc_dma_seg);
4437 next_scb->ahc_softc = ahc;
4438 next_scb->flags = SCB_FREE;
4439 #ifndef __linux__
4440 error = ahc_dmamap_create(ahc, ahc->buffer_dmat, /*flags*/0,
4441 &next_scb->dmamap);
4442 if (error != 0)
4443 break;
4444 #endif
4445 next_scb->hscb = &scb_data->hscbs[scb_data->numscbs];
4446 next_scb->hscb->tag = ahc->scb_data->numscbs;
4447 SLIST_INSERT_HEAD(&ahc->scb_data->free_scbs,
4448 next_scb, links.sle);
4449 segs += AHC_NSEG;
4450 physaddr += (AHC_NSEG * sizeof(struct ahc_dma_seg));
4451 next_scb++;
4452 ahc->scb_data->numscbs++;
4453 }
4454 }
4455
4456 void
4457 ahc_controller_info(struct ahc_softc *ahc, char *buf)
4458 {
4459 int len;
4460
4461 len = sprintf(buf, "%s: ", ahc_chip_names[ahc->chip & AHC_CHIPID_MASK]);
4462 buf += len;
4463 if ((ahc->features & AHC_TWIN) != 0)
4464 len = sprintf(buf, "Twin Channel, A SCSI Id=%d, "
4465 "B SCSI Id=%d, primary %c, ",
4466 ahc->our_id, ahc->our_id_b,
4467 (ahc->flags & AHC_PRIMARY_CHANNEL) + 'A');
4468 else {
4469 const char *speed;
4470 const char *type;
4471
4472 speed = "";
4473 if ((ahc->features & AHC_ULTRA) != 0) {
4474 speed = "Ultra ";
4475 } else if ((ahc->features & AHC_DT) != 0) {
4476 speed = "Ultra160 ";
4477 } else if ((ahc->features & AHC_ULTRA2) != 0) {
4478 speed = "Ultra2 ";
4479 }
4480 if ((ahc->features & AHC_WIDE) != 0) {
4481 type = "Wide";
4482 } else {
4483 type = "Single";
4484 }
4485 len = sprintf(buf, "%s%s Channel %c, SCSI Id=%d, ",
4486 speed, type, ahc->channel, ahc->our_id);
4487 }
4488 buf += len;
4489
4490 if ((ahc->flags & AHC_PAGESCBS) != 0)
4491 sprintf(buf, "%d/%d SCBs",
4492 ahc->scb_data->maxhscbs, AHC_MAX_QUEUE);
4493 else
4494 sprintf(buf, "%d SCBs", ahc->scb_data->maxhscbs);
4495 }
4496
4497 int
4498 ahc_chip_init(struct ahc_softc *ahc)
4499 {
4500 int term;
4501 int error;
4502 u_int i;
4503 u_int scsi_conf;
4504 u_int scsiseq_template;
4505 uint32_t physaddr;
4506
4507 ahc_outb(ahc, SEQ_FLAGS, 0);
4508 ahc_outb(ahc, SEQ_FLAGS2, 0);
4509
4510 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1, for both channels*/
4511 if (ahc->features & AHC_TWIN) {
4512
4513 /*
4514 * Setup Channel B first.
4515 */
4516 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) | SELBUSB);
4517 term = (ahc->flags & AHC_TERM_ENB_B) != 0 ? STPWEN : 0;
4518 ahc_outb(ahc, SCSIID, ahc->our_id_b);
4519 scsi_conf = ahc_inb(ahc, SCSICONF + 1);
4520 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL))
4521 |term|ahc->seltime_b|ENSTIMER|ACTNEGEN);
4522 if ((ahc->features & AHC_ULTRA2) != 0)
4523 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR);
4524 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
4525 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN);
4526
4527 /* Select Channel A */
4528 ahc_outb(ahc, SBLKCTL, ahc_inb(ahc, SBLKCTL) & ~SELBUSB);
4529 }
4530 term = (ahc->flags & AHC_TERM_ENB_A) != 0 ? STPWEN : 0;
4531 if ((ahc->features & AHC_ULTRA2) != 0)
4532 ahc_outb(ahc, SCSIID_ULTRA2, ahc->our_id);
4533 else
4534 ahc_outb(ahc, SCSIID, ahc->our_id);
4535 scsi_conf = ahc_inb(ahc, SCSICONF);
4536 ahc_outb(ahc, SXFRCTL1, (scsi_conf & (ENSPCHK|STIMESEL))
4537 |term|ahc->seltime
4538 |ENSTIMER|ACTNEGEN);
4539 if ((ahc->features & AHC_ULTRA2) != 0)
4540 ahc_outb(ahc, SIMODE0, ahc_inb(ahc, SIMODE0)|ENIOERR);
4541 ahc_outb(ahc, SIMODE1, ENSELTIMO|ENSCSIRST|ENSCSIPERR);
4542 ahc_outb(ahc, SXFRCTL0, DFON|SPIOEN);
4543
4544 /* There are no untagged SCBs active yet. */
4545 for (i = 0; i < 16; i++) {
4546 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, 0));
4547 if ((ahc->flags & AHC_SCB_BTT) != 0) {
4548 int lun;
4549
4550 /*
4551 * The SCB based BTT allows an entry per
4552 * target and lun pair.
4553 */
4554 for (lun = 1; lun < AHC_NUM_LUNS; lun++)
4555 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, lun));
4556 }
4557 }
4558
4559 /* All of our queues are empty */
4560 for (i = 0; i < 256; i++)
4561 ahc->qoutfifo[i] = SCB_LIST_NULL;
4562 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_PREREAD);
4563
4564 for (i = 0; i < 256; i++)
4565 ahc->qinfifo[i] = SCB_LIST_NULL;
4566
4567 if ((ahc->features & AHC_MULTI_TID) != 0) {
4568 ahc_outb(ahc, TARGID, 0);
4569 ahc_outb(ahc, TARGID + 1, 0);
4570 }
4571
4572 /*
4573 * Tell the sequencer where it can find our arrays in memory.
4574 */
4575 physaddr = ahc->scb_data->hscb_busaddr;
4576 ahc_outb(ahc, HSCB_ADDR, physaddr & 0xFF);
4577 ahc_outb(ahc, HSCB_ADDR + 1, (physaddr >> 8) & 0xFF);
4578 ahc_outb(ahc, HSCB_ADDR + 2, (physaddr >> 16) & 0xFF);
4579 ahc_outb(ahc, HSCB_ADDR + 3, (physaddr >> 24) & 0xFF);
4580
4581 physaddr = ahc->shared_data_busaddr;
4582 ahc_outb(ahc, SHARED_DATA_ADDR, physaddr & 0xFF);
4583 ahc_outb(ahc, SHARED_DATA_ADDR + 1, (physaddr >> 8) & 0xFF);
4584 ahc_outb(ahc, SHARED_DATA_ADDR + 2, (physaddr >> 16) & 0xFF);
4585 ahc_outb(ahc, SHARED_DATA_ADDR + 3, (physaddr >> 24) & 0xFF);
4586
4587 /*
4588 * Initialize the group code to command length table.
4589 * This overrides the values in TARG_SCSIRATE, so only
4590 * setup the table after we have processed that information.
4591 */
4592 ahc_outb(ahc, CMDSIZE_TABLE, 5);
4593 ahc_outb(ahc, CMDSIZE_TABLE + 1, 9);
4594 ahc_outb(ahc, CMDSIZE_TABLE + 2, 9);
4595 ahc_outb(ahc, CMDSIZE_TABLE + 3, 0);
4596 ahc_outb(ahc, CMDSIZE_TABLE + 4, 15);
4597 ahc_outb(ahc, CMDSIZE_TABLE + 5, 11);
4598 ahc_outb(ahc, CMDSIZE_TABLE + 6, 0);
4599 ahc_outb(ahc, CMDSIZE_TABLE + 7, 0);
4600
4601 if ((ahc->features & AHC_HS_MAILBOX) != 0)
4602 ahc_outb(ahc, HS_MAILBOX, 0);
4603
4604 /* Tell the sequencer of our initial queue positions */
4605 if ((ahc->features & AHC_TARGETMODE) != 0) {
4606 ahc->tqinfifonext = 1;
4607 ahc_outb(ahc, KERNEL_TQINPOS, ahc->tqinfifonext - 1);
4608 ahc_outb(ahc, TQINPOS, ahc->tqinfifonext);
4609 }
4610 ahc->qinfifonext = 0;
4611 ahc->qoutfifonext = 0;
4612 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
4613 ahc_outb(ahc, QOFF_CTLSTA, SCB_QSIZE_256);
4614 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
4615 ahc_outb(ahc, SNSCB_QOFF, ahc->qinfifonext);
4616 ahc_outb(ahc, SDSCB_QOFF, 0);
4617 } else {
4618 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
4619 ahc_outb(ahc, QINPOS, ahc->qinfifonext);
4620 ahc_outb(ahc, QOUTPOS, ahc->qoutfifonext);
4621 }
4622
4623 /* We don't have any waiting selections */
4624 ahc_outb(ahc, WAITING_SCBH, SCB_LIST_NULL);
4625
4626 /* Our disconnection list is empty too */
4627 ahc_outb(ahc, DISCONNECTED_SCBH, SCB_LIST_NULL);
4628
4629 /* Message out buffer starts empty */
4630 ahc_outb(ahc, MSG_OUT, MSG_NOOP);
4631
4632 /*
4633 * Setup the allowed SCSI Sequences based on operational mode.
4634 * If we are a target, we'll enalbe select in operations once
4635 * we've had a lun enabled.
4636 */
4637 scsiseq_template = ENSELO|ENAUTOATNO|ENAUTOATNP;
4638 if ((ahc->flags & AHC_INITIATORROLE) != 0)
4639 scsiseq_template |= ENRSELI;
4640 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq_template);
4641
4642 /* Initialize our list of free SCBs. */
4643 ahc_build_free_scb_list(ahc);
4644
4645 /*
4646 * Tell the sequencer which SCB will be the next one it receives.
4647 */
4648 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag);
4649
4650 /*
4651 * Load the Sequencer program and Enable the adapter
4652 * in "fast" mode.
4653 */
4654 if (bootverbose)
4655 printf("%s: Downloading Sequencer Program...",
4656 ahc_name(ahc));
4657
4658 error = ahc_loadseq(ahc);
4659 if (error != 0)
4660 return (error);
4661
4662 if ((ahc->features & AHC_ULTRA2) != 0) {
4663 int wait;
4664
4665 /*
4666 * Wait for up to 500ms for our transceivers
4667 * to settle. If the adapter does not have
4668 * a cable attached, the transceivers may
4669 * never settle, so don't complain if we
4670 * fail here.
4671 */
4672 for (wait = 5000;
4673 (ahc_inb(ahc, SBLKCTL) & (ENAB40|ENAB20)) == 0 && wait;
4674 wait--)
4675 ahc_delay(100);
4676 }
4677 ahc_restart(ahc);
4678 return (0);
4679 }
4680
4681 /*
4682 * Start the board, ready for normal operation
4683 */
4684 int
4685 ahc_init(struct ahc_softc *ahc)
4686 {
4687 int max_targ;
4688 u_int i;
4689 u_int scsi_conf;
4690 u_int ultraenb;
4691 u_int discenable;
4692 u_int tagenable;
4693 size_t driver_data_size;
4694
4695 #ifdef AHC_DEBUG
4696 if ((ahc_debug & AHC_DEBUG_SEQUENCER) != 0)
4697 ahc->flags |= AHC_SEQUENCER_DEBUG;
4698 #endif
4699
4700 #ifdef AHC_PRINT_SRAM
4701 printf("Scratch Ram:");
4702 for (i = 0x20; i < 0x5f; i++) {
4703 if (((i % 8) == 0) && (i != 0)) {
4704 printf ("\n ");
4705 }
4706 printf (" 0x%x", ahc_inb(ahc, i));
4707 }
4708 if ((ahc->features & AHC_MORE_SRAM) != 0) {
4709 for (i = 0x70; i < 0x7f; i++) {
4710 if (((i % 8) == 0) && (i != 0)) {
4711 printf ("\n ");
4712 }
4713 printf (" 0x%x", ahc_inb(ahc, i));
4714 }
4715 }
4716 printf ("\n");
4717 /*
4718 * Reading uninitialized scratch ram may
4719 * generate parity errors.
4720 */
4721 ahc_outb(ahc, CLRINT, CLRPARERR);
4722 ahc_outb(ahc, CLRINT, CLRBRKADRINT);
4723 #endif
4724 max_targ = 15;
4725
4726 /*
4727 * Assume we have a board at this stage and it has been reset.
4728 */
4729 if ((ahc->flags & AHC_USEDEFAULTS) != 0)
4730 ahc->our_id = ahc->our_id_b = 7;
4731
4732 /*
4733 * Default to allowing initiator operations.
4734 */
4735 ahc->flags |= AHC_INITIATORROLE;
4736
4737 /*
4738 * Only allow target mode features if this unit has them enabled.
4739 */
4740 if ((AHC_TMODE_ENABLE & (0x1 << ahc->unit)) == 0)
4741 ahc->features &= ~AHC_TARGETMODE;
4742
4743 #ifndef __linux__
4744 /* DMA tag for mapping buffers into device visible space. */
4745 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4746 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4747 /*lowaddr*/ahc->flags & AHC_39BIT_ADDRESSING
4748 ? (dma_addr_t)0x7FFFFFFFFFULL
4749 : BUS_SPACE_MAXADDR_32BIT,
4750 /*highaddr*/BUS_SPACE_MAXADDR,
4751 /*filter*/NULL, /*filterarg*/NULL,
4752 /*maxsize*/(AHC_NSEG - 1) * PAGE_SIZE,
4753 /*nsegments*/AHC_NSEG,
4754 /*maxsegsz*/AHC_MAXTRANSFER_SIZE,
4755 /*flags*/BUS_DMA_ALLOCNOW,
4756 &ahc->buffer_dmat) != 0) {
4757 return (ENOMEM);
4758 }
4759 #endif
4760
4761 ahc->init_level++;
4762
4763 /*
4764 * DMA tag for our command fifos and other data in system memory
4765 * the card's sequencer must be able to access. For initiator
4766 * roles, we need to allocate space for the qinfifo and qoutfifo.
4767 * The qinfifo and qoutfifo are composed of 256 1 byte elements.
4768 * When providing for the target mode role, we must additionally
4769 * provide space for the incoming target command fifo and an extra
4770 * byte to deal with a dma bug in some chip versions.
4771 */
4772 driver_data_size = 2 * 256 * sizeof(uint8_t);
4773 if ((ahc->features & AHC_TARGETMODE) != 0)
4774 driver_data_size += AHC_TMODE_CMDS * sizeof(struct target_cmd)
4775 + /*DMA WideOdd Bug Buffer*/1;
4776 if (ahc_dma_tag_create(ahc, ahc->parent_dmat, /*alignment*/1,
4777 /*boundary*/BUS_SPACE_MAXADDR_32BIT + 1,
4778 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT,
4779 /*highaddr*/BUS_SPACE_MAXADDR,
4780 /*filter*/NULL, /*filterarg*/NULL,
4781 driver_data_size,
4782 /*nsegments*/1,
4783 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT,
4784 /*flags*/0, &ahc->shared_data_dmat) != 0) {
4785 return (ENOMEM);
4786 }
4787
4788 ahc->init_level++;
4789
4790 /* Allocation of driver data */
4791 if (ahc_dmamem_alloc(ahc, ahc->shared_data_dmat,
4792 (void **)&ahc->qoutfifo,
4793 BUS_DMA_NOWAIT, &ahc->shared_data_dmamap) != 0) {
4794 return (ENOMEM);
4795 }
4796
4797 ahc->init_level++;
4798
4799 /* And permanently map it in */
4800 ahc_dmamap_load(ahc, ahc->shared_data_dmat, ahc->shared_data_dmamap,
4801 ahc->qoutfifo, driver_data_size, ahc_dmamap_cb,
4802 &ahc->shared_data_busaddr, /*flags*/0);
4803
4804 if ((ahc->features & AHC_TARGETMODE) != 0) {
4805 ahc->targetcmds = (struct target_cmd *)ahc->qoutfifo;
4806 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[AHC_TMODE_CMDS];
4807 ahc->dma_bug_buf = ahc->shared_data_busaddr
4808 + driver_data_size - 1;
4809 /* All target command blocks start out invalid. */
4810 for (i = 0; i < AHC_TMODE_CMDS; i++)
4811 ahc->targetcmds[i].cmd_valid = 0;
4812 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_PREREAD);
4813 ahc->qoutfifo = (uint8_t *)&ahc->targetcmds[256];
4814 }
4815 ahc->qinfifo = &ahc->qoutfifo[256];
4816
4817 ahc->init_level++;
4818
4819 /* Allocate SCB data now that buffer_dmat is initialized */
4820 if (ahc->scb_data->maxhscbs == 0)
4821 if (ahc_init_scbdata(ahc) != 0)
4822 return (ENOMEM);
4823
4824 /*
4825 * Allocate a tstate to house information for our
4826 * initiator presence on the bus as well as the user
4827 * data for any target mode initiator.
4828 */
4829 if (ahc_alloc_tstate(ahc, ahc->our_id, 'A') == NULL) {
4830 printf("%s: unable to allocate ahc_tmode_tstate. "
4831 "Failing attach\n", ahc_name(ahc));
4832 return (ENOMEM);
4833 }
4834
4835 if ((ahc->features & AHC_TWIN) != 0) {
4836 if (ahc_alloc_tstate(ahc, ahc->our_id_b, 'B') == NULL) {
4837 printf("%s: unable to allocate ahc_tmode_tstate. "
4838 "Failing attach\n", ahc_name(ahc));
4839 return (ENOMEM);
4840 }
4841 }
4842
4843 if (ahc->scb_data->maxhscbs < AHC_SCB_MAX_ALLOC) {
4844 ahc->flags |= AHC_PAGESCBS;
4845 } else {
4846 ahc->flags &= ~AHC_PAGESCBS;
4847 }
4848
4849 #ifdef AHC_DEBUG
4850 if (ahc_debug & AHC_SHOW_MISC) {
4851 printf("%s: hardware scb %u bytes; kernel scb %u bytes; "
4852 "ahc_dma %u bytes\n",
4853 ahc_name(ahc),
4854 (u_int)sizeof(struct hardware_scb),
4855 (u_int)sizeof(struct scb),
4856 (u_int)sizeof(struct ahc_dma_seg));
4857 }
4858 #endif /* AHC_DEBUG */
4859
4860 /*
4861 * Look at the information that board initialization or
4862 * the board bios has left us.
4863 */
4864 if (ahc->features & AHC_TWIN) {
4865 scsi_conf = ahc_inb(ahc, SCSICONF + 1);
4866 if ((scsi_conf & RESET_SCSI) != 0
4867 && (ahc->flags & AHC_INITIATORROLE) != 0)
4868 ahc->flags |= AHC_RESET_BUS_B;
4869 }
4870
4871 scsi_conf = ahc_inb(ahc, SCSICONF);
4872 if ((scsi_conf & RESET_SCSI) != 0
4873 && (ahc->flags & AHC_INITIATORROLE) != 0)
4874 ahc->flags |= AHC_RESET_BUS_A;
4875
4876 ultraenb = 0;
4877 tagenable = ALL_TARGETS_MASK;
4878
4879 /* Grab the disconnection disable table and invert it for our needs */
4880 if ((ahc->flags & AHC_USEDEFAULTS) != 0) {
4881 printf("%s: Host Adapter Bios disabled. Using default SCSI "
4882 "device parameters\n", ahc_name(ahc));
4883 ahc->flags |= AHC_EXTENDED_TRANS_A|AHC_EXTENDED_TRANS_B|
4884 AHC_TERM_ENB_A|AHC_TERM_ENB_B;
4885 discenable = ALL_TARGETS_MASK;
4886 if ((ahc->features & AHC_ULTRA) != 0)
4887 ultraenb = ALL_TARGETS_MASK;
4888 } else {
4889 discenable = ~((ahc_inb(ahc, DISC_DSB + 1) << 8)
4890 | ahc_inb(ahc, DISC_DSB));
4891 if ((ahc->features & (AHC_ULTRA|AHC_ULTRA2)) != 0)
4892 ultraenb = (ahc_inb(ahc, ULTRA_ENB + 1) << 8)
4893 | ahc_inb(ahc, ULTRA_ENB);
4894 }
4895
4896 if ((ahc->features & (AHC_WIDE|AHC_TWIN)) == 0)
4897 max_targ = 7;
4898
4899 for (i = 0; i <= max_targ; i++) {
4900 struct ahc_initiator_tinfo *tinfo;
4901 struct ahc_tmode_tstate *tstate;
4902 u_int our_id;
4903 u_int target_id;
4904 char channel;
4905
4906 channel = 'A';
4907 our_id = ahc->our_id;
4908 target_id = i;
4909 if (i > 7 && (ahc->features & AHC_TWIN) != 0) {
4910 channel = 'B';
4911 our_id = ahc->our_id_b;
4912 target_id = i % 8;
4913 }
4914 tinfo = ahc_fetch_transinfo(ahc, channel, our_id,
4915 target_id, &tstate);
4916 /* Default to async narrow across the board */
4917 memset(tinfo, 0, sizeof(*tinfo));
4918 if (ahc->flags & AHC_USEDEFAULTS) {
4919 if ((ahc->features & AHC_WIDE) != 0)
4920 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
4921
4922 /*
4923 * These will be truncated when we determine the
4924 * connection type we have with the target.
4925 */
4926 tinfo->user.period = ahc_syncrates->period;
4927 tinfo->user.offset = MAX_OFFSET;
4928 } else {
4929 u_int scsirate;
4930 uint16_t mask;
4931
4932 /* Take the settings leftover in scratch RAM. */
4933 scsirate = ahc_inb(ahc, TARG_SCSIRATE + i);
4934 mask = (0x01 << i);
4935 if ((ahc->features & AHC_ULTRA2) != 0) {
4936 u_int offset;
4937 u_int maxsync;
4938
4939 if ((scsirate & SOFS) == 0x0F) {
4940 /*
4941 * Haven't negotiated yet,
4942 * so the format is different.
4943 */
4944 scsirate = (scsirate & SXFR) >> 4
4945 | (ultraenb & mask)
4946 ? 0x08 : 0x0
4947 | (scsirate & WIDEXFER);
4948 offset = MAX_OFFSET_ULTRA2;
4949 } else
4950 offset = ahc_inb(ahc, TARG_OFFSET + i);
4951 if ((scsirate & ~WIDEXFER) == 0 && offset != 0)
4952 /* Set to the lowest sync rate, 5MHz */
4953 scsirate |= 0x1c;
4954 maxsync = AHC_SYNCRATE_ULTRA2;
4955 if ((ahc->features & AHC_DT) != 0)
4956 maxsync = AHC_SYNCRATE_DT;
4957 tinfo->user.period =
4958 ahc_find_period(ahc, scsirate, maxsync);
4959 if (offset == 0)
4960 tinfo->user.period = 0;
4961 else
4962 tinfo->user.offset = MAX_OFFSET;
4963 if ((scsirate & SXFR_ULTRA2) <= 8/*10MHz*/
4964 && (ahc->features & AHC_DT) != 0)
4965 tinfo->user.ppr_options =
4966 MSG_EXT_PPR_DT_REQ;
4967 } else if ((scsirate & SOFS) != 0) {
4968 if ((scsirate & SXFR) == 0x40
4969 && (ultraenb & mask) != 0) {
4970 /* Treat 10MHz as a non-ultra speed */
4971 scsirate &= ~SXFR;
4972 ultraenb &= ~mask;
4973 }
4974 tinfo->user.period =
4975 ahc_find_period(ahc, scsirate,
4976 (ultraenb & mask)
4977 ? AHC_SYNCRATE_ULTRA
4978 : AHC_SYNCRATE_FAST);
4979 if (tinfo->user.period != 0)
4980 tinfo->user.offset = MAX_OFFSET;
4981 }
4982 if (tinfo->user.period == 0)
4983 tinfo->user.offset = 0;
4984 if ((scsirate & WIDEXFER) != 0
4985 && (ahc->features & AHC_WIDE) != 0)
4986 tinfo->user.width = MSG_EXT_WDTR_BUS_16_BIT;
4987 tinfo->user.protocol_version = 4;
4988 if ((ahc->features & AHC_DT) != 0)
4989 tinfo->user.transport_version = 3;
4990 else
4991 tinfo->user.transport_version = 2;
4992 tinfo->goal.protocol_version = 2;
4993 tinfo->goal.transport_version = 2;
4994 tinfo->curr.protocol_version = 2;
4995 tinfo->curr.transport_version = 2;
4996 }
4997 tstate->ultraenb = 0;
4998 }
4999 ahc->user_discenable = discenable;
5000 ahc->user_tagenable = tagenable;
5001
5002 return (ahc->bus_chip_init(ahc));
5003 }
5004
5005 void
5006 ahc_intr_enable(struct ahc_softc *ahc, int enable)
5007 {
5008 u_int hcntrl;
5009
5010 hcntrl = ahc_inb(ahc, HCNTRL);
5011 hcntrl &= ~INTEN;
5012 ahc->pause &= ~INTEN;
5013 ahc->unpause &= ~INTEN;
5014 if (enable) {
5015 hcntrl |= INTEN;
5016 ahc->pause |= INTEN;
5017 ahc->unpause |= INTEN;
5018 }
5019 ahc_outb(ahc, HCNTRL, hcntrl);
5020 }
5021
5022 /*
5023 * Ensure that the card is paused in a location
5024 * outside of all critical sections and that all
5025 * pending work is completed prior to returning.
5026 * This routine should only be called from outside
5027 * an interrupt context.
5028 */
5029 void
5030 ahc_pause_and_flushwork(struct ahc_softc *ahc)
5031 {
5032 int intstat;
5033 int maxloops;
5034 int paused;
5035
5036 maxloops = 1000;
5037 ahc->flags |= AHC_ALL_INTERRUPTS;
5038 paused = FALSE;
5039 do {
5040 if (paused) {
5041 ahc_unpause(ahc);
5042 /*
5043 * Give the sequencer some time to service
5044 * any active selections.
5045 */
5046 ahc_delay(500);
5047 }
5048 ahc_intr(ahc);
5049 ahc_pause(ahc);
5050 paused = TRUE;
5051 ahc_outb(ahc, SCSISEQ, ahc_inb(ahc, SCSISEQ) & ~ENSELO);
5052 intstat = ahc_inb(ahc, INTSTAT);
5053 if ((intstat & INT_PEND) == 0) {
5054 ahc_clear_critical_section(ahc);
5055 intstat = ahc_inb(ahc, INTSTAT);
5056 }
5057 } while (--maxloops
5058 && (intstat != 0xFF || (ahc->features & AHC_REMOVABLE) == 0)
5059 && ((intstat & INT_PEND) != 0
5060 || (ahc_inb(ahc, SSTAT0) & (SELDO|SELINGO)) != 0));
5061 if (maxloops == 0) {
5062 printf("Infinite interrupt loop, INTSTAT = %x",
5063 ahc_inb(ahc, INTSTAT));
5064 }
5065 ahc_platform_flushwork(ahc);
5066 ahc->flags &= ~AHC_ALL_INTERRUPTS;
5067 }
5068
5069 int
5070 ahc_suspend(struct ahc_softc *ahc)
5071 {
5072
5073 ahc_pause_and_flushwork(ahc);
5074
5075 if (LIST_FIRST(&ahc->pending_scbs) != NULL) {
5076 ahc_unpause(ahc);
5077 return (EBUSY);
5078 }
5079
5080 #ifdef AHC_TARGET_MODE
5081 /*
5082 * XXX What about ATIOs that have not yet been serviced?
5083 * Perhaps we should just refuse to be suspended if we
5084 * are acting in a target role.
5085 */
5086 if (ahc->pending_device != NULL) {
5087 ahc_unpause(ahc);
5088 return (EBUSY);
5089 }
5090 #endif
5091 ahc_shutdown(ahc);
5092 return (0);
5093 }
5094
5095 int
5096 ahc_resume(struct ahc_softc *ahc)
5097 {
5098
5099 ahc_reset(ahc, /*reinit*/TRUE);
5100 ahc_intr_enable(ahc, TRUE);
5101 ahc_restart(ahc);
5102 return (0);
5103 }
5104
5105 /************************** Busy Target Table *********************************/
5106 /*
5107 * Return the untagged transaction id for a given target/channel lun.
5108 * Optionally, clear the entry.
5109 */
5110 u_int
5111 ahc_index_busy_tcl(struct ahc_softc *ahc, u_int tcl)
5112 {
5113 u_int scbid;
5114 u_int target_offset;
5115
5116 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5117 u_int saved_scbptr;
5118
5119 saved_scbptr = ahc_inb(ahc, SCBPTR);
5120 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5121 scbid = ahc_inb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl));
5122 ahc_outb(ahc, SCBPTR, saved_scbptr);
5123 } else {
5124 target_offset = TCL_TARGET_OFFSET(tcl);
5125 scbid = ahc_inb(ahc, BUSY_TARGETS + target_offset);
5126 }
5127
5128 return (scbid);
5129 }
5130
5131 void
5132 ahc_unbusy_tcl(struct ahc_softc *ahc, u_int tcl)
5133 {
5134 u_int target_offset;
5135
5136 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5137 u_int saved_scbptr;
5138
5139 saved_scbptr = ahc_inb(ahc, SCBPTR);
5140 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5141 ahc_outb(ahc, SCB_64_BTT+TCL_TARGET_OFFSET(tcl), SCB_LIST_NULL);
5142 ahc_outb(ahc, SCBPTR, saved_scbptr);
5143 } else {
5144 target_offset = TCL_TARGET_OFFSET(tcl);
5145 ahc_outb(ahc, BUSY_TARGETS + target_offset, SCB_LIST_NULL);
5146 }
5147 }
5148
5149 void
5150 ahc_busy_tcl(struct ahc_softc *ahc, u_int tcl, u_int scbid)
5151 {
5152 u_int target_offset;
5153
5154 if ((ahc->flags & AHC_SCB_BTT) != 0) {
5155 u_int saved_scbptr;
5156
5157 saved_scbptr = ahc_inb(ahc, SCBPTR);
5158 ahc_outb(ahc, SCBPTR, TCL_LUN(tcl));
5159 ahc_outb(ahc, SCB_64_BTT + TCL_TARGET_OFFSET(tcl), scbid);
5160 ahc_outb(ahc, SCBPTR, saved_scbptr);
5161 } else {
5162 target_offset = TCL_TARGET_OFFSET(tcl);
5163 ahc_outb(ahc, BUSY_TARGETS + target_offset, scbid);
5164 }
5165 }
5166
5167 /************************** SCB and SCB queue management **********************/
5168 int
5169 ahc_match_scb(struct ahc_softc *ahc, struct scb *scb, int target,
5170 char channel, int lun, u_int tag, role_t role)
5171 {
5172 int targ = SCB_GET_TARGET(ahc, scb);
5173 char chan = SCB_GET_CHANNEL(ahc, scb);
5174 int slun = SCB_GET_LUN(scb);
5175 int match;
5176
5177 match = ((chan == channel) || (channel == ALL_CHANNELS));
5178 if (match != 0)
5179 match = ((targ == target) || (target == CAM_TARGET_WILDCARD));
5180 if (match != 0)
5181 match = ((lun == slun) || (lun == CAM_LUN_WILDCARD));
5182 if (match != 0) {
5183 #ifdef AHC_TARGET_MODE
5184 int group;
5185
5186 group = XPT_FC_GROUP(scb->io_ctx->ccb_h.func_code);
5187 if (role == ROLE_INITIATOR) {
5188 match = (group != XPT_FC_GROUP_TMODE)
5189 && ((tag == scb->hscb->tag)
5190 || (tag == SCB_LIST_NULL));
5191 } else if (role == ROLE_TARGET) {
5192 match = (group == XPT_FC_GROUP_TMODE)
5193 && ((tag == scb->io_ctx->csio.tag_id)
5194 || (tag == SCB_LIST_NULL));
5195 }
5196 #else /* !AHC_TARGET_MODE */
5197 match = ((tag == scb->hscb->tag) || (tag == SCB_LIST_NULL));
5198 #endif /* AHC_TARGET_MODE */
5199 }
5200
5201 return match;
5202 }
5203
5204 void
5205 ahc_freeze_devq(struct ahc_softc *ahc, struct scb *scb)
5206 {
5207 int target;
5208 char channel;
5209 int lun;
5210
5211 target = SCB_GET_TARGET(ahc, scb);
5212 lun = SCB_GET_LUN(scb);
5213 channel = SCB_GET_CHANNEL(ahc, scb);
5214
5215 ahc_search_qinfifo(ahc, target, channel, lun,
5216 /*tag*/SCB_LIST_NULL, ROLE_UNKNOWN,
5217 CAM_REQUEUE_REQ, SEARCH_COMPLETE);
5218
5219 ahc_platform_freeze_devq(ahc, scb);
5220 }
5221
5222 void
5223 ahc_qinfifo_requeue_tail(struct ahc_softc *ahc, struct scb *scb)
5224 {
5225 struct scb *prev_scb;
5226
5227 prev_scb = NULL;
5228 if (ahc_qinfifo_count(ahc) != 0) {
5229 u_int prev_tag;
5230 uint8_t prev_pos;
5231
5232 prev_pos = ahc->qinfifonext - 1;
5233 prev_tag = ahc->qinfifo[prev_pos];
5234 prev_scb = ahc_lookup_scb(ahc, prev_tag);
5235 }
5236 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5237 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5238 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
5239 } else {
5240 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
5241 }
5242 }
5243
5244 static void
5245 ahc_qinfifo_requeue(struct ahc_softc *ahc, struct scb *prev_scb,
5246 struct scb *scb)
5247 {
5248 if (prev_scb == NULL) {
5249 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag);
5250 } else {
5251 prev_scb->hscb->next = scb->hscb->tag;
5252 ahc_sync_scb(ahc, prev_scb,
5253 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
5254 }
5255 ahc->qinfifo[ahc->qinfifonext++] = scb->hscb->tag;
5256 scb->hscb->next = ahc->next_queued_scb->hscb->tag;
5257 ahc_sync_scb(ahc, scb, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
5258 }
5259
5260 static int
5261 ahc_qinfifo_count(struct ahc_softc *ahc)
5262 {
5263 uint8_t qinpos;
5264 uint8_t diff;
5265
5266 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5267 qinpos = ahc_inb(ahc, SNSCB_QOFF);
5268 ahc_outb(ahc, SNSCB_QOFF, qinpos);
5269 } else
5270 qinpos = ahc_inb(ahc, QINPOS);
5271 diff = ahc->qinfifonext - qinpos;
5272 return (diff);
5273 }
5274
5275 int
5276 ahc_search_qinfifo(struct ahc_softc *ahc, int target, char channel,
5277 int lun, u_int tag, role_t role, uint32_t status,
5278 ahc_search_action action)
5279 {
5280 struct scb *scb;
5281 struct scb *prev_scb;
5282 uint8_t qinstart;
5283 uint8_t qinpos;
5284 uint8_t qintail;
5285 uint8_t next;
5286 uint8_t prev;
5287 uint8_t curscbptr;
5288 int found;
5289 int have_qregs;
5290
5291 qintail = ahc->qinfifonext;
5292 have_qregs = (ahc->features & AHC_QUEUE_REGS) != 0;
5293 if (have_qregs) {
5294 qinstart = ahc_inb(ahc, SNSCB_QOFF);
5295 ahc_outb(ahc, SNSCB_QOFF, qinstart);
5296 } else
5297 qinstart = ahc_inb(ahc, QINPOS);
5298 qinpos = qinstart;
5299 found = 0;
5300 prev_scb = NULL;
5301
5302 if (action == SEARCH_COMPLETE) {
5303 /*
5304 * Don't attempt to run any queued untagged transactions
5305 * until we are done with the abort process.
5306 */
5307 ahc_freeze_untagged_queues(ahc);
5308 }
5309
5310 /*
5311 * Start with an empty queue. Entries that are not chosen
5312 * for removal will be re-added to the queue as we go.
5313 */
5314 ahc->qinfifonext = qinpos;
5315 ahc_outb(ahc, NEXT_QUEUED_SCB, ahc->next_queued_scb->hscb->tag);
5316
5317 while (qinpos != qintail) {
5318 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinpos]);
5319 if (scb == NULL) {
5320 printf("qinpos = %d, SCB index = %d\n",
5321 qinpos, ahc->qinfifo[qinpos]);
5322 panic("Loop 1\n");
5323 }
5324
5325 if (ahc_match_scb(ahc, scb, target, channel, lun, tag, role)) {
5326 /*
5327 * We found an scb that needs to be acted on.
5328 */
5329 found++;
5330 switch (action) {
5331 case SEARCH_COMPLETE:
5332 {
5333 cam_status ostat;
5334 cam_status cstat;
5335
5336 ostat = ahc_get_transaction_status(scb);
5337 if (ostat == CAM_REQ_INPROG)
5338 ahc_set_transaction_status(scb, status);
5339 cstat = ahc_get_transaction_status(scb);
5340 if (cstat != CAM_REQ_CMP)
5341 ahc_freeze_scb(scb);
5342 if ((scb->flags & SCB_ACTIVE) == 0)
5343 printf("Inactive SCB in qinfifo\n");
5344 ahc_done(ahc, scb);
5345
5346 /* FALLTHROUGH */
5347 }
5348 case SEARCH_REMOVE:
5349 break;
5350 case SEARCH_COUNT:
5351 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5352 prev_scb = scb;
5353 break;
5354 }
5355 } else {
5356 ahc_qinfifo_requeue(ahc, prev_scb, scb);
5357 prev_scb = scb;
5358 }
5359 qinpos++;
5360 }
5361
5362 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
5363 ahc_outb(ahc, HNSCB_QOFF, ahc->qinfifonext);
5364 } else {
5365 ahc_outb(ahc, KERNEL_QINPOS, ahc->qinfifonext);
5366 }
5367
5368 if (action != SEARCH_COUNT
5369 && (found != 0)
5370 && (qinstart != ahc->qinfifonext)) {
5371 /*
5372 * The sequencer may be in the process of dmaing
5373 * down the SCB at the beginning of the queue.
5374 * This could be problematic if either the first,
5375 * or the second SCB is removed from the queue
5376 * (the first SCB includes a pointer to the "next"
5377 * SCB to dma). If we have removed any entries, swap
5378 * the first element in the queue with the next HSCB
5379 * so the sequencer will notice that NEXT_QUEUED_SCB
5380 * has changed during its dma attempt and will retry
5381 * the DMA.
5382 */
5383 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qinstart]);
5384
5385 if (scb == NULL) {
5386 printf("found = %d, qinstart = %d, qinfifionext = %d\n",
5387 found, qinstart, ahc->qinfifonext);
5388 panic("First/Second Qinfifo fixup\n");
5389 }
5390 /*
5391 * ahc_swap_with_next_hscb forces our next pointer to
5392 * point to the reserved SCB for future commands. Save
5393 * and restore our original next pointer to maintain
5394 * queue integrity.
5395 */
5396 next = scb->hscb->next;
5397 ahc->scb_data->scbindex[scb->hscb->tag] = NULL;
5398 ahc_swap_with_next_hscb(ahc, scb);
5399 scb->hscb->next = next;
5400 ahc->qinfifo[qinstart] = scb->hscb->tag;
5401
5402 /* Tell the card about the new head of the qinfifo. */
5403 ahc_outb(ahc, NEXT_QUEUED_SCB, scb->hscb->tag);
5404
5405 /* Fixup the tail "next" pointer. */
5406 qintail = ahc->qinfifonext - 1;
5407 scb = ahc_lookup_scb(ahc, ahc->qinfifo[qintail]);
5408 scb->hscb->next = ahc->next_queued_scb->hscb->tag;
5409 }
5410
5411 /*
5412 * Search waiting for selection list.
5413 */
5414 curscbptr = ahc_inb(ahc, SCBPTR);
5415 next = ahc_inb(ahc, WAITING_SCBH); /* Start at head of list. */
5416 prev = SCB_LIST_NULL;
5417
5418 while (next != SCB_LIST_NULL) {
5419 uint8_t scb_index;
5420
5421 ahc_outb(ahc, SCBPTR, next);
5422 scb_index = ahc_inb(ahc, SCB_TAG);
5423 if (scb_index >= ahc->scb_data->numscbs) {
5424 printf("Waiting List inconsistency. "
5425 "SCB index == %d, yet numscbs == %d.",
5426 scb_index, ahc->scb_data->numscbs);
5427 ahc_dump_card_state(ahc);
5428 panic("for safety");
5429 }
5430 scb = ahc_lookup_scb(ahc, scb_index);
5431 if (scb == NULL) {
5432 printf("scb_index = %d, next = %d\n",
5433 scb_index, next);
5434 panic("Waiting List traversal\n");
5435 }
5436 if (ahc_match_scb(ahc, scb, target, channel,
5437 lun, SCB_LIST_NULL, role)) {
5438 /*
5439 * We found an scb that needs to be acted on.
5440 */
5441 found++;
5442 switch (action) {
5443 case SEARCH_COMPLETE:
5444 {
5445 cam_status ostat;
5446 cam_status cstat;
5447
5448 ostat = ahc_get_transaction_status(scb);
5449 if (ostat == CAM_REQ_INPROG)
5450 ahc_set_transaction_status(scb,
5451 status);
5452 cstat = ahc_get_transaction_status(scb);
5453 if (cstat != CAM_REQ_CMP)
5454 ahc_freeze_scb(scb);
5455 if ((scb->flags & SCB_ACTIVE) == 0)
5456 printf("Inactive SCB in Waiting List\n");
5457 ahc_done(ahc, scb);
5458 /* FALLTHROUGH */
5459 }
5460 case SEARCH_REMOVE:
5461 next = ahc_rem_wscb(ahc, next, prev);
5462 break;
5463 case SEARCH_COUNT:
5464 prev = next;
5465 next = ahc_inb(ahc, SCB_NEXT);
5466 break;
5467 }
5468 } else {
5469
5470 prev = next;
5471 next = ahc_inb(ahc, SCB_NEXT);
5472 }
5473 }
5474 ahc_outb(ahc, SCBPTR, curscbptr);
5475
5476 found += ahc_search_untagged_queues(ahc, /*ahc_io_ctx_t*/NULL, target,
5477 channel, lun, status, action);
5478
5479 if (action == SEARCH_COMPLETE)
5480 ahc_release_untagged_queues(ahc);
5481 return (found);
5482 }
5483
5484 int
5485 ahc_search_untagged_queues(struct ahc_softc *ahc, ahc_io_ctx_t ctx,
5486 int target, char channel, int lun, uint32_t status,
5487 ahc_search_action action)
5488 {
5489 struct scb *scb;
5490 int maxtarget;
5491 int found;
5492 int i;
5493
5494 if (action == SEARCH_COMPLETE) {
5495 /*
5496 * Don't attempt to run any queued untagged transactions
5497 * until we are done with the abort process.
5498 */
5499 ahc_freeze_untagged_queues(ahc);
5500 }
5501
5502 found = 0;
5503 i = 0;
5504 if ((ahc->flags & AHC_SCB_BTT) == 0) {
5505
5506 maxtarget = 16;
5507 if (target != CAM_TARGET_WILDCARD) {
5508
5509 i = target;
5510 if (channel == 'B')
5511 i += 8;
5512 maxtarget = i + 1;
5513 }
5514 } else {
5515 maxtarget = 0;
5516 }
5517
5518 for (; i < maxtarget; i++) {
5519 struct scb_tailq *untagged_q;
5520 struct scb *next_scb;
5521
5522 untagged_q = &(ahc->untagged_queues[i]);
5523 next_scb = TAILQ_FIRST(untagged_q);
5524 while (next_scb != NULL) {
5525
5526 scb = next_scb;
5527 next_scb = TAILQ_NEXT(scb, links.tqe);
5528
5529 /*
5530 * The head of the list may be the currently
5531 * active untagged command for a device.
5532 * We're only searching for commands that
5533 * have not been started. A transaction
5534 * marked active but still in the qinfifo
5535 * is removed by the qinfifo scanning code
5536 * above.
5537 */
5538 if ((scb->flags & SCB_ACTIVE) != 0)
5539 continue;
5540
5541 if (ahc_match_scb(ahc, scb, target, channel, lun,
5542 SCB_LIST_NULL, ROLE_INITIATOR) == 0
5543 || (ctx != NULL && ctx != scb->io_ctx))
5544 continue;
5545
5546 /*
5547 * We found an scb that needs to be acted on.
5548 */
5549 found++;
5550 switch (action) {
5551 case SEARCH_COMPLETE:
5552 {
5553 cam_status ostat;
5554 cam_status cstat;
5555
5556 ostat = ahc_get_transaction_status(scb);
5557 if (ostat == CAM_REQ_INPROG)
5558 ahc_set_transaction_status(scb, status);
5559 cstat = ahc_get_transaction_status(scb);
5560 if (cstat != CAM_REQ_CMP)
5561 ahc_freeze_scb(scb);
5562 if ((scb->flags & SCB_ACTIVE) == 0)
5563 printf("Inactive SCB in untaggedQ\n");
5564 ahc_done(ahc, scb);
5565 break;
5566 }
5567 case SEARCH_REMOVE:
5568 scb->flags &= ~SCB_UNTAGGEDQ;
5569 TAILQ_REMOVE(untagged_q, scb, links.tqe);
5570 break;
5571 case SEARCH_COUNT:
5572 break;
5573 }
5574 }
5575 }
5576
5577 if (action == SEARCH_COMPLETE)
5578 ahc_release_untagged_queues(ahc);
5579 return (found);
5580 }
5581
5582 int
5583 ahc_search_disc_list(struct ahc_softc *ahc, int target, char channel,
5584 int lun, u_int tag, int stop_on_first, int remove,
5585 int save_state)
5586 {
5587 struct scb *scbp;
5588 u_int next;
5589 u_int prev;
5590 u_int count;
5591 u_int active_scb;
5592
5593 count = 0;
5594 next = ahc_inb(ahc, DISCONNECTED_SCBH);
5595 prev = SCB_LIST_NULL;
5596
5597 if (save_state) {
5598 /* restore this when we're done */
5599 active_scb = ahc_inb(ahc, SCBPTR);
5600 } else
5601 /* Silence compiler */
5602 active_scb = SCB_LIST_NULL;
5603
5604 while (next != SCB_LIST_NULL) {
5605 u_int scb_index;
5606
5607 ahc_outb(ahc, SCBPTR, next);
5608 scb_index = ahc_inb(ahc, SCB_TAG);
5609 if (scb_index >= ahc->scb_data->numscbs) {
5610 printf("Disconnected List inconsistency. "
5611 "SCB index == %d, yet numscbs == %d.",
5612 scb_index, ahc->scb_data->numscbs);
5613 ahc_dump_card_state(ahc);
5614 panic("for safety");
5615 }
5616
5617 if (next == prev) {
5618 panic("Disconnected List Loop. "
5619 "cur SCBPTR == %x, prev SCBPTR == %x.",
5620 next, prev);
5621 }
5622 scbp = ahc_lookup_scb(ahc, scb_index);
5623 if (ahc_match_scb(ahc, scbp, target, channel, lun,
5624 tag, ROLE_INITIATOR)) {
5625 count++;
5626 if (remove) {
5627 next =
5628 ahc_rem_scb_from_disc_list(ahc, prev, next);
5629 } else {
5630 prev = next;
5631 next = ahc_inb(ahc, SCB_NEXT);
5632 }
5633 if (stop_on_first)
5634 break;
5635 } else {
5636 prev = next;
5637 next = ahc_inb(ahc, SCB_NEXT);
5638 }
5639 }
5640 if (save_state)
5641 ahc_outb(ahc, SCBPTR, active_scb);
5642 return (count);
5643 }
5644
5645 /*
5646 * Remove an SCB from the on chip list of disconnected transactions.
5647 * This is empty/unused if we are not performing SCB paging.
5648 */
5649 static u_int
5650 ahc_rem_scb_from_disc_list(struct ahc_softc *ahc, u_int prev, u_int scbptr)
5651 {
5652 u_int next;
5653
5654 ahc_outb(ahc, SCBPTR, scbptr);
5655 next = ahc_inb(ahc, SCB_NEXT);
5656
5657 ahc_outb(ahc, SCB_CONTROL, 0);
5658
5659 ahc_add_curscb_to_free_list(ahc);
5660
5661 if (prev != SCB_LIST_NULL) {
5662 ahc_outb(ahc, SCBPTR, prev);
5663 ahc_outb(ahc, SCB_NEXT, next);
5664 } else
5665 ahc_outb(ahc, DISCONNECTED_SCBH, next);
5666
5667 return (next);
5668 }
5669
5670 /*
5671 * Add the SCB as selected by SCBPTR onto the on chip list of
5672 * free hardware SCBs. This list is empty/unused if we are not
5673 * performing SCB paging.
5674 */
5675 static void
5676 ahc_add_curscb_to_free_list(struct ahc_softc *ahc)
5677 {
5678 /*
5679 * Invalidate the tag so that our abort
5680 * routines don't think it's active.
5681 */
5682 ahc_outb(ahc, SCB_TAG, SCB_LIST_NULL);
5683
5684 if ((ahc->flags & AHC_PAGESCBS) != 0) {
5685 ahc_outb(ahc, SCB_NEXT, ahc_inb(ahc, FREE_SCBH));
5686 ahc_outb(ahc, FREE_SCBH, ahc_inb(ahc, SCBPTR));
5687 }
5688 }
5689
5690 /*
5691 * Manipulate the waiting for selection list and return the
5692 * scb that follows the one that we remove.
5693 */
5694 static u_int
5695 ahc_rem_wscb(struct ahc_softc *ahc, u_int scbpos, u_int prev)
5696 {
5697 u_int curscb, next;
5698
5699 /*
5700 * Select the SCB we want to abort and
5701 * pull the next pointer out of it.
5702 */
5703 curscb = ahc_inb(ahc, SCBPTR);
5704 ahc_outb(ahc, SCBPTR, scbpos);
5705 next = ahc_inb(ahc, SCB_NEXT);
5706
5707 /* Clear the necessary fields */
5708 ahc_outb(ahc, SCB_CONTROL, 0);
5709
5710 ahc_add_curscb_to_free_list(ahc);
5711
5712 /* update the waiting list */
5713 if (prev == SCB_LIST_NULL) {
5714 /* First in the list */
5715 ahc_outb(ahc, WAITING_SCBH, next);
5716
5717 /*
5718 * Ensure we aren't attempting to perform
5719 * selection for this entry.
5720 */
5721 ahc_outb(ahc, SCSISEQ, (ahc_inb(ahc, SCSISEQ) & ~ENSELO));
5722 } else {
5723 /*
5724 * Select the scb that pointed to us
5725 * and update its next pointer.
5726 */
5727 ahc_outb(ahc, SCBPTR, prev);
5728 ahc_outb(ahc, SCB_NEXT, next);
5729 }
5730
5731 /*
5732 * Point us back at the original scb position.
5733 */
5734 ahc_outb(ahc, SCBPTR, curscb);
5735 return next;
5736 }
5737
5738 /******************************** Error Handling ******************************/
5739 /*
5740 * Abort all SCBs that match the given description (target/channel/lun/tag),
5741 * setting their status to the passed in status if the status has not already
5742 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer
5743 * is paused before it is called.
5744 */
5745 int
5746 ahc_abort_scbs(struct ahc_softc *ahc, int target, char channel,
5747 int lun, u_int tag, role_t role, uint32_t status)
5748 {
5749 struct scb *scbp;
5750 struct scb *scbp_next;
5751 u_int active_scb;
5752 int i, j;
5753 int maxtarget;
5754 int minlun;
5755 int maxlun;
5756
5757 int found;
5758
5759 /*
5760 * Don't attempt to run any queued untagged transactions
5761 * until we are done with the abort process.
5762 */
5763 ahc_freeze_untagged_queues(ahc);
5764
5765 /* restore this when we're done */
5766 active_scb = ahc_inb(ahc, SCBPTR);
5767
5768 found = ahc_search_qinfifo(ahc, target, channel, lun, SCB_LIST_NULL,
5769 role, CAM_REQUEUE_REQ, SEARCH_COMPLETE);
5770
5771 /*
5772 * Clean out the busy target table for any untagged commands.
5773 */
5774 i = 0;
5775 maxtarget = 16;
5776 if (target != CAM_TARGET_WILDCARD) {
5777 i = target;
5778 if (channel == 'B')
5779 i += 8;
5780 maxtarget = i + 1;
5781 }
5782
5783 if (lun == CAM_LUN_WILDCARD) {
5784
5785 /*
5786 * Unless we are using an SCB based
5787 * busy targets table, there is only
5788 * one table entry for all luns of
5789 * a target.
5790 */
5791 minlun = 0;
5792 maxlun = 1;
5793 if ((ahc->flags & AHC_SCB_BTT) != 0)
5794 maxlun = AHC_NUM_LUNS;
5795 } else {
5796 minlun = lun;
5797 maxlun = lun + 1;
5798 }
5799
5800 if (role != ROLE_TARGET) {
5801 for (;i < maxtarget; i++) {
5802 for (j = minlun;j < maxlun; j++) {
5803 u_int scbid;
5804 u_int tcl;
5805
5806 tcl = BUILD_TCL(i << 4, j);
5807 scbid = ahc_index_busy_tcl(ahc, tcl);
5808 scbp = ahc_lookup_scb(ahc, scbid);
5809 if (scbp == NULL
5810 || ahc_match_scb(ahc, scbp, target, channel,
5811 lun, tag, role) == 0)
5812 continue;
5813 ahc_unbusy_tcl(ahc, BUILD_TCL(i << 4, j));
5814 }
5815 }
5816
5817 /*
5818 * Go through the disconnected list and remove any entries we
5819 * have queued for completion, 0'ing their control byte too.
5820 * We save the active SCB and restore it ourselves, so there
5821 * is no reason for this search to restore it too.
5822 */
5823 ahc_search_disc_list(ahc, target, channel, lun, tag,
5824 /*stop_on_first*/FALSE, /*remove*/TRUE,
5825 /*save_state*/FALSE);
5826 }
5827
5828 /*
5829 * Go through the hardware SCB array looking for commands that
5830 * were active but not on any list. In some cases, these remnants
5831 * might not still have mappings in the scbindex array (e.g. unexpected
5832 * bus free with the same scb queued for an abort). Don't hold this
5833 * against them.
5834 */
5835 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
5836 u_int scbid;
5837
5838 ahc_outb(ahc, SCBPTR, i);
5839 scbid = ahc_inb(ahc, SCB_TAG);
5840 scbp = ahc_lookup_scb(ahc, scbid);
5841 if ((scbp == NULL && scbid != SCB_LIST_NULL)
5842 || (scbp != NULL
5843 && ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)))
5844 ahc_add_curscb_to_free_list(ahc);
5845 }
5846
5847 /*
5848 * Go through the pending CCB list and look for
5849 * commands for this target that are still active.
5850 * These are other tagged commands that were
5851 * disconnected when the reset occurred.
5852 */
5853 scbp_next = LIST_FIRST(&ahc->pending_scbs);
5854 while (scbp_next != NULL) {
5855 scbp = scbp_next;
5856 scbp_next = LIST_NEXT(scbp, pending_links);
5857 if (ahc_match_scb(ahc, scbp, target, channel, lun, tag, role)) {
5858 cam_status ostat;
5859
5860 ostat = ahc_get_transaction_status(scbp);
5861 if (ostat == CAM_REQ_INPROG)
5862 ahc_set_transaction_status(scbp, status);
5863 if (ahc_get_transaction_status(scbp) != CAM_REQ_CMP)
5864 ahc_freeze_scb(scbp);
5865 if ((scbp->flags & SCB_ACTIVE) == 0)
5866 printf("Inactive SCB on pending list\n");
5867 ahc_done(ahc, scbp);
5868 found++;
5869 }
5870 }
5871 ahc_outb(ahc, SCBPTR, active_scb);
5872 ahc_platform_abort_scbs(ahc, target, channel, lun, tag, role, status);
5873 ahc_release_untagged_queues(ahc);
5874 return found;
5875 }
5876
5877 static void
5878 ahc_reset_current_bus(struct ahc_softc *ahc)
5879 {
5880 uint8_t scsiseq;
5881
5882 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) & ~ENSCSIRST);
5883 scsiseq = ahc_inb(ahc, SCSISEQ);
5884 ahc_outb(ahc, SCSISEQ, scsiseq | SCSIRSTO);
5885 ahc_flush_device_writes(ahc);
5886 ahc_delay(AHC_BUSRESET_DELAY);
5887 /* Turn off the bus reset */
5888 ahc_outb(ahc, SCSISEQ, scsiseq & ~SCSIRSTO);
5889
5890 ahc_clear_intstat(ahc);
5891
5892 /* Re-enable reset interrupts */
5893 ahc_outb(ahc, SIMODE1, ahc_inb(ahc, SIMODE1) | ENSCSIRST);
5894 }
5895
5896 int
5897 ahc_reset_channel(struct ahc_softc *ahc, char channel, int initiate_reset)
5898 {
5899 struct ahc_devinfo devinfo;
5900 u_int initiator, target, max_scsiid;
5901 u_int sblkctl;
5902 u_int scsiseq;
5903 u_int simode1;
5904 int found;
5905 int restart_needed;
5906 char cur_channel;
5907
5908 ahc->pending_device = NULL;
5909
5910 ahc_compile_devinfo(&devinfo,
5911 CAM_TARGET_WILDCARD,
5912 CAM_TARGET_WILDCARD,
5913 CAM_LUN_WILDCARD,
5914 channel, ROLE_UNKNOWN);
5915 ahc_pause(ahc);
5916
5917 /* Make sure the sequencer is in a safe location. */
5918 ahc_clear_critical_section(ahc);
5919
5920 /*
5921 * Run our command complete fifos to ensure that we perform
5922 * completion processing on any commands that 'completed'
5923 * before the reset occurred.
5924 */
5925 ahc_run_qoutfifo(ahc);
5926 #ifdef AHC_TARGET_MODE
5927 /*
5928 * XXX - In Twin mode, the tqinfifo may have commands
5929 * for an unaffected channel in it. However, if
5930 * we have run out of ATIO resources to drain that
5931 * queue, we may not get them all out here. Further,
5932 * the blocked transactions for the reset channel
5933 * should just be killed off, irrespecitve of whether
5934 * we are blocked on ATIO resources. Write a routine
5935 * to compact the tqinfifo appropriately.
5936 */
5937 if ((ahc->flags & AHC_TARGETROLE) != 0) {
5938 ahc_run_tqinfifo(ahc, /*paused*/TRUE);
5939 }
5940 #endif
5941
5942 /*
5943 * Reset the bus if we are initiating this reset
5944 */
5945 sblkctl = ahc_inb(ahc, SBLKCTL);
5946 cur_channel = 'A';
5947 if ((ahc->features & AHC_TWIN) != 0
5948 && ((sblkctl & SELBUSB) != 0))
5949 cur_channel = 'B';
5950 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
5951 if (cur_channel != channel) {
5952 /* Case 1: Command for another bus is active
5953 * Stealthily reset the other bus without
5954 * upsetting the current bus.
5955 */
5956 ahc_outb(ahc, SBLKCTL, sblkctl ^ SELBUSB);
5957 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST);
5958 #ifdef AHC_TARGET_MODE
5959 /*
5960 * Bus resets clear ENSELI, so we cannot
5961 * defer re-enabling bus reset interrupts
5962 * if we are in target mode.
5963 */
5964 if ((ahc->flags & AHC_TARGETROLE) != 0)
5965 simode1 |= ENSCSIRST;
5966 #endif
5967 ahc_outb(ahc, SIMODE1, simode1);
5968 if (initiate_reset)
5969 ahc_reset_current_bus(ahc);
5970 ahc_clear_intstat(ahc);
5971 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP));
5972 ahc_outb(ahc, SBLKCTL, sblkctl);
5973 restart_needed = FALSE;
5974 } else {
5975 /* Case 2: A command from this bus is active or we're idle */
5976 simode1 = ahc_inb(ahc, SIMODE1) & ~(ENBUSFREE|ENSCSIRST);
5977 #ifdef AHC_TARGET_MODE
5978 /*
5979 * Bus resets clear ENSELI, so we cannot
5980 * defer re-enabling bus reset interrupts
5981 * if we are in target mode.
5982 */
5983 if ((ahc->flags & AHC_TARGETROLE) != 0)
5984 simode1 |= ENSCSIRST;
5985 #endif
5986 ahc_outb(ahc, SIMODE1, simode1);
5987 if (initiate_reset)
5988 ahc_reset_current_bus(ahc);
5989 ahc_clear_intstat(ahc);
5990 ahc_outb(ahc, SCSISEQ, scsiseq & (ENSELI|ENRSELI|ENAUTOATNP));
5991 restart_needed = TRUE;
5992 }
5993
5994 /*
5995 * Clean up all the state information for the
5996 * pending transactions on this bus.
5997 */
5998 found = ahc_abort_scbs(ahc, CAM_TARGET_WILDCARD, channel,
5999 CAM_LUN_WILDCARD, SCB_LIST_NULL,
6000 ROLE_UNKNOWN, CAM_SCSI_BUS_RESET);
6001
6002 max_scsiid = (ahc->features & AHC_WIDE) ? 15 : 7;
6003
6004 #ifdef AHC_TARGET_MODE
6005 /*
6006 * Send an immediate notify ccb to all target more peripheral
6007 * drivers affected by this action.
6008 */
6009 for (target = 0; target <= max_scsiid; target++) {
6010 struct ahc_tmode_tstate* tstate;
6011 u_int lun;
6012
6013 tstate = ahc->enabled_targets[target];
6014 if (tstate == NULL)
6015 continue;
6016 for (lun = 0; lun < AHC_NUM_LUNS; lun++) {
6017 struct ahc_tmode_lstate* lstate;
6018
6019 lstate = tstate->enabled_luns[lun];
6020 if (lstate == NULL)
6021 continue;
6022
6023 ahc_queue_lstate_event(ahc, lstate, CAM_TARGET_WILDCARD,
6024 EVENT_TYPE_BUS_RESET, /*arg*/0);
6025 ahc_send_lstate_events(ahc, lstate);
6026 }
6027 }
6028 #endif
6029 /* Notify the XPT that a bus reset occurred */
6030 ahc_send_async(ahc, devinfo.channel, CAM_TARGET_WILDCARD,
6031 CAM_LUN_WILDCARD, AC_BUS_RESET, NULL);
6032
6033 /*
6034 * Revert to async/narrow transfers until we renegotiate.
6035 */
6036 for (target = 0; target <= max_scsiid; target++) {
6037
6038 if (ahc->enabled_targets[target] == NULL)
6039 continue;
6040 for (initiator = 0; initiator <= max_scsiid; initiator++) {
6041 struct ahc_devinfo devinfo;
6042
6043 ahc_compile_devinfo(&devinfo, target, initiator,
6044 CAM_LUN_WILDCARD,
6045 channel, ROLE_UNKNOWN);
6046 ahc_set_width(ahc, &devinfo, MSG_EXT_WDTR_BUS_8_BIT,
6047 AHC_TRANS_CUR, /*paused*/TRUE);
6048 ahc_set_syncrate(ahc, &devinfo, /*syncrate*/NULL,
6049 /*period*/0, /*offset*/0,
6050 /*ppr_options*/0, AHC_TRANS_CUR,
6051 /*paused*/TRUE);
6052 }
6053 }
6054
6055 if (restart_needed)
6056 ahc_restart(ahc);
6057 else
6058 ahc_unpause(ahc);
6059 return found;
6060 }
6061
6062
6063 /***************************** Residual Processing ****************************/
6064 /*
6065 * Calculate the residual for a just completed SCB.
6066 */
6067 void
6068 ahc_calc_residual(struct ahc_softc *ahc, struct scb *scb)
6069 {
6070 struct hardware_scb *hscb;
6071 struct status_pkt *spkt;
6072 uint32_t sgptr;
6073 uint32_t resid_sgptr;
6074 uint32_t resid;
6075
6076 /*
6077 * 5 cases.
6078 * 1) No residual.
6079 * SG_RESID_VALID clear in sgptr.
6080 * 2) Transferless command
6081 * 3) Never performed any transfers.
6082 * sgptr has SG_FULL_RESID set.
6083 * 4) No residual but target did not
6084 * save data pointers after the
6085 * last transfer, so sgptr was
6086 * never updated.
6087 * 5) We have a partial residual.
6088 * Use residual_sgptr to determine
6089 * where we are.
6090 */
6091
6092 hscb = scb->hscb;
6093 sgptr = ahc_le32toh(hscb->sgptr);
6094 if ((sgptr & SG_RESID_VALID) == 0)
6095 /* Case 1 */
6096 return;
6097 sgptr &= ~SG_RESID_VALID;
6098
6099 if ((sgptr & SG_LIST_NULL) != 0)
6100 /* Case 2 */
6101 return;
6102
6103 spkt = &hscb->shared_data.status;
6104 resid_sgptr = ahc_le32toh(spkt->residual_sg_ptr);
6105 if ((sgptr & SG_FULL_RESID) != 0) {
6106 /* Case 3 */
6107 resid = ahc_get_transfer_length(scb);
6108 } else if ((resid_sgptr & SG_LIST_NULL) != 0) {
6109 /* Case 4 */
6110 return;
6111 } else if ((resid_sgptr & ~SG_PTR_MASK) != 0) {
6112 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr);
6113 } else {
6114 struct ahc_dma_seg *sg;
6115
6116 /*
6117 * Remainder of the SG where the transfer
6118 * stopped.
6119 */
6120 resid = ahc_le32toh(spkt->residual_datacnt) & AHC_SG_LEN_MASK;
6121 sg = ahc_sg_bus_to_virt(scb, resid_sgptr & SG_PTR_MASK);
6122
6123 /* The residual sg_ptr always points to the next sg */
6124 sg--;
6125
6126 /*
6127 * Add up the contents of all residual
6128 * SG segments that are after the SG where
6129 * the transfer stopped.
6130 */
6131 while ((ahc_le32toh(sg->len) & AHC_DMA_LAST_SEG) == 0) {
6132 sg++;
6133 resid += ahc_le32toh(sg->len) & AHC_SG_LEN_MASK;
6134 }
6135 }
6136 if ((scb->flags & SCB_SENSE) == 0)
6137 ahc_set_residual(scb, resid);
6138 else
6139 ahc_set_sense_residual(scb, resid);
6140
6141 #ifdef AHC_DEBUG
6142 if ((ahc_debug & AHC_SHOW_MISC) != 0) {
6143 ahc_print_path(ahc, scb);
6144 printf("Handled %sResidual of %d bytes\n",
6145 (scb->flags & SCB_SENSE) ? "Sense " : "", resid);
6146 }
6147 #endif
6148 }
6149
6150 /******************************* Target Mode **********************************/
6151 #ifdef AHC_TARGET_MODE
6152 /*
6153 * Add a target mode event to this lun's queue
6154 */
6155 static void
6156 ahc_queue_lstate_event(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate,
6157 u_int initiator_id, u_int event_type, u_int event_arg)
6158 {
6159 struct ahc_tmode_event *event;
6160 int pending;
6161
6162 xpt_freeze_devq(lstate->path, /*count*/1);
6163 if (lstate->event_w_idx >= lstate->event_r_idx)
6164 pending = lstate->event_w_idx - lstate->event_r_idx;
6165 else
6166 pending = AHC_TMODE_EVENT_BUFFER_SIZE + 1
6167 - (lstate->event_r_idx - lstate->event_w_idx);
6168
6169 if (event_type == EVENT_TYPE_BUS_RESET
6170 || event_type == MSG_BUS_DEV_RESET) {
6171 /*
6172 * Any earlier events are irrelevant, so reset our buffer.
6173 * This has the effect of allowing us to deal with reset
6174 * floods (an external device holding down the reset line)
6175 * without losing the event that is really interesting.
6176 */
6177 lstate->event_r_idx = 0;
6178 lstate->event_w_idx = 0;
6179 xpt_release_devq(lstate->path, pending, /*runqueue*/FALSE);
6180 }
6181
6182 if (pending == AHC_TMODE_EVENT_BUFFER_SIZE) {
6183 xpt_print_path(lstate->path);
6184 printf("immediate event %x:%x lost\n",
6185 lstate->event_buffer[lstate->event_r_idx].event_type,
6186 lstate->event_buffer[lstate->event_r_idx].event_arg);
6187 lstate->event_r_idx++;
6188 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6189 lstate->event_r_idx = 0;
6190 xpt_release_devq(lstate->path, /*count*/1, /*runqueue*/FALSE);
6191 }
6192
6193 event = &lstate->event_buffer[lstate->event_w_idx];
6194 event->initiator_id = initiator_id;
6195 event->event_type = event_type;
6196 event->event_arg = event_arg;
6197 lstate->event_w_idx++;
6198 if (lstate->event_w_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6199 lstate->event_w_idx = 0;
6200 }
6201
6202 /*
6203 * Send any target mode events queued up waiting
6204 * for immediate notify resources.
6205 */
6206 void
6207 ahc_send_lstate_events(struct ahc_softc *ahc, struct ahc_tmode_lstate *lstate)
6208 {
6209 struct ccb_hdr *ccbh;
6210 struct ccb_immed_notify *inot;
6211
6212 while (lstate->event_r_idx != lstate->event_w_idx
6213 && (ccbh = SLIST_FIRST(&lstate->immed_notifies)) != NULL) {
6214 struct ahc_tmode_event *event;
6215
6216 event = &lstate->event_buffer[lstate->event_r_idx];
6217 SLIST_REMOVE_HEAD(&lstate->immed_notifies, sim_links.sle);
6218 inot = (struct ccb_immed_notify *)ccbh;
6219 switch (event->event_type) {
6220 case EVENT_TYPE_BUS_RESET:
6221 ccbh->status = CAM_SCSI_BUS_RESET|CAM_DEV_QFRZN;
6222 break;
6223 default:
6224 ccbh->status = CAM_MESSAGE_RECV|CAM_DEV_QFRZN;
6225 inot->message_args[0] = event->event_type;
6226 inot->message_args[1] = event->event_arg;
6227 break;
6228 }
6229 inot->initiator_id = event->initiator_id;
6230 inot->sense_len = 0;
6231 xpt_done((union ccb *)inot);
6232 lstate->event_r_idx++;
6233 if (lstate->event_r_idx == AHC_TMODE_EVENT_BUFFER_SIZE)
6234 lstate->event_r_idx = 0;
6235 }
6236 }
6237 #endif
6238
6239 /******************** Sequencer Program Patching/Download *********************/
6240
6241 #ifdef AHC_DUMP_SEQ
6242 void
6243 ahc_dumpseq(struct ahc_softc* ahc)
6244 {
6245 int i;
6246
6247 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
6248 ahc_outb(ahc, SEQADDR0, 0);
6249 ahc_outb(ahc, SEQADDR1, 0);
6250 for (i = 0; i < ahc->instruction_ram_size; i++) {
6251 uint8_t ins_bytes[4];
6252
6253 ahc_insb(ahc, SEQRAM, ins_bytes, 4);
6254 printf("0x%08x\n", ins_bytes[0] << 24
6255 | ins_bytes[1] << 16
6256 | ins_bytes[2] << 8
6257 | ins_bytes[3]);
6258 }
6259 }
6260 #endif
6261
6262 static int
6263 ahc_loadseq(struct ahc_softc *ahc)
6264 {
6265 struct cs cs_table[num_critical_sections];
6266 u_int begin_set[num_critical_sections];
6267 u_int end_set[num_critical_sections];
6268 struct patch *cur_patch;
6269 u_int cs_count;
6270 u_int cur_cs;
6271 u_int i;
6272 u_int skip_addr;
6273 u_int sg_prefetch_cnt;
6274 int downloaded;
6275 uint8_t download_consts[7];
6276
6277 /*
6278 * Start out with 0 critical sections
6279 * that apply to this firmware load.
6280 */
6281 cs_count = 0;
6282 cur_cs = 0;
6283 memset(begin_set, 0, sizeof(begin_set));
6284 memset(end_set, 0, sizeof(end_set));
6285
6286 /* Setup downloadable constant table */
6287 download_consts[QOUTFIFO_OFFSET] = 0;
6288 if (ahc->targetcmds != NULL)
6289 download_consts[QOUTFIFO_OFFSET] += 32;
6290 download_consts[QINFIFO_OFFSET] = download_consts[QOUTFIFO_OFFSET] + 1;
6291 download_consts[CACHESIZE_MASK] = ahc->pci_cachesize - 1;
6292 download_consts[INVERTED_CACHESIZE_MASK] = ~(ahc->pci_cachesize - 1);
6293 sg_prefetch_cnt = ahc->pci_cachesize;
6294 if (sg_prefetch_cnt < (2 * sizeof(struct ahc_dma_seg)))
6295 sg_prefetch_cnt = 2 * sizeof(struct ahc_dma_seg);
6296 download_consts[SG_PREFETCH_CNT] = sg_prefetch_cnt;
6297 download_consts[SG_PREFETCH_ALIGN_MASK] = ~(sg_prefetch_cnt - 1);
6298 download_consts[SG_PREFETCH_ADDR_MASK] = (sg_prefetch_cnt - 1);
6299
6300 cur_patch = patches;
6301 downloaded = 0;
6302 skip_addr = 0;
6303 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE|LOADRAM);
6304 ahc_outb(ahc, SEQADDR0, 0);
6305 ahc_outb(ahc, SEQADDR1, 0);
6306
6307 for (i = 0; i < sizeof(seqprog)/4; i++) {
6308 if (ahc_check_patch(ahc, &cur_patch, i, &skip_addr) == 0) {
6309 /*
6310 * Don't download this instruction as it
6311 * is in a patch that was removed.
6312 */
6313 continue;
6314 }
6315
6316 if (downloaded == ahc->instruction_ram_size) {
6317 /*
6318 * We're about to exceed the instruction
6319 * storage capacity for this chip. Fail
6320 * the load.
6321 */
6322 printf("\n%s: Program too large for instruction memory "
6323 "size of %d!\n", ahc_name(ahc),
6324 ahc->instruction_ram_size);
6325 return (ENOMEM);
6326 }
6327
6328 /*
6329 * Move through the CS table until we find a CS
6330 * that might apply to this instruction.
6331 */
6332 for (; cur_cs < num_critical_sections; cur_cs++) {
6333 if (critical_sections[cur_cs].end <= i) {
6334 if (begin_set[cs_count] == TRUE
6335 && end_set[cs_count] == FALSE) {
6336 cs_table[cs_count].end = downloaded;
6337 end_set[cs_count] = TRUE;
6338 cs_count++;
6339 }
6340 continue;
6341 }
6342 if (critical_sections[cur_cs].begin <= i
6343 && begin_set[cs_count] == FALSE) {
6344 cs_table[cs_count].begin = downloaded;
6345 begin_set[cs_count] = TRUE;
6346 }
6347 break;
6348 }
6349 ahc_download_instr(ahc, i, download_consts);
6350 downloaded++;
6351 }
6352
6353 ahc->num_critical_sections = cs_count;
6354 if (cs_count != 0) {
6355
6356 cs_count *= sizeof(struct cs);
6357 ahc->critical_sections = malloc(cs_count, M_DEVBUF, M_NOWAIT);
6358 if (ahc->critical_sections == NULL)
6359 panic("ahc_loadseq: Could not malloc");
6360 memcpy(ahc->critical_sections, cs_table, cs_count);
6361 }
6362 ahc_outb(ahc, SEQCTL, PERRORDIS|FAILDIS|FASTMODE);
6363
6364 if (bootverbose) {
6365 printf(" %d instructions downloaded\n", downloaded);
6366 printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n",
6367 ahc_name(ahc), ahc->features, ahc->bugs, ahc->flags);
6368 }
6369 return (0);
6370 }
6371
6372 static int
6373 ahc_check_patch(struct ahc_softc *ahc, struct patch **start_patch,
6374 u_int start_instr, u_int *skip_addr)
6375 {
6376 struct patch *cur_patch;
6377 struct patch *last_patch;
6378 u_int num_patches;
6379
6380 num_patches = sizeof(patches)/sizeof(struct patch);
6381 last_patch = &patches[num_patches];
6382 cur_patch = *start_patch;
6383
6384 while (cur_patch < last_patch && start_instr == cur_patch->begin) {
6385
6386 if (cur_patch->patch_func(ahc) == 0) {
6387
6388 /* Start rejecting code */
6389 *skip_addr = start_instr + cur_patch->skip_instr;
6390 cur_patch += cur_patch->skip_patch;
6391 } else {
6392 /* Accepted this patch. Advance to the next
6393 * one and wait for our intruction pointer to
6394 * hit this point.
6395 */
6396 cur_patch++;
6397 }
6398 }
6399
6400 *start_patch = cur_patch;
6401 if (start_instr < *skip_addr)
6402 /* Still skipping */
6403 return (0);
6404
6405 return (1);
6406 }
6407
6408 static void
6409 ahc_download_instr(struct ahc_softc *ahc, u_int instrptr, uint8_t *dconsts)
6410 {
6411 union ins_formats instr;
6412 struct ins_format1 *fmt1_ins;
6413 struct ins_format3 *fmt3_ins;
6414 u_int opcode;
6415
6416 /*
6417 * The firmware is always compiled into a little endian format.
6418 */
6419 instr.integer = ahc_le32toh(*(uint32_t*)&seqprog[instrptr * 4]);
6420
6421 fmt1_ins = &instr.format1;
6422 fmt3_ins = NULL;
6423
6424 /* Pull the opcode */
6425 opcode = instr.format1.opcode;
6426 switch (opcode) {
6427 case AIC_OP_JMP:
6428 case AIC_OP_JC:
6429 case AIC_OP_JNC:
6430 case AIC_OP_CALL:
6431 case AIC_OP_JNE:
6432 case AIC_OP_JNZ:
6433 case AIC_OP_JE:
6434 case AIC_OP_JZ:
6435 {
6436 struct patch *cur_patch;
6437 int address_offset;
6438 u_int address;
6439 u_int skip_addr;
6440 u_int i;
6441
6442 fmt3_ins = &instr.format3;
6443 address_offset = 0;
6444 address = fmt3_ins->address;
6445 cur_patch = patches;
6446 skip_addr = 0;
6447
6448 for (i = 0; i < address;) {
6449
6450 ahc_check_patch(ahc, &cur_patch, i, &skip_addr);
6451
6452 if (skip_addr > i) {
6453 int end_addr;
6454
6455 end_addr = MIN(address, skip_addr);
6456 address_offset += end_addr - i;
6457 i = skip_addr;
6458 } else {
6459 i++;
6460 }
6461 }
6462 address -= address_offset;
6463 fmt3_ins->address = address;
6464 /* FALLTHROUGH */
6465 }
6466 case AIC_OP_OR:
6467 case AIC_OP_AND:
6468 case AIC_OP_XOR:
6469 case AIC_OP_ADD:
6470 case AIC_OP_ADC:
6471 case AIC_OP_BMOV:
6472 if (fmt1_ins->parity != 0) {
6473 fmt1_ins->immediate = dconsts[fmt1_ins->immediate];
6474 }
6475 fmt1_ins->parity = 0;
6476 if ((ahc->features & AHC_CMD_CHAN) == 0
6477 && opcode == AIC_OP_BMOV) {
6478 /*
6479 * Block move was added at the same time
6480 * as the command channel. Verify that
6481 * this is only a move of a single element
6482 * and convert the BMOV to a MOV
6483 * (AND with an immediate of FF).
6484 */
6485 if (fmt1_ins->immediate != 1)
6486 panic("%s: BMOV not supported\n",
6487 ahc_name(ahc));
6488 fmt1_ins->opcode = AIC_OP_AND;
6489 fmt1_ins->immediate = 0xff;
6490 }
6491 /* FALLTHROUGH */
6492 case AIC_OP_ROL:
6493 if ((ahc->features & AHC_ULTRA2) != 0) {
6494 int i, count;
6495
6496 /* Calculate odd parity for the instruction */
6497 for (i = 0, count = 0; i < 31; i++) {
6498 uint32_t mask;
6499
6500 mask = 0x01 << i;
6501 if ((instr.integer & mask) != 0)
6502 count++;
6503 }
6504 if ((count & 0x01) == 0)
6505 instr.format1.parity = 1;
6506 } else {
6507 /* Compress the instruction for older sequencers */
6508 if (fmt3_ins != NULL) {
6509 instr.integer =
6510 fmt3_ins->immediate
6511 | (fmt3_ins->source << 8)
6512 | (fmt3_ins->address << 16)
6513 | (fmt3_ins->opcode << 25);
6514 } else {
6515 instr.integer =
6516 fmt1_ins->immediate
6517 | (fmt1_ins->source << 8)
6518 | (fmt1_ins->destination << 16)
6519 | (fmt1_ins->ret << 24)
6520 | (fmt1_ins->opcode << 25);
6521 }
6522 }
6523 /* The sequencer is a little endian cpu */
6524 instr.integer = ahc_htole32(instr.integer);
6525 ahc_outsb(ahc, SEQRAM, instr.bytes, 4);
6526 break;
6527 default:
6528 panic("Unknown opcode encountered in seq program");
6529 break;
6530 }
6531 }
6532
6533 int
6534 ahc_print_register(ahc_reg_parse_entry_t *table, u_int num_entries,
6535 const char *name, u_int address, u_int value,
6536 u_int *cur_column, u_int wrap_point)
6537 {
6538 int printed;
6539 u_int printed_mask;
6540
6541 if (cur_column != NULL && *cur_column >= wrap_point) {
6542 printf("\n");
6543 *cur_column = 0;
6544 }
6545 printed = printf("%s[0x%x]", name, value);
6546 if (table == NULL) {
6547 printed += printf(" ");
6548 *cur_column += printed;
6549 return (printed);
6550 }
6551 printed_mask = 0;
6552 while (printed_mask != 0xFF) {
6553 int entry;
6554
6555 for (entry = 0; entry < num_entries; entry++) {
6556 if (((value & table[entry].mask)
6557 != table[entry].value)
6558 || ((printed_mask & table[entry].mask)
6559 == table[entry].mask))
6560 continue;
6561
6562 printed += printf("%s%s",
6563 printed_mask == 0 ? ":(" : "|",
6564 table[entry].name);
6565 printed_mask |= table[entry].mask;
6566
6567 break;
6568 }
6569 if (entry >= num_entries)
6570 break;
6571 }
6572 if (printed_mask != 0)
6573 printed += printf(") ");
6574 else
6575 printed += printf(" ");
6576 if (cur_column != NULL)
6577 *cur_column += printed;
6578 return (printed);
6579 }
6580
6581 void
6582 ahc_dump_card_state(struct ahc_softc *ahc)
6583 {
6584 struct scb *scb;
6585 struct scb_tailq *untagged_q;
6586 u_int cur_col;
6587 int paused;
6588 int target;
6589 int maxtarget;
6590 int i;
6591 uint8_t last_phase;
6592 uint8_t qinpos;
6593 uint8_t qintail;
6594 uint8_t qoutpos;
6595 uint8_t scb_index;
6596 uint8_t saved_scbptr;
6597
6598 if (ahc_is_paused(ahc)) {
6599 paused = 1;
6600 } else {
6601 paused = 0;
6602 ahc_pause(ahc);
6603 }
6604
6605 saved_scbptr = ahc_inb(ahc, SCBPTR);
6606 last_phase = ahc_inb(ahc, LASTPHASE);
6607 printf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n"
6608 "%s: Dumping Card State %s, at SEQADDR 0x%x\n",
6609 ahc_name(ahc), ahc_lookup_phase_entry(last_phase)->phasemsg,
6610 ahc_inb(ahc, SEQADDR0) | (ahc_inb(ahc, SEQADDR1) << 8));
6611 if (paused)
6612 printf("Card was paused\n");
6613 printf("ACCUM = 0x%x, SINDEX = 0x%x, DINDEX = 0x%x, ARG_2 = 0x%x\n",
6614 ahc_inb(ahc, ACCUM), ahc_inb(ahc, SINDEX), ahc_inb(ahc, DINDEX),
6615 ahc_inb(ahc, ARG_2));
6616 printf("HCNT = 0x%x SCBPTR = 0x%x\n", ahc_inb(ahc, HCNT),
6617 ahc_inb(ahc, SCBPTR));
6618 cur_col = 0;
6619 if ((ahc->features & AHC_DT) != 0)
6620 ahc_scsiphase_print(ahc_inb(ahc, SCSIPHASE), &cur_col, 50);
6621 ahc_scsisigi_print(ahc_inb(ahc, SCSISIGI), &cur_col, 50);
6622 ahc_error_print(ahc_inb(ahc, ERROR), &cur_col, 50);
6623 ahc_scsibusl_print(ahc_inb(ahc, SCSIBUSL), &cur_col, 50);
6624 ahc_lastphase_print(ahc_inb(ahc, LASTPHASE), &cur_col, 50);
6625 ahc_scsiseq_print(ahc_inb(ahc, SCSISEQ), &cur_col, 50);
6626 ahc_sblkctl_print(ahc_inb(ahc, SBLKCTL), &cur_col, 50);
6627 ahc_scsirate_print(ahc_inb(ahc, SCSIRATE), &cur_col, 50);
6628 ahc_seqctl_print(ahc_inb(ahc, SEQCTL), &cur_col, 50);
6629 ahc_seq_flags_print(ahc_inb(ahc, SEQ_FLAGS), &cur_col, 50);
6630 ahc_sstat0_print(ahc_inb(ahc, SSTAT0), &cur_col, 50);
6631 ahc_sstat1_print(ahc_inb(ahc, SSTAT1), &cur_col, 50);
6632 ahc_sstat2_print(ahc_inb(ahc, SSTAT2), &cur_col, 50);
6633 ahc_sstat3_print(ahc_inb(ahc, SSTAT3), &cur_col, 50);
6634 ahc_simode0_print(ahc_inb(ahc, SIMODE0), &cur_col, 50);
6635 ahc_simode1_print(ahc_inb(ahc, SIMODE1), &cur_col, 50);
6636 ahc_sxfrctl0_print(ahc_inb(ahc, SXFRCTL0), &cur_col, 50);
6637 ahc_dfcntrl_print(ahc_inb(ahc, DFCNTRL), &cur_col, 50);
6638 ahc_dfstatus_print(ahc_inb(ahc, DFSTATUS), &cur_col, 50);
6639 if (cur_col != 0)
6640 printf("\n");
6641 printf("STACK:");
6642 for (i = 0; i < STACK_SIZE; i++)
6643 printf(" 0x%x", ahc_inb(ahc, STACK)|(ahc_inb(ahc, STACK) << 8));
6644 printf("\nSCB count = %d\n", ahc->scb_data->numscbs);
6645 printf("Kernel NEXTQSCB = %d\n", ahc->next_queued_scb->hscb->tag);
6646 printf("Card NEXTQSCB = %d\n", ahc_inb(ahc, NEXT_QUEUED_SCB));
6647 /* QINFIFO */
6648 printf("QINFIFO entries: ");
6649 if ((ahc->features & AHC_QUEUE_REGS) != 0) {
6650 qinpos = ahc_inb(ahc, SNSCB_QOFF);
6651 ahc_outb(ahc, SNSCB_QOFF, qinpos);
6652 } else
6653 qinpos = ahc_inb(ahc, QINPOS);
6654 qintail = ahc->qinfifonext;
6655 while (qinpos != qintail) {
6656 printf("%d ", ahc->qinfifo[qinpos]);
6657 qinpos++;
6658 }
6659 printf("\n");
6660
6661 printf("Waiting Queue entries: ");
6662 scb_index = ahc_inb(ahc, WAITING_SCBH);
6663 i = 0;
6664 while (scb_index != SCB_LIST_NULL && i++ < 256) {
6665 ahc_outb(ahc, SCBPTR, scb_index);
6666 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG));
6667 scb_index = ahc_inb(ahc, SCB_NEXT);
6668 }
6669 printf("\n");
6670
6671 printf("Disconnected Queue entries: ");
6672 scb_index = ahc_inb(ahc, DISCONNECTED_SCBH);
6673 i = 0;
6674 while (scb_index != SCB_LIST_NULL && i++ < 256) {
6675 ahc_outb(ahc, SCBPTR, scb_index);
6676 printf("%d:%d ", scb_index, ahc_inb(ahc, SCB_TAG));
6677 scb_index = ahc_inb(ahc, SCB_NEXT);
6678 }
6679 printf("\n");
6680
6681 ahc_sync_qoutfifo(ahc, BUS_DMASYNC_POSTREAD);
6682 printf("QOUTFIFO entries: ");
6683 qoutpos = ahc->qoutfifonext;
6684 i = 0;
6685 while (ahc->qoutfifo[qoutpos] != SCB_LIST_NULL && i++ < 256) {
6686 printf("%d ", ahc->qoutfifo[qoutpos]);
6687 qoutpos++;
6688 }
6689 printf("\n");
6690
6691 printf("Sequencer Free SCB List: ");
6692 scb_index = ahc_inb(ahc, FREE_SCBH);
6693 i = 0;
6694 while (scb_index != SCB_LIST_NULL && i++ < 256) {
6695 ahc_outb(ahc, SCBPTR, scb_index);
6696 printf("%d ", scb_index);
6697 scb_index = ahc_inb(ahc, SCB_NEXT);
6698 }
6699 printf("\n");
6700
6701 printf("Sequencer SCB Info: ");
6702 for (i = 0; i < ahc->scb_data->maxhscbs; i++) {
6703 ahc_outb(ahc, SCBPTR, i);
6704 cur_col = printf("\n%3d ", i);
6705
6706 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL), &cur_col, 60);
6707 ahc_scb_scsiid_print(ahc_inb(ahc, SCB_SCSIID), &cur_col, 60);
6708 ahc_scb_lun_print(ahc_inb(ahc, SCB_LUN), &cur_col, 60);
6709 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60);
6710 }
6711 printf("\n");
6712
6713 printf("Pending list: ");
6714 i = 0;
6715 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) {
6716 if (i++ > 256)
6717 break;
6718 cur_col = printf("\n%3d ", scb->hscb->tag);
6719 ahc_scb_control_print(scb->hscb->control, &cur_col, 60);
6720 ahc_scb_scsiid_print(scb->hscb->scsiid, &cur_col, 60);
6721 ahc_scb_lun_print(scb->hscb->lun, &cur_col, 60);
6722 if ((ahc->flags & AHC_PAGESCBS) == 0) {
6723 ahc_outb(ahc, SCBPTR, scb->hscb->tag);
6724 printf("(");
6725 ahc_scb_control_print(ahc_inb(ahc, SCB_CONTROL),
6726 &cur_col, 60);
6727 ahc_scb_tag_print(ahc_inb(ahc, SCB_TAG), &cur_col, 60);
6728 printf(")");
6729 }
6730 }
6731 printf("\n");
6732
6733 printf("Kernel Free SCB list: ");
6734 i = 0;
6735 SLIST_FOREACH(scb, &ahc->scb_data->free_scbs, links.sle) {
6736 if (i++ > 256)
6737 break;
6738 printf("%d ", scb->hscb->tag);
6739 }
6740 printf("\n");
6741
6742 maxtarget = (ahc->features & (AHC_WIDE|AHC_TWIN)) ? 15 : 7;
6743 for (target = 0; target <= maxtarget; target++) {
6744 untagged_q = &ahc->untagged_queues[target];
6745 if (TAILQ_FIRST(untagged_q) == NULL)
6746 continue;
6747 printf("Untagged Q(%d): ", target);
6748 i = 0;
6749 TAILQ_FOREACH(scb, untagged_q, links.tqe) {
6750 if (i++ > 256)
6751 break;
6752 printf("%d ", scb->hscb->tag);
6753 }
6754 printf("\n");
6755 }
6756
6757 ahc_platform_dump_card_state(ahc);
6758 printf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n");
6759 ahc_outb(ahc, SCBPTR, saved_scbptr);
6760 if (paused == 0)
6761 ahc_unpause(ahc);
6762 }
6763
6764 /************************* Target Mode ****************************************/
6765 #ifdef AHC_TARGET_MODE
6766 cam_status
6767 ahc_find_tmode_devs(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb,
6768 struct ahc_tmode_tstate **tstate,
6769 struct ahc_tmode_lstate **lstate,
6770 int notfound_failure)
6771 {
6772
6773 if ((ahc->features & AHC_TARGETMODE) == 0)
6774 return (CAM_REQ_INVALID);
6775
6776 /*
6777 * Handle the 'black hole' device that sucks up
6778 * requests to unattached luns on enabled targets.
6779 */
6780 if (ccb->ccb_h.target_id == CAM_TARGET_WILDCARD
6781 && ccb->ccb_h.target_lun == CAM_LUN_WILDCARD) {
6782 *tstate = NULL;
6783 *lstate = ahc->black_hole;
6784 } else {
6785 u_int max_id;
6786
6787 max_id = (ahc->features & AHC_WIDE) ? 15 : 7;
6788 if (ccb->ccb_h.target_id > max_id)
6789 return (CAM_TID_INVALID);
6790
6791 if (ccb->ccb_h.target_lun >= AHC_NUM_LUNS)
6792 return (CAM_LUN_INVALID);
6793
6794 *tstate = ahc->enabled_targets[ccb->ccb_h.target_id];
6795 *lstate = NULL;
6796 if (*tstate != NULL)
6797 *lstate =
6798 (*tstate)->enabled_luns[ccb->ccb_h.target_lun];
6799 }
6800
6801 if (notfound_failure != 0 && *lstate == NULL)
6802 return (CAM_PATH_INVALID);
6803
6804 return (CAM_REQ_CMP);
6805 }
6806
6807 void
6808 ahc_handle_en_lun(struct ahc_softc *ahc, struct cam_sim *sim, union ccb *ccb)
6809 {
6810 struct ahc_tmode_tstate *tstate;
6811 struct ahc_tmode_lstate *lstate;
6812 struct ccb_en_lun *cel;
6813 cam_status status;
6814 u_long s;
6815 u_int target;
6816 u_int lun;
6817 u_int target_mask;
6818 u_int our_id;
6819 int error;
6820 char channel;
6821
6822 status = ahc_find_tmode_devs(ahc, sim, ccb, &tstate, &lstate,
6823 /*notfound_failure*/FALSE);
6824
6825 if (status != CAM_REQ_CMP) {
6826 ccb->ccb_h.status = status;
6827 return;
6828 }
6829
6830 if (cam_sim_bus(sim) == 0)
6831 our_id = ahc->our_id;
6832 else
6833 our_id = ahc->our_id_b;
6834
6835 if (ccb->ccb_h.target_id != our_id) {
6836 /*
6837 * our_id represents our initiator ID, or
6838 * the ID of the first target to have an
6839 * enabled lun in target mode. There are
6840 * two cases that may preclude enabling a
6841 * target id other than our_id.
6842 *
6843 * o our_id is for an active initiator role.
6844 * Since the hardware does not support
6845 * reselections to the initiator role at
6846 * anything other than our_id, and our_id
6847 * is used by the hardware to indicate the
6848 * ID to use for both select-out and
6849 * reselect-out operations, the only target
6850 * ID we can support in this mode is our_id.
6851 *
6852 * o The MULTARGID feature is not available and
6853 * a previous target mode ID has been enabled.
6854 */
6855 if ((ahc->features & AHC_MULTIROLE) != 0) {
6856
6857 if ((ahc->features & AHC_MULTI_TID) != 0
6858 && (ahc->flags & AHC_INITIATORROLE) != 0) {
6859 /*
6860 * Only allow additional targets if
6861 * the initiator role is disabled.
6862 * The hardware cannot handle a re-select-in
6863 * on the initiator id during a re-select-out
6864 * on a different target id.
6865 */
6866 status = CAM_TID_INVALID;
6867 } else if ((ahc->flags & AHC_INITIATORROLE) != 0
6868 || ahc->enabled_luns > 0) {
6869 /*
6870 * Only allow our target id to change
6871 * if the initiator role is not configured
6872 * and there are no enabled luns which
6873 * are attached to the currently registered
6874 * scsi id.
6875 */
6876 status = CAM_TID_INVALID;
6877 }
6878 } else if ((ahc->features & AHC_MULTI_TID) == 0
6879 && ahc->enabled_luns > 0) {
6880
6881 status = CAM_TID_INVALID;
6882 }
6883 }
6884
6885 if (status != CAM_REQ_CMP) {
6886 ccb->ccb_h.status = status;
6887 return;
6888 }
6889
6890 /*
6891 * We now have an id that is valid.
6892 * If we aren't in target mode, switch modes.
6893 */
6894 if ((ahc->flags & AHC_TARGETROLE) == 0
6895 && ccb->ccb_h.target_id != CAM_TARGET_WILDCARD) {
6896 u_long s;
6897 ahc_flag saved_flags;
6898
6899 printf("Configuring Target Mode\n");
6900 ahc_lock(ahc, &s);
6901 if (LIST_FIRST(&ahc->pending_scbs) != NULL) {
6902 ccb->ccb_h.status = CAM_BUSY;
6903 ahc_unlock(ahc, &s);
6904 return;
6905 }
6906 saved_flags = ahc->flags;
6907 ahc->flags |= AHC_TARGETROLE;
6908 if ((ahc->features & AHC_MULTIROLE) == 0)
6909 ahc->flags &= ~AHC_INITIATORROLE;
6910 ahc_pause(ahc);
6911 error = ahc_loadseq(ahc);
6912 if (error != 0) {
6913 /*
6914 * Restore original configuration and notify
6915 * the caller that we cannot support target mode.
6916 * Since the adapter started out in this
6917 * configuration, the firmware load will succeed,
6918 * so there is no point in checking ahc_loadseq's
6919 * return value.
6920 */
6921 ahc->flags = saved_flags;
6922 (void)ahc_loadseq(ahc);
6923 ahc_restart(ahc);
6924 ahc_unlock(ahc, &s);
6925 ccb->ccb_h.status = CAM_FUNC_NOTAVAIL;
6926 return;
6927 }
6928 ahc_restart(ahc);
6929 ahc_unlock(ahc, &s);
6930 }
6931 cel = &ccb->cel;
6932 target = ccb->ccb_h.target_id;
6933 lun = ccb->ccb_h.target_lun;
6934 channel = SIM_CHANNEL(ahc, sim);
6935 target_mask = 0x01 << target;
6936 if (channel == 'B')
6937 target_mask <<= 8;
6938
6939 if (cel->enable != 0) {
6940 u_int scsiseq;
6941
6942 /* Are we already enabled?? */
6943 if (lstate != NULL) {
6944 xpt_print_path(ccb->ccb_h.path);
6945 printf("Lun already enabled\n");
6946 ccb->ccb_h.status = CAM_LUN_ALRDY_ENA;
6947 return;
6948 }
6949
6950 if (cel->grp6_len != 0
6951 || cel->grp7_len != 0) {
6952 /*
6953 * Don't (yet?) support vendor
6954 * specific commands.
6955 */
6956 ccb->ccb_h.status = CAM_REQ_INVALID;
6957 printf("Non-zero Group Codes\n");
6958 return;
6959 }
6960
6961 /*
6962 * Seems to be okay.
6963 * Setup our data structures.
6964 */
6965 if (target != CAM_TARGET_WILDCARD && tstate == NULL) {
6966 tstate = ahc_alloc_tstate(ahc, target, channel);
6967 if (tstate == NULL) {
6968 xpt_print_path(ccb->ccb_h.path);
6969 printf("Couldn't allocate tstate\n");
6970 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
6971 return;
6972 }
6973 }
6974 lstate = malloc(sizeof(*lstate), M_DEVBUF, M_NOWAIT);
6975 if (lstate == NULL) {
6976 xpt_print_path(ccb->ccb_h.path);
6977 printf("Couldn't allocate lstate\n");
6978 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
6979 return;
6980 }
6981 memset(lstate, 0, sizeof(*lstate));
6982 status = xpt_create_path(&lstate->path, /*periph*/NULL,
6983 xpt_path_path_id(ccb->ccb_h.path),
6984 xpt_path_target_id(ccb->ccb_h.path),
6985 xpt_path_lun_id(ccb->ccb_h.path));
6986 if (status != CAM_REQ_CMP) {
6987 free(lstate, M_DEVBUF);
6988 xpt_print_path(ccb->ccb_h.path);
6989 printf("Couldn't allocate path\n");
6990 ccb->ccb_h.status = CAM_RESRC_UNAVAIL;
6991 return;
6992 }
6993 SLIST_INIT(&lstate->accept_tios);
6994 SLIST_INIT(&lstate->immed_notifies);
6995 ahc_lock(ahc, &s);
6996 ahc_pause(ahc);
6997 if (target != CAM_TARGET_WILDCARD) {
6998 tstate->enabled_luns[lun] = lstate;
6999 ahc->enabled_luns++;
7000
7001 if ((ahc->features & AHC_MULTI_TID) != 0) {
7002 u_int targid_mask;
7003
7004 targid_mask = ahc_inb(ahc, TARGID)
7005 | (ahc_inb(ahc, TARGID + 1) << 8);
7006
7007 targid_mask |= target_mask;
7008 ahc_outb(ahc, TARGID, targid_mask);
7009 ahc_outb(ahc, TARGID+1, (targid_mask >> 8));
7010
7011 ahc_update_scsiid(ahc, targid_mask);
7012 } else {
7013 u_int our_id;
7014 char channel;
7015
7016 channel = SIM_CHANNEL(ahc, sim);
7017 our_id = SIM_SCSI_ID(ahc, sim);
7018
7019 /*
7020 * This can only happen if selections
7021 * are not enabled
7022 */
7023 if (target != our_id) {
7024 u_int sblkctl;
7025 char cur_channel;
7026 int swap;
7027
7028 sblkctl = ahc_inb(ahc, SBLKCTL);
7029 cur_channel = (sblkctl & SELBUSB)
7030 ? 'B' : 'A';
7031 if ((ahc->features & AHC_TWIN) == 0)
7032 cur_channel = 'A';
7033 swap = cur_channel != channel;
7034 if (channel == 'A')
7035 ahc->our_id = target;
7036 else
7037 ahc->our_id_b = target;
7038
7039 if (swap)
7040 ahc_outb(ahc, SBLKCTL,
7041 sblkctl ^ SELBUSB);
7042
7043 ahc_outb(ahc, SCSIID, target);
7044
7045 if (swap)
7046 ahc_outb(ahc, SBLKCTL, sblkctl);
7047 }
7048 }
7049 } else
7050 ahc->black_hole = lstate;
7051 /* Allow select-in operations */
7052 if (ahc->black_hole != NULL && ahc->enabled_luns > 0) {
7053 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
7054 scsiseq |= ENSELI;
7055 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq);
7056 scsiseq = ahc_inb(ahc, SCSISEQ);
7057 scsiseq |= ENSELI;
7058 ahc_outb(ahc, SCSISEQ, scsiseq);
7059 }
7060 ahc_unpause(ahc);
7061 ahc_unlock(ahc, &s);
7062 ccb->ccb_h.status = CAM_REQ_CMP;
7063 xpt_print_path(ccb->ccb_h.path);
7064 printf("Lun now enabled for target mode\n");
7065 } else {
7066 struct scb *scb;
7067 int i, empty;
7068
7069 if (lstate == NULL) {
7070 ccb->ccb_h.status = CAM_LUN_INVALID;
7071 return;
7072 }
7073
7074 ahc_lock(ahc, &s);
7075
7076 ccb->ccb_h.status = CAM_REQ_CMP;
7077 LIST_FOREACH(scb, &ahc->pending_scbs, pending_links) {
7078 struct ccb_hdr *ccbh;
7079
7080 ccbh = &scb->io_ctx->ccb_h;
7081 if (ccbh->func_code == XPT_CONT_TARGET_IO
7082 && !xpt_path_comp(ccbh->path, ccb->ccb_h.path)){
7083 printf("CTIO pending\n");
7084 ccb->ccb_h.status = CAM_REQ_INVALID;
7085 ahc_unlock(ahc, &s);
7086 return;
7087 }
7088 }
7089
7090 if (SLIST_FIRST(&lstate->accept_tios) != NULL) {
7091 printf("ATIOs pending\n");
7092 ccb->ccb_h.status = CAM_REQ_INVALID;
7093 }
7094
7095 if (SLIST_FIRST(&lstate->immed_notifies) != NULL) {
7096 printf("INOTs pending\n");
7097 ccb->ccb_h.status = CAM_REQ_INVALID;
7098 }
7099
7100 if (ccb->ccb_h.status != CAM_REQ_CMP) {
7101 ahc_unlock(ahc, &s);
7102 return;
7103 }
7104
7105 xpt_print_path(ccb->ccb_h.path);
7106 printf("Target mode disabled\n");
7107 xpt_free_path(lstate->path);
7108 free(lstate, M_DEVBUF);
7109
7110 ahc_pause(ahc);
7111 /* Can we clean up the target too? */
7112 if (target != CAM_TARGET_WILDCARD) {
7113 tstate->enabled_luns[lun] = NULL;
7114 ahc->enabled_luns--;
7115 for (empty = 1, i = 0; i < 8; i++)
7116 if (tstate->enabled_luns[i] != NULL) {
7117 empty = 0;
7118 break;
7119 }
7120
7121 if (empty) {
7122 ahc_free_tstate(ahc, target, channel,
7123 /*force*/FALSE);
7124 if (ahc->features & AHC_MULTI_TID) {
7125 u_int targid_mask;
7126
7127 targid_mask = ahc_inb(ahc, TARGID)
7128 | (ahc_inb(ahc, TARGID + 1)
7129 << 8);
7130
7131 targid_mask &= ~target_mask;
7132 ahc_outb(ahc, TARGID, targid_mask);
7133 ahc_outb(ahc, TARGID+1,
7134 (targid_mask >> 8));
7135 ahc_update_scsiid(ahc, targid_mask);
7136 }
7137 }
7138 } else {
7139
7140 ahc->black_hole = NULL;
7141
7142 /*
7143 * We can't allow selections without
7144 * our black hole device.
7145 */
7146 empty = TRUE;
7147 }
7148 if (ahc->enabled_luns == 0) {
7149 /* Disallow select-in */
7150 u_int scsiseq;
7151
7152 scsiseq = ahc_inb(ahc, SCSISEQ_TEMPLATE);
7153 scsiseq &= ~ENSELI;
7154 ahc_outb(ahc, SCSISEQ_TEMPLATE, scsiseq);
7155 scsiseq = ahc_inb(ahc, SCSISEQ);
7156 scsiseq &= ~ENSELI;
7157 ahc_outb(ahc, SCSISEQ, scsiseq);
7158
7159 if ((ahc->features & AHC_MULTIROLE) == 0) {
7160 printf("Configuring Initiator Mode\n");
7161 ahc->flags &= ~AHC_TARGETROLE;
7162 ahc->flags |= AHC_INITIATORROLE;
7163 /*
7164 * Returning to a configuration that
7165 * fit previously will always succeed.
7166 */
7167 (void)ahc_loadseq(ahc);
7168 ahc_restart(ahc);
7169 /*
7170 * Unpaused. The extra unpause
7171 * that follows is harmless.
7172 */
7173 }
7174 }
7175 ahc_unpause(ahc);
7176 ahc_unlock(ahc, &s);
7177 }
7178 }
7179
7180 static void
7181 ahc_update_scsiid(struct ahc_softc *ahc, u_int targid_mask)
7182 {
7183 u_int scsiid_mask;
7184 u_int scsiid;
7185
7186 if ((ahc->features & AHC_MULTI_TID) == 0)
7187 panic("ahc_update_scsiid called on non-multitid unit\n");
7188
7189 /*
7190 * Since we will rely on the TARGID mask
7191 * for selection enables, ensure that OID
7192 * in SCSIID is not set to some other ID
7193 * that we don't want to allow selections on.
7194 */
7195 if ((ahc->features & AHC_ULTRA2) != 0)
7196 scsiid = ahc_inb(ahc, SCSIID_ULTRA2);
7197 else
7198 scsiid = ahc_inb(ahc, SCSIID);
7199 scsiid_mask = 0x1 << (scsiid & OID);
7200 if ((targid_mask & scsiid_mask) == 0) {
7201 u_int our_id;
7202
7203 /* ffs counts from 1 */
7204 our_id = ffs(targid_mask);
7205 if (our_id == 0)
7206 our_id = ahc->our_id;
7207 else
7208 our_id--;
7209 scsiid &= TID;
7210 scsiid |= our_id;
7211 }
7212 if ((ahc->features & AHC_ULTRA2) != 0)
7213 ahc_outb(ahc, SCSIID_ULTRA2, scsiid);
7214 else
7215 ahc_outb(ahc, SCSIID, scsiid);
7216 }
7217
7218 void
7219 ahc_run_tqinfifo(struct ahc_softc *ahc, int paused)
7220 {
7221 struct target_cmd *cmd;
7222
7223 /*
7224 * If the card supports auto-access pause,
7225 * we can access the card directly regardless
7226 * of whether it is paused or not.
7227 */
7228 if ((ahc->features & AHC_AUTOPAUSE) != 0)
7229 paused = TRUE;
7230
7231 ahc_sync_tqinfifo(ahc, BUS_DMASYNC_POSTREAD);
7232 while ((cmd = &ahc->targetcmds[ahc->tqinfifonext])->cmd_valid != 0) {
7233
7234 /*
7235 * Only advance through the queue if we
7236 * have the resources to process the command.
7237 */
7238 if (ahc_handle_target_cmd(ahc, cmd) != 0)
7239 break;
7240
7241 cmd->cmd_valid = 0;
7242 ahc_dmamap_sync(ahc, ahc->shared_data_dmat,
7243 ahc->shared_data_dmamap,
7244 ahc_targetcmd_offset(ahc, ahc->tqinfifonext),
7245 sizeof(struct target_cmd),
7246 BUS_DMASYNC_PREREAD);
7247 ahc->tqinfifonext++;
7248
7249 /*
7250 * Lazily update our position in the target mode incoming
7251 * command queue as seen by the sequencer.
7252 */
7253 if ((ahc->tqinfifonext & (HOST_TQINPOS - 1)) == 1) {
7254 if ((ahc->features & AHC_HS_MAILBOX) != 0) {
7255 u_int hs_mailbox;
7256
7257 hs_mailbox = ahc_inb(ahc, HS_MAILBOX);
7258 hs_mailbox &= ~HOST_TQINPOS;
7259 hs_mailbox |= ahc->tqinfifonext & HOST_TQINPOS;
7260 ahc_outb(ahc, HS_MAILBOX, hs_mailbox);
7261 } else {
7262 if (!paused)
7263 ahc_pause(ahc);
7264 ahc_outb(ahc, KERNEL_TQINPOS,
7265 ahc->tqinfifonext & HOST_TQINPOS);
7266 if (!paused)
7267 ahc_unpause(ahc);
7268 }
7269 }
7270 }
7271 }
7272
7273 static int
7274 ahc_handle_target_cmd(struct ahc_softc *ahc, struct target_cmd *cmd)
7275 {
7276 struct ahc_tmode_tstate *tstate;
7277 struct ahc_tmode_lstate *lstate;
7278 struct ccb_accept_tio *atio;
7279 uint8_t *byte;
7280 int initiator;
7281 int target;
7282 int lun;
7283
7284 initiator = SCSIID_TARGET(ahc, cmd->scsiid);
7285 target = SCSIID_OUR_ID(cmd->scsiid);
7286 lun = (cmd->identify & MSG_IDENTIFY_LUNMASK);
7287
7288 byte = cmd->bytes;
7289 tstate = ahc->enabled_targets[target];
7290 lstate = NULL;
7291 if (tstate != NULL)
7292 lstate = tstate->enabled_luns[lun];
7293
7294 /*
7295 * Commands for disabled luns go to the black hole driver.
7296 */
7297 if (lstate == NULL)
7298 lstate = ahc->black_hole;
7299
7300 atio = (struct ccb_accept_tio*)SLIST_FIRST(&lstate->accept_tios);
7301 if (atio == NULL) {
7302 ahc->flags |= AHC_TQINFIFO_BLOCKED;
7303 /*
7304 * Wait for more ATIOs from the peripheral driver for this lun.
7305 */
7306 if (bootverbose)
7307 printf("%s: ATIOs exhausted\n", ahc_name(ahc));
7308 return (1);
7309 } else
7310 ahc->flags &= ~AHC_TQINFIFO_BLOCKED;
7311 #if 0
7312 printf("Incoming command from %d for %d:%d%s\n",
7313 initiator, target, lun,
7314 lstate == ahc->black_hole ? "(Black Holed)" : "");
7315 #endif
7316 SLIST_REMOVE_HEAD(&lstate->accept_tios, sim_links.sle);
7317
7318 if (lstate == ahc->black_hole) {
7319 /* Fill in the wildcards */
7320 atio->ccb_h.target_id = target;
7321 atio->ccb_h.target_lun = lun;
7322 }
7323
7324 /*
7325 * Package it up and send it off to
7326 * whomever has this lun enabled.
7327 */
7328 atio->sense_len = 0;
7329 atio->init_id = initiator;
7330 if (byte[0] != 0xFF) {
7331 /* Tag was included */
7332 atio->tag_action = *byte++;
7333 atio->tag_id = *byte++;
7334 atio->ccb_h.flags = CAM_TAG_ACTION_VALID;
7335 } else {
7336 atio->ccb_h.flags = 0;
7337 }
7338 byte++;
7339
7340 /* Okay. Now determine the cdb size based on the command code */
7341 switch (*byte >> CMD_GROUP_CODE_SHIFT) {
7342 case 0:
7343 atio->cdb_len = 6;
7344 break;
7345 case 1:
7346 case 2:
7347 atio->cdb_len = 10;
7348 break;
7349 case 4:
7350 atio->cdb_len = 16;
7351 break;
7352 case 5:
7353 atio->cdb_len = 12;
7354 break;
7355 case 3:
7356 default:
7357 /* Only copy the opcode. */
7358 atio->cdb_len = 1;
7359 printf("Reserved or VU command code type encountered\n");
7360 break;
7361 }
7362
7363 memcpy(atio->cdb_io.cdb_bytes, byte, atio->cdb_len);
7364
7365 atio->ccb_h.status |= CAM_CDB_RECVD;
7366
7367 if ((cmd->identify & MSG_IDENTIFY_DISCFLAG) == 0) {
7368 /*
7369 * We weren't allowed to disconnect.
7370 * We're hanging on the bus until a
7371 * continue target I/O comes in response
7372 * to this accept tio.
7373 */
7374 #if 0
7375 printf("Received Immediate Command %d:%d:%d - %p\n",
7376 initiator, target, lun, ahc->pending_device);
7377 #endif
7378 ahc->pending_device = lstate;
7379 ahc_freeze_ccb((union ccb *)atio);
7380 atio->ccb_h.flags |= CAM_DIS_DISCONNECT;
7381 }
7382 xpt_done((union ccb*)atio);
7383 return (0);
7384 }
7385
7386 #endif
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