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[PATCH] W1: w1_netlink: New init/fini netlink callbacks.
[linux-2.6/verdex.git] / drivers / scsi / ata_piix.c
blob5f868852904149645e559ff2ac7c7ec2dd432756
1 /*
2 * ata_piix.c - Intel PATA/SATA controllers
3 *
4 * Maintained by: Jeff Garzik <jgarzik@pobox.com>
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 *
9 * Copyright 2003-2005 Red Hat Inc
10 * Copyright 2003-2005 Jeff Garzik
11 *
12 *
13 * Copyright header from piix.c:
14 *
15 * Copyright (C) 1998-1999 Andrzej Krzysztofowicz, Author and Maintainer
16 * Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
17 * Copyright (C) 2003 Red Hat Inc <alan@redhat.com>
18 *
19 *
20 * This program is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2, or (at your option)
23 * any later version.
24 *
25 * This program is distributed in the hope that it will be useful,
26 * but WITHOUT ANY WARRANTY; without even the implied warranty of
27 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
28 * GNU General Public License for more details.
29 *
30 * You should have received a copy of the GNU General Public License
31 * along with this program; see the file COPYING. If not, write to
32 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
33 *
34 *
35 * libata documentation is available via 'make {ps|pdf}docs',
36 * as Documentation/DocBook/libata.*
37 *
38 * Hardware documentation available at http://developer.intel.com/
39 *
40 */
41
42 #include <linux/kernel.h>
43 #include <linux/module.h>
44 #include <linux/pci.h>
45 #include <linux/init.h>
46 #include <linux/blkdev.h>
47 #include <linux/delay.h>
48 #include "scsi.h"
49 #include <scsi/scsi_host.h>
50 #include <linux/libata.h>
51
52 #define DRV_NAME "ata_piix"
53 #define DRV_VERSION "1.04"
54
55 enum {
56 PIIX_IOCFG = 0x54, /* IDE I/O configuration register */
57 ICH5_PMR = 0x90, /* port mapping register */
58 ICH5_PCS = 0x92, /* port control and status */
59 PIIX_SCC = 0x0A, /* sub-class code register */
60
61 PIIX_FLAG_AHCI = (1 << 28), /* AHCI possible */
62 PIIX_FLAG_CHECKINTR = (1 << 29), /* make sure PCI INTx enabled */
63 PIIX_FLAG_COMBINED = (1 << 30), /* combined mode possible */
64
65 /* combined mode. if set, PATA is channel 0.
66 * if clear, PATA is channel 1.
67 */
68 PIIX_COMB_PATA_P0 = (1 << 1),
69 PIIX_COMB = (1 << 2), /* combined mode enabled? */
70
71 PIIX_PORT_ENABLED = (1 << 0),
72 PIIX_PORT_PRESENT = (1 << 4),
73
74 PIIX_80C_PRI = (1 << 5) | (1 << 4),
75 PIIX_80C_SEC = (1 << 7) | (1 << 6),
76
77 ich5_pata = 0,
78 ich5_sata = 1,
79 piix4_pata = 2,
80 ich6_sata = 3,
81 ich6_sata_rm = 4,
82 ich7_sata = 5,
83 esb2_sata = 6,
84
85 PIIX_AHCI_DEVICE = 6,
86 };
87
88 static int piix_init_one (struct pci_dev *pdev,
89 const struct pci_device_id *ent);
90
91 static void piix_pata_phy_reset(struct ata_port *ap);
92 static void piix_sata_phy_reset(struct ata_port *ap);
93 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev);
94 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev);
95
96 static unsigned int in_module_init = 1;
97
98 static struct pci_device_id piix_pci_tbl[] = {
99 #ifdef ATA_ENABLE_PATA
100 { 0x8086, 0x7111, PCI_ANY_ID, PCI_ANY_ID, 0, 0, piix4_pata },
101 { 0x8086, 0x24db, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
102 { 0x8086, 0x25a2, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_pata },
103 #endif
104
105 /* NOTE: The following PCI ids must be kept in sync with the
106 * list in drivers/pci/quirks.c.
107 */
108
109 { 0x8086, 0x24d1, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
110 { 0x8086, 0x24df, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
111 { 0x8086, 0x25a3, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
112 { 0x8086, 0x25b0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich5_sata },
113 { 0x8086, 0x2651, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata },
114 { 0x8086, 0x2652, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_rm },
115 { 0x8086, 0x2653, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich6_sata_rm },
116 { 0x8086, 0x27c0, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7_sata },
117 { 0x8086, 0x27c4, PCI_ANY_ID, PCI_ANY_ID, 0, 0, ich7_sata },
118 { 0x8086, 0x2680, PCI_ANY_ID, PCI_ANY_ID, 0, 0, esb2_sata },
119
120 { } /* terminate list */
121 };
122
123 static struct pci_driver piix_pci_driver = {
124 .name = DRV_NAME,
125 .id_table = piix_pci_tbl,
126 .probe = piix_init_one,
127 .remove = ata_pci_remove_one,
128 };
129
130 static Scsi_Host_Template piix_sht = {
131 .module = THIS_MODULE,
132 .name = DRV_NAME,
133 .ioctl = ata_scsi_ioctl,
134 .queuecommand = ata_scsi_queuecmd,
135 .eh_strategy_handler = ata_scsi_error,
136 .can_queue = ATA_DEF_QUEUE,
137 .this_id = ATA_SHT_THIS_ID,
138 .sg_tablesize = LIBATA_MAX_PRD,
139 .max_sectors = ATA_MAX_SECTORS,
140 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
141 .emulated = ATA_SHT_EMULATED,
142 .use_clustering = ATA_SHT_USE_CLUSTERING,
143 .proc_name = DRV_NAME,
144 .dma_boundary = ATA_DMA_BOUNDARY,
145 .slave_configure = ata_scsi_slave_config,
146 .bios_param = ata_std_bios_param,
147 .ordered_flush = 1,
148 };
149
150 static struct ata_port_operations piix_pata_ops = {
151 .port_disable = ata_port_disable,
152 .set_piomode = piix_set_piomode,
153 .set_dmamode = piix_set_dmamode,
154
155 .tf_load = ata_tf_load,
156 .tf_read = ata_tf_read,
157 .check_status = ata_check_status,
158 .exec_command = ata_exec_command,
159 .dev_select = ata_std_dev_select,
160
161 .phy_reset = piix_pata_phy_reset,
162
163 .bmdma_setup = ata_bmdma_setup,
164 .bmdma_start = ata_bmdma_start,
165 .bmdma_stop = ata_bmdma_stop,
166 .bmdma_status = ata_bmdma_status,
167 .qc_prep = ata_qc_prep,
168 .qc_issue = ata_qc_issue_prot,
169
170 .eng_timeout = ata_eng_timeout,
171
172 .irq_handler = ata_interrupt,
173 .irq_clear = ata_bmdma_irq_clear,
174
175 .port_start = ata_port_start,
176 .port_stop = ata_port_stop,
177 .host_stop = ata_host_stop,
178 };
179
180 static struct ata_port_operations piix_sata_ops = {
181 .port_disable = ata_port_disable,
182
183 .tf_load = ata_tf_load,
184 .tf_read = ata_tf_read,
185 .check_status = ata_check_status,
186 .exec_command = ata_exec_command,
187 .dev_select = ata_std_dev_select,
188
189 .phy_reset = piix_sata_phy_reset,
190
191 .bmdma_setup = ata_bmdma_setup,
192 .bmdma_start = ata_bmdma_start,
193 .bmdma_stop = ata_bmdma_stop,
194 .bmdma_status = ata_bmdma_status,
195 .qc_prep = ata_qc_prep,
196 .qc_issue = ata_qc_issue_prot,
197
198 .eng_timeout = ata_eng_timeout,
199
200 .irq_handler = ata_interrupt,
201 .irq_clear = ata_bmdma_irq_clear,
202
203 .port_start = ata_port_start,
204 .port_stop = ata_port_stop,
205 .host_stop = ata_host_stop,
206 };
207
208 static struct ata_port_info piix_port_info[] = {
209 /* ich5_pata */
210 {
211 .sht = &piix_sht,
212 .host_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST |
213 PIIX_FLAG_CHECKINTR,
214 .pio_mask = 0x1f, /* pio0-4 */
215 #if 0
216 .mwdma_mask = 0x06, /* mwdma1-2 */
217 #else
218 .mwdma_mask = 0x00, /* mwdma broken */
219 #endif
220 .udma_mask = 0x3f, /* udma0-5 */
221 .port_ops = &piix_pata_ops,
222 },
223
224 /* ich5_sata */
225 {
226 .sht = &piix_sht,
227 .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST |
228 PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR,
229 .pio_mask = 0x1f, /* pio0-4 */
230 .mwdma_mask = 0x07, /* mwdma0-2 */
231 .udma_mask = 0x7f, /* udma0-6 */
232 .port_ops = &piix_sata_ops,
233 },
234
235 /* piix4_pata */
236 {
237 .sht = &piix_sht,
238 .host_flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST,
239 .pio_mask = 0x1f, /* pio0-4 */
240 #if 0
241 .mwdma_mask = 0x06, /* mwdma1-2 */
242 #else
243 .mwdma_mask = 0x00, /* mwdma broken */
244 #endif
245 .udma_mask = ATA_UDMA_MASK_40C,
246 .port_ops = &piix_pata_ops,
247 },
248
249 /* ich6_sata */
250 {
251 .sht = &piix_sht,
252 .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST |
253 PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR |
254 ATA_FLAG_SLAVE_POSS,
255 .pio_mask = 0x1f, /* pio0-4 */
256 .mwdma_mask = 0x07, /* mwdma0-2 */
257 .udma_mask = 0x7f, /* udma0-6 */
258 .port_ops = &piix_sata_ops,
259 },
260
261 /* ich6_sata_rm */
262 {
263 .sht = &piix_sht,
264 .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST |
265 PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR |
266 ATA_FLAG_SLAVE_POSS | PIIX_FLAG_AHCI,
267 .pio_mask = 0x1f, /* pio0-4 */
268 .mwdma_mask = 0x07, /* mwdma0-2 */
269 .udma_mask = 0x7f, /* udma0-6 */
270 .port_ops = &piix_sata_ops,
271 },
272
273 /* ich7_sata */
274 {
275 .sht = &piix_sht,
276 .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST |
277 PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR |
278 ATA_FLAG_SLAVE_POSS | PIIX_FLAG_AHCI,
279 .pio_mask = 0x1f, /* pio0-4 */
280 .mwdma_mask = 0x07, /* mwdma0-2 */
281 .udma_mask = 0x7f, /* udma0-6 */
282 .port_ops = &piix_sata_ops,
283 },
284
285 /* esb2_sata */
286 {
287 .sht = &piix_sht,
288 .host_flags = ATA_FLAG_SATA | ATA_FLAG_SRST |
289 PIIX_FLAG_COMBINED | PIIX_FLAG_CHECKINTR |
290 ATA_FLAG_SLAVE_POSS | PIIX_FLAG_AHCI,
291 .pio_mask = 0x1f, /* pio0-4 */
292 .mwdma_mask = 0x07, /* mwdma0-2 */
293 .udma_mask = 0x7f, /* udma0-6 */
294 .port_ops = &piix_sata_ops,
295 },
296 };
297
298 static struct pci_bits piix_enable_bits[] = {
299 { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */
300 { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */
301 };
302
303 MODULE_AUTHOR("Andre Hedrick, Alan Cox, Andrzej Krzysztofowicz, Jeff Garzik");
304 MODULE_DESCRIPTION("SCSI low-level driver for Intel PIIX/ICH ATA controllers");
305 MODULE_LICENSE("GPL");
306 MODULE_DEVICE_TABLE(pci, piix_pci_tbl);
307 MODULE_VERSION(DRV_VERSION);
308
309 /**
310 * piix_pata_cbl_detect - Probe host controller cable detect info
311 * @ap: Port for which cable detect info is desired
312 *
313 * Read 80c cable indicator from ATA PCI device's PCI config
314 * register. This register is normally set by firmware (BIOS).
315 *
316 * LOCKING:
317 * None (inherited from caller).
318 */
319 static void piix_pata_cbl_detect(struct ata_port *ap)
320 {
321 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
322 u8 tmp, mask;
323
324 /* no 80c support in host controller? */
325 if ((ap->udma_mask & ~ATA_UDMA_MASK_40C) == 0)
326 goto cbl40;
327
328 /* check BIOS cable detect results */
329 mask = ap->hard_port_no == 0 ? PIIX_80C_PRI : PIIX_80C_SEC;
330 pci_read_config_byte(pdev, PIIX_IOCFG, &tmp);
331 if ((tmp & mask) == 0)
332 goto cbl40;
333
334 ap->cbl = ATA_CBL_PATA80;
335 return;
336
337 cbl40:
338 ap->cbl = ATA_CBL_PATA40;
339 ap->udma_mask &= ATA_UDMA_MASK_40C;
340 }
341
342 /**
343 * piix_pata_phy_reset - Probe specified port on PATA host controller
344 * @ap: Port to probe
345 *
346 * Probe PATA phy.
347 *
348 * LOCKING:
349 * None (inherited from caller).
350 */
351
352 static void piix_pata_phy_reset(struct ata_port *ap)
353 {
354 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
355
356 if (!pci_test_config_bits(pdev, &piix_enable_bits[ap->hard_port_no])) {
357 ata_port_disable(ap);
358 printk(KERN_INFO "ata%u: port disabled. ignoring.\n", ap->id);
359 return;
360 }
361
362 piix_pata_cbl_detect(ap);
363
364 ata_port_probe(ap);
365
366 ata_bus_reset(ap);
367 }
368
369 /**
370 * piix_sata_probe - Probe PCI device for present SATA devices
371 * @ap: Port associated with the PCI device we wish to probe
372 *
373 * Reads SATA PCI device's PCI config register Port Configuration
374 * and Status (PCS) to determine port and device availability.
375 *
376 * LOCKING:
377 * None (inherited from caller).
378 *
379 * RETURNS:
380 * Non-zero if port is enabled, it may or may not have a device
381 * attached in that case (PRESENT bit would only be set if BIOS probe
382 * was done). Zero is returned if port is disabled.
383 */
384 static int piix_sata_probe (struct ata_port *ap)
385 {
386 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
387 int combined = (ap->flags & ATA_FLAG_SLAVE_POSS);
388 int orig_mask, mask, i;
389 u8 pcs;
390
391 mask = (PIIX_PORT_PRESENT << ap->hard_port_no) |
392 (PIIX_PORT_ENABLED << ap->hard_port_no);
393
394 pci_read_config_byte(pdev, ICH5_PCS, &pcs);
395 orig_mask = (int) pcs & 0xff;
396
397 /* TODO: this is vaguely wrong for ICH6 combined mode,
398 * where only two of the four SATA ports are mapped
399 * onto a single ATA channel. It is also vaguely inaccurate
400 * for ICH5, which has only two ports. However, this is ok,
401 * as further device presence detection code will handle
402 * any false positives produced here.
403 */
404
405 for (i = 0; i < 4; i++) {
406 mask = (PIIX_PORT_ENABLED << i);
407
408 if ((orig_mask & mask) == mask)
409 if (combined || (i == ap->hard_port_no))
410 return 1;
411 }
412
413 return 0;
414 }
415
416 /**
417 * piix_sata_phy_reset - Probe specified port on SATA host controller
418 * @ap: Port to probe
419 *
420 * Probe SATA phy.
421 *
422 * LOCKING:
423 * None (inherited from caller).
424 */
425
426 static void piix_sata_phy_reset(struct ata_port *ap)
427 {
428 if (!piix_sata_probe(ap)) {
429 ata_port_disable(ap);
430 printk(KERN_INFO "ata%u: SATA port has no device.\n", ap->id);
431 return;
432 }
433
434 ap->cbl = ATA_CBL_SATA;
435
436 ata_port_probe(ap);
437
438 ata_bus_reset(ap);
439 }
440
441 /**
442 * piix_set_piomode - Initialize host controller PATA PIO timings
443 * @ap: Port whose timings we are configuring
444 * @adev: um
445 * @pio: PIO mode, 0 - 4
446 *
447 * Set PIO mode for device, in host controller PCI config space.
448 *
449 * LOCKING:
450 * None (inherited from caller).
451 */
452
453 static void piix_set_piomode (struct ata_port *ap, struct ata_device *adev)
454 {
455 unsigned int pio = adev->pio_mode - XFER_PIO_0;
456 struct pci_dev *dev = to_pci_dev(ap->host_set->dev);
457 unsigned int is_slave = (adev->devno != 0);
458 unsigned int master_port= ap->hard_port_no ? 0x42 : 0x40;
459 unsigned int slave_port = 0x44;
460 u16 master_data;
461 u8 slave_data;
462
463 static const /* ISP RTC */
464 u8 timings[][2] = { { 0, 0 },
465 { 0, 0 },
466 { 1, 0 },
467 { 2, 1 },
468 { 2, 3 }, };
469
470 pci_read_config_word(dev, master_port, &master_data);
471 if (is_slave) {
472 master_data |= 0x4000;
473 /* enable PPE, IE and TIME */
474 master_data |= 0x0070;
475 pci_read_config_byte(dev, slave_port, &slave_data);
476 slave_data &= (ap->hard_port_no ? 0x0f : 0xf0);
477 slave_data |=
478 (timings[pio][0] << 2) |
479 (timings[pio][1] << (ap->hard_port_no ? 4 : 0));
480 } else {
481 master_data &= 0xccf8;
482 /* enable PPE, IE and TIME */
483 master_data |= 0x0007;
484 master_data |=
485 (timings[pio][0] << 12) |
486 (timings[pio][1] << 8);
487 }
488 pci_write_config_word(dev, master_port, master_data);
489 if (is_slave)
490 pci_write_config_byte(dev, slave_port, slave_data);
491 }
492
493 /**
494 * piix_set_dmamode - Initialize host controller PATA PIO timings
495 * @ap: Port whose timings we are configuring
496 * @adev: um
497 * @udma: udma mode, 0 - 6
498 *
499 * Set UDMA mode for device, in host controller PCI config space.
500 *
501 * LOCKING:
502 * None (inherited from caller).
503 */
504
505 static void piix_set_dmamode (struct ata_port *ap, struct ata_device *adev)
506 {
507 unsigned int udma = adev->dma_mode; /* FIXME: MWDMA too */
508 struct pci_dev *dev = to_pci_dev(ap->host_set->dev);
509 u8 maslave = ap->hard_port_no ? 0x42 : 0x40;
510 u8 speed = udma;
511 unsigned int drive_dn = (ap->hard_port_no ? 2 : 0) + adev->devno;
512 int a_speed = 3 << (drive_dn * 4);
513 int u_flag = 1 << drive_dn;
514 int v_flag = 0x01 << drive_dn;
515 int w_flag = 0x10 << drive_dn;
516 int u_speed = 0;
517 int sitre;
518 u16 reg4042, reg4a;
519 u8 reg48, reg54, reg55;
520
521 pci_read_config_word(dev, maslave, &reg4042);
522 DPRINTK("reg4042 = 0x%04x\n", reg4042);
523 sitre = (reg4042 & 0x4000) ? 1 : 0;
524 pci_read_config_byte(dev, 0x48, &reg48);
525 pci_read_config_word(dev, 0x4a, &reg4a);
526 pci_read_config_byte(dev, 0x54, &reg54);
527 pci_read_config_byte(dev, 0x55, &reg55);
528
529 switch(speed) {
530 case XFER_UDMA_4:
531 case XFER_UDMA_2: u_speed = 2 << (drive_dn * 4); break;
532 case XFER_UDMA_6:
533 case XFER_UDMA_5:
534 case XFER_UDMA_3:
535 case XFER_UDMA_1: u_speed = 1 << (drive_dn * 4); break;
536 case XFER_UDMA_0: u_speed = 0 << (drive_dn * 4); break;
537 case XFER_MW_DMA_2:
538 case XFER_MW_DMA_1: break;
539 default:
540 BUG();
541 return;
542 }
543
544 if (speed >= XFER_UDMA_0) {
545 if (!(reg48 & u_flag))
546 pci_write_config_byte(dev, 0x48, reg48 | u_flag);
547 if (speed == XFER_UDMA_5) {
548 pci_write_config_byte(dev, 0x55, (u8) reg55|w_flag);
549 } else {
550 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
551 }
552 if ((reg4a & a_speed) != u_speed)
553 pci_write_config_word(dev, 0x4a, (reg4a & ~a_speed) | u_speed);
554 if (speed > XFER_UDMA_2) {
555 if (!(reg54 & v_flag))
556 pci_write_config_byte(dev, 0x54, reg54 | v_flag);
557 } else
558 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
559 } else {
560 if (reg48 & u_flag)
561 pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
562 if (reg4a & a_speed)
563 pci_write_config_word(dev, 0x4a, reg4a & ~a_speed);
564 if (reg54 & v_flag)
565 pci_write_config_byte(dev, 0x54, reg54 & ~v_flag);
566 if (reg55 & w_flag)
567 pci_write_config_byte(dev, 0x55, (u8) reg55 & ~w_flag);
568 }
569 }
570
571 /* move to PCI layer, integrate w/ MSI stuff */
572 static void pci_enable_intx(struct pci_dev *pdev)
573 {
574 u16 pci_command;
575
576 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
577 if (pci_command & PCI_COMMAND_INTX_DISABLE) {
578 pci_command &= ~PCI_COMMAND_INTX_DISABLE;
579 pci_write_config_word(pdev, PCI_COMMAND, pci_command);
580 }
581 }
582
583 #define AHCI_PCI_BAR 5
584 #define AHCI_GLOBAL_CTL 0x04
585 #define AHCI_ENABLE (1 << 31)
586 static int piix_disable_ahci(struct pci_dev *pdev)
587 {
588 void __iomem *mmio;
589 u32 tmp;
590 int rc = 0;
591
592 /* BUG: pci_enable_device has not yet been called. This
593 * works because this device is usually set up by BIOS.
594 */
595
596 if (!pci_resource_start(pdev, AHCI_PCI_BAR) ||
597 !pci_resource_len(pdev, AHCI_PCI_BAR))
598 return 0;
599
600 mmio = pci_iomap(pdev, AHCI_PCI_BAR, 64);
601 if (!mmio)
602 return -ENOMEM;
603
604 tmp = readl(mmio + AHCI_GLOBAL_CTL);
605 if (tmp & AHCI_ENABLE) {
606 tmp &= ~AHCI_ENABLE;
607 writel(tmp, mmio + AHCI_GLOBAL_CTL);
608
609 tmp = readl(mmio + AHCI_GLOBAL_CTL);
610 if (tmp & AHCI_ENABLE)
611 rc = -EIO;
612 }
613
614 pci_iounmap(pdev, mmio);
615 return rc;
616 }
617
618 /**
619 * piix_init_one - Register PIIX ATA PCI device with kernel services
620 * @pdev: PCI device to register
621 * @ent: Entry in piix_pci_tbl matching with @pdev
622 *
623 * Called from kernel PCI layer. We probe for combined mode (sigh),
624 * and then hand over control to libata, for it to do the rest.
625 *
626 * LOCKING:
627 * Inherited from PCI layer (may sleep).
628 *
629 * RETURNS:
630 * Zero on success, or -ERRNO value.
631 */
632
633 static int piix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
634 {
635 static int printed_version;
636 struct ata_port_info *port_info[2];
637 unsigned int combined = 0, n_ports = 1;
638 unsigned int pata_chan = 0, sata_chan = 0;
639
640 if (!printed_version++)
641 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
642
643 /* no hotplugging support (FIXME) */
644 if (!in_module_init)
645 return -ENODEV;
646
647 port_info[0] = &piix_port_info[ent->driver_data];
648 port_info[1] = NULL;
649
650 if (port_info[0]->host_flags & PIIX_FLAG_AHCI) {
651 u8 tmp;
652 pci_read_config_byte(pdev, PIIX_SCC, &tmp);
653 if (tmp == PIIX_AHCI_DEVICE) {
654 int rc = piix_disable_ahci(pdev);
655 if (rc)
656 return rc;
657 }
658 }
659
660 if (port_info[0]->host_flags & PIIX_FLAG_COMBINED) {
661 u8 tmp;
662 pci_read_config_byte(pdev, ICH5_PMR, &tmp);
663
664 if (tmp & PIIX_COMB) {
665 combined = 1;
666 if (tmp & PIIX_COMB_PATA_P0)
667 sata_chan = 1;
668 else
669 pata_chan = 1;
670 }
671 }
672
673 /* On ICH5, some BIOSen disable the interrupt using the
674 * PCI_COMMAND_INTX_DISABLE bit added in PCI 2.3.
675 * On ICH6, this bit has the same effect, but only when
676 * MSI is disabled (and it is disabled, as we don't use
677 * message-signalled interrupts currently).
678 */
679 if (port_info[0]->host_flags & PIIX_FLAG_CHECKINTR)
680 pci_enable_intx(pdev);
681
682 if (combined) {
683 port_info[sata_chan] = &piix_port_info[ent->driver_data];
684 port_info[sata_chan]->host_flags |= ATA_FLAG_SLAVE_POSS;
685 port_info[pata_chan] = &piix_port_info[ich5_pata];
686 n_ports++;
687
688 printk(KERN_WARNING DRV_NAME ": combined mode detected\n");
689 }
690
691 return ata_pci_init_one(pdev, port_info, n_ports);
692 }
693
694 static int __init piix_init(void)
695 {
696 int rc;
697
698 DPRINTK("pci_module_init\n");
699 rc = pci_module_init(&piix_pci_driver);
700 if (rc)
701 return rc;
702
703 in_module_init = 0;
704
705 DPRINTK("done\n");
706 return 0;
707 }
708
709 static void __exit piix_exit(void)
710 {
711 pci_unregister_driver(&piix_pci_driver);
712 }
713
714 module_init(piix_init);
715 module_exit(piix_exit);
716
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