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[PATCH] W1: w1_netlink: New init/fini netlink callbacks.
[linux-2.6/verdex.git] / drivers / scsi / qla2xxx / qla_def.h
blobb455c31405e49bb622191bab04357ccab7277478
1 /********************************************************************************
2 * QLOGIC LINUX SOFTWARE
3 *
4 * QLogic ISP2x00 device driver for Linux 2.6.x
5 * Copyright (C) 2003-2005 QLogic Corporation
6 * (www.qlogic.com)
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2, or (at your option) any
11 * later version.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 **
18 ******************************************************************************/
19
20 #ifndef __QLA_DEF_H
21 #define __QLA_DEF_H
22
23 #include <linux/kernel.h>
24 #include <linux/init.h>
25 #include <linux/types.h>
26 #include <linux/module.h>
27 #include <linux/list.h>
28 #include <linux/pci.h>
29 #include <linux/dma-mapping.h>
30 #include <linux/sched.h>
31 #include <linux/slab.h>
32 #include <linux/dmapool.h>
33 #include <linux/mempool.h>
34 #include <linux/spinlock.h>
35 #include <linux/completion.h>
36 #include <linux/interrupt.h>
37 #include <asm/semaphore.h>
38
39 #include <scsi/scsi.h>
40 #include <scsi/scsi_host.h>
41 #include <scsi/scsi_device.h>
42 #include <scsi/scsi_cmnd.h>
43
44 #if defined(CONFIG_SCSI_QLA21XX) || defined(CONFIG_SCSI_QLA21XX_MODULE)
45 #define IS_QLA2100(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2100)
46 #else
47 #define IS_QLA2100(ha) 0
48 #endif
49
50 #if defined(CONFIG_SCSI_QLA22XX) || defined(CONFIG_SCSI_QLA22XX_MODULE)
51 #define IS_QLA2200(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2200)
52 #else
53 #define IS_QLA2200(ha) 0
54 #endif
55
56 #if defined(CONFIG_SCSI_QLA2300) || defined(CONFIG_SCSI_QLA2300_MODULE)
57 #define IS_QLA2300(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2300)
58 #define IS_QLA2312(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2312)
59 #else
60 #define IS_QLA2300(ha) 0
61 #define IS_QLA2312(ha) 0
62 #endif
63
64 #if defined(CONFIG_SCSI_QLA2322) || defined(CONFIG_SCSI_QLA2322_MODULE)
65 #define IS_QLA2322(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2322)
66 #else
67 #define IS_QLA2322(ha) 0
68 #endif
69
70 #if defined(CONFIG_SCSI_QLA6312) || defined(CONFIG_SCSI_QLA6312_MODULE)
71 #define IS_QLA6312(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP6312)
72 #define IS_QLA6322(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP6322)
73 #else
74 #define IS_QLA6312(ha) 0
75 #define IS_QLA6322(ha) 0
76 #endif
77
78 #if defined(CONFIG_SCSI_QLA24XX) || defined(CONFIG_SCSI_QLA24XX_MODULE)
79 #define IS_QLA2422(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2422)
80 #define IS_QLA2432(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2432)
81 #else
82 #define IS_QLA2422(ha) 0
83 #define IS_QLA2432(ha) 0
84 #endif
85
86 #if defined(CONFIG_SCSI_QLA25XX) || defined(CONFIG_SCSI_QLA25XX_MODULE)
87 #define IS_QLA2512(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2512)
88 #define IS_QLA2522(ha) ((ha)->pdev->device == PCI_DEVICE_ID_QLOGIC_ISP2522)
89 #else
90 #define IS_QLA2512(ha) 0
91 #define IS_QLA2522(ha) 0
92 #endif
93
94 #define IS_QLA23XX(ha) (IS_QLA2300(ha) || IS_QLA2312(ha) || IS_QLA2322(ha) || \
95 IS_QLA6312(ha) || IS_QLA6322(ha))
96
97 #define IS_QLA24XX(ha) (IS_QLA2422(ha) || IS_QLA2432(ha))
98 #define IS_QLA25XX(ha) (IS_QLA2512(ha) || IS_QLA2522(ha))
99
100 /*
101 * Only non-ISP2[12]00 have extended addressing support in the firmware.
102 */
103 #define HAS_EXTENDED_IDS(ha) (!IS_QLA2100(ha) && !IS_QLA2200(ha))
104
105 /*
106 * We have MAILBOX_REGISTER_COUNT sized arrays in a few places,
107 * but that's fine as we don't look at the last 24 ones for
108 * ISP2100 HBAs.
109 */
110 #define MAILBOX_REGISTER_COUNT_2100 8
111 #define MAILBOX_REGISTER_COUNT 32
112
113 #define QLA2200A_RISC_ROM_VER 4
114 #define FPM_2300 6
115 #define FPM_2310 7
116
117 #include "qla_settings.h"
118
119 /*
120 * Data bit definitions
121 */
122 #define BIT_0 0x1
123 #define BIT_1 0x2
124 #define BIT_2 0x4
125 #define BIT_3 0x8
126 #define BIT_4 0x10
127 #define BIT_5 0x20
128 #define BIT_6 0x40
129 #define BIT_7 0x80
130 #define BIT_8 0x100
131 #define BIT_9 0x200
132 #define BIT_10 0x400
133 #define BIT_11 0x800
134 #define BIT_12 0x1000
135 #define BIT_13 0x2000
136 #define BIT_14 0x4000
137 #define BIT_15 0x8000
138 #define BIT_16 0x10000
139 #define BIT_17 0x20000
140 #define BIT_18 0x40000
141 #define BIT_19 0x80000
142 #define BIT_20 0x100000
143 #define BIT_21 0x200000
144 #define BIT_22 0x400000
145 #define BIT_23 0x800000
146 #define BIT_24 0x1000000
147 #define BIT_25 0x2000000
148 #define BIT_26 0x4000000
149 #define BIT_27 0x8000000
150 #define BIT_28 0x10000000
151 #define BIT_29 0x20000000
152 #define BIT_30 0x40000000
153 #define BIT_31 0x80000000
154
155 #define LSB(x) ((uint8_t)(x))
156 #define MSB(x) ((uint8_t)((uint16_t)(x) >> 8))
157
158 #define LSW(x) ((uint16_t)(x))
159 #define MSW(x) ((uint16_t)((uint32_t)(x) >> 16))
160
161 #define LSD(x) ((uint32_t)((uint64_t)(x)))
162 #define MSD(x) ((uint32_t)((((uint64_t)(x)) >> 16) >> 16))
163
164
165 /*
166 * I/O register
167 */
168
169 #define RD_REG_BYTE(addr) readb(addr)
170 #define RD_REG_WORD(addr) readw(addr)
171 #define RD_REG_DWORD(addr) readl(addr)
172 #define RD_REG_BYTE_RELAXED(addr) readb_relaxed(addr)
173 #define RD_REG_WORD_RELAXED(addr) readw_relaxed(addr)
174 #define RD_REG_DWORD_RELAXED(addr) readl_relaxed(addr)
175 #define WRT_REG_BYTE(addr, data) writeb(data,addr)
176 #define WRT_REG_WORD(addr, data) writew(data,addr)
177 #define WRT_REG_DWORD(addr, data) writel(data,addr)
178
179 /*
180 * Fibre Channel device definitions.
181 */
182 #define WWN_SIZE 8 /* Size of WWPN, WWN & WWNN */
183 #define MAX_FIBRE_DEVICES 512
184 #define MAX_FIBRE_LUNS 0xFFFF
185 #define MAX_RSCN_COUNT 32
186 #define MAX_HOST_COUNT 16
187
188 /*
189 * Host adapter default definitions.
190 */
191 #define MAX_BUSES 1 /* We only have one bus today */
192 #define MAX_TARGETS_2100 MAX_FIBRE_DEVICES
193 #define MAX_TARGETS_2200 MAX_FIBRE_DEVICES
194 #define MIN_LUNS 8
195 #define MAX_LUNS MAX_FIBRE_LUNS
196 #define MAX_CMDS_PER_LUN 255
197
198 /*
199 * Fibre Channel device definitions.
200 */
201 #define SNS_LAST_LOOP_ID_2100 0xfe
202 #define SNS_LAST_LOOP_ID_2300 0x7ff
203
204 #define LAST_LOCAL_LOOP_ID 0x7d
205 #define SNS_FL_PORT 0x7e
206 #define FABRIC_CONTROLLER 0x7f
207 #define SIMPLE_NAME_SERVER 0x80
208 #define SNS_FIRST_LOOP_ID 0x81
209 #define MANAGEMENT_SERVER 0xfe
210 #define BROADCAST 0xff
211
212 /*
213 * There is no correspondence between an N-PORT id and an AL_PA. Therefore the
214 * valid range of an N-PORT id is 0 through 0x7ef.
215 */
216 #define NPH_LAST_HANDLE 0x7ef
217 #define NPH_MGMT_SERVER 0x7fa /* FFFFFA */
218 #define NPH_SNS 0x7fc /* FFFFFC */
219 #define NPH_FABRIC_CONTROLLER 0x7fd /* FFFFFD */
220 #define NPH_F_PORT 0x7fe /* FFFFFE */
221 #define NPH_IP_BROADCAST 0x7ff /* FFFFFF */
222
223 #define MAX_CMDSZ 16 /* SCSI maximum CDB size. */
224 #include "qla_fw.h"
225
226 /*
227 * Timeout timer counts in seconds
228 */
229 #define PORT_RETRY_TIME 1
230 #define LOOP_DOWN_TIMEOUT 60
231 #define LOOP_DOWN_TIME 255 /* 240 */
232 #define LOOP_DOWN_RESET (LOOP_DOWN_TIME - 30)
233
234 /* Maximum outstanding commands in ISP queues (1-65535) */
235 #define MAX_OUTSTANDING_COMMANDS 1024
236
237 /* ISP request and response entry counts (37-65535) */
238 #define REQUEST_ENTRY_CNT_2100 128 /* Number of request entries. */
239 #define REQUEST_ENTRY_CNT_2200 2048 /* Number of request entries. */
240 #define REQUEST_ENTRY_CNT_2XXX_EXT_MEM 4096 /* Number of request entries. */
241 #define REQUEST_ENTRY_CNT_24XX 4096 /* Number of request entries. */
242 #define RESPONSE_ENTRY_CNT_2100 64 /* Number of response entries.*/
243 #define RESPONSE_ENTRY_CNT_2300 512 /* Number of response entries.*/
244
245 /*
246 * SCSI Request Block
247 */
248 typedef struct srb {
249 struct list_head list;
250
251 struct scsi_qla_host *ha; /* HA the SP is queued on */
252 struct fc_port *fcport;
253
254 struct scsi_cmnd *cmd; /* Linux SCSI command pkt */
255
256 struct timer_list timer; /* Command timer */
257 atomic_t ref_count; /* Reference count for this structure */
258 uint16_t flags;
259
260 /* Request state */
261 uint16_t state;
262
263 /* Single transfer DMA context */
264 dma_addr_t dma_handle;
265
266 uint32_t request_sense_length;
267 uint8_t *request_sense_ptr;
268
269 /* SRB magic number */
270 uint16_t magic;
271 #define SRB_MAGIC 0x10CB
272 } srb_t;
273
274 /*
275 * SRB flag definitions
276 */
277 #define SRB_TIMEOUT BIT_0 /* Command timed out */
278 #define SRB_DMA_VALID BIT_1 /* Command sent to ISP */
279 #define SRB_WATCHDOG BIT_2 /* Command on watchdog list */
280 #define SRB_ABORT_PENDING BIT_3 /* Command abort sent to device */
281
282 #define SRB_ABORTED BIT_4 /* Command aborted command already */
283 #define SRB_RETRY BIT_5 /* Command needs retrying */
284 #define SRB_GOT_SENSE BIT_6 /* Command has sense data */
285 #define SRB_FAILOVER BIT_7 /* Command in failover state */
286
287 #define SRB_BUSY BIT_8 /* Command is in busy retry state */
288 #define SRB_FO_CANCEL BIT_9 /* Command don't need to do failover */
289 #define SRB_IOCTL BIT_10 /* IOCTL command. */
290 #define SRB_TAPE BIT_11 /* FCP2 (Tape) command. */
291
292 /*
293 * SRB state definitions
294 */
295 #define SRB_FREE_STATE 0 /* returned back */
296 #define SRB_PENDING_STATE 1 /* queued in LUN Q */
297 #define SRB_ACTIVE_STATE 2 /* in Active Array */
298 #define SRB_DONE_STATE 3 /* queued in Done Queue */
299 #define SRB_RETRY_STATE 4 /* in Retry Queue */
300 #define SRB_SUSPENDED_STATE 5 /* in suspended state */
301 #define SRB_NO_QUEUE_STATE 6 /* is in between states */
302 #define SRB_ACTIVE_TIMEOUT_STATE 7 /* in Active Array but timed out */
303 #define SRB_FAILOVER_STATE 8 /* in Failover Queue */
304 #define SRB_SCSI_RETRY_STATE 9 /* in Scsi Retry Queue */
305
306
307 /*
308 * ISP I/O Register Set structure definitions.
309 */
310 struct device_reg_2xxx {
311 uint16_t flash_address; /* Flash BIOS address */
312 uint16_t flash_data; /* Flash BIOS data */
313 uint16_t unused_1[1]; /* Gap */
314 uint16_t ctrl_status; /* Control/Status */
315 #define CSR_FLASH_64K_BANK BIT_3 /* Flash upper 64K bank select */
316 #define CSR_FLASH_ENABLE BIT_1 /* Flash BIOS Read/Write enable */
317 #define CSR_ISP_SOFT_RESET BIT_0 /* ISP soft reset */
318
319 uint16_t ictrl; /* Interrupt control */
320 #define ICR_EN_INT BIT_15 /* ISP enable interrupts. */
321 #define ICR_EN_RISC BIT_3 /* ISP enable RISC interrupts. */
322
323 uint16_t istatus; /* Interrupt status */
324 #define ISR_RISC_INT BIT_3 /* RISC interrupt */
325
326 uint16_t semaphore; /* Semaphore */
327 uint16_t nvram; /* NVRAM register. */
328 #define NVR_DESELECT 0
329 #define NVR_BUSY BIT_15
330 #define NVR_WRT_ENABLE BIT_14 /* Write enable */
331 #define NVR_PR_ENABLE BIT_13 /* Protection register enable */
332 #define NVR_DATA_IN BIT_3
333 #define NVR_DATA_OUT BIT_2
334 #define NVR_SELECT BIT_1
335 #define NVR_CLOCK BIT_0
336
337 union {
338 struct {
339 uint16_t mailbox0;
340 uint16_t mailbox1;
341 uint16_t mailbox2;
342 uint16_t mailbox3;
343 uint16_t mailbox4;
344 uint16_t mailbox5;
345 uint16_t mailbox6;
346 uint16_t mailbox7;
347 uint16_t unused_2[59]; /* Gap */
348 } __attribute__((packed)) isp2100;
349 struct {
350 /* Request Queue */
351 uint16_t req_q_in; /* In-Pointer */
352 uint16_t req_q_out; /* Out-Pointer */
353 /* Response Queue */
354 uint16_t rsp_q_in; /* In-Pointer */
355 uint16_t rsp_q_out; /* Out-Pointer */
356
357 /* RISC to Host Status */
358 uint32_t host_status;
359 #define HSR_RISC_INT BIT_15 /* RISC interrupt */
360 #define HSR_RISC_PAUSED BIT_8 /* RISC Paused */
361
362 /* Host to Host Semaphore */
363 uint16_t host_semaphore;
364 uint16_t unused_3[17]; /* Gap */
365 uint16_t mailbox0;
366 uint16_t mailbox1;
367 uint16_t mailbox2;
368 uint16_t mailbox3;
369 uint16_t mailbox4;
370 uint16_t mailbox5;
371 uint16_t mailbox6;
372 uint16_t mailbox7;
373 uint16_t mailbox8;
374 uint16_t mailbox9;
375 uint16_t mailbox10;
376 uint16_t mailbox11;
377 uint16_t mailbox12;
378 uint16_t mailbox13;
379 uint16_t mailbox14;
380 uint16_t mailbox15;
381 uint16_t mailbox16;
382 uint16_t mailbox17;
383 uint16_t mailbox18;
384 uint16_t mailbox19;
385 uint16_t mailbox20;
386 uint16_t mailbox21;
387 uint16_t mailbox22;
388 uint16_t mailbox23;
389 uint16_t mailbox24;
390 uint16_t mailbox25;
391 uint16_t mailbox26;
392 uint16_t mailbox27;
393 uint16_t mailbox28;
394 uint16_t mailbox29;
395 uint16_t mailbox30;
396 uint16_t mailbox31;
397 uint16_t fb_cmd;
398 uint16_t unused_4[10]; /* Gap */
399 } __attribute__((packed)) isp2300;
400 } u;
401
402 uint16_t fpm_diag_config;
403 uint16_t unused_5[0x6]; /* Gap */
404 uint16_t pcr; /* Processor Control Register. */
405 uint16_t unused_6[0x5]; /* Gap */
406 uint16_t mctr; /* Memory Configuration and Timing. */
407 uint16_t unused_7[0x3]; /* Gap */
408 uint16_t fb_cmd_2100; /* Unused on 23XX */
409 uint16_t unused_8[0x3]; /* Gap */
410 uint16_t hccr; /* Host command & control register. */
411 #define HCCR_HOST_INT BIT_7 /* Host interrupt bit */
412 #define HCCR_RISC_PAUSE BIT_5 /* Pause mode bit */
413 /* HCCR commands */
414 #define HCCR_RESET_RISC 0x1000 /* Reset RISC */
415 #define HCCR_PAUSE_RISC 0x2000 /* Pause RISC */
416 #define HCCR_RELEASE_RISC 0x3000 /* Release RISC from reset. */
417 #define HCCR_SET_HOST_INT 0x5000 /* Set host interrupt */
418 #define HCCR_CLR_HOST_INT 0x6000 /* Clear HOST interrupt */
419 #define HCCR_CLR_RISC_INT 0x7000 /* Clear RISC interrupt */
420 #define HCCR_DISABLE_PARITY_PAUSE 0x4001 /* Disable parity error RISC pause. */
421 #define HCCR_ENABLE_PARITY 0xA000 /* Enable PARITY interrupt */
422
423 uint16_t unused_9[5]; /* Gap */
424 uint16_t gpiod; /* GPIO Data register. */
425 uint16_t gpioe; /* GPIO Enable register. */
426 #define GPIO_LED_MASK 0x00C0
427 #define GPIO_LED_GREEN_OFF_AMBER_OFF 0x0000
428 #define GPIO_LED_GREEN_ON_AMBER_OFF 0x0040
429 #define GPIO_LED_GREEN_OFF_AMBER_ON 0x0080
430 #define GPIO_LED_GREEN_ON_AMBER_ON 0x00C0
431
432 union {
433 struct {
434 uint16_t unused_10[8]; /* Gap */
435 uint16_t mailbox8;
436 uint16_t mailbox9;
437 uint16_t mailbox10;
438 uint16_t mailbox11;
439 uint16_t mailbox12;
440 uint16_t mailbox13;
441 uint16_t mailbox14;
442 uint16_t mailbox15;
443 uint16_t mailbox16;
444 uint16_t mailbox17;
445 uint16_t mailbox18;
446 uint16_t mailbox19;
447 uint16_t mailbox20;
448 uint16_t mailbox21;
449 uint16_t mailbox22;
450 uint16_t mailbox23; /* Also probe reg. */
451 } __attribute__((packed)) isp2200;
452 } u_end;
453 };
454
455 typedef union {
456 struct device_reg_2xxx isp;
457 struct device_reg_24xx isp24;
458 } device_reg_t;
459
460 #define ISP_REQ_Q_IN(ha, reg) \
461 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
462 &(reg)->u.isp2100.mailbox4 : \
463 &(reg)->u.isp2300.req_q_in)
464 #define ISP_REQ_Q_OUT(ha, reg) \
465 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
466 &(reg)->u.isp2100.mailbox4 : \
467 &(reg)->u.isp2300.req_q_out)
468 #define ISP_RSP_Q_IN(ha, reg) \
469 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
470 &(reg)->u.isp2100.mailbox5 : \
471 &(reg)->u.isp2300.rsp_q_in)
472 #define ISP_RSP_Q_OUT(ha, reg) \
473 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
474 &(reg)->u.isp2100.mailbox5 : \
475 &(reg)->u.isp2300.rsp_q_out)
476
477 #define MAILBOX_REG(ha, reg, num) \
478 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
479 (num < 8 ? \
480 &(reg)->u.isp2100.mailbox0 + (num) : \
481 &(reg)->u_end.isp2200.mailbox8 + (num) - 8) : \
482 &(reg)->u.isp2300.mailbox0 + (num))
483 #define RD_MAILBOX_REG(ha, reg, num) \
484 RD_REG_WORD(MAILBOX_REG(ha, reg, num))
485 #define WRT_MAILBOX_REG(ha, reg, num, data) \
486 WRT_REG_WORD(MAILBOX_REG(ha, reg, num), data)
487
488 #define FB_CMD_REG(ha, reg) \
489 (IS_QLA2100(ha) || IS_QLA2200(ha) ? \
490 &(reg)->fb_cmd_2100 : \
491 &(reg)->u.isp2300.fb_cmd)
492 #define RD_FB_CMD_REG(ha, reg) \
493 RD_REG_WORD(FB_CMD_REG(ha, reg))
494 #define WRT_FB_CMD_REG(ha, reg, data) \
495 WRT_REG_WORD(FB_CMD_REG(ha, reg), data)
496
497 typedef struct {
498 uint32_t out_mb; /* outbound from driver */
499 uint32_t in_mb; /* Incoming from RISC */
500 uint16_t mb[MAILBOX_REGISTER_COUNT];
501 long buf_size;
502 void *bufp;
503 uint32_t tov;
504 uint8_t flags;
505 #define MBX_DMA_IN BIT_0
506 #define MBX_DMA_OUT BIT_1
507 #define IOCTL_CMD BIT_2
508 } mbx_cmd_t;
509
510 #define MBX_TOV_SECONDS 30
511
512 /*
513 * ISP product identification definitions in mailboxes after reset.
514 */
515 #define PROD_ID_1 0x4953
516 #define PROD_ID_2 0x0000
517 #define PROD_ID_2a 0x5020
518 #define PROD_ID_3 0x2020
519
520 /*
521 * ISP mailbox Self-Test status codes
522 */
523 #define MBS_FRM_ALIVE 0 /* Firmware Alive. */
524 #define MBS_CHKSUM_ERR 1 /* Checksum Error. */
525 #define MBS_BUSY 4 /* Busy. */
526
527 /*
528 * ISP mailbox command complete status codes
529 */
530 #define MBS_COMMAND_COMPLETE 0x4000
531 #define MBS_INVALID_COMMAND 0x4001
532 #define MBS_HOST_INTERFACE_ERROR 0x4002
533 #define MBS_TEST_FAILED 0x4003
534 #define MBS_COMMAND_ERROR 0x4005
535 #define MBS_COMMAND_PARAMETER_ERROR 0x4006
536 #define MBS_PORT_ID_USED 0x4007
537 #define MBS_LOOP_ID_USED 0x4008
538 #define MBS_ALL_IDS_IN_USE 0x4009
539 #define MBS_NOT_LOGGED_IN 0x400A
540 #define MBS_LINK_DOWN_ERROR 0x400B
541 #define MBS_DIAG_ECHO_TEST_ERROR 0x400C
542
543 /*
544 * ISP mailbox asynchronous event status codes
545 */
546 #define MBA_ASYNC_EVENT 0x8000 /* Asynchronous event. */
547 #define MBA_RESET 0x8001 /* Reset Detected. */
548 #define MBA_SYSTEM_ERR 0x8002 /* System Error. */
549 #define MBA_REQ_TRANSFER_ERR 0x8003 /* Request Transfer Error. */
550 #define MBA_RSP_TRANSFER_ERR 0x8004 /* Response Transfer Error. */
551 #define MBA_WAKEUP_THRES 0x8005 /* Request Queue Wake-up. */
552 #define MBA_LIP_OCCURRED 0x8010 /* Loop Initialization Procedure */
553 /* occurred. */
554 #define MBA_LOOP_UP 0x8011 /* FC Loop UP. */
555 #define MBA_LOOP_DOWN 0x8012 /* FC Loop Down. */
556 #define MBA_LIP_RESET 0x8013 /* LIP reset occurred. */
557 #define MBA_PORT_UPDATE 0x8014 /* Port Database update. */
558 #define MBA_RSCN_UPDATE 0x8015 /* Register State Chg Notification. */
559 #define MBA_LIP_F8 0x8016 /* Received a LIP F8. */
560 #define MBA_LOOP_INIT_ERR 0x8017 /* Loop Initialization Error. */
561 #define MBA_FABRIC_AUTH_REQ 0x801b /* Fabric Authentication Required. */
562 #define MBA_SCSI_COMPLETION 0x8020 /* SCSI Command Complete. */
563 #define MBA_CTIO_COMPLETION 0x8021 /* CTIO Complete. */
564 #define MBA_IP_COMPLETION 0x8022 /* IP Transmit Command Complete. */
565 #define MBA_IP_RECEIVE 0x8023 /* IP Received. */
566 #define MBA_IP_BROADCAST 0x8024 /* IP Broadcast Received. */
567 #define MBA_IP_LOW_WATER_MARK 0x8025 /* IP Low Water Mark reached. */
568 #define MBA_IP_RCV_BUFFER_EMPTY 0x8026 /* IP receive buffer queue empty. */
569 #define MBA_IP_HDR_DATA_SPLIT 0x8027 /* IP header/data splitting feature */
570 /* used. */
571 #define MBA_POINT_TO_POINT 0x8030 /* Point to point mode. */
572 #define MBA_CMPLT_1_16BIT 0x8031 /* Completion 1 16bit IOSB. */
573 #define MBA_CMPLT_2_16BIT 0x8032 /* Completion 2 16bit IOSB. */
574 #define MBA_CMPLT_3_16BIT 0x8033 /* Completion 3 16bit IOSB. */
575 #define MBA_CMPLT_4_16BIT 0x8034 /* Completion 4 16bit IOSB. */
576 #define MBA_CMPLT_5_16BIT 0x8035 /* Completion 5 16bit IOSB. */
577 #define MBA_CHG_IN_CONNECTION 0x8036 /* Change in connection mode. */
578 #define MBA_RIO_RESPONSE 0x8040 /* RIO response queue update. */
579 #define MBA_ZIO_RESPONSE 0x8040 /* ZIO response queue update. */
580 #define MBA_CMPLT_2_32BIT 0x8042 /* Completion 2 32bit IOSB. */
581 #define MBA_BYPASS_NOTIFICATION 0x8043 /* Auto bypass notification. */
582 #define MBA_DISCARD_RND_FRAME 0x8048 /* discard RND frame due to error. */
583 #define MBA_REJECTED_FCP_CMD 0x8049 /* rejected FCP_CMD. */
584
585 /*
586 * Firmware options 1, 2, 3.
587 */
588 #define FO1_AE_ON_LIPF8 BIT_0
589 #define FO1_AE_ALL_LIP_RESET BIT_1
590 #define FO1_CTIO_RETRY BIT_3
591 #define FO1_DISABLE_LIP_F7_SW BIT_4
592 #define FO1_DISABLE_100MS_LOS_WAIT BIT_5
593 #define FO1_DISABLE_GPIO6_7 BIT_6 /* LED bits */
594 #define FO1_AE_ON_LOOP_INIT_ERR BIT_7
595 #define FO1_SET_EMPHASIS_SWING BIT_8
596 #define FO1_AE_AUTO_BYPASS BIT_9
597 #define FO1_ENABLE_PURE_IOCB BIT_10
598 #define FO1_AE_PLOGI_RJT BIT_11
599 #define FO1_ENABLE_ABORT_SEQUENCE BIT_12
600 #define FO1_AE_QUEUE_FULL BIT_13
601
602 #define FO2_ENABLE_ATIO_TYPE_3 BIT_0
603 #define FO2_REV_LOOPBACK BIT_1
604
605 #define FO3_ENABLE_EMERG_IOCB BIT_0
606 #define FO3_AE_RND_ERROR BIT_1
607
608 /* 24XX additional firmware options */
609 #define ADD_FO_COUNT 3
610 #define ADD_FO1_DISABLE_GPIO_LED_CTRL BIT_6 /* LED bits */
611 #define ADD_FO1_ENABLE_PUREX_IOCB BIT_10
612
613 #define ADD_FO2_ENABLE_SEL_CLS2 BIT_5
614
615 #define ADD_FO3_NO_ABT_ON_LINK_DOWN BIT_14
616
617 /*
618 * ISP mailbox commands
619 */
620 #define MBC_LOAD_RAM 1 /* Load RAM. */
621 #define MBC_EXECUTE_FIRMWARE 2 /* Execute firmware. */
622 #define MBC_WRITE_RAM_WORD 4 /* Write RAM word. */
623 #define MBC_READ_RAM_WORD 5 /* Read RAM word. */
624 #define MBC_MAILBOX_REGISTER_TEST 6 /* Wrap incoming mailboxes */
625 #define MBC_VERIFY_CHECKSUM 7 /* Verify checksum. */
626 #define MBC_GET_FIRMWARE_VERSION 8 /* Get firmware revision. */
627 #define MBC_LOAD_RISC_RAM 9 /* Load RAM command. */
628 #define MBC_DUMP_RISC_RAM 0xa /* Dump RAM command. */
629 #define MBC_LOAD_RISC_RAM_EXTENDED 0xb /* Load RAM extended. */
630 #define MBC_DUMP_RISC_RAM_EXTENDED 0xc /* Dump RAM extended. */
631 #define MBC_WRITE_RAM_WORD_EXTENDED 0xd /* Write RAM word extended */
632 #define MBC_READ_RAM_EXTENDED 0xf /* Read RAM extended. */
633 #define MBC_IOCB_COMMAND 0x12 /* Execute IOCB command. */
634 #define MBC_STOP_FIRMWARE 0x14 /* Stop firmware. */
635 #define MBC_ABORT_COMMAND 0x15 /* Abort IOCB command. */
636 #define MBC_ABORT_DEVICE 0x16 /* Abort device (ID/LUN). */
637 #define MBC_ABORT_TARGET 0x17 /* Abort target (ID). */
638 #define MBC_RESET 0x18 /* Reset. */
639 #define MBC_GET_ADAPTER_LOOP_ID 0x20 /* Get loop id of ISP2200. */
640 #define MBC_GET_RETRY_COUNT 0x22 /* Get f/w retry cnt/delay. */
641 #define MBC_DISABLE_VI 0x24 /* Disable VI operation. */
642 #define MBC_ENABLE_VI 0x25 /* Enable VI operation. */
643 #define MBC_GET_FIRMWARE_OPTION 0x28 /* Get Firmware Options. */
644 #define MBC_SET_FIRMWARE_OPTION 0x38 /* Set Firmware Options. */
645 #define MBC_LOOP_PORT_BYPASS 0x40 /* Loop Port Bypass. */
646 #define MBC_LOOP_PORT_ENABLE 0x41 /* Loop Port Enable. */
647 #define MBC_GET_RESOURCE_COUNTS 0x42 /* Get Resource Counts. */
648 #define MBC_NON_PARTICIPATE 0x43 /* Non-Participating Mode. */
649 #define MBC_DIAGNOSTIC_ECHO 0x44 /* Diagnostic echo. */
650 #define MBC_DIAGNOSTIC_LOOP_BACK 0x45 /* Diagnostic loop back. */
651 #define MBC_ONLINE_SELF_TEST 0x46 /* Online self-test. */
652 #define MBC_ENHANCED_GET_PORT_DATABASE 0x47 /* Get port database + login */
653 #define MBC_RESET_LINK_STATUS 0x52 /* Reset Link Error Status */
654 #define MBC_IOCB_COMMAND_A64 0x54 /* Execute IOCB command (64) */
655 #define MBC_SEND_RNID_ELS 0x57 /* Send RNID ELS request */
656 #define MBC_SET_RNID_PARAMS 0x59 /* Set RNID parameters */
657 #define MBC_GET_RNID_PARAMS 0x5a /* Data Rate */
658 #define MBC_DATA_RATE 0x5d /* Get RNID parameters */
659 #define MBC_INITIALIZE_FIRMWARE 0x60 /* Initialize firmware */
660 #define MBC_INITIATE_LIP 0x62 /* Initiate Loop */
661 /* Initialization Procedure */
662 #define MBC_GET_FC_AL_POSITION_MAP 0x63 /* Get FC_AL Position Map. */
663 #define MBC_GET_PORT_DATABASE 0x64 /* Get Port Database. */
664 #define MBC_CLEAR_ACA 0x65 /* Clear ACA. */
665 #define MBC_TARGET_RESET 0x66 /* Target Reset. */
666 #define MBC_CLEAR_TASK_SET 0x67 /* Clear Task Set. */
667 #define MBC_ABORT_TASK_SET 0x68 /* Abort Task Set. */
668 #define MBC_GET_FIRMWARE_STATE 0x69 /* Get firmware state. */
669 #define MBC_GET_PORT_NAME 0x6a /* Get port name. */
670 #define MBC_GET_LINK_STATUS 0x6b /* Get port link status. */
671 #define MBC_LIP_RESET 0x6c /* LIP reset. */
672 #define MBC_SEND_SNS_COMMAND 0x6e /* Send Simple Name Server */
673 /* commandd. */
674 #define MBC_LOGIN_FABRIC_PORT 0x6f /* Login fabric port. */
675 #define MBC_SEND_CHANGE_REQUEST 0x70 /* Send Change Request. */
676 #define MBC_LOGOUT_FABRIC_PORT 0x71 /* Logout fabric port. */
677 #define MBC_LIP_FULL_LOGIN 0x72 /* Full login LIP. */
678 #define MBC_LOGIN_LOOP_PORT 0x74 /* Login Loop Port. */
679 #define MBC_PORT_NODE_NAME_LIST 0x75 /* Get port/node name list. */
680 #define MBC_INITIALIZE_RECEIVE_QUEUE 0x77 /* Initialize receive queue */
681 #define MBC_UNLOAD_IP 0x79 /* Shutdown IP */
682 #define MBC_GET_ID_LIST 0x7C /* Get Port ID list. */
683 #define MBC_SEND_LFA_COMMAND 0x7D /* Send Loop Fabric Address */
684 #define MBC_LUN_RESET 0x7E /* Send LUN reset */
685
686 /*
687 * ISP24xx mailbox commands
688 */
689 #define MBC_SERDES_PARAMS 0x10 /* Serdes Tx Parameters. */
690 #define MBC_GET_IOCB_STATUS 0x12 /* Get IOCB status command. */
691 #define MBC_GET_TIMEOUT_PARAMS 0x22 /* Get FW timeouts. */
692 #define MBC_GEN_SYSTEM_ERROR 0x2a /* Generate System Error. */
693 #define MBC_SET_TIMEOUT_PARAMS 0x32 /* Set FW timeouts. */
694 #define MBC_MID_INITIALIZE_FIRMWARE 0x48 /* MID Initialize firmware. */
695 #define MBC_MID_GET_VP_DATABASE 0x49 /* MID Get VP Database. */
696 #define MBC_MID_GET_VP_ENTRY 0x4a /* MID Get VP Entry. */
697 #define MBC_HOST_MEMORY_COPY 0x53 /* Host Memory Copy. */
698 #define MBC_SEND_RNFT_ELS 0x5e /* Send RNFT ELS request */
699 #define MBC_GET_LINK_PRIV_STATS 0x6d /* Get link & private data. */
700 #define MBC_SET_VENDOR_ID 0x76 /* Set Vendor ID. */
701
702 /* Firmware return data sizes */
703 #define FCAL_MAP_SIZE 128
704
705 /* Mailbox bit definitions for out_mb and in_mb */
706 #define MBX_31 BIT_31
707 #define MBX_30 BIT_30
708 #define MBX_29 BIT_29
709 #define MBX_28 BIT_28
710 #define MBX_27 BIT_27
711 #define MBX_26 BIT_26
712 #define MBX_25 BIT_25
713 #define MBX_24 BIT_24
714 #define MBX_23 BIT_23
715 #define MBX_22 BIT_22
716 #define MBX_21 BIT_21
717 #define MBX_20 BIT_20
718 #define MBX_19 BIT_19
719 #define MBX_18 BIT_18
720 #define MBX_17 BIT_17
721 #define MBX_16 BIT_16
722 #define MBX_15 BIT_15
723 #define MBX_14 BIT_14
724 #define MBX_13 BIT_13
725 #define MBX_12 BIT_12
726 #define MBX_11 BIT_11
727 #define MBX_10 BIT_10
728 #define MBX_9 BIT_9
729 #define MBX_8 BIT_8
730 #define MBX_7 BIT_7
731 #define MBX_6 BIT_6
732 #define MBX_5 BIT_5
733 #define MBX_4 BIT_4
734 #define MBX_3 BIT_3
735 #define MBX_2 BIT_2
736 #define MBX_1 BIT_1
737 #define MBX_0 BIT_0
738
739 /*
740 * Firmware state codes from get firmware state mailbox command
741 */
742 #define FSTATE_CONFIG_WAIT 0
743 #define FSTATE_WAIT_AL_PA 1
744 #define FSTATE_WAIT_LOGIN 2
745 #define FSTATE_READY 3
746 #define FSTATE_LOSS_OF_SYNC 4
747 #define FSTATE_ERROR 5
748 #define FSTATE_REINIT 6
749 #define FSTATE_NON_PART 7
750
751 #define FSTATE_CONFIG_CORRECT 0
752 #define FSTATE_P2P_RCV_LIP 1
753 #define FSTATE_P2P_CHOOSE_LOOP 2
754 #define FSTATE_P2P_RCV_UNIDEN_LIP 3
755 #define FSTATE_FATAL_ERROR 4
756 #define FSTATE_LOOP_BACK_CONN 5
757
758 /*
759 * Port Database structure definition
760 * Little endian except where noted.
761 */
762 #define PORT_DATABASE_SIZE 128 /* bytes */
763 typedef struct {
764 uint8_t options;
765 uint8_t control;
766 uint8_t master_state;
767 uint8_t slave_state;
768 uint8_t reserved[2];
769 uint8_t hard_address;
770 uint8_t reserved_1;
771 uint8_t port_id[4];
772 uint8_t node_name[WWN_SIZE];
773 uint8_t port_name[WWN_SIZE];
774 uint16_t execution_throttle;
775 uint16_t execution_count;
776 uint8_t reset_count;
777 uint8_t reserved_2;
778 uint16_t resource_allocation;
779 uint16_t current_allocation;
780 uint16_t queue_head;
781 uint16_t queue_tail;
782 uint16_t transmit_execution_list_next;
783 uint16_t transmit_execution_list_previous;
784 uint16_t common_features;
785 uint16_t total_concurrent_sequences;
786 uint16_t RO_by_information_category;
787 uint8_t recipient;
788 uint8_t initiator;
789 uint16_t receive_data_size;
790 uint16_t concurrent_sequences;
791 uint16_t open_sequences_per_exchange;
792 uint16_t lun_abort_flags;
793 uint16_t lun_stop_flags;
794 uint16_t stop_queue_head;
795 uint16_t stop_queue_tail;
796 uint16_t port_retry_timer;
797 uint16_t next_sequence_id;
798 uint16_t frame_count;
799 uint16_t PRLI_payload_length;
800 uint8_t prli_svc_param_word_0[2]; /* Big endian */
801 /* Bits 15-0 of word 0 */
802 uint8_t prli_svc_param_word_3[2]; /* Big endian */
803 /* Bits 15-0 of word 3 */
804 uint16_t loop_id;
805 uint16_t extended_lun_info_list_pointer;
806 uint16_t extended_lun_stop_list_pointer;
807 } port_database_t;
808
809 /*
810 * Port database slave/master states
811 */
812 #define PD_STATE_DISCOVERY 0
813 #define PD_STATE_WAIT_DISCOVERY_ACK 1
814 #define PD_STATE_PORT_LOGIN 2
815 #define PD_STATE_WAIT_PORT_LOGIN_ACK 3
816 #define PD_STATE_PROCESS_LOGIN 4
817 #define PD_STATE_WAIT_PROCESS_LOGIN_ACK 5
818 #define PD_STATE_PORT_LOGGED_IN 6
819 #define PD_STATE_PORT_UNAVAILABLE 7
820 #define PD_STATE_PROCESS_LOGOUT 8
821 #define PD_STATE_WAIT_PROCESS_LOGOUT_ACK 9
822 #define PD_STATE_PORT_LOGOUT 10
823 #define PD_STATE_WAIT_PORT_LOGOUT_ACK 11
824
825
826 /*
827 * ISP Initialization Control Block.
828 * Little endian except where noted.
829 */
830 #define ICB_VERSION 1
831 typedef struct {
832 uint8_t version;
833 uint8_t reserved_1;
834
835 /*
836 * LSB BIT 0 = Enable Hard Loop Id
837 * LSB BIT 1 = Enable Fairness
838 * LSB BIT 2 = Enable Full-Duplex
839 * LSB BIT 3 = Enable Fast Posting
840 * LSB BIT 4 = Enable Target Mode
841 * LSB BIT 5 = Disable Initiator Mode
842 * LSB BIT 6 = Enable ADISC
843 * LSB BIT 7 = Enable Target Inquiry Data
844 *
845 * MSB BIT 0 = Enable PDBC Notify
846 * MSB BIT 1 = Non Participating LIP
847 * MSB BIT 2 = Descending Loop ID Search
848 * MSB BIT 3 = Acquire Loop ID in LIPA
849 * MSB BIT 4 = Stop PortQ on Full Status
850 * MSB BIT 5 = Full Login after LIP
851 * MSB BIT 6 = Node Name Option
852 * MSB BIT 7 = Ext IFWCB enable bit
853 */
854 uint8_t firmware_options[2];
855
856 uint16_t frame_payload_size;
857 uint16_t max_iocb_allocation;
858 uint16_t execution_throttle;
859 uint8_t retry_count;
860 uint8_t retry_delay; /* unused */
861 uint8_t port_name[WWN_SIZE]; /* Big endian. */
862 uint16_t hard_address;
863 uint8_t inquiry_data;
864 uint8_t login_timeout;
865 uint8_t node_name[WWN_SIZE]; /* Big endian. */
866
867 uint16_t request_q_outpointer;
868 uint16_t response_q_inpointer;
869 uint16_t request_q_length;
870 uint16_t response_q_length;
871 uint32_t request_q_address[2];
872 uint32_t response_q_address[2];
873
874 uint16_t lun_enables;
875 uint8_t command_resource_count;
876 uint8_t immediate_notify_resource_count;
877 uint16_t timeout;
878 uint8_t reserved_2[2];
879
880 /*
881 * LSB BIT 0 = Timer Operation mode bit 0
882 * LSB BIT 1 = Timer Operation mode bit 1
883 * LSB BIT 2 = Timer Operation mode bit 2
884 * LSB BIT 3 = Timer Operation mode bit 3
885 * LSB BIT 4 = Init Config Mode bit 0
886 * LSB BIT 5 = Init Config Mode bit 1
887 * LSB BIT 6 = Init Config Mode bit 2
888 * LSB BIT 7 = Enable Non part on LIHA failure
889 *
890 * MSB BIT 0 = Enable class 2
891 * MSB BIT 1 = Enable ACK0
892 * MSB BIT 2 =
893 * MSB BIT 3 =
894 * MSB BIT 4 = FC Tape Enable
895 * MSB BIT 5 = Enable FC Confirm
896 * MSB BIT 6 = Enable command queuing in target mode
897 * MSB BIT 7 = No Logo On Link Down
898 */
899 uint8_t add_firmware_options[2];
900
901 uint8_t response_accumulation_timer;
902 uint8_t interrupt_delay_timer;
903
904 /*
905 * LSB BIT 0 = Enable Read xfr_rdy
906 * LSB BIT 1 = Soft ID only
907 * LSB BIT 2 =
908 * LSB BIT 3 =
909 * LSB BIT 4 = FCP RSP Payload [0]
910 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
911 * LSB BIT 6 = Enable Out-of-Order frame handling
912 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
913 *
914 * MSB BIT 0 = Sbus enable - 2300
915 * MSB BIT 1 =
916 * MSB BIT 2 =
917 * MSB BIT 3 =
918 * MSB BIT 4 = LED mode
919 * MSB BIT 5 = enable 50 ohm termination
920 * MSB BIT 6 = Data Rate (2300 only)
921 * MSB BIT 7 = Data Rate (2300 only)
922 */
923 uint8_t special_options[2];
924
925 uint8_t reserved_3[26];
926 } init_cb_t;
927
928 /*
929 * Get Link Status mailbox command return buffer.
930 */
931 #define GLSO_SEND_RPS BIT_0
932 #define GLSO_USE_DID BIT_3
933
934 typedef struct {
935 uint32_t link_fail_cnt;
936 uint32_t loss_sync_cnt;
937 uint32_t loss_sig_cnt;
938 uint32_t prim_seq_err_cnt;
939 uint32_t inval_xmit_word_cnt;
940 uint32_t inval_crc_cnt;
941 } link_stat_t;
942
943 /*
944 * NVRAM Command values.
945 */
946 #define NV_START_BIT BIT_2
947 #define NV_WRITE_OP (BIT_26+BIT_24)
948 #define NV_READ_OP (BIT_26+BIT_25)
949 #define NV_ERASE_OP (BIT_26+BIT_25+BIT_24)
950 #define NV_MASK_OP (BIT_26+BIT_25+BIT_24)
951 #define NV_DELAY_COUNT 10
952
953 /*
954 * QLogic ISP2100, ISP2200 and ISP2300 NVRAM structure definition.
955 */
956 typedef struct {
957 /*
958 * NVRAM header
959 */
960 uint8_t id[4];
961 uint8_t nvram_version;
962 uint8_t reserved_0;
963
964 /*
965 * NVRAM RISC parameter block
966 */
967 uint8_t parameter_block_version;
968 uint8_t reserved_1;
969
970 /*
971 * LSB BIT 0 = Enable Hard Loop Id
972 * LSB BIT 1 = Enable Fairness
973 * LSB BIT 2 = Enable Full-Duplex
974 * LSB BIT 3 = Enable Fast Posting
975 * LSB BIT 4 = Enable Target Mode
976 * LSB BIT 5 = Disable Initiator Mode
977 * LSB BIT 6 = Enable ADISC
978 * LSB BIT 7 = Enable Target Inquiry Data
979 *
980 * MSB BIT 0 = Enable PDBC Notify
981 * MSB BIT 1 = Non Participating LIP
982 * MSB BIT 2 = Descending Loop ID Search
983 * MSB BIT 3 = Acquire Loop ID in LIPA
984 * MSB BIT 4 = Stop PortQ on Full Status
985 * MSB BIT 5 = Full Login after LIP
986 * MSB BIT 6 = Node Name Option
987 * MSB BIT 7 = Ext IFWCB enable bit
988 */
989 uint8_t firmware_options[2];
990
991 uint16_t frame_payload_size;
992 uint16_t max_iocb_allocation;
993 uint16_t execution_throttle;
994 uint8_t retry_count;
995 uint8_t retry_delay; /* unused */
996 uint8_t port_name[WWN_SIZE]; /* Big endian. */
997 uint16_t hard_address;
998 uint8_t inquiry_data;
999 uint8_t login_timeout;
1000 uint8_t node_name[WWN_SIZE]; /* Big endian. */
1001
1002 /*
1003 * LSB BIT 0 = Timer Operation mode bit 0
1004 * LSB BIT 1 = Timer Operation mode bit 1
1005 * LSB BIT 2 = Timer Operation mode bit 2
1006 * LSB BIT 3 = Timer Operation mode bit 3
1007 * LSB BIT 4 = Init Config Mode bit 0
1008 * LSB BIT 5 = Init Config Mode bit 1
1009 * LSB BIT 6 = Init Config Mode bit 2
1010 * LSB BIT 7 = Enable Non part on LIHA failure
1011 *
1012 * MSB BIT 0 = Enable class 2
1013 * MSB BIT 1 = Enable ACK0
1014 * MSB BIT 2 =
1015 * MSB BIT 3 =
1016 * MSB BIT 4 = FC Tape Enable
1017 * MSB BIT 5 = Enable FC Confirm
1018 * MSB BIT 6 = Enable command queuing in target mode
1019 * MSB BIT 7 = No Logo On Link Down
1020 */
1021 uint8_t add_firmware_options[2];
1022
1023 uint8_t response_accumulation_timer;
1024 uint8_t interrupt_delay_timer;
1025
1026 /*
1027 * LSB BIT 0 = Enable Read xfr_rdy
1028 * LSB BIT 1 = Soft ID only
1029 * LSB BIT 2 =
1030 * LSB BIT 3 =
1031 * LSB BIT 4 = FCP RSP Payload [0]
1032 * LSB BIT 5 = FCP RSP Payload [1] / Sbus enable - 2200
1033 * LSB BIT 6 = Enable Out-of-Order frame handling
1034 * LSB BIT 7 = Disable Automatic PLOGI on Local Loop
1035 *
1036 * MSB BIT 0 = Sbus enable - 2300
1037 * MSB BIT 1 =
1038 * MSB BIT 2 =
1039 * MSB BIT 3 =
1040 * MSB BIT 4 = LED mode
1041 * MSB BIT 5 = enable 50 ohm termination
1042 * MSB BIT 6 = Data Rate (2300 only)
1043 * MSB BIT 7 = Data Rate (2300 only)
1044 */
1045 uint8_t special_options[2];
1046
1047 /* Reserved for expanded RISC parameter block */
1048 uint8_t reserved_2[22];
1049
1050 /*
1051 * LSB BIT 0 = Tx Sensitivity 1G bit 0
1052 * LSB BIT 1 = Tx Sensitivity 1G bit 1
1053 * LSB BIT 2 = Tx Sensitivity 1G bit 2
1054 * LSB BIT 3 = Tx Sensitivity 1G bit 3
1055 * LSB BIT 4 = Rx Sensitivity 1G bit 0
1056 * LSB BIT 5 = Rx Sensitivity 1G bit 1
1057 * LSB BIT 6 = Rx Sensitivity 1G bit 2
1058 * LSB BIT 7 = Rx Sensitivity 1G bit 3
1059 *
1060 * MSB BIT 0 = Tx Sensitivity 2G bit 0
1061 * MSB BIT 1 = Tx Sensitivity 2G bit 1
1062 * MSB BIT 2 = Tx Sensitivity 2G bit 2
1063 * MSB BIT 3 = Tx Sensitivity 2G bit 3
1064 * MSB BIT 4 = Rx Sensitivity 2G bit 0
1065 * MSB BIT 5 = Rx Sensitivity 2G bit 1
1066 * MSB BIT 6 = Rx Sensitivity 2G bit 2
1067 * MSB BIT 7 = Rx Sensitivity 2G bit 3
1068 *
1069 * LSB BIT 0 = Output Swing 1G bit 0
1070 * LSB BIT 1 = Output Swing 1G bit 1
1071 * LSB BIT 2 = Output Swing 1G bit 2
1072 * LSB BIT 3 = Output Emphasis 1G bit 0
1073 * LSB BIT 4 = Output Emphasis 1G bit 1
1074 * LSB BIT 5 = Output Swing 2G bit 0
1075 * LSB BIT 6 = Output Swing 2G bit 1
1076 * LSB BIT 7 = Output Swing 2G bit 2
1077 *
1078 * MSB BIT 0 = Output Emphasis 2G bit 0
1079 * MSB BIT 1 = Output Emphasis 2G bit 1
1080 * MSB BIT 2 = Output Enable
1081 * MSB BIT 3 =
1082 * MSB BIT 4 =
1083 * MSB BIT 5 =
1084 * MSB BIT 6 =
1085 * MSB BIT 7 =
1086 */
1087 uint8_t seriallink_options[4];
1088
1089 /*
1090 * NVRAM host parameter block
1091 *
1092 * LSB BIT 0 = Enable spinup delay
1093 * LSB BIT 1 = Disable BIOS
1094 * LSB BIT 2 = Enable Memory Map BIOS
1095 * LSB BIT 3 = Enable Selectable Boot
1096 * LSB BIT 4 = Disable RISC code load
1097 * LSB BIT 5 = Set cache line size 1
1098 * LSB BIT 6 = PCI Parity Disable
1099 * LSB BIT 7 = Enable extended logging
1100 *
1101 * MSB BIT 0 = Enable 64bit addressing
1102 * MSB BIT 1 = Enable lip reset
1103 * MSB BIT 2 = Enable lip full login
1104 * MSB BIT 3 = Enable target reset
1105 * MSB BIT 4 = Enable database storage
1106 * MSB BIT 5 = Enable cache flush read
1107 * MSB BIT 6 = Enable database load
1108 * MSB BIT 7 = Enable alternate WWN
1109 */
1110 uint8_t host_p[2];
1111
1112 uint8_t boot_node_name[WWN_SIZE];
1113 uint8_t boot_lun_number;
1114 uint8_t reset_delay;
1115 uint8_t port_down_retry_count;
1116 uint8_t boot_id_number;
1117 uint16_t max_luns_per_target;
1118 uint8_t fcode_boot_port_name[WWN_SIZE];
1119 uint8_t alternate_port_name[WWN_SIZE];
1120 uint8_t alternate_node_name[WWN_SIZE];
1121
1122 /*
1123 * BIT 0 = Selective Login
1124 * BIT 1 = Alt-Boot Enable
1125 * BIT 2 =
1126 * BIT 3 = Boot Order List
1127 * BIT 4 =
1128 * BIT 5 = Selective LUN
1129 * BIT 6 =
1130 * BIT 7 = unused
1131 */
1132 uint8_t efi_parameters;
1133
1134 uint8_t link_down_timeout;
1135
1136 uint8_t adapter_id[16];
1137
1138 uint8_t alt1_boot_node_name[WWN_SIZE];
1139 uint16_t alt1_boot_lun_number;
1140 uint8_t alt2_boot_node_name[WWN_SIZE];
1141 uint16_t alt2_boot_lun_number;
1142 uint8_t alt3_boot_node_name[WWN_SIZE];
1143 uint16_t alt3_boot_lun_number;
1144 uint8_t alt4_boot_node_name[WWN_SIZE];
1145 uint16_t alt4_boot_lun_number;
1146 uint8_t alt5_boot_node_name[WWN_SIZE];
1147 uint16_t alt5_boot_lun_number;
1148 uint8_t alt6_boot_node_name[WWN_SIZE];
1149 uint16_t alt6_boot_lun_number;
1150 uint8_t alt7_boot_node_name[WWN_SIZE];
1151 uint16_t alt7_boot_lun_number;
1152
1153 uint8_t reserved_3[2];
1154
1155 /* Offset 200-215 : Model Number */
1156 uint8_t model_number[16];
1157
1158 /* OEM related items */
1159 uint8_t oem_specific[16];
1160
1161 /*
1162 * NVRAM Adapter Features offset 232-239
1163 *
1164 * LSB BIT 0 = External GBIC
1165 * LSB BIT 1 = Risc RAM parity
1166 * LSB BIT 2 = Buffer Plus Module
1167 * LSB BIT 3 = Multi Chip Adapter
1168 * LSB BIT 4 = Internal connector
1169 * LSB BIT 5 =
1170 * LSB BIT 6 =
1171 * LSB BIT 7 =
1172 *
1173 * MSB BIT 0 =
1174 * MSB BIT 1 =
1175 * MSB BIT 2 =
1176 * MSB BIT 3 =
1177 * MSB BIT 4 =
1178 * MSB BIT 5 =
1179 * MSB BIT 6 =
1180 * MSB BIT 7 =
1181 */
1182 uint8_t adapter_features[2];
1183
1184 uint8_t reserved_4[16];
1185
1186 /* Subsystem vendor ID for ISP2200 */
1187 uint16_t subsystem_vendor_id_2200;
1188
1189 /* Subsystem device ID for ISP2200 */
1190 uint16_t subsystem_device_id_2200;
1191
1192 uint8_t reserved_5;
1193 uint8_t checksum;
1194 } nvram_t;
1195
1196 /*
1197 * ISP queue - response queue entry definition.
1198 */
1199 typedef struct {
1200 uint8_t data[60];
1201 uint32_t signature;
1202 #define RESPONSE_PROCESSED 0xDEADDEAD /* Signature */
1203 } response_t;
1204
1205 typedef union {
1206 uint16_t extended;
1207 struct {
1208 uint8_t reserved;
1209 uint8_t standard;
1210 } id;
1211 } target_id_t;
1212
1213 #define SET_TARGET_ID(ha, to, from) \
1214 do { \
1215 if (HAS_EXTENDED_IDS(ha)) \
1216 to.extended = cpu_to_le16(from); \
1217 else \
1218 to.id.standard = (uint8_t)from; \
1219 } while (0)
1220
1221 /*
1222 * ISP queue - command entry structure definition.
1223 */
1224 #define COMMAND_TYPE 0x11 /* Command entry */
1225 typedef struct {
1226 uint8_t entry_type; /* Entry type. */
1227 uint8_t entry_count; /* Entry count. */
1228 uint8_t sys_define; /* System defined. */
1229 uint8_t entry_status; /* Entry Status. */
1230 uint32_t handle; /* System handle. */
1231 target_id_t target; /* SCSI ID */
1232 uint16_t lun; /* SCSI LUN */
1233 uint16_t control_flags; /* Control flags. */
1234 #define CF_WRITE BIT_6
1235 #define CF_READ BIT_5
1236 #define CF_SIMPLE_TAG BIT_3
1237 #define CF_ORDERED_TAG BIT_2
1238 #define CF_HEAD_TAG BIT_1
1239 uint16_t reserved_1;
1240 uint16_t timeout; /* Command timeout. */
1241 uint16_t dseg_count; /* Data segment count. */
1242 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1243 uint32_t byte_count; /* Total byte count. */
1244 uint32_t dseg_0_address; /* Data segment 0 address. */
1245 uint32_t dseg_0_length; /* Data segment 0 length. */
1246 uint32_t dseg_1_address; /* Data segment 1 address. */
1247 uint32_t dseg_1_length; /* Data segment 1 length. */
1248 uint32_t dseg_2_address; /* Data segment 2 address. */
1249 uint32_t dseg_2_length; /* Data segment 2 length. */
1250 } cmd_entry_t;
1251
1252 /*
1253 * ISP queue - 64-Bit addressing, command entry structure definition.
1254 */
1255 #define COMMAND_A64_TYPE 0x19 /* Command A64 entry */
1256 typedef struct {
1257 uint8_t entry_type; /* Entry type. */
1258 uint8_t entry_count; /* Entry count. */
1259 uint8_t sys_define; /* System defined. */
1260 uint8_t entry_status; /* Entry Status. */
1261 uint32_t handle; /* System handle. */
1262 target_id_t target; /* SCSI ID */
1263 uint16_t lun; /* SCSI LUN */
1264 uint16_t control_flags; /* Control flags. */
1265 uint16_t reserved_1;
1266 uint16_t timeout; /* Command timeout. */
1267 uint16_t dseg_count; /* Data segment count. */
1268 uint8_t scsi_cdb[MAX_CMDSZ]; /* SCSI command words. */
1269 uint32_t byte_count; /* Total byte count. */
1270 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1271 uint32_t dseg_0_length; /* Data segment 0 length. */
1272 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1273 uint32_t dseg_1_length; /* Data segment 1 length. */
1274 } cmd_a64_entry_t, request_t;
1275
1276 /*
1277 * ISP queue - continuation entry structure definition.
1278 */
1279 #define CONTINUE_TYPE 0x02 /* Continuation entry. */
1280 typedef struct {
1281 uint8_t entry_type; /* Entry type. */
1282 uint8_t entry_count; /* Entry count. */
1283 uint8_t sys_define; /* System defined. */
1284 uint8_t entry_status; /* Entry Status. */
1285 uint32_t reserved;
1286 uint32_t dseg_0_address; /* Data segment 0 address. */
1287 uint32_t dseg_0_length; /* Data segment 0 length. */
1288 uint32_t dseg_1_address; /* Data segment 1 address. */
1289 uint32_t dseg_1_length; /* Data segment 1 length. */
1290 uint32_t dseg_2_address; /* Data segment 2 address. */
1291 uint32_t dseg_2_length; /* Data segment 2 length. */
1292 uint32_t dseg_3_address; /* Data segment 3 address. */
1293 uint32_t dseg_3_length; /* Data segment 3 length. */
1294 uint32_t dseg_4_address; /* Data segment 4 address. */
1295 uint32_t dseg_4_length; /* Data segment 4 length. */
1296 uint32_t dseg_5_address; /* Data segment 5 address. */
1297 uint32_t dseg_5_length; /* Data segment 5 length. */
1298 uint32_t dseg_6_address; /* Data segment 6 address. */
1299 uint32_t dseg_6_length; /* Data segment 6 length. */
1300 } cont_entry_t;
1301
1302 /*
1303 * ISP queue - 64-Bit addressing, continuation entry structure definition.
1304 */
1305 #define CONTINUE_A64_TYPE 0x0A /* Continuation A64 entry. */
1306 typedef struct {
1307 uint8_t entry_type; /* Entry type. */
1308 uint8_t entry_count; /* Entry count. */
1309 uint8_t sys_define; /* System defined. */
1310 uint8_t entry_status; /* Entry Status. */
1311 uint32_t dseg_0_address[2]; /* Data segment 0 address. */
1312 uint32_t dseg_0_length; /* Data segment 0 length. */
1313 uint32_t dseg_1_address[2]; /* Data segment 1 address. */
1314 uint32_t dseg_1_length; /* Data segment 1 length. */
1315 uint32_t dseg_2_address [2]; /* Data segment 2 address. */
1316 uint32_t dseg_2_length; /* Data segment 2 length. */
1317 uint32_t dseg_3_address[2]; /* Data segment 3 address. */
1318 uint32_t dseg_3_length; /* Data segment 3 length. */
1319 uint32_t dseg_4_address[2]; /* Data segment 4 address. */
1320 uint32_t dseg_4_length; /* Data segment 4 length. */
1321 } cont_a64_entry_t;
1322
1323 /*
1324 * ISP queue - status entry structure definition.
1325 */
1326 #define STATUS_TYPE 0x03 /* Status entry. */
1327 typedef struct {
1328 uint8_t entry_type; /* Entry type. */
1329 uint8_t entry_count; /* Entry count. */
1330 uint8_t sys_define; /* System defined. */
1331 uint8_t entry_status; /* Entry Status. */
1332 uint32_t handle; /* System handle. */
1333 uint16_t scsi_status; /* SCSI status. */
1334 uint16_t comp_status; /* Completion status. */
1335 uint16_t state_flags; /* State flags. */
1336 uint16_t status_flags; /* Status flags. */
1337 uint16_t rsp_info_len; /* Response Info Length. */
1338 uint16_t req_sense_length; /* Request sense data length. */
1339 uint32_t residual_length; /* Residual transfer length. */
1340 uint8_t rsp_info[8]; /* FCP response information. */
1341 uint8_t req_sense_data[32]; /* Request sense data. */
1342 } sts_entry_t;
1343
1344 /*
1345 * Status entry entry status
1346 */
1347 #define RF_RQ_DMA_ERROR BIT_6 /* Request Queue DMA error. */
1348 #define RF_INV_E_ORDER BIT_5 /* Invalid entry order. */
1349 #define RF_INV_E_COUNT BIT_4 /* Invalid entry count. */
1350 #define RF_INV_E_PARAM BIT_3 /* Invalid entry parameter. */
1351 #define RF_INV_E_TYPE BIT_2 /* Invalid entry type. */
1352 #define RF_BUSY BIT_1 /* Busy */
1353 #define RF_MASK (RF_RQ_DMA_ERROR | RF_INV_E_ORDER | RF_INV_E_COUNT | \
1354 RF_INV_E_PARAM | RF_INV_E_TYPE | RF_BUSY)
1355 #define RF_MASK_24XX (RF_INV_E_ORDER | RF_INV_E_COUNT | RF_INV_E_PARAM | \
1356 RF_INV_E_TYPE)
1357
1358 /*
1359 * Status entry SCSI status bit definitions.
1360 */
1361 #define SS_MASK 0xfff /* Reserved bits BIT_12-BIT_15*/
1362 #define SS_RESIDUAL_UNDER BIT_11
1363 #define SS_RESIDUAL_OVER BIT_10
1364 #define SS_SENSE_LEN_VALID BIT_9
1365 #define SS_RESPONSE_INFO_LEN_VALID BIT_8
1366
1367 #define SS_RESERVE_CONFLICT (BIT_4 | BIT_3)
1368 #define SS_BUSY_CONDITION BIT_3
1369 #define SS_CONDITION_MET BIT_2
1370 #define SS_CHECK_CONDITION BIT_1
1371
1372 /*
1373 * Status entry completion status
1374 */
1375 #define CS_COMPLETE 0x0 /* No errors */
1376 #define CS_INCOMPLETE 0x1 /* Incomplete transfer of cmd. */
1377 #define CS_DMA 0x2 /* A DMA direction error. */
1378 #define CS_TRANSPORT 0x3 /* Transport error. */
1379 #define CS_RESET 0x4 /* SCSI bus reset occurred */
1380 #define CS_ABORTED 0x5 /* System aborted command. */
1381 #define CS_TIMEOUT 0x6 /* Timeout error. */
1382 #define CS_DATA_OVERRUN 0x7 /* Data overrun. */
1383
1384 #define CS_DATA_UNDERRUN 0x15 /* Data Underrun. */
1385 #define CS_QUEUE_FULL 0x1C /* Queue Full. */
1386 #define CS_PORT_UNAVAILABLE 0x28 /* Port unavailable */
1387 /* (selection timeout) */
1388 #define CS_PORT_LOGGED_OUT 0x29 /* Port Logged Out */
1389 #define CS_PORT_CONFIG_CHG 0x2A /* Port Configuration Changed */
1390 #define CS_PORT_BUSY 0x2B /* Port Busy */
1391 #define CS_COMPLETE_CHKCOND 0x30 /* Error? */
1392 #define CS_BAD_PAYLOAD 0x80 /* Driver defined */
1393 #define CS_UNKNOWN 0x81 /* Driver defined */
1394 #define CS_RETRY 0x82 /* Driver defined */
1395 #define CS_LOOP_DOWN_ABORT 0x83 /* Driver defined */
1396
1397 /*
1398 * Status entry status flags
1399 */
1400 #define SF_ABTS_TERMINATED BIT_10
1401 #define SF_LOGOUT_SENT BIT_13
1402
1403 /*
1404 * ISP queue - status continuation entry structure definition.
1405 */
1406 #define STATUS_CONT_TYPE 0x10 /* Status continuation entry. */
1407 typedef struct {
1408 uint8_t entry_type; /* Entry type. */
1409 uint8_t entry_count; /* Entry count. */
1410 uint8_t sys_define; /* System defined. */
1411 uint8_t entry_status; /* Entry Status. */
1412 uint8_t data[60]; /* data */
1413 } sts_cont_entry_t;
1414
1415 /*
1416 * ISP queue - RIO Type 1 status entry (32 bit I/O entry handles)
1417 * structure definition.
1418 */
1419 #define STATUS_TYPE_21 0x21 /* Status entry. */
1420 typedef struct {
1421 uint8_t entry_type; /* Entry type. */
1422 uint8_t entry_count; /* Entry count. */
1423 uint8_t handle_count; /* Handle count. */
1424 uint8_t entry_status; /* Entry Status. */
1425 uint32_t handle[15]; /* System handles. */
1426 } sts21_entry_t;
1427
1428 /*
1429 * ISP queue - RIO Type 2 status entry (16 bit I/O entry handles)
1430 * structure definition.
1431 */
1432 #define STATUS_TYPE_22 0x22 /* Status entry. */
1433 typedef struct {
1434 uint8_t entry_type; /* Entry type. */
1435 uint8_t entry_count; /* Entry count. */
1436 uint8_t handle_count; /* Handle count. */
1437 uint8_t entry_status; /* Entry Status. */
1438 uint16_t handle[30]; /* System handles. */
1439 } sts22_entry_t;
1440
1441 /*
1442 * ISP queue - marker entry structure definition.
1443 */
1444 #define MARKER_TYPE 0x04 /* Marker entry. */
1445 typedef struct {
1446 uint8_t entry_type; /* Entry type. */
1447 uint8_t entry_count; /* Entry count. */
1448 uint8_t handle_count; /* Handle count. */
1449 uint8_t entry_status; /* Entry Status. */
1450 uint32_t sys_define_2; /* System defined. */
1451 target_id_t target; /* SCSI ID */
1452 uint8_t modifier; /* Modifier (7-0). */
1453 #define MK_SYNC_ID_LUN 0 /* Synchronize ID/LUN */
1454 #define MK_SYNC_ID 1 /* Synchronize ID */
1455 #define MK_SYNC_ALL 2 /* Synchronize all ID/LUN */
1456 #define MK_SYNC_LIP 3 /* Synchronize all ID/LUN, */
1457 /* clear port changed, */
1458 /* use sequence number. */
1459 uint8_t reserved_1;
1460 uint16_t sequence_number; /* Sequence number of event */
1461 uint16_t lun; /* SCSI LUN */
1462 uint8_t reserved_2[48];
1463 } mrk_entry_t;
1464
1465 /*
1466 * ISP queue - Management Server entry structure definition.
1467 */
1468 #define MS_IOCB_TYPE 0x29 /* Management Server IOCB entry */
1469 typedef struct {
1470 uint8_t entry_type; /* Entry type. */
1471 uint8_t entry_count; /* Entry count. */
1472 uint8_t handle_count; /* Handle count. */
1473 uint8_t entry_status; /* Entry Status. */
1474 uint32_t handle1; /* System handle. */
1475 target_id_t loop_id;
1476 uint16_t status;
1477 uint16_t control_flags; /* Control flags. */
1478 uint16_t reserved2;
1479 uint16_t timeout;
1480 uint16_t cmd_dsd_count;
1481 uint16_t total_dsd_count;
1482 uint8_t type;
1483 uint8_t r_ctl;
1484 uint16_t rx_id;
1485 uint16_t reserved3;
1486 uint32_t handle2;
1487 uint32_t rsp_bytecount;
1488 uint32_t req_bytecount;
1489 uint32_t dseg_req_address[2]; /* Data segment 0 address. */
1490 uint32_t dseg_req_length; /* Data segment 0 length. */
1491 uint32_t dseg_rsp_address[2]; /* Data segment 1 address. */
1492 uint32_t dseg_rsp_length; /* Data segment 1 length. */
1493 } ms_iocb_entry_t;
1494
1495
1496 /*
1497 * ISP queue - Mailbox Command entry structure definition.
1498 */
1499 #define MBX_IOCB_TYPE 0x39
1500 struct mbx_entry {
1501 uint8_t entry_type;
1502 uint8_t entry_count;
1503 uint8_t sys_define1;
1504 /* Use sys_define1 for source type */
1505 #define SOURCE_SCSI 0x00
1506 #define SOURCE_IP 0x01
1507 #define SOURCE_VI 0x02
1508 #define SOURCE_SCTP 0x03
1509 #define SOURCE_MP 0x04
1510 #define SOURCE_MPIOCTL 0x05
1511 #define SOURCE_ASYNC_IOCB 0x07
1512
1513 uint8_t entry_status;
1514
1515 uint32_t handle;
1516 target_id_t loop_id;
1517
1518 uint16_t status;
1519 uint16_t state_flags;
1520 uint16_t status_flags;
1521
1522 uint32_t sys_define2[2];
1523
1524 uint16_t mb0;
1525 uint16_t mb1;
1526 uint16_t mb2;
1527 uint16_t mb3;
1528 uint16_t mb6;
1529 uint16_t mb7;
1530 uint16_t mb9;
1531 uint16_t mb10;
1532 uint32_t reserved_2[2];
1533 uint8_t node_name[WWN_SIZE];
1534 uint8_t port_name[WWN_SIZE];
1535 };
1536
1537 /*
1538 * ISP request and response queue entry sizes
1539 */
1540 #define RESPONSE_ENTRY_SIZE (sizeof(response_t))
1541 #define REQUEST_ENTRY_SIZE (sizeof(request_t))
1542
1543
1544 /*
1545 * 24 bit port ID type definition.
1546 */
1547 typedef union {
1548 uint32_t b24 : 24;
1549
1550 struct {
1551 uint8_t d_id[3];
1552 uint8_t rsvd_1;
1553 } r;
1554
1555 struct {
1556 uint8_t al_pa;
1557 uint8_t area;
1558 uint8_t domain;
1559 uint8_t rsvd_1;
1560 } b;
1561 } port_id_t;
1562 #define INVALID_PORT_ID 0xFFFFFF
1563
1564 /*
1565 * Switch info gathering structure.
1566 */
1567 typedef struct {
1568 port_id_t d_id;
1569 uint8_t node_name[WWN_SIZE];
1570 uint8_t port_name[WWN_SIZE];
1571 } sw_info_t;
1572
1573 /*
1574 * Inquiry command structure.
1575 */
1576 #define INQ_DATA_SIZE 36
1577
1578 /*
1579 * Inquiry mailbox IOCB packet definition.
1580 */
1581 typedef struct {
1582 union {
1583 cmd_a64_entry_t cmd;
1584 sts_entry_t rsp;
1585 struct cmd_type_7 cmd24;
1586 struct sts_entry_24xx rsp24;
1587 } p;
1588 uint8_t inq[INQ_DATA_SIZE];
1589 } inq_cmd_rsp_t;
1590
1591 /*
1592 * Report LUN command structure.
1593 */
1594 #define CHAR_TO_SHORT(a, b) (uint16_t)((uint8_t)b << 8 | (uint8_t)a)
1595
1596 typedef struct {
1597 uint32_t len;
1598 uint32_t rsrv;
1599 } rpt_hdr_t;
1600
1601 typedef struct {
1602 struct {
1603 uint8_t b : 6;
1604 uint8_t address_method : 2;
1605 } msb;
1606 uint8_t lsb;
1607 uint8_t unused[6];
1608 } rpt_lun_t;
1609
1610 typedef struct {
1611 rpt_hdr_t hdr;
1612 rpt_lun_t lst[MAX_LUNS];
1613 } rpt_lun_lst_t;
1614
1615 /*
1616 * Report Lun mailbox IOCB packet definition.
1617 */
1618 typedef struct {
1619 union {
1620 cmd_a64_entry_t cmd;
1621 sts_entry_t rsp;
1622 struct cmd_type_7 cmd24;
1623 struct sts_entry_24xx rsp24;
1624 } p;
1625 rpt_lun_lst_t list;
1626 } rpt_lun_cmd_rsp_t;
1627
1628
1629 /*
1630 * Fibre channel port type.
1631 */
1632 typedef enum {
1633 FCT_UNKNOWN,
1634 FCT_RSCN,
1635 FCT_SWITCH,
1636 FCT_BROADCAST,
1637 FCT_INITIATOR,
1638 FCT_TARGET
1639 } fc_port_type_t;
1640
1641 /*
1642 * Fibre channel port structure.
1643 */
1644 typedef struct fc_port {
1645 struct list_head list;
1646 struct scsi_qla_host *ha;
1647 struct scsi_qla_host *vis_ha; /* only used when suspending lun */
1648
1649 uint8_t node_name[WWN_SIZE];
1650 uint8_t port_name[WWN_SIZE];
1651 port_id_t d_id;
1652 uint16_t loop_id;
1653 uint16_t old_loop_id;
1654
1655 fc_port_type_t port_type;
1656
1657 atomic_t state;
1658 uint32_t flags;
1659
1660 unsigned int os_target_id;
1661
1662 uint16_t iodesc_idx_sent;
1663
1664 int port_login_retry_count;
1665 int login_retry;
1666 atomic_t port_down_timer;
1667
1668 uint8_t device_type;
1669 uint8_t unused;
1670
1671 uint8_t mp_byte; /* multi-path byte (not used) */
1672 uint8_t cur_path; /* current path id */
1673
1674 struct fc_rport *rport;
1675 u32 supported_classes;
1676 } fc_port_t;
1677
1678 /*
1679 * Fibre channel port/lun states.
1680 */
1681 #define FCS_UNCONFIGURED 1
1682 #define FCS_DEVICE_DEAD 2
1683 #define FCS_DEVICE_LOST 3
1684 #define FCS_ONLINE 4
1685 #define FCS_NOT_SUPPORTED 5
1686 #define FCS_FAILOVER 6
1687 #define FCS_FAILOVER_FAILED 7
1688
1689 /*
1690 * FC port flags.
1691 */
1692 #define FCF_FABRIC_DEVICE BIT_0
1693 #define FCF_LOGIN_NEEDED BIT_1
1694 #define FCF_FO_MASKED BIT_2
1695 #define FCF_FAILOVER_NEEDED BIT_3
1696 #define FCF_RESET_NEEDED BIT_4
1697 #define FCF_PERSISTENT_BOUND BIT_5
1698 #define FCF_TAPE_PRESENT BIT_6
1699 #define FCF_FARP_DONE BIT_7
1700 #define FCF_FARP_FAILED BIT_8
1701 #define FCF_FARP_REPLY_NEEDED BIT_9
1702 #define FCF_AUTH_REQ BIT_10
1703 #define FCF_SEND_AUTH_REQ BIT_11
1704 #define FCF_RECEIVE_AUTH_REQ BIT_12
1705 #define FCF_AUTH_SUCCESS BIT_13
1706 #define FCF_RLC_SUPPORT BIT_14
1707 #define FCF_CONFIG BIT_15 /* Needed? */
1708 #define FCF_RESCAN_NEEDED BIT_16
1709 #define FCF_XP_DEVICE BIT_17
1710 #define FCF_MSA_DEVICE BIT_18
1711 #define FCF_EVA_DEVICE BIT_19
1712 #define FCF_MSA_PORT_ACTIVE BIT_20
1713 #define FCF_FAILBACK_DISABLE BIT_21
1714 #define FCF_FAILOVER_DISABLE BIT_22
1715 #define FCF_DSXXX_DEVICE BIT_23
1716 #define FCF_AA_EVA_DEVICE BIT_24
1717 #define FCF_AA_MSA_DEVICE BIT_25
1718
1719 /* No loop ID flag. */
1720 #define FC_NO_LOOP_ID 0x1000
1721
1722 /*
1723 * FC-CT interface
1724 *
1725 * NOTE: All structures are big-endian in form.
1726 */
1727
1728 #define CT_REJECT_RESPONSE 0x8001
1729 #define CT_ACCEPT_RESPONSE 0x8002
1730 #define CT_REASON_CANNOT_PERFORM 0x09
1731 #define CT_EXPL_ALREADY_REGISTERED 0x10
1732
1733 #define NS_N_PORT_TYPE 0x01
1734 #define NS_NL_PORT_TYPE 0x02
1735 #define NS_NX_PORT_TYPE 0x7F
1736
1737 #define GA_NXT_CMD 0x100
1738 #define GA_NXT_REQ_SIZE (16 + 4)
1739 #define GA_NXT_RSP_SIZE (16 + 620)
1740
1741 #define GID_PT_CMD 0x1A1
1742 #define GID_PT_REQ_SIZE (16 + 4)
1743 #define GID_PT_RSP_SIZE (16 + (MAX_FIBRE_DEVICES * 4))
1744
1745 #define GPN_ID_CMD 0x112
1746 #define GPN_ID_REQ_SIZE (16 + 4)
1747 #define GPN_ID_RSP_SIZE (16 + 8)
1748
1749 #define GNN_ID_CMD 0x113
1750 #define GNN_ID_REQ_SIZE (16 + 4)
1751 #define GNN_ID_RSP_SIZE (16 + 8)
1752
1753 #define GFT_ID_CMD 0x117
1754 #define GFT_ID_REQ_SIZE (16 + 4)
1755 #define GFT_ID_RSP_SIZE (16 + 32)
1756
1757 #define RFT_ID_CMD 0x217
1758 #define RFT_ID_REQ_SIZE (16 + 4 + 32)
1759 #define RFT_ID_RSP_SIZE 16
1760
1761 #define RFF_ID_CMD 0x21F
1762 #define RFF_ID_REQ_SIZE (16 + 4 + 2 + 1 + 1)
1763 #define RFF_ID_RSP_SIZE 16
1764
1765 #define RNN_ID_CMD 0x213
1766 #define RNN_ID_REQ_SIZE (16 + 4 + 8)
1767 #define RNN_ID_RSP_SIZE 16
1768
1769 #define RSNN_NN_CMD 0x239
1770 #define RSNN_NN_REQ_SIZE (16 + 8 + 1 + 255)
1771 #define RSNN_NN_RSP_SIZE 16
1772
1773 /*
1774 * HBA attribute types.
1775 */
1776 #define FDMI_HBA_ATTR_COUNT 9
1777 #define FDMI_HBA_NODE_NAME 1
1778 #define FDMI_HBA_MANUFACTURER 2
1779 #define FDMI_HBA_SERIAL_NUMBER 3
1780 #define FDMI_HBA_MODEL 4
1781 #define FDMI_HBA_MODEL_DESCRIPTION 5
1782 #define FDMI_HBA_HARDWARE_VERSION 6
1783 #define FDMI_HBA_DRIVER_VERSION 7
1784 #define FDMI_HBA_OPTION_ROM_VERSION 8
1785 #define FDMI_HBA_FIRMWARE_VERSION 9
1786 #define FDMI_HBA_OS_NAME_AND_VERSION 0xa
1787 #define FDMI_HBA_MAXIMUM_CT_PAYLOAD_LENGTH 0xb
1788
1789 struct ct_fdmi_hba_attr {
1790 uint16_t type;
1791 uint16_t len;
1792 union {
1793 uint8_t node_name[WWN_SIZE];
1794 uint8_t manufacturer[32];
1795 uint8_t serial_num[8];
1796 uint8_t model[16];
1797 uint8_t model_desc[80];
1798 uint8_t hw_version[16];
1799 uint8_t driver_version[32];
1800 uint8_t orom_version[16];
1801 uint8_t fw_version[16];
1802 uint8_t os_version[128];
1803 uint8_t max_ct_len[4];
1804 } a;
1805 };
1806
1807 struct ct_fdmi_hba_attributes {
1808 uint32_t count;
1809 struct ct_fdmi_hba_attr entry[FDMI_HBA_ATTR_COUNT];
1810 };
1811
1812 /*
1813 * Port attribute types.
1814 */
1815 #define FDMI_PORT_ATTR_COUNT 5
1816 #define FDMI_PORT_FC4_TYPES 1
1817 #define FDMI_PORT_SUPPORT_SPEED 2
1818 #define FDMI_PORT_CURRENT_SPEED 3
1819 #define FDMI_PORT_MAX_FRAME_SIZE 4
1820 #define FDMI_PORT_OS_DEVICE_NAME 5
1821 #define FDMI_PORT_HOST_NAME 6
1822
1823 struct ct_fdmi_port_attr {
1824 uint16_t type;
1825 uint16_t len;
1826 union {
1827 uint8_t fc4_types[32];
1828 uint32_t sup_speed;
1829 uint32_t cur_speed;
1830 uint32_t max_frame_size;
1831 uint8_t os_dev_name[32];
1832 uint8_t host_name[32];
1833 } a;
1834 };
1835
1836 /*
1837 * Port Attribute Block.
1838 */
1839 struct ct_fdmi_port_attributes {
1840 uint32_t count;
1841 struct ct_fdmi_port_attr entry[FDMI_PORT_ATTR_COUNT];
1842 };
1843
1844 /* FDMI definitions. */
1845 #define GRHL_CMD 0x100
1846 #define GHAT_CMD 0x101
1847 #define GRPL_CMD 0x102
1848 #define GPAT_CMD 0x110
1849
1850 #define RHBA_CMD 0x200
1851 #define RHBA_RSP_SIZE 16
1852
1853 #define RHAT_CMD 0x201
1854 #define RPRT_CMD 0x210
1855
1856 #define RPA_CMD 0x211
1857 #define RPA_RSP_SIZE 16
1858
1859 #define DHBA_CMD 0x300
1860 #define DHBA_REQ_SIZE (16 + 8)
1861 #define DHBA_RSP_SIZE 16
1862
1863 #define DHAT_CMD 0x301
1864 #define DPRT_CMD 0x310
1865 #define DPA_CMD 0x311
1866
1867 /* CT command header -- request/response common fields */
1868 struct ct_cmd_hdr {
1869 uint8_t revision;
1870 uint8_t in_id[3];
1871 uint8_t gs_type;
1872 uint8_t gs_subtype;
1873 uint8_t options;
1874 uint8_t reserved;
1875 };
1876
1877 /* CT command request */
1878 struct ct_sns_req {
1879 struct ct_cmd_hdr header;
1880 uint16_t command;
1881 uint16_t max_rsp_size;
1882 uint8_t fragment_id;
1883 uint8_t reserved[3];
1884
1885 union {
1886 /* GA_NXT, GPN_ID, GNN_ID, GFT_ID */
1887 struct {
1888 uint8_t reserved;
1889 uint8_t port_id[3];
1890 } port_id;
1891
1892 struct {
1893 uint8_t port_type;
1894 uint8_t domain;
1895 uint8_t area;
1896 uint8_t reserved;
1897 } gid_pt;
1898
1899 struct {
1900 uint8_t reserved;
1901 uint8_t port_id[3];
1902 uint8_t fc4_types[32];
1903 } rft_id;
1904
1905 struct {
1906 uint8_t reserved;
1907 uint8_t port_id[3];
1908 uint16_t reserved2;
1909 uint8_t fc4_feature;
1910 uint8_t fc4_type;
1911 } rff_id;
1912
1913 struct {
1914 uint8_t reserved;
1915 uint8_t port_id[3];
1916 uint8_t node_name[8];
1917 } rnn_id;
1918
1919 struct {
1920 uint8_t node_name[8];
1921 uint8_t name_len;
1922 uint8_t sym_node_name[255];
1923 } rsnn_nn;
1924
1925 struct {
1926 uint8_t hba_indentifier[8];
1927 } ghat;
1928
1929 struct {
1930 uint8_t hba_identifier[8];
1931 uint32_t entry_count;
1932 uint8_t port_name[8];
1933 struct ct_fdmi_hba_attributes attrs;
1934 } rhba;
1935
1936 struct {
1937 uint8_t hba_identifier[8];
1938 struct ct_fdmi_hba_attributes attrs;
1939 } rhat;
1940
1941 struct {
1942 uint8_t port_name[8];
1943 struct ct_fdmi_port_attributes attrs;
1944 } rpa;
1945
1946 struct {
1947 uint8_t port_name[8];
1948 } dhba;
1949
1950 struct {
1951 uint8_t port_name[8];
1952 } dhat;
1953
1954 struct {
1955 uint8_t port_name[8];
1956 } dprt;
1957
1958 struct {
1959 uint8_t port_name[8];
1960 } dpa;
1961 } req;
1962 };
1963
1964 /* CT command response header */
1965 struct ct_rsp_hdr {
1966 struct ct_cmd_hdr header;
1967 uint16_t response;
1968 uint16_t residual;
1969 uint8_t fragment_id;
1970 uint8_t reason_code;
1971 uint8_t explanation_code;
1972 uint8_t vendor_unique;
1973 };
1974
1975 struct ct_sns_gid_pt_data {
1976 uint8_t control_byte;
1977 uint8_t port_id[3];
1978 };
1979
1980 struct ct_sns_rsp {
1981 struct ct_rsp_hdr header;
1982
1983 union {
1984 struct {
1985 uint8_t port_type;
1986 uint8_t port_id[3];
1987 uint8_t port_name[8];
1988 uint8_t sym_port_name_len;
1989 uint8_t sym_port_name[255];
1990 uint8_t node_name[8];
1991 uint8_t sym_node_name_len;
1992 uint8_t sym_node_name[255];
1993 uint8_t init_proc_assoc[8];
1994 uint8_t node_ip_addr[16];
1995 uint8_t class_of_service[4];
1996 uint8_t fc4_types[32];
1997 uint8_t ip_address[16];
1998 uint8_t fabric_port_name[8];
1999 uint8_t reserved;
2000 uint8_t hard_address[3];
2001 } ga_nxt;
2002
2003 struct {
2004 struct ct_sns_gid_pt_data entries[MAX_FIBRE_DEVICES];
2005 } gid_pt;
2006
2007 struct {
2008 uint8_t port_name[8];
2009 } gpn_id;
2010
2011 struct {
2012 uint8_t node_name[8];
2013 } gnn_id;
2014
2015 struct {
2016 uint8_t fc4_types[32];
2017 } gft_id;
2018
2019 struct {
2020 uint32_t entry_count;
2021 uint8_t port_name[8];
2022 struct ct_fdmi_hba_attributes attrs;
2023 } ghat;
2024 } rsp;
2025 };
2026
2027 struct ct_sns_pkt {
2028 union {
2029 struct ct_sns_req req;
2030 struct ct_sns_rsp rsp;
2031 } p;
2032 };
2033
2034 /*
2035 * SNS command structures -- for 2200 compatability.
2036 */
2037 #define RFT_ID_SNS_SCMD_LEN 22
2038 #define RFT_ID_SNS_CMD_SIZE 60
2039 #define RFT_ID_SNS_DATA_SIZE 16
2040
2041 #define RNN_ID_SNS_SCMD_LEN 10
2042 #define RNN_ID_SNS_CMD_SIZE 36
2043 #define RNN_ID_SNS_DATA_SIZE 16
2044
2045 #define GA_NXT_SNS_SCMD_LEN 6
2046 #define GA_NXT_SNS_CMD_SIZE 28
2047 #define GA_NXT_SNS_DATA_SIZE (620 + 16)
2048
2049 #define GID_PT_SNS_SCMD_LEN 6
2050 #define GID_PT_SNS_CMD_SIZE 28
2051 #define GID_PT_SNS_DATA_SIZE (MAX_FIBRE_DEVICES * 4 + 16)
2052
2053 #define GPN_ID_SNS_SCMD_LEN 6
2054 #define GPN_ID_SNS_CMD_SIZE 28
2055 #define GPN_ID_SNS_DATA_SIZE (8 + 16)
2056
2057 #define GNN_ID_SNS_SCMD_LEN 6
2058 #define GNN_ID_SNS_CMD_SIZE 28
2059 #define GNN_ID_SNS_DATA_SIZE (8 + 16)
2060
2061 struct sns_cmd_pkt {
2062 union {
2063 struct {
2064 uint16_t buffer_length;
2065 uint16_t reserved_1;
2066 uint32_t buffer_address[2];
2067 uint16_t subcommand_length;
2068 uint16_t reserved_2;
2069 uint16_t subcommand;
2070 uint16_t size;
2071 uint32_t reserved_3;
2072 uint8_t param[36];
2073 } cmd;
2074
2075 uint8_t rft_data[RFT_ID_SNS_DATA_SIZE];
2076 uint8_t rnn_data[RNN_ID_SNS_DATA_SIZE];
2077 uint8_t gan_data[GA_NXT_SNS_DATA_SIZE];
2078 uint8_t gid_data[GID_PT_SNS_DATA_SIZE];
2079 uint8_t gpn_data[GPN_ID_SNS_DATA_SIZE];
2080 uint8_t gnn_data[GNN_ID_SNS_DATA_SIZE];
2081 } p;
2082 };
2083
2084 /* IO descriptors */
2085 #define MAX_IO_DESCRIPTORS 32
2086
2087 #define ABORT_IOCB_CB 0
2088 #define ADISC_PORT_IOCB_CB 1
2089 #define LOGOUT_PORT_IOCB_CB 2
2090 #define LOGIN_PORT_IOCB_CB 3
2091 #define LAST_IOCB_CB 4
2092
2093 #define IODESC_INVALID_INDEX 0xFFFF
2094 #define IODESC_ADISC_NEEDED 0xFFFE
2095 #define IODESC_LOGIN_NEEDED 0xFFFD
2096
2097 struct io_descriptor {
2098 uint16_t used:1;
2099 uint16_t idx:11;
2100 uint16_t cb_idx:4;
2101
2102 struct timer_list timer;
2103
2104 struct scsi_qla_host *ha;
2105
2106 port_id_t d_id;
2107 fc_port_t *remote_fcport;
2108
2109 uint32_t signature;
2110 };
2111
2112 struct qla_fw_info {
2113 unsigned short addressing; /* addressing method used to load fw */
2114 #define FW_INFO_ADDR_NORMAL 0
2115 #define FW_INFO_ADDR_EXTENDED 1
2116 #define FW_INFO_ADDR_NOMORE 0xffff
2117 unsigned short *fwcode; /* pointer to FW array */
2118 unsigned short *fwlen; /* number of words in array */
2119 unsigned short *fwstart; /* start address for F/W */
2120 unsigned long *lfwstart; /* start address (long) for F/W */
2121 };
2122
2123 struct qla_board_info {
2124 char *drv_name;
2125
2126 char isp_name[8];
2127 struct qla_fw_info *fw_info;
2128 char *fw_fname;
2129 struct scsi_host_template *sht;
2130 };
2131
2132 /* Return data from MBC_GET_ID_LIST call. */
2133 struct gid_list_info {
2134 uint8_t al_pa;
2135 uint8_t area;
2136 uint8_t domain;
2137 uint8_t loop_id_2100; /* ISP2100/ISP2200 -- 4 bytes. */
2138 uint16_t loop_id; /* ISP23XX -- 6 bytes. */
2139 uint16_t reserved_1; /* ISP24XX -- 8 bytes. */
2140 };
2141 #define GID_LIST_SIZE (sizeof(struct gid_list_info) * MAX_FIBRE_DEVICES)
2142
2143 /*
2144 * ISP operations
2145 */
2146 struct isp_operations {
2147
2148 int (*pci_config) (struct scsi_qla_host *);
2149 void (*reset_chip) (struct scsi_qla_host *);
2150 int (*chip_diag) (struct scsi_qla_host *);
2151 void (*config_rings) (struct scsi_qla_host *);
2152 void (*reset_adapter) (struct scsi_qla_host *);
2153 int (*nvram_config) (struct scsi_qla_host *);
2154 void (*update_fw_options) (struct scsi_qla_host *);
2155 int (*load_risc) (struct scsi_qla_host *, uint32_t *);
2156
2157 char * (*pci_info_str) (struct scsi_qla_host *, char *);
2158 char * (*fw_version_str) (struct scsi_qla_host *, char *);
2159
2160 irqreturn_t (*intr_handler) (int, void *, struct pt_regs *);
2161 void (*enable_intrs) (struct scsi_qla_host *);
2162 void (*disable_intrs) (struct scsi_qla_host *);
2163
2164 int (*abort_command) (struct scsi_qla_host *, srb_t *);
2165 int (*abort_target) (struct fc_port *);
2166 int (*fabric_login) (struct scsi_qla_host *, uint16_t, uint8_t,
2167 uint8_t, uint8_t, uint16_t *, uint8_t);
2168 int (*fabric_logout) (struct scsi_qla_host *, uint16_t, uint8_t,
2169 uint8_t, uint8_t);
2170
2171 uint16_t (*calc_req_entries) (uint16_t);
2172 void (*build_iocbs) (srb_t *, cmd_entry_t *, uint16_t);
2173 void * (*prep_ms_iocb) (struct scsi_qla_host *, uint32_t, uint32_t);
2174 void * (*prep_ms_fdmi_iocb) (struct scsi_qla_host *, uint32_t,
2175 uint32_t);
2176
2177 uint8_t * (*read_nvram) (struct scsi_qla_host *, uint8_t *,
2178 uint32_t, uint32_t);
2179 int (*write_nvram) (struct scsi_qla_host *, uint8_t *, uint32_t,
2180 uint32_t);
2181
2182 void (*fw_dump) (struct scsi_qla_host *, int);
2183 void (*ascii_fw_dump) (struct scsi_qla_host *);
2184 };
2185
2186 /*
2187 * Linux Host Adapter structure
2188 */
2189 typedef struct scsi_qla_host {
2190 struct list_head list;
2191
2192 /* Commonly used flags and state information. */
2193 struct Scsi_Host *host;
2194 struct pci_dev *pdev;
2195
2196 unsigned long host_no;
2197 unsigned long instance;
2198
2199 volatile struct {
2200 uint32_t init_done :1;
2201 uint32_t online :1;
2202 uint32_t mbox_int :1;
2203 uint32_t mbox_busy :1;
2204 uint32_t rscn_queue_overflow :1;
2205 uint32_t reset_active :1;
2206
2207 uint32_t management_server_logged_in :1;
2208 uint32_t process_response_queue :1;
2209
2210 uint32_t disable_risc_code_load :1;
2211 uint32_t enable_64bit_addressing :1;
2212 uint32_t enable_lip_reset :1;
2213 uint32_t enable_lip_full_login :1;
2214 uint32_t enable_target_reset :1;
2215 uint32_t enable_led_scheme :1;
2216 uint32_t msi_enabled :1;
2217 uint32_t msix_enabled :1;
2218 } flags;
2219
2220 atomic_t loop_state;
2221 #define LOOP_TIMEOUT 1
2222 #define LOOP_DOWN 2
2223 #define LOOP_UP 3
2224 #define LOOP_UPDATE 4
2225 #define LOOP_READY 5
2226 #define LOOP_DEAD 6
2227
2228 unsigned long dpc_flags;
2229 #define RESET_MARKER_NEEDED 0 /* Send marker to ISP. */
2230 #define RESET_ACTIVE 1
2231 #define ISP_ABORT_NEEDED 2 /* Initiate ISP abort. */
2232 #define ABORT_ISP_ACTIVE 3 /* ISP abort in progress. */
2233 #define LOOP_RESYNC_NEEDED 4 /* Device Resync needed. */
2234 #define LOOP_RESYNC_ACTIVE 5
2235 #define LOCAL_LOOP_UPDATE 6 /* Perform a local loop update. */
2236 #define RSCN_UPDATE 7 /* Perform an RSCN update. */
2237 #define MAILBOX_RETRY 8
2238 #define ISP_RESET_NEEDED 9 /* Initiate a ISP reset. */
2239 #define FAILOVER_EVENT_NEEDED 10
2240 #define FAILOVER_EVENT 11
2241 #define FAILOVER_NEEDED 12
2242 #define SCSI_RESTART_NEEDED 13 /* Processes SCSI retry queue. */
2243 #define PORT_RESTART_NEEDED 14 /* Processes Retry queue. */
2244 #define RESTART_QUEUES_NEEDED 15 /* Restarts the Lun queue. */
2245 #define ABORT_QUEUES_NEEDED 16
2246 #define RELOGIN_NEEDED 17
2247 #define LOGIN_RETRY_NEEDED 18 /* Initiate required fabric logins. */
2248 #define REGISTER_FC4_NEEDED 19 /* SNS FC4 registration required. */
2249 #define ISP_ABORT_RETRY 20 /* ISP aborted. */
2250 #define FCPORT_RESCAN_NEEDED 21 /* IO descriptor processing needed */
2251 #define IODESC_PROCESS_NEEDED 22 /* IO descriptor processing needed */
2252 #define IOCTL_ERROR_RECOVERY 23
2253 #define LOOP_RESET_NEEDED 24
2254 #define BEACON_BLINK_NEEDED 25
2255 #define REGISTER_FDMI_NEEDED 26
2256
2257 uint32_t device_flags;
2258 #define DFLG_LOCAL_DEVICES BIT_0
2259 #define DFLG_RETRY_LOCAL_DEVICES BIT_1
2260 #define DFLG_FABRIC_DEVICES BIT_2
2261 #define SWITCH_FOUND BIT_3
2262 #define DFLG_NO_CABLE BIT_4
2263
2264 /* SRB cache. */
2265 #define SRB_MIN_REQ 128
2266 mempool_t *srb_mempool;
2267
2268 /* This spinlock is used to protect "io transactions", you must
2269 * aquire it before doing any IO to the card, eg with RD_REG*() and
2270 * WRT_REG*() for the duration of your entire commandtransaction.
2271 *
2272 * This spinlock is of lower priority than the io request lock.
2273 */
2274
2275 spinlock_t hardware_lock ____cacheline_aligned;
2276
2277 device_reg_t __iomem *iobase; /* Base I/O address */
2278 unsigned long pio_address;
2279 unsigned long pio_length;
2280 #define MIN_IOBASE_LEN 0x100
2281
2282 /* ISP ring lock, rings, and indexes */
2283 dma_addr_t request_dma; /* Physical address. */
2284 request_t *request_ring; /* Base virtual address */
2285 request_t *request_ring_ptr; /* Current address. */
2286 uint16_t req_ring_index; /* Current index. */
2287 uint16_t req_q_cnt; /* Number of available entries. */
2288 uint16_t request_q_length;
2289
2290 dma_addr_t response_dma; /* Physical address. */
2291 response_t *response_ring; /* Base virtual address */
2292 response_t *response_ring_ptr; /* Current address. */
2293 uint16_t rsp_ring_index; /* Current index. */
2294 uint16_t response_q_length;
2295
2296 struct isp_operations isp_ops;
2297
2298 /* Outstandings ISP commands. */
2299 srb_t *outstanding_cmds[MAX_OUTSTANDING_COMMANDS];
2300 uint32_t current_outstanding_cmd;
2301 srb_t *status_srb; /* Status continuation entry. */
2302
2303 uint16_t revision;
2304 uint8_t ports;
2305
2306 /* ISP configuration data. */
2307 uint16_t loop_id; /* Host adapter loop id */
2308 uint16_t fb_rev;
2309
2310 port_id_t d_id; /* Host adapter port id */
2311 uint16_t max_public_loop_ids;
2312 uint16_t min_external_loopid; /* First external loop Id */
2313
2314 uint16_t link_data_rate; /* F/W operating speed */
2315
2316 uint8_t current_topology;
2317 uint8_t prev_topology;
2318 #define ISP_CFG_NL 1
2319 #define ISP_CFG_N 2
2320 #define ISP_CFG_FL 4
2321 #define ISP_CFG_F 8
2322
2323 uint8_t operating_mode; /* F/W operating mode */
2324 #define LOOP 0
2325 #define P2P 1
2326 #define LOOP_P2P 2
2327 #define P2P_LOOP 3
2328
2329 uint8_t marker_needed;
2330
2331 uint8_t interrupts_on;
2332
2333 /* HBA serial number */
2334 uint8_t serial0;
2335 uint8_t serial1;
2336 uint8_t serial2;
2337
2338 /* NVRAM configuration data */
2339 uint16_t nvram_size;
2340 uint16_t nvram_base;
2341
2342 uint16_t loop_reset_delay;
2343 uint8_t retry_count;
2344 uint8_t login_timeout;
2345 uint16_t r_a_tov;
2346 int port_down_retry_count;
2347 uint8_t mbx_count;
2348 uint16_t last_loop_id;
2349 uint16_t mgmt_svr_loop_id;
2350
2351 uint32_t login_retry_count;
2352
2353 /* Fibre Channel Device List. */
2354 struct list_head fcports;
2355 struct list_head rscn_fcports;
2356
2357 struct io_descriptor io_descriptors[MAX_IO_DESCRIPTORS];
2358 uint16_t iodesc_signature;
2359
2360 /* RSCN queue. */
2361 uint32_t rscn_queue[MAX_RSCN_COUNT];
2362 uint8_t rscn_in_ptr;
2363 uint8_t rscn_out_ptr;
2364
2365 /* SNS command interfaces. */
2366 ms_iocb_entry_t *ms_iocb;
2367 dma_addr_t ms_iocb_dma;
2368 struct ct_sns_pkt *ct_sns;
2369 dma_addr_t ct_sns_dma;
2370 /* SNS command interfaces for 2200. */
2371 struct sns_cmd_pkt *sns_cmd;
2372 dma_addr_t sns_cmd_dma;
2373
2374 pid_t dpc_pid;
2375 int dpc_should_die;
2376 struct completion dpc_inited;
2377 struct completion dpc_exited;
2378 struct semaphore *dpc_wait;
2379 uint8_t dpc_active; /* DPC routine is active */
2380
2381 /* Timeout timers. */
2382 uint8_t loop_down_abort_time; /* port down timer */
2383 atomic_t loop_down_timer; /* loop down timer */
2384 uint8_t link_down_timeout; /* link down timeout */
2385
2386 uint32_t timer_active;
2387 struct timer_list timer;
2388
2389 dma_addr_t gid_list_dma;
2390 struct gid_list_info *gid_list;
2391 int gid_list_info_size;
2392
2393 dma_addr_t rlc_rsp_dma;
2394 rpt_lun_cmd_rsp_t *rlc_rsp;
2395
2396 /* Small DMA pool allocations -- maximum 256 bytes in length. */
2397 #define DMA_POOL_SIZE 256
2398 struct dma_pool *s_dma_pool;
2399
2400 dma_addr_t init_cb_dma;
2401 init_cb_t *init_cb;
2402 int init_cb_size;
2403
2404 dma_addr_t iodesc_pd_dma;
2405 port_database_t *iodesc_pd;
2406
2407 /* These are used by mailbox operations. */
2408 volatile uint16_t mailbox_out[MAILBOX_REGISTER_COUNT];
2409
2410 mbx_cmd_t *mcp;
2411 unsigned long mbx_cmd_flags;
2412 #define MBX_INTERRUPT 1
2413 #define MBX_INTR_WAIT 2
2414 #define MBX_UPDATE_FLASH_ACTIVE 3
2415
2416 spinlock_t mbx_reg_lock; /* Mbx Cmd Register Lock */
2417
2418 struct semaphore mbx_cmd_sem; /* Serialialize mbx access */
2419 struct semaphore mbx_intr_sem; /* Used for completion notification */
2420
2421 uint32_t mbx_flags;
2422 #define MBX_IN_PROGRESS BIT_0
2423 #define MBX_BUSY BIT_1 /* Got the Access */
2424 #define MBX_SLEEPING_ON_SEM BIT_2
2425 #define MBX_POLLING_FOR_COMP BIT_3
2426 #define MBX_COMPLETED BIT_4
2427 #define MBX_TIMEDOUT BIT_5
2428 #define MBX_ACCESS_TIMEDOUT BIT_6
2429
2430 mbx_cmd_t mc;
2431
2432 /* Basic firmware related information. */
2433 struct qla_board_info *brd_info;
2434 uint16_t fw_major_version;
2435 uint16_t fw_minor_version;
2436 uint16_t fw_subminor_version;
2437 uint16_t fw_attributes;
2438 uint32_t fw_memory_size;
2439 uint32_t fw_transfer_size;
2440
2441 uint16_t fw_options[16]; /* slots: 1,2,3,10,11 */
2442 uint8_t fw_seriallink_options[4];
2443 uint16_t fw_seriallink_options24[4];
2444
2445 /* Firmware dump information. */
2446 void *fw_dump;
2447 int fw_dump_order;
2448 int fw_dump_reading;
2449 char *fw_dump_buffer;
2450 int fw_dump_buffer_len;
2451
2452 int fw_dumped;
2453 void *fw_dump24;
2454 int fw_dump24_len;
2455
2456 uint8_t host_str[16];
2457 uint32_t pci_attr;
2458
2459 uint16_t product_id[4];
2460
2461 uint8_t model_number[16+1];
2462 #define BINZERO "\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0"
2463 char *model_desc;
2464 uint8_t adapter_id[16+1];
2465
2466 uint8_t *node_name;
2467 uint8_t *port_name;
2468 uint32_t isp_abort_cnt;
2469
2470 /* Needed for BEACON */
2471 uint16_t beacon_blink_led;
2472 uint16_t beacon_green_on;
2473 } scsi_qla_host_t;
2474
2475
2476 /*
2477 * Macros to help code, maintain, etc.
2478 */
2479 #define LOOP_TRANSITION(ha) \
2480 (test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
2481 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags))
2482
2483 #define LOOP_NOT_READY(ha) \
2484 ((test_bit(ISP_ABORT_NEEDED, &ha->dpc_flags) || \
2485 test_bit(ABORT_ISP_ACTIVE, &ha->dpc_flags) || \
2486 test_bit(LOOP_RESYNC_NEEDED, &ha->dpc_flags) || \
2487 test_bit(LOOP_RESYNC_ACTIVE, &ha->dpc_flags)) || \
2488 atomic_read(&ha->loop_state) == LOOP_DOWN)
2489
2490 #define LOOP_RDY(ha) (!LOOP_NOT_READY(ha))
2491
2492 #define TGT_Q(ha, t) (ha->otgt[t])
2493
2494 #define to_qla_host(x) ((scsi_qla_host_t *) (x)->hostdata)
2495
2496 #define qla_printk(level, ha, format, arg...) \
2497 dev_printk(level , &((ha)->pdev->dev) , format , ## arg)
2498
2499 /*
2500 * qla2x00 local function return status codes
2501 */
2502 #define MBS_MASK 0x3fff
2503
2504 #define QLA_SUCCESS (MBS_COMMAND_COMPLETE & MBS_MASK)
2505 #define QLA_INVALID_COMMAND (MBS_INVALID_COMMAND & MBS_MASK)
2506 #define QLA_INTERFACE_ERROR (MBS_HOST_INTERFACE_ERROR & MBS_MASK)
2507 #define QLA_TEST_FAILED (MBS_TEST_FAILED & MBS_MASK)
2508 #define QLA_COMMAND_ERROR (MBS_COMMAND_ERROR & MBS_MASK)
2509 #define QLA_PARAMETER_ERROR (MBS_COMMAND_PARAMETER_ERROR & MBS_MASK)
2510 #define QLA_PORT_ID_USED (MBS_PORT_ID_USED & MBS_MASK)
2511 #define QLA_LOOP_ID_USED (MBS_LOOP_ID_USED & MBS_MASK)
2512 #define QLA_ALL_IDS_IN_USE (MBS_ALL_IDS_IN_USE & MBS_MASK)
2513 #define QLA_NOT_LOGGED_IN (MBS_NOT_LOGGED_IN & MBS_MASK)
2514
2515 #define QLA_FUNCTION_TIMEOUT 0x100
2516 #define QLA_FUNCTION_PARAMETER_ERROR 0x101
2517 #define QLA_FUNCTION_FAILED 0x102
2518 #define QLA_MEMORY_ALLOC_FAILED 0x103
2519 #define QLA_LOCK_TIMEOUT 0x104
2520 #define QLA_ABORTED 0x105
2521 #define QLA_SUSPENDED 0x106
2522 #define QLA_BUSY 0x107
2523 #define QLA_RSCNS_HANDLED 0x108
2524 #define QLA_ALREADY_REGISTERED 0x109
2525
2526 /*
2527 * Stat info for all adpaters
2528 */
2529 struct _qla2x00stats {
2530 unsigned long mboxtout; /* mailbox timeouts */
2531 unsigned long mboxerr; /* mailbox errors */
2532 unsigned long ispAbort; /* ISP aborts */
2533 unsigned long debugNo;
2534 unsigned long loop_resync;
2535 unsigned long outarray_full;
2536 unsigned long retry_q_cnt;
2537 };
2538
2539 #define NVRAM_DELAY() udelay(10)
2540
2541 #define INVALID_HANDLE (MAX_OUTSTANDING_COMMANDS+1)
2542
2543 /*
2544 * Flash support definitions
2545 */
2546 #define FLASH_IMAGE_SIZE 131072
2547
2548 #include "qla_gbl.h"
2549 #include "qla_dbg.h"
2550 #include "qla_inline.h"
2551
2552 /*
2553 * String arrays
2554 */
2555 #define LINESIZE 256
2556 #define MAXARGS 26
2557
2558 #define CMD_SP(Cmnd) ((Cmnd)->SCp.ptr)
2559 #define CMD_COMPL_STATUS(Cmnd) ((Cmnd)->SCp.this_residual)
2560 #define CMD_RESID_LEN(Cmnd) ((Cmnd)->SCp.buffers_residual)
2561 #define CMD_SCSI_STATUS(Cmnd) ((Cmnd)->SCp.Status)
2562 #define CMD_ACTUAL_SNSLEN(Cmnd) ((Cmnd)->SCp.Message)
2563 #define CMD_ENTRY_STATUS(Cmnd) ((Cmnd)->SCp.have_data_in)
2564
2565 #endif
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