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[PATCH] W1: w1_netlink: New init/fini netlink callbacks.
[linux-2.6/verdex.git] / drivers / scsi / sata_sis.c
blob7d1aaa99aaae0d502eaf838c5766779b36a42ed9
1 /*
2 * sata_sis.c - Silicon Integrated Systems SATA
3 *
4 * Maintained by: Uwe Koziolek
5 * Please ALWAYS copy linux-ide@vger.kernel.org
6 * on emails.
7 *
8 * Copyright 2004 Uwe Koziolek
9 *
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2, or (at your option)
14 * any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; see the file COPYING. If not, write to
23 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
24 *
25 *
26 * libata documentation is available via 'make {ps|pdf}docs',
27 * as Documentation/DocBook/libata.*
28 *
29 * Hardware documentation available under NDA.
30 *
31 */
32
33 #include <linux/config.h>
34 #include <linux/kernel.h>
35 #include <linux/module.h>
36 #include <linux/pci.h>
37 #include <linux/init.h>
38 #include <linux/blkdev.h>
39 #include <linux/delay.h>
40 #include <linux/interrupt.h>
41 #include "scsi.h"
42 #include <scsi/scsi_host.h>
43 #include <linux/libata.h>
44
45 #define DRV_NAME "sata_sis"
46 #define DRV_VERSION "0.5"
47
48 enum {
49 sis_180 = 0,
50 SIS_SCR_PCI_BAR = 5,
51
52 /* PCI configuration registers */
53 SIS_GENCTL = 0x54, /* IDE General Control register */
54 SIS_SCR_BASE = 0xc0, /* sata0 phy SCR registers */
55 SIS180_SATA1_OFS = 0x10, /* offset from sata0->sata1 phy regs */
56 SIS182_SATA1_OFS = 0x20, /* offset from sata0->sata1 phy regs */
57 SIS_PMR = 0x90, /* port mapping register */
58 SIS_PMR_COMBINED = 0x30,
59
60 /* random bits */
61 SIS_FLAG_CFGSCR = (1 << 30), /* host flag: SCRs via PCI cfg */
62
63 GENCTL_IOMAPPED_SCR = (1 << 26), /* if set, SCRs are in IO space */
64 };
65
66 static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent);
67 static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg);
68 static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val);
69
70 static struct pci_device_id sis_pci_tbl[] = {
71 { PCI_VENDOR_ID_SI, 0x180, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sis_180 },
72 { PCI_VENDOR_ID_SI, 0x181, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sis_180 },
73 { PCI_VENDOR_ID_SI, 0x182, PCI_ANY_ID, PCI_ANY_ID, 0, 0, sis_180 },
74 { } /* terminate list */
75 };
76
77
78 static struct pci_driver sis_pci_driver = {
79 .name = DRV_NAME,
80 .id_table = sis_pci_tbl,
81 .probe = sis_init_one,
82 .remove = ata_pci_remove_one,
83 };
84
85 static Scsi_Host_Template sis_sht = {
86 .module = THIS_MODULE,
87 .name = DRV_NAME,
88 .ioctl = ata_scsi_ioctl,
89 .queuecommand = ata_scsi_queuecmd,
90 .eh_strategy_handler = ata_scsi_error,
91 .can_queue = ATA_DEF_QUEUE,
92 .this_id = ATA_SHT_THIS_ID,
93 .sg_tablesize = ATA_MAX_PRD,
94 .max_sectors = ATA_MAX_SECTORS,
95 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
96 .emulated = ATA_SHT_EMULATED,
97 .use_clustering = ATA_SHT_USE_CLUSTERING,
98 .proc_name = DRV_NAME,
99 .dma_boundary = ATA_DMA_BOUNDARY,
100 .slave_configure = ata_scsi_slave_config,
101 .bios_param = ata_std_bios_param,
102 .ordered_flush = 1,
103 };
104
105 static struct ata_port_operations sis_ops = {
106 .port_disable = ata_port_disable,
107 .tf_load = ata_tf_load,
108 .tf_read = ata_tf_read,
109 .check_status = ata_check_status,
110 .exec_command = ata_exec_command,
111 .dev_select = ata_std_dev_select,
112 .phy_reset = sata_phy_reset,
113 .bmdma_setup = ata_bmdma_setup,
114 .bmdma_start = ata_bmdma_start,
115 .bmdma_stop = ata_bmdma_stop,
116 .bmdma_status = ata_bmdma_status,
117 .qc_prep = ata_qc_prep,
118 .qc_issue = ata_qc_issue_prot,
119 .eng_timeout = ata_eng_timeout,
120 .irq_handler = ata_interrupt,
121 .irq_clear = ata_bmdma_irq_clear,
122 .scr_read = sis_scr_read,
123 .scr_write = sis_scr_write,
124 .port_start = ata_port_start,
125 .port_stop = ata_port_stop,
126 .host_stop = ata_host_stop,
127 };
128
129 static struct ata_port_info sis_port_info = {
130 .sht = &sis_sht,
131 .host_flags = ATA_FLAG_SATA | ATA_FLAG_SATA_RESET |
132 ATA_FLAG_NO_LEGACY,
133 .pio_mask = 0x1f,
134 .mwdma_mask = 0x7,
135 .udma_mask = 0x7f,
136 .port_ops = &sis_ops,
137 };
138
139
140 MODULE_AUTHOR("Uwe Koziolek");
141 MODULE_DESCRIPTION("low-level driver for Silicon Integratad Systems SATA controller");
142 MODULE_LICENSE("GPL");
143 MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
144 MODULE_VERSION(DRV_VERSION);
145
146 static unsigned int get_scr_cfg_addr(unsigned int port_no, unsigned int sc_reg, int device)
147 {
148 unsigned int addr = SIS_SCR_BASE + (4 * sc_reg);
149
150 if (port_no)
151 if (device == 0x182)
152 addr += SIS182_SATA1_OFS;
153 else
154 addr += SIS180_SATA1_OFS;
155 return addr;
156 }
157
158 static u32 sis_scr_cfg_read (struct ata_port *ap, unsigned int sc_reg)
159 {
160 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
161 unsigned int cfg_addr = get_scr_cfg_addr(ap->port_no, sc_reg, pdev->device);
162 u32 val, val2;
163 u8 pmr;
164
165 if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
166 return 0xffffffff;
167
168 pci_read_config_byte(pdev, SIS_PMR, &pmr);
169
170 pci_read_config_dword(pdev, cfg_addr, &val);
171
172 if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED))
173 pci_read_config_dword(pdev, cfg_addr+0x10, &val2);
174
175 return val|val2;
176 }
177
178 static void sis_scr_cfg_write (struct ata_port *ap, unsigned int scr, u32 val)
179 {
180 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
181 unsigned int cfg_addr = get_scr_cfg_addr(ap->port_no, scr, pdev->device);
182 u8 pmr;
183
184 if (scr == SCR_ERROR) /* doesn't exist in PCI cfg space */
185 return;
186
187 pci_read_config_byte(pdev, SIS_PMR, &pmr);
188
189 pci_write_config_dword(pdev, cfg_addr, val);
190
191 if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED))
192 pci_write_config_dword(pdev, cfg_addr+0x10, val);
193 }
194
195 static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg)
196 {
197 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
198 u32 val,val2;
199 u8 pmr;
200
201 if (sc_reg > SCR_CONTROL)
202 return 0xffffffffU;
203
204 if (ap->flags & SIS_FLAG_CFGSCR)
205 return sis_scr_cfg_read(ap, sc_reg);
206
207 pci_read_config_byte(pdev, SIS_PMR, &pmr);
208
209 val = inl(ap->ioaddr.scr_addr + (sc_reg * 4));
210
211 if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED))
212 val2 = inl(ap->ioaddr.scr_addr + (sc_reg * 4)+0x10);
213
214 return val|val2;
215 }
216
217 static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val)
218 {
219 struct pci_dev *pdev = to_pci_dev(ap->host_set->dev);
220 u8 pmr;
221
222 if (sc_reg > SCR_CONTROL)
223 return;
224
225 pci_read_config_byte(pdev, SIS_PMR, &pmr);
226
227 if (ap->flags & SIS_FLAG_CFGSCR)
228 sis_scr_cfg_write(ap, sc_reg, val);
229 else {
230 outl(val, ap->ioaddr.scr_addr + (sc_reg * 4));
231 if ((pdev->device == 0x182) || (pmr & SIS_PMR_COMBINED))
232 outl(val, ap->ioaddr.scr_addr + (sc_reg * 4)+0x10);
233 }
234 }
235
236 /* move to PCI layer, integrate w/ MSI stuff */
237 static void pci_enable_intx(struct pci_dev *pdev)
238 {
239 u16 pci_command;
240
241 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
242 if (pci_command & PCI_COMMAND_INTX_DISABLE) {
243 pci_command &= ~PCI_COMMAND_INTX_DISABLE;
244 pci_write_config_word(pdev, PCI_COMMAND, pci_command);
245 }
246 }
247
248 static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
249 {
250 struct ata_probe_ent *probe_ent = NULL;
251 int rc;
252 u32 genctl;
253 struct ata_port_info *ppi;
254 int pci_dev_busy = 0;
255 u8 pmr;
256 u8 port2_start;
257
258 rc = pci_enable_device(pdev);
259 if (rc)
260 return rc;
261
262 rc = pci_request_regions(pdev, DRV_NAME);
263 if (rc) {
264 pci_dev_busy = 1;
265 goto err_out;
266 }
267
268 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
269 if (rc)
270 goto err_out_regions;
271 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
272 if (rc)
273 goto err_out_regions;
274
275 ppi = &sis_port_info;
276 probe_ent = ata_pci_init_native_mode(pdev, &ppi);
277 if (!probe_ent) {
278 rc = -ENOMEM;
279 goto err_out_regions;
280 }
281
282 /* check and see if the SCRs are in IO space or PCI cfg space */
283 pci_read_config_dword(pdev, SIS_GENCTL, &genctl);
284 if ((genctl & GENCTL_IOMAPPED_SCR) == 0)
285 probe_ent->host_flags |= SIS_FLAG_CFGSCR;
286
287 /* if hardware thinks SCRs are in IO space, but there are
288 * no IO resources assigned, change to PCI cfg space.
289 */
290 if ((!(probe_ent->host_flags & SIS_FLAG_CFGSCR)) &&
291 ((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) ||
292 (pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) {
293 genctl &= ~GENCTL_IOMAPPED_SCR;
294 pci_write_config_dword(pdev, SIS_GENCTL, genctl);
295 probe_ent->host_flags |= SIS_FLAG_CFGSCR;
296 }
297
298 pci_read_config_byte(pdev, SIS_PMR, &pmr);
299 if (ent->device != 0x182) {
300 if ((pmr & SIS_PMR_COMBINED) == 0) {
301 printk(KERN_INFO "sata_sis: Detected SiS 180/181 chipset in SATA mode\n");
302 port2_start=0x64;
303 }
304 else {
305 printk(KERN_INFO "sata_sis: Detected SiS 180/181 chipset in combined mode\n");
306 port2_start=0;
307 }
308 }
309 else {
310 printk(KERN_INFO "sata_sis: Detected SiS 182 chipset\n");
311 port2_start = 0x20;
312 }
313
314 if (!(probe_ent->host_flags & SIS_FLAG_CFGSCR)) {
315 probe_ent->port[0].scr_addr =
316 pci_resource_start(pdev, SIS_SCR_PCI_BAR);
317 probe_ent->port[1].scr_addr =
318 pci_resource_start(pdev, SIS_SCR_PCI_BAR) + port2_start;
319 }
320
321 pci_set_master(pdev);
322 pci_enable_intx(pdev);
323
324 /* FIXME: check ata_device_add return value */
325 ata_device_add(probe_ent);
326 kfree(probe_ent);
327
328 return 0;
329
330 err_out_regions:
331 pci_release_regions(pdev);
332
333 err_out:
334 if (!pci_dev_busy)
335 pci_disable_device(pdev);
336 return rc;
337
338 }
339
340 static int __init sis_init(void)
341 {
342 return pci_module_init(&sis_pci_driver);
343 }
344
345 static void __exit sis_exit(void)
346 {
347 pci_unregister_driver(&sis_pci_driver);
348 }
349
350 module_init(sis_init);
351 module_exit(sis_exit);
352
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