drivers/scsi/sata_vsc.c

   1 /*
   2  *  sata_vsc.c - Vitesse VSC7174 4 port DPA SATA
   3  *
   4  *  Maintained by:  Jeremy Higdon @ SGI
   5  *                  Please ALWAYS copy linux-ide@vger.kernel.org
   6  *                  on emails.
   7  *
   8  *  Copyright 2004 SGI
   9  *
  10  *  Bits from Jeff Garzik, Copyright RedHat, Inc.
  11  *
  12  *
  13  *  This program is free software; you can redistribute it and/or modify
  14  *  it under the terms of the GNU General Public License as published by
  15  *  the Free Software Foundation; either version 2, or (at your option)
  16  *  any later version.
  17  *
  18  *  This program is distributed in the hope that it will be useful,
  19  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
  20  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  21  *  GNU General Public License for more details.
  22  *
  23  *  You should have received a copy of the GNU General Public License
  24  *  along with this program; see the file COPYING.  If not, write to
  25  *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
  26  *
  27  *
  28  *  libata documentation is available via 'make {ps|pdf}docs',
  29  *  as Documentation/DocBook/libata.*
  30  *
  31  *  Vitesse hardware documentation presumably available under NDA.
  32  *  Intel 31244 (same hardware interface) documentation presumably
  33  *  available from http://developer.intel.com/
  34  *
  35  */
  36
  37 #include <linux/kernel.h>
  38 #include <linux/module.h>
  39 #include <linux/pci.h>
  40 #include <linux/init.h>
  41 #include <linux/blkdev.h>
  42 #include <linux/delay.h>
  43 #include <linux/interrupt.h>
  44 #include <linux/dma-mapping.h>
  45 #include "scsi.h"
  46 #include <scsi/scsi_host.h>
  47 #include <linux/libata.h>
  48
  49 #define DRV_NAME        "sata_vsc"
  50 #define DRV_VERSION     "1.0"
  51
  52 /* Interrupt register offsets (from chip base address) */
  53 #define VSC_SATA_INT_STAT_OFFSET        0x00
  54 #define VSC_SATA_INT_MASK_OFFSET        0x04
  55
  56 /* Taskfile registers offsets */
  57 #define VSC_SATA_TF_CMD_OFFSET          0x00
  58 #define VSC_SATA_TF_DATA_OFFSET         0x00
  59 #define VSC_SATA_TF_ERROR_OFFSET        0x04
  60 #define VSC_SATA_TF_FEATURE_OFFSET      0x06
  61 #define VSC_SATA_TF_NSECT_OFFSET        0x08
  62 #define VSC_SATA_TF_LBAL_OFFSET         0x0c
  63 #define VSC_SATA_TF_LBAM_OFFSET         0x10
  64 #define VSC_SATA_TF_LBAH_OFFSET         0x14
  65 #define VSC_SATA_TF_DEVICE_OFFSET       0x18
  66 #define VSC_SATA_TF_STATUS_OFFSET       0x1c
  67 #define VSC_SATA_TF_COMMAND_OFFSET      0x1d
  68 #define VSC_SATA_TF_ALTSTATUS_OFFSET    0x28
  69 #define VSC_SATA_TF_CTL_OFFSET          0x29
  70
  71 /* DMA base */
  72 #define VSC_SATA_UP_DESCRIPTOR_OFFSET   0x64
  73 #define VSC_SATA_UP_DATA_BUFFER_OFFSET  0x6C
  74 #define VSC_SATA_DMA_CMD_OFFSET         0x70
  75
  76 /* SCRs base */
  77 #define VSC_SATA_SCR_STATUS_OFFSET      0x100
  78 #define VSC_SATA_SCR_ERROR_OFFSET       0x104
  79 #define VSC_SATA_SCR_CONTROL_OFFSET     0x108
  80
  81 /* Port stride */
  82 #define VSC_SATA_PORT_OFFSET            0x200
  83
  84
  85 static u32 vsc_sata_scr_read (struct ata_port *ap, unsigned int sc_reg)
  86 {
  87         if (sc_reg > SCR_CONTROL)
  88                 return 0xffffffffU;
  89         return readl((void *) ap->ioaddr.scr_addr + (sc_reg * 4));
  90 }
  91
  92
  93 static void vsc_sata_scr_write (struct ata_port *ap, unsigned int sc_reg,
  94                                u32 val)
  95 {
  96         if (sc_reg > SCR_CONTROL)
  97                 return;
  98         writel(val, (void *) ap->ioaddr.scr_addr + (sc_reg * 4));
  99 }
 100
 101
 102 static void vsc_intr_mask_update(struct ata_port *ap, u8 ctl)
 103 {
 104         unsigned long mask_addr;
 105         u8 mask;
 106
 107         mask_addr = (unsigned long) ap->host_set->mmio_base +
 108                 VSC_SATA_INT_MASK_OFFSET + ap->port_no;
 109         mask = readb(mask_addr);
 110         if (ctl & ATA_NIEN)
 111                 mask |= 0x80;
 112         else
 113                 mask &= 0x7F;
 114         writeb(mask, mask_addr);
 115 }
 116
 117
 118 static void vsc_sata_tf_load(struct ata_port *ap, struct ata_taskfile *tf)
 119 {
 120         struct ata_ioports *ioaddr = &ap->ioaddr;
 121         unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
 122
 123         /*
 124          * The only thing the ctl register is used for is SRST.
 125          * That is not enabled or disabled via tf_load.
 126          * However, if ATA_NIEN is changed, then we need to change the interrupt register.
 127          */
 128         if ((tf->ctl & ATA_NIEN) != (ap->last_ctl & ATA_NIEN)) {
 129                 ap->last_ctl = tf->ctl;
 130                 vsc_intr_mask_update(ap, tf->ctl & ATA_NIEN);
 131         }
 132         if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
 133                 writew(tf->feature | (((u16)tf->hob_feature) << 8), ioaddr->feature_addr);
 134                 writew(tf->nsect | (((u16)tf->hob_nsect) << 8), ioaddr->nsect_addr);
 135                 writew(tf->lbal | (((u16)tf->hob_lbal) << 8), ioaddr->lbal_addr);
 136                 writew(tf->lbam | (((u16)tf->hob_lbam) << 8), ioaddr->lbam_addr);
 137                 writew(tf->lbah | (((u16)tf->hob_lbah) << 8), ioaddr->lbah_addr);
 138         } else if (is_addr) {
 139                 writew(tf->feature, ioaddr->feature_addr);
 140                 writew(tf->nsect, ioaddr->nsect_addr);
 141                 writew(tf->lbal, ioaddr->lbal_addr);
 142                 writew(tf->lbam, ioaddr->lbam_addr);
 143                 writew(tf->lbah, ioaddr->lbah_addr);
 144         }
 145
 146         if (tf->flags & ATA_TFLAG_DEVICE)
 147                 writeb(tf->device, ioaddr->device_addr);
 148
 149         ata_wait_idle(ap);
 150 }
 151
 152
 153 static void vsc_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
 154 {
 155         struct ata_ioports *ioaddr = &ap->ioaddr;
 156         u16 nsect, lbal, lbam, lbah;
 157
 158         nsect = tf->nsect = readw(ioaddr->nsect_addr);
 159         lbal = tf->lbal = readw(ioaddr->lbal_addr);
 160         lbam = tf->lbam = readw(ioaddr->lbam_addr);
 161         lbah = tf->lbah = readw(ioaddr->lbah_addr);
 162         tf->device = readw(ioaddr->device_addr);
 163
 164         if (tf->flags & ATA_TFLAG_LBA48) {
 165                 tf->hob_feature = readb(ioaddr->error_addr);
 166                 tf->hob_nsect = nsect >> 8;
 167                 tf->hob_lbal = lbal >> 8;
 168                 tf->hob_lbam = lbam >> 8;
 169                 tf->hob_lbah = lbah >> 8;
 170         }
 171 }
 172
 173
 174 /*
 175  * vsc_sata_interrupt
 176  *
 177  * Read the interrupt register and process for the devices that have them pending.
 178  */
 179 static irqreturn_t vsc_sata_interrupt (int irq, void *dev_instance,
 180                                        struct pt_regs *regs)
 181 {
 182         struct ata_host_set *host_set = dev_instance;
 183         unsigned int i;
 184         unsigned int handled = 0;
 185         u32 int_status;
 186
 187         spin_lock(&host_set->lock);
 188
 189         int_status = readl(host_set->mmio_base + VSC_SATA_INT_STAT_OFFSET);
 190
 191         for (i = 0; i < host_set->n_ports; i++) {
 192                 if (int_status & ((u32) 0xFF << (8 * i))) {
 193                         struct ata_port *ap;
 194
 195                         ap = host_set->ports[i];
 196                         if (ap && !(ap->flags &
 197                                     (ATA_FLAG_PORT_DISABLED|ATA_FLAG_NOINTR))) {
 198                                 struct ata_queued_cmd *qc;
 199
 200                                 qc = ata_qc_from_tag(ap, ap->active_tag);
 201                                 if (qc && (!(qc->tf.ctl & ATA_NIEN)))
 202                                         handled += ata_host_intr(ap, qc);
 203                         }
 204                 }
 205         }
 206
 207         spin_unlock(&host_set->lock);
 208
 209         return IRQ_RETVAL(handled);
 210 }
 211
 212
 213 static Scsi_Host_Template vsc_sata_sht = {
 214         .module                 = THIS_MODULE,
 215         .name                   = DRV_NAME,
 216         .ioctl                  = ata_scsi_ioctl,
 217         .queuecommand           = ata_scsi_queuecmd,
 218         .eh_strategy_handler    = ata_scsi_error,
 219         .can_queue              = ATA_DEF_QUEUE,
 220         .this_id                = ATA_SHT_THIS_ID,
 221         .sg_tablesize           = LIBATA_MAX_PRD,
 222         .max_sectors            = ATA_MAX_SECTORS,
 223         .cmd_per_lun            = ATA_SHT_CMD_PER_LUN,
 224         .emulated               = ATA_SHT_EMULATED,
 225         .use_clustering         = ATA_SHT_USE_CLUSTERING,
 226         .proc_name              = DRV_NAME,
 227         .dma_boundary           = ATA_DMA_BOUNDARY,
 228         .slave_configure        = ata_scsi_slave_config,
 229         .bios_param             = ata_std_bios_param,
 230         .ordered_flush          = 1,
 231 };
 232
 233
 234 static struct ata_port_operations vsc_sata_ops = {
 235         .port_disable           = ata_port_disable,
 236         .tf_load                = vsc_sata_tf_load,
 237         .tf_read                = vsc_sata_tf_read,
 238         .exec_command           = ata_exec_command,
 239         .check_status           = ata_check_status,
 240         .dev_select             = ata_std_dev_select,
 241         .phy_reset              = sata_phy_reset,
 242         .bmdma_setup            = ata_bmdma_setup,
 243         .bmdma_start            = ata_bmdma_start,
 244         .bmdma_stop             = ata_bmdma_stop,
 245         .bmdma_status           = ata_bmdma_status,
 246         .qc_prep                = ata_qc_prep,
 247         .qc_issue               = ata_qc_issue_prot,
 248         .eng_timeout            = ata_eng_timeout,
 249         .irq_handler            = vsc_sata_interrupt,
 250         .irq_clear              = ata_bmdma_irq_clear,
 251         .scr_read               = vsc_sata_scr_read,
 252         .scr_write              = vsc_sata_scr_write,
 253         .port_start             = ata_port_start,
 254         .port_stop              = ata_port_stop,
 255         .host_stop              = ata_pci_host_stop,
 256 };
 257
 258 static void __devinit vsc_sata_setup_port(struct ata_ioports *port, unsigned long base)
 259 {
 260         port->cmd_addr          = base + VSC_SATA_TF_CMD_OFFSET;
 261         port->data_addr         = base + VSC_SATA_TF_DATA_OFFSET;
 262         port->error_addr        = base + VSC_SATA_TF_ERROR_OFFSET;
 263         port->feature_addr      = base + VSC_SATA_TF_FEATURE_OFFSET;
 264         port->nsect_addr        = base + VSC_SATA_TF_NSECT_OFFSET;
 265         port->lbal_addr         = base + VSC_SATA_TF_LBAL_OFFSET;
 266         port->lbam_addr         = base + VSC_SATA_TF_LBAM_OFFSET;
 267         port->lbah_addr         = base + VSC_SATA_TF_LBAH_OFFSET;
 268         port->device_addr       = base + VSC_SATA_TF_DEVICE_OFFSET;
 269         port->status_addr       = base + VSC_SATA_TF_STATUS_OFFSET;
 270         port->command_addr      = base + VSC_SATA_TF_COMMAND_OFFSET;
 271         port->altstatus_addr    = base + VSC_SATA_TF_ALTSTATUS_OFFSET;
 272         port->ctl_addr          = base + VSC_SATA_TF_CTL_OFFSET;
 273         port->bmdma_addr        = base + VSC_SATA_DMA_CMD_OFFSET;
 274         port->scr_addr          = base + VSC_SATA_SCR_STATUS_OFFSET;
 275         writel(0, base + VSC_SATA_UP_DESCRIPTOR_OFFSET);
 276         writel(0, base + VSC_SATA_UP_DATA_BUFFER_OFFSET);
 277 }
 278
 279
 280 static int __devinit vsc_sata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent)
 281 {
 282         static int printed_version;
 283         struct ata_probe_ent *probe_ent = NULL;
 284         unsigned long base;
 285         int pci_dev_busy = 0;
 286         void *mmio_base;
 287         int rc;
 288
 289         if (!printed_version++)
 290                 printk(KERN_DEBUG DRV_NAME " version " DRV_VERSION "\n");
 291
 292         rc = pci_enable_device(pdev);
 293         if (rc)
 294                 return rc;
 295
 296         /*
 297          * Check if we have needed resource mapped.
 298          */
 299         if (pci_resource_len(pdev, 0) == 0) {
 300                 rc = -ENODEV;
 301                 goto err_out;
 302         }
 303
 304         rc = pci_request_regions(pdev, DRV_NAME);
 305         if (rc) {
 306                 pci_dev_busy = 1;
 307                 goto err_out;
 308         }
 309
 310         /*
 311          * Use 32 bit DMA mask, because 64 bit address support is poor.
 312          */
 313         rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
 314         if (rc)
 315                 goto err_out_regions;
 316         rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
 317         if (rc)
 318                 goto err_out_regions;
 319
 320         probe_ent = kmalloc(sizeof(*probe_ent), GFP_KERNEL);
 321         if (probe_ent == NULL) {
 322                 rc = -ENOMEM;
 323                 goto err_out_regions;
 324         }
 325         memset(probe_ent, 0, sizeof(*probe_ent));
 326         probe_ent->dev = pci_dev_to_dev(pdev);
 327         INIT_LIST_HEAD(&probe_ent->node);
 328
 329         mmio_base = pci_iomap(pdev, 0, 0);
 330         if (mmio_base == NULL) {
 331                 rc = -ENOMEM;
 332                 goto err_out_free_ent;
 333         }
 334         base = (unsigned long) mmio_base;
 335
 336         /*
 337          * Due to a bug in the chip, the default cache line size can't be used
 338          */
 339         pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x80);
 340
 341         probe_ent->sht = &vsc_sata_sht;
 342         probe_ent->host_flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
 343                                 ATA_FLAG_MMIO | ATA_FLAG_SATA_RESET;
 344         probe_ent->port_ops = &vsc_sata_ops;
 345         probe_ent->n_ports = 4;
 346         probe_ent->irq = pdev->irq;
 347         probe_ent->irq_flags = SA_SHIRQ;
 348         probe_ent->mmio_base = mmio_base;
 349
 350         /* We don't care much about the PIO/UDMA masks, but the core won't like us
 351          * if we don't fill these
 352          */
 353         probe_ent->pio_mask = 0x1f;
 354         probe_ent->mwdma_mask = 0x07;
 355         probe_ent->udma_mask = 0x7f;
 356
 357         /* We have 4 ports per PCI function */
 358         vsc_sata_setup_port(&probe_ent->port[0], base + 1 * VSC_SATA_PORT_OFFSET);
 359         vsc_sata_setup_port(&probe_ent->port[1], base + 2 * VSC_SATA_PORT_OFFSET);
 360         vsc_sata_setup_port(&probe_ent->port[2], base + 3 * VSC_SATA_PORT_OFFSET);
 361         vsc_sata_setup_port(&probe_ent->port[3], base + 4 * VSC_SATA_PORT_OFFSET);
 362
 363         pci_set_master(pdev);
 364
 365         /*
 366          * Config offset 0x98 is "Extended Control and Status Register 0"
 367          * Default value is (1 << 28).  All bits except bit 28 are reserved in
 368          * DPA mode.  If bit 28 is set, LED 0 reflects all ports' activity.
 369          * If bit 28 is clear, each port has its own LED.
 370          */
 371         pci_write_config_dword(pdev, 0x98, 0);
 372
 373         /* FIXME: check ata_device_add return value */
 374         ata_device_add(probe_ent);
 375         kfree(probe_ent);
 376
 377         return 0;
 378
 379 err_out_free_ent:
 380         kfree(probe_ent);
 381 err_out_regions:
 382         pci_release_regions(pdev);
 383 err_out:
 384         if (!pci_dev_busy)
 385                 pci_disable_device(pdev);
 386         return rc;
 387 }
 388
 389
 390 /*
 391  * 0x1725/0x7174 is the Vitesse VSC-7174
 392  * 0x8086/0x3200 is the Intel 31244, which is supposed to be identical
 393  * compatibility is untested as of yet
 394  */
 395 static struct pci_device_id vsc_sata_pci_tbl[] = {
 396         { 0x1725, 0x7174, PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
 397         { 0x8086, 0x3200, PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
 398         { }
 399 };
 400
 401
 402 static struct pci_driver vsc_sata_pci_driver = {
 403         .name                   = DRV_NAME,
 404         .id_table               = vsc_sata_pci_tbl,
 405         .probe                  = vsc_sata_init_one,
 406         .remove                 = ata_pci_remove_one,
 407 };
 408
 409
 410 static int __init vsc_sata_init(void)
 411 {
 412         return pci_module_init(&vsc_sata_pci_driver);
 413 }
 414
 415
 416 static void __exit vsc_sata_exit(void)
 417 {
 418         pci_unregister_driver(&vsc_sata_pci_driver);
 419 }
 420
 421
 422 MODULE_AUTHOR("Jeremy Higdon");
 423 MODULE_DESCRIPTION("low-level driver for Vitesse VSC7174 SATA controller");
 424 MODULE_LICENSE("GPL");
 425 MODULE_DEVICE_TABLE(pci, vsc_sata_pci_tbl);
 426 MODULE_VERSION(DRV_VERSION);
 427
 428 module_init(vsc_sata_init);
 429 module_exit(vsc_sata_exit);