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[PATCH] W1: w1_netlink: New init/fini netlink callbacks.
[linux-2.6/verdex.git] / drivers / scsi / sym53c8xx_defs.h
blob4c4ae7d4713fde0e4db425594727b34312ed1727
1 /******************************************************************************
2 ** High Performance device driver for the Symbios 53C896 controller.
3 **
4 ** Copyright (C) 1998-2001 Gerard Roudier <groudier@free.fr>
5 **
6 ** This driver also supports all the Symbios 53C8XX controller family,
7 ** except 53C810 revisions < 16, 53C825 revisions < 16 and all
8 ** revisions of 53C815 controllers.
9 **
10 ** This driver is based on the Linux port of the FreeBSD ncr driver.
11 **
12 ** Copyright (C) 1994 Wolfgang Stanglmeier
13 **
14 **-----------------------------------------------------------------------------
15 **
16 ** This program is free software; you can redistribute it and/or modify
17 ** it under the terms of the GNU General Public License as published by
18 ** the Free Software Foundation; either version 2 of the License, or
19 ** (at your option) any later version.
20 **
21 ** This program is distributed in the hope that it will be useful,
22 ** but WITHOUT ANY WARRANTY; without even the implied warranty of
23 ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 ** GNU General Public License for more details.
25 **
26 ** You should have received a copy of the GNU General Public License
27 ** along with this program; if not, write to the Free Software
28 ** Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
29 **
30 **-----------------------------------------------------------------------------
31 **
32 ** The Linux port of the FreeBSD ncr driver has been achieved in
33 ** november 1995 by:
34 **
35 ** Gerard Roudier <groudier@free.fr>
36 **
37 ** Being given that this driver originates from the FreeBSD version, and
38 ** in order to keep synergy on both, any suggested enhancements and corrections
39 ** received on Linux are automatically a potential candidate for the FreeBSD
40 ** version.
41 **
42 ** The original driver has been written for 386bsd and FreeBSD by
43 ** Wolfgang Stanglmeier <wolf@cologne.de>
44 ** Stefan Esser <se@mi.Uni-Koeln.de>
45 **
46 **-----------------------------------------------------------------------------
47 **
48 ** Major contributions:
49 ** --------------------
50 **
51 ** NVRAM detection and reading.
52 ** Copyright (C) 1997 Richard Waltham <dormouse@farsrobt.demon.co.uk>
53 **
54 ** Added support for MIPS big endian systems.
55 ** Carsten Langgaard, carstenl@mips.com
56 ** Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
57 **
58 ** Added support for HP PARISC big endian systems.
59 ** Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
60 **
61 *******************************************************************************
62 */
63
64 #ifndef SYM53C8XX_DEFS_H
65 #define SYM53C8XX_DEFS_H
66
67 #include <linux/config.h>
68
69 /*
70 ** If you want a driver as small as possible, donnot define the
71 ** following options.
72 */
73 #define SCSI_NCR_BOOT_COMMAND_LINE_SUPPORT
74 #define SCSI_NCR_DEBUG_INFO_SUPPORT
75
76 /*
77 ** To disable integrity checking, do not define the
78 ** following option.
79 */
80 #ifdef CONFIG_SCSI_NCR53C8XX_INTEGRITY_CHECK
81 # define SCSI_NCR_ENABLE_INTEGRITY_CHECK
82 #endif
83
84 /* ---------------------------------------------------------------------
85 ** Take into account kernel configured parameters.
86 ** Most of these options can be overridden at startup by a command line.
87 ** ---------------------------------------------------------------------
88 */
89
90 /*
91 * For Ultra2 and Ultra3 SCSI support option, use special features.
92 *
93 * Value (default) means:
94 * bit 0 : all features enabled, except:
95 * bit 1 : PCI Write And Invalidate.
96 * bit 2 : Data Phase Mismatch handling from SCRIPTS.
97 *
98 * Use boot options ncr53c8xx=specf:1 if you want all chip features to be
99 * enabled by the driver.
100 */
101 #define SCSI_NCR_SETUP_SPECIAL_FEATURES (3)
102
103 #define SCSI_NCR_MAX_SYNC (80)
104
105 /*
106 * Allow tags from 2 to 256, default 8
107 */
108 #ifdef CONFIG_SCSI_NCR53C8XX_MAX_TAGS
109 #if CONFIG_SCSI_NCR53C8XX_MAX_TAGS < 2
110 #define SCSI_NCR_MAX_TAGS (2)
111 #elif CONFIG_SCSI_NCR53C8XX_MAX_TAGS > 256
112 #define SCSI_NCR_MAX_TAGS (256)
113 #else
114 #define SCSI_NCR_MAX_TAGS CONFIG_SCSI_NCR53C8XX_MAX_TAGS
115 #endif
116 #else
117 #define SCSI_NCR_MAX_TAGS (8)
118 #endif
119
120 /*
121 * Allow tagged command queuing support if configured with default number
122 * of tags set to max (see above).
123 */
124 #ifdef CONFIG_SCSI_NCR53C8XX_DEFAULT_TAGS
125 #define SCSI_NCR_SETUP_DEFAULT_TAGS CONFIG_SCSI_NCR53C8XX_DEFAULT_TAGS
126 #elif defined CONFIG_SCSI_NCR53C8XX_TAGGED_QUEUE
127 #define SCSI_NCR_SETUP_DEFAULT_TAGS SCSI_NCR_MAX_TAGS
128 #else
129 #define SCSI_NCR_SETUP_DEFAULT_TAGS (0)
130 #endif
131
132 /*
133 * Immediate arbitration
134 */
135 #if defined(CONFIG_SCSI_NCR53C8XX_IARB)
136 #define SCSI_NCR_IARB_SUPPORT
137 #endif
138
139 /*
140 * Sync transfer frequency at startup.
141 * Allow from 5Mhz to 80Mhz default 20 Mhz.
142 */
143 #ifndef CONFIG_SCSI_NCR53C8XX_SYNC
144 #define CONFIG_SCSI_NCR53C8XX_SYNC (20)
145 #elif CONFIG_SCSI_NCR53C8XX_SYNC > SCSI_NCR_MAX_SYNC
146 #undef CONFIG_SCSI_NCR53C8XX_SYNC
147 #define CONFIG_SCSI_NCR53C8XX_SYNC SCSI_NCR_MAX_SYNC
148 #endif
149
150 #if CONFIG_SCSI_NCR53C8XX_SYNC == 0
151 #define SCSI_NCR_SETUP_DEFAULT_SYNC (255)
152 #elif CONFIG_SCSI_NCR53C8XX_SYNC <= 5
153 #define SCSI_NCR_SETUP_DEFAULT_SYNC (50)
154 #elif CONFIG_SCSI_NCR53C8XX_SYNC <= 20
155 #define SCSI_NCR_SETUP_DEFAULT_SYNC (250/(CONFIG_SCSI_NCR53C8XX_SYNC))
156 #elif CONFIG_SCSI_NCR53C8XX_SYNC <= 33
157 #define SCSI_NCR_SETUP_DEFAULT_SYNC (11)
158 #elif CONFIG_SCSI_NCR53C8XX_SYNC <= 40
159 #define SCSI_NCR_SETUP_DEFAULT_SYNC (10)
160 #else
161 #define SCSI_NCR_SETUP_DEFAULT_SYNC (9)
162 #endif
163
164 /*
165 * Disallow disconnections at boot-up
166 */
167 #ifdef CONFIG_SCSI_NCR53C8XX_NO_DISCONNECT
168 #define SCSI_NCR_SETUP_DISCONNECTION (0)
169 #else
170 #define SCSI_NCR_SETUP_DISCONNECTION (1)
171 #endif
172
173 /*
174 * Force synchronous negotiation for all targets
175 */
176 #ifdef CONFIG_SCSI_NCR53C8XX_FORCE_SYNC_NEGO
177 #define SCSI_NCR_SETUP_FORCE_SYNC_NEGO (1)
178 #else
179 #define SCSI_NCR_SETUP_FORCE_SYNC_NEGO (0)
180 #endif
181
182 /*
183 * Disable master parity checking (flawed hardwares need that)
184 */
185 #ifdef CONFIG_SCSI_NCR53C8XX_DISABLE_MPARITY_CHECK
186 #define SCSI_NCR_SETUP_MASTER_PARITY (0)
187 #else
188 #define SCSI_NCR_SETUP_MASTER_PARITY (1)
189 #endif
190
191 /*
192 * Disable scsi parity checking (flawed devices may need that)
193 */
194 #ifdef CONFIG_SCSI_NCR53C8XX_DISABLE_PARITY_CHECK
195 #define SCSI_NCR_SETUP_SCSI_PARITY (0)
196 #else
197 #define SCSI_NCR_SETUP_SCSI_PARITY (1)
198 #endif
199
200 /*
201 * Settle time after reset at boot-up
202 */
203 #define SCSI_NCR_SETUP_SETTLE_TIME (2)
204
205 /*
206 ** Bridge quirks work-around option defaulted to 1.
207 */
208 #ifndef SCSI_NCR_PCIQ_WORK_AROUND_OPT
209 #define SCSI_NCR_PCIQ_WORK_AROUND_OPT 1
210 #endif
211
212 /*
213 ** Work-around common bridge misbehaviour.
214 **
215 ** - Do not flush posted writes in the opposite
216 ** direction on read.
217 ** - May reorder DMA writes to memory.
218 **
219 ** This option should not affect performances
220 ** significantly, so it is the default.
221 */
222 #if SCSI_NCR_PCIQ_WORK_AROUND_OPT == 1
223 #define SCSI_NCR_PCIQ_MAY_NOT_FLUSH_PW_UPSTREAM
224 #define SCSI_NCR_PCIQ_MAY_REORDER_WRITES
225 #define SCSI_NCR_PCIQ_MAY_MISS_COMPLETIONS
226
227 /*
228 ** Same as option 1, but also deal with
229 ** misconfigured interrupts.
230 **
231 ** - Edge triggerred instead of level sensitive.
232 ** - No interrupt line connected.
233 ** - IRQ number misconfigured.
234 **
235 ** If no interrupt is delivered, the driver will
236 ** catch the interrupt conditions 10 times per
237 ** second. No need to say that this option is
238 ** not recommended.
239 */
240 #elif SCSI_NCR_PCIQ_WORK_AROUND_OPT == 2
241 #define SCSI_NCR_PCIQ_MAY_NOT_FLUSH_PW_UPSTREAM
242 #define SCSI_NCR_PCIQ_MAY_REORDER_WRITES
243 #define SCSI_NCR_PCIQ_MAY_MISS_COMPLETIONS
244 #define SCSI_NCR_PCIQ_BROKEN_INTR
245
246 /*
247 ** Some bridge designers decided to flush
248 ** everything prior to deliver the interrupt.
249 ** This option tries to deal with such a
250 ** behaviour.
251 */
252 #elif SCSI_NCR_PCIQ_WORK_AROUND_OPT == 3
253 #define SCSI_NCR_PCIQ_SYNC_ON_INTR
254 #endif
255
256 /*
257 ** Other parameters not configurable with "make config"
258 ** Avoid to change these constants, unless you know what you are doing.
259 */
260
261 #define SCSI_NCR_ALWAYS_SIMPLE_TAG
262 #define SCSI_NCR_MAX_SCATTER (127)
263 #define SCSI_NCR_MAX_TARGET (16)
264
265 /*
266 ** Compute some desirable value for CAN_QUEUE
267 ** and CMD_PER_LUN.
268 ** The driver will use lower values if these
269 ** ones appear to be too large.
270 */
271 #define SCSI_NCR_CAN_QUEUE (8*SCSI_NCR_MAX_TAGS + 2*SCSI_NCR_MAX_TARGET)
272 #define SCSI_NCR_CMD_PER_LUN (SCSI_NCR_MAX_TAGS)
273
274 #define SCSI_NCR_SG_TABLESIZE (SCSI_NCR_MAX_SCATTER)
275 #define SCSI_NCR_TIMER_INTERVAL (HZ)
276
277 #if 1 /* defined CONFIG_SCSI_MULTI_LUN */
278 #define SCSI_NCR_MAX_LUN (16)
279 #else
280 #define SCSI_NCR_MAX_LUN (1)
281 #endif
282
283 /*
284 ** These simple macros limit expression involving
285 ** kernel time values (jiffies) to some that have
286 ** chance not to be too much incorrect. :-)
287 */
288 #define ktime_get(o) (jiffies + (u_long) o)
289 #define ktime_exp(b) ((long)(jiffies) - (long)(b) >= 0)
290 #define ktime_dif(a, b) ((long)(a) - (long)(b))
291 /* These ones are not used in this driver */
292 #define ktime_add(a, o) ((a) + (u_long)(o))
293 #define ktime_sub(a, o) ((a) - (u_long)(o))
294
295
296 /*
297 * IO functions definition for big/little endian CPU support.
298 * For now, the NCR is only supported in little endian addressing mode,
299 */
300
301 #ifdef __BIG_ENDIAN
302
303 #define inw_l2b inw
304 #define inl_l2b inl
305 #define outw_b2l outw
306 #define outl_b2l outl
307
308 #define readb_raw readb
309 #define writeb_raw writeb
310
311 #if defined(SCSI_NCR_BIG_ENDIAN)
312 #define readw_l2b __raw_readw
313 #define readl_l2b __raw_readl
314 #define writew_b2l __raw_writew
315 #define writel_b2l __raw_writel
316 #define readw_raw __raw_readw
317 #define readl_raw __raw_readl
318 #define writew_raw __raw_writew
319 #define writel_raw __raw_writel
320 #else /* Other big-endian */
321 #define readw_l2b readw
322 #define readl_l2b readl
323 #define writew_b2l writew
324 #define writel_b2l writel
325 #define readw_raw readw
326 #define readl_raw readl
327 #define writew_raw writew
328 #define writel_raw writel
329 #endif
330
331 #else /* little endian */
332
333 #define inw_raw inw
334 #define inl_raw inl
335 #define outw_raw outw
336 #define outl_raw outl
337
338 #define readb_raw readb
339 #define readw_raw readw
340 #define readl_raw readl
341 #define writeb_raw writeb
342 #define writew_raw writew
343 #define writel_raw writel
344
345 #endif
346
347 #if !defined(__hppa__) && !defined(__mips__)
348 #ifdef SCSI_NCR_BIG_ENDIAN
349 #error "The NCR in BIG ENDIAN addressing mode is not (yet) supported"
350 #endif
351 #endif
352
353 #define MEMORY_BARRIER() mb()
354
355
356 /*
357 * If the NCR uses big endian addressing mode over the
358 * PCI, actual io register addresses for byte and word
359 * accesses must be changed according to lane routing.
360 * Btw, ncr_offb() and ncr_offw() macros only apply to
361 * constants and so donnot generate bloated code.
362 */
363
364 #if defined(SCSI_NCR_BIG_ENDIAN)
365
366 #define ncr_offb(o) (((o)&~3)+((~((o)&3))&3))
367 #define ncr_offw(o) (((o)&~3)+((~((o)&3))&2))
368
369 #else
370
371 #define ncr_offb(o) (o)
372 #define ncr_offw(o) (o)
373
374 #endif
375
376 /*
377 * If the CPU and the NCR use same endian-ness addressing,
378 * no byte reordering is needed for script patching.
379 * Macro cpu_to_scr() is to be used for script patching.
380 * Macro scr_to_cpu() is to be used for getting a DWORD
381 * from the script.
382 */
383
384 #if defined(__BIG_ENDIAN) && !defined(SCSI_NCR_BIG_ENDIAN)
385
386 #define cpu_to_scr(dw) cpu_to_le32(dw)
387 #define scr_to_cpu(dw) le32_to_cpu(dw)
388
389 #elif defined(__LITTLE_ENDIAN) && defined(SCSI_NCR_BIG_ENDIAN)
390
391 #define cpu_to_scr(dw) cpu_to_be32(dw)
392 #define scr_to_cpu(dw) be32_to_cpu(dw)
393
394 #else
395
396 #define cpu_to_scr(dw) (dw)
397 #define scr_to_cpu(dw) (dw)
398
399 #endif
400
401 /*
402 * Access to the controller chip.
403 *
404 * If the CPU and the NCR use same endian-ness addressing,
405 * no byte reordering is needed for accessing chip io
406 * registers. Functions suffixed by '_raw' are assumed
407 * to access the chip over the PCI without doing byte
408 * reordering. Functions suffixed by '_l2b' are
409 * assumed to perform little-endian to big-endian byte
410 * reordering, those suffixed by '_b2l' blah, blah,
411 * blah, ...
412 */
413
414 /*
415 * MEMORY mapped IO input / output
416 */
417
418 #define INB_OFF(o) readb_raw((char __iomem *)np->reg + ncr_offb(o))
419 #define OUTB_OFF(o, val) writeb_raw((val), (char __iomem *)np->reg + ncr_offb(o))
420
421 #if defined(__BIG_ENDIAN) && !defined(SCSI_NCR_BIG_ENDIAN)
422
423 #define INW_OFF(o) readw_l2b((char __iomem *)np->reg + ncr_offw(o))
424 #define INL_OFF(o) readl_l2b((char __iomem *)np->reg + (o))
425
426 #define OUTW_OFF(o, val) writew_b2l((val), (char __iomem *)np->reg + ncr_offw(o))
427 #define OUTL_OFF(o, val) writel_b2l((val), (char __iomem *)np->reg + (o))
428
429 #elif defined(__LITTLE_ENDIAN) && defined(SCSI_NCR_BIG_ENDIAN)
430
431 #define INW_OFF(o) readw_b2l((char __iomem *)np->reg + ncr_offw(o))
432 #define INL_OFF(o) readl_b2l((char __iomem *)np->reg + (o))
433
434 #define OUTW_OFF(o, val) writew_l2b((val), (char __iomem *)np->reg + ncr_offw(o))
435 #define OUTL_OFF(o, val) writel_l2b((val), (char __iomem *)np->reg + (o))
436
437 #else
438
439 #ifdef CONFIG_SCSI_NCR53C8XX_NO_WORD_TRANSFERS
440 /* Only 8 or 32 bit transfers allowed */
441 #define INW_OFF(o) (readb((char __iomem *)np->reg + ncr_offw(o)) << 8 | readb((char __iomem *)np->reg + ncr_offw(o) + 1))
442 #else
443 #define INW_OFF(o) readw_raw((char __iomem *)np->reg + ncr_offw(o))
444 #endif
445 #define INL_OFF(o) readl_raw((char __iomem *)np->reg + (o))
446
447 #ifdef CONFIG_SCSI_NCR53C8XX_NO_WORD_TRANSFERS
448 /* Only 8 or 32 bit transfers allowed */
449 #define OUTW_OFF(o, val) do { writeb((char)((val) >> 8), (char __iomem *)np->reg + ncr_offw(o)); writeb((char)(val), (char __iomem *)np->reg + ncr_offw(o) + 1); } while (0)
450 #else
451 #define OUTW_OFF(o, val) writew_raw((val), (char __iomem *)np->reg + ncr_offw(o))
452 #endif
453 #define OUTL_OFF(o, val) writel_raw((val), (char __iomem *)np->reg + (o))
454
455 #endif
456
457 #define INB(r) INB_OFF (offsetof(struct ncr_reg,r))
458 #define INW(r) INW_OFF (offsetof(struct ncr_reg,r))
459 #define INL(r) INL_OFF (offsetof(struct ncr_reg,r))
460
461 #define OUTB(r, val) OUTB_OFF (offsetof(struct ncr_reg,r), (val))
462 #define OUTW(r, val) OUTW_OFF (offsetof(struct ncr_reg,r), (val))
463 #define OUTL(r, val) OUTL_OFF (offsetof(struct ncr_reg,r), (val))
464
465 /*
466 * Set bit field ON, OFF
467 */
468
469 #define OUTONB(r, m) OUTB(r, INB(r) | (m))
470 #define OUTOFFB(r, m) OUTB(r, INB(r) & ~(m))
471 #define OUTONW(r, m) OUTW(r, INW(r) | (m))
472 #define OUTOFFW(r, m) OUTW(r, INW(r) & ~(m))
473 #define OUTONL(r, m) OUTL(r, INL(r) | (m))
474 #define OUTOFFL(r, m) OUTL(r, INL(r) & ~(m))
475
476 /*
477 * We normally want the chip to have a consistent view
478 * of driver internal data structures when we restart it.
479 * Thus these macros.
480 */
481 #define OUTL_DSP(v) \
482 do { \
483 MEMORY_BARRIER(); \
484 OUTL (nc_dsp, (v)); \
485 } while (0)
486
487 #define OUTONB_STD() \
488 do { \
489 MEMORY_BARRIER(); \
490 OUTONB (nc_dcntl, (STD|NOCOM)); \
491 } while (0)
492
493
494 /*
495 ** NCR53C8XX devices features table.
496 */
497 struct ncr_chip {
498 unsigned short revision_id;
499 unsigned char burst_max; /* log-base-2 of max burst */
500 unsigned char offset_max;
501 unsigned char nr_divisor;
502 unsigned int features;
503 #define FE_LED0 (1<<0)
504 #define FE_WIDE (1<<1) /* Wide data transfers */
505 #define FE_ULTRA (1<<2) /* Ultra speed 20Mtrans/sec */
506 #define FE_DBLR (1<<4) /* Clock doubler present */
507 #define FE_QUAD (1<<5) /* Clock quadrupler present */
508 #define FE_ERL (1<<6) /* Enable read line */
509 #define FE_CLSE (1<<7) /* Cache line size enable */
510 #define FE_WRIE (1<<8) /* Write & Invalidate enable */
511 #define FE_ERMP (1<<9) /* Enable read multiple */
512 #define FE_BOF (1<<10) /* Burst opcode fetch */
513 #define FE_DFS (1<<11) /* DMA fifo size */
514 #define FE_PFEN (1<<12) /* Prefetch enable */
515 #define FE_LDSTR (1<<13) /* Load/Store supported */
516 #define FE_RAM (1<<14) /* On chip RAM present */
517 #define FE_VARCLK (1<<15) /* SCSI clock may vary */
518 #define FE_RAM8K (1<<16) /* On chip RAM sized 8Kb */
519 #define FE_64BIT (1<<17) /* Have a 64-bit PCI interface */
520 #define FE_IO256 (1<<18) /* Requires full 256 bytes in PCI space */
521 #define FE_NOPM (1<<19) /* Scripts handles phase mismatch */
522 #define FE_LEDC (1<<20) /* Hardware control of LED */
523 #define FE_DIFF (1<<21) /* Support Differential SCSI */
524 #define FE_66MHZ (1<<23) /* 66MHz PCI Support */
525 #define FE_DAC (1<<24) /* Support DAC cycles (64 bit addressing) */
526 #define FE_ISTAT1 (1<<25) /* Have ISTAT1, MBOX0, MBOX1 registers */
527 #define FE_DAC_IN_USE (1<<26) /* Platform does DAC cycles */
528 #define FE_EHP (1<<27) /* 720: Even host parity */
529 #define FE_MUX (1<<28) /* 720: Multiplexed bus */
530 #define FE_EA (1<<29) /* 720: Enable Ack */
531
532 #define FE_CACHE_SET (FE_ERL|FE_CLSE|FE_WRIE|FE_ERMP)
533 #define FE_SCSI_SET (FE_WIDE|FE_ULTRA|FE_DBLR|FE_QUAD|F_CLK80)
534 #define FE_SPECIAL_SET (FE_CACHE_SET|FE_BOF|FE_DFS|FE_LDSTR|FE_PFEN|FE_RAM)
535 };
536
537
538 /*
539 ** Driver setup structure.
540 **
541 ** This structure is initialized from linux config options.
542 ** It can be overridden at boot-up by the boot command line.
543 */
544 #define SCSI_NCR_MAX_EXCLUDES 8
545 struct ncr_driver_setup {
546 u8 master_parity;
547 u8 scsi_parity;
548 u8 disconnection;
549 u8 special_features;
550 u8 force_sync_nego;
551 u8 reverse_probe;
552 u8 pci_fix_up;
553 u8 use_nvram;
554 u8 verbose;
555 u8 default_tags;
556 u16 default_sync;
557 u16 debug;
558 u8 burst_max;
559 u8 led_pin;
560 u8 max_wide;
561 u8 settle_delay;
562 u8 diff_support;
563 u8 irqm;
564 u8 bus_check;
565 u8 optimize;
566 u8 recovery;
567 u8 host_id;
568 u16 iarb;
569 u32 excludes[SCSI_NCR_MAX_EXCLUDES];
570 char tag_ctrl[100];
571 };
572
573 /*
574 ** Initial setup.
575 ** Can be overriden at startup by a command line.
576 */
577 #define SCSI_NCR_DRIVER_SETUP \
578 { \
579 SCSI_NCR_SETUP_MASTER_PARITY, \
580 SCSI_NCR_SETUP_SCSI_PARITY, \
581 SCSI_NCR_SETUP_DISCONNECTION, \
582 SCSI_NCR_SETUP_SPECIAL_FEATURES, \
583 SCSI_NCR_SETUP_FORCE_SYNC_NEGO, \
584 0, \
585 0, \
586 1, \
587 0, \
588 SCSI_NCR_SETUP_DEFAULT_TAGS, \
589 SCSI_NCR_SETUP_DEFAULT_SYNC, \
590 0x00, \
591 7, \
592 0, \
593 1, \
594 SCSI_NCR_SETUP_SETTLE_TIME, \
595 0, \
596 0, \
597 1, \
598 0, \
599 0, \
600 255, \
601 0x00 \
602 }
603
604 /*
605 ** Boot fail safe setup.
606 ** Override initial setup from boot command line:
607 ** ncr53c8xx=safe:y
608 */
609 #define SCSI_NCR_DRIVER_SAFE_SETUP \
610 { \
611 0, \
612 1, \
613 0, \
614 0, \
615 0, \
616 0, \
617 0, \
618 1, \
619 2, \
620 0, \
621 255, \
622 0x00, \
623 255, \
624 0, \
625 0, \
626 10, \
627 1, \
628 1, \
629 1, \
630 0, \
631 0, \
632 255 \
633 }
634
635 /**************** ORIGINAL CONTENT of ncrreg.h from FreeBSD ******************/
636
637 /*-----------------------------------------------------------------
638 **
639 ** The ncr 53c810 register structure.
640 **
641 **-----------------------------------------------------------------
642 */
643
644 struct ncr_reg {
645 /*00*/ u8 nc_scntl0; /* full arb., ena parity, par->ATN */
646
647 /*01*/ u8 nc_scntl1; /* no reset */
648 #define ISCON 0x10 /* connected to scsi */
649 #define CRST 0x08 /* force reset */
650 #define IARB 0x02 /* immediate arbitration */
651
652 /*02*/ u8 nc_scntl2; /* no disconnect expected */
653 #define SDU 0x80 /* cmd: disconnect will raise error */
654 #define CHM 0x40 /* sta: chained mode */
655 #define WSS 0x08 /* sta: wide scsi send [W]*/
656 #define WSR 0x01 /* sta: wide scsi received [W]*/
657
658 /*03*/ u8 nc_scntl3; /* cnf system clock dependent */
659 #define EWS 0x08 /* cmd: enable wide scsi [W]*/
660 #define ULTRA 0x80 /* cmd: ULTRA enable */
661 /* bits 0-2, 7 rsvd for C1010 */
662
663 /*04*/ u8 nc_scid; /* cnf host adapter scsi address */
664 #define RRE 0x40 /* r/w:e enable response to resel. */
665 #define SRE 0x20 /* r/w:e enable response to select */
666
667 /*05*/ u8 nc_sxfer; /* ### Sync speed and count */
668 /* bits 6-7 rsvd for C1010 */
669
670 /*06*/ u8 nc_sdid; /* ### Destination-ID */
671
672 /*07*/ u8 nc_gpreg; /* ??? IO-Pins */
673
674 /*08*/ u8 nc_sfbr; /* ### First byte in phase */
675
676 /*09*/ u8 nc_socl;
677 #define CREQ 0x80 /* r/w: SCSI-REQ */
678 #define CACK 0x40 /* r/w: SCSI-ACK */
679 #define CBSY 0x20 /* r/w: SCSI-BSY */
680 #define CSEL 0x10 /* r/w: SCSI-SEL */
681 #define CATN 0x08 /* r/w: SCSI-ATN */
682 #define CMSG 0x04 /* r/w: SCSI-MSG */
683 #define CC_D 0x02 /* r/w: SCSI-C_D */
684 #define CI_O 0x01 /* r/w: SCSI-I_O */
685
686 /*0a*/ u8 nc_ssid;
687
688 /*0b*/ u8 nc_sbcl;
689
690 /*0c*/ u8 nc_dstat;
691 #define DFE 0x80 /* sta: dma fifo empty */
692 #define MDPE 0x40 /* int: master data parity error */
693 #define BF 0x20 /* int: script: bus fault */
694 #define ABRT 0x10 /* int: script: command aborted */
695 #define SSI 0x08 /* int: script: single step */
696 #define SIR 0x04 /* int: script: interrupt instruct. */
697 #define IID 0x01 /* int: script: illegal instruct. */
698
699 /*0d*/ u8 nc_sstat0;
700 #define ILF 0x80 /* sta: data in SIDL register lsb */
701 #define ORF 0x40 /* sta: data in SODR register lsb */
702 #define OLF 0x20 /* sta: data in SODL register lsb */
703 #define AIP 0x10 /* sta: arbitration in progress */
704 #define LOA 0x08 /* sta: arbitration lost */
705 #define WOA 0x04 /* sta: arbitration won */
706 #define IRST 0x02 /* sta: scsi reset signal */
707 #define SDP 0x01 /* sta: scsi parity signal */
708
709 /*0e*/ u8 nc_sstat1;
710 #define FF3210 0xf0 /* sta: bytes in the scsi fifo */
711
712 /*0f*/ u8 nc_sstat2;
713 #define ILF1 0x80 /* sta: data in SIDL register msb[W]*/
714 #define ORF1 0x40 /* sta: data in SODR register msb[W]*/
715 #define OLF1 0x20 /* sta: data in SODL register msb[W]*/
716 #define DM 0x04 /* sta: DIFFSENS mismatch (895/6 only) */
717 #define LDSC 0x02 /* sta: disconnect & reconnect */
718
719 /*10*/ u8 nc_dsa; /* --> Base page */
720 /*11*/ u8 nc_dsa1;
721 /*12*/ u8 nc_dsa2;
722 /*13*/ u8 nc_dsa3;
723
724 /*14*/ u8 nc_istat; /* --> Main Command and status */
725 #define CABRT 0x80 /* cmd: abort current operation */
726 #define SRST 0x40 /* mod: reset chip */
727 #define SIGP 0x20 /* r/w: message from host to ncr */
728 #define SEM 0x10 /* r/w: message between host + ncr */
729 #define CON 0x08 /* sta: connected to scsi */
730 #define INTF 0x04 /* sta: int on the fly (reset by wr)*/
731 #define SIP 0x02 /* sta: scsi-interrupt */
732 #define DIP 0x01 /* sta: host/script interrupt */
733
734 /*15*/ u8 nc_istat1; /* 896 and later cores only */
735 #define FLSH 0x04 /* sta: chip is flushing */
736 #define SRUN 0x02 /* sta: scripts are running */
737 #define SIRQD 0x01 /* r/w: disable INT pin */
738
739 /*16*/ u8 nc_mbox0; /* 896 and later cores only */
740 /*17*/ u8 nc_mbox1; /* 896 and later cores only */
741
742 /*18*/ u8 nc_ctest0;
743 #define EHP 0x04 /* 720 even host parity */
744 /*19*/ u8 nc_ctest1;
745
746 /*1a*/ u8 nc_ctest2;
747 #define CSIGP 0x40
748 /* bits 0-2,7 rsvd for C1010 */
749
750 /*1b*/ u8 nc_ctest3;
751 #define FLF 0x08 /* cmd: flush dma fifo */
752 #define CLF 0x04 /* cmd: clear dma fifo */
753 #define FM 0x02 /* mod: fetch pin mode */
754 #define WRIE 0x01 /* mod: write and invalidate enable */
755 /* bits 4-7 rsvd for C1010 */
756
757 /*1c*/ u32 nc_temp; /* ### Temporary stack */
758
759 /*20*/ u8 nc_dfifo;
760 /*21*/ u8 nc_ctest4;
761 #define MUX 0x80 /* 720 host bus multiplex mode */
762 #define BDIS 0x80 /* mod: burst disable */
763 #define MPEE 0x08 /* mod: master parity error enable */
764
765 /*22*/ u8 nc_ctest5;
766 #define DFS 0x20 /* mod: dma fifo size */
767 /* bits 0-1, 3-7 rsvd for C1010 */
768 /*23*/ u8 nc_ctest6;
769
770 /*24*/ u32 nc_dbc; /* ### Byte count and command */
771 /*28*/ u32 nc_dnad; /* ### Next command register */
772 /*2c*/ u32 nc_dsp; /* --> Script Pointer */
773 /*30*/ u32 nc_dsps; /* --> Script pointer save/opcode#2 */
774
775 /*34*/ u8 nc_scratcha; /* Temporary register a */
776 /*35*/ u8 nc_scratcha1;
777 /*36*/ u8 nc_scratcha2;
778 /*37*/ u8 nc_scratcha3;
779
780 /*38*/ u8 nc_dmode;
781 #define BL_2 0x80 /* mod: burst length shift value +2 */
782 #define BL_1 0x40 /* mod: burst length shift value +1 */
783 #define ERL 0x08 /* mod: enable read line */
784 #define ERMP 0x04 /* mod: enable read multiple */
785 #define BOF 0x02 /* mod: burst op code fetch */
786
787 /*39*/ u8 nc_dien;
788 /*3a*/ u8 nc_sbr;
789
790 /*3b*/ u8 nc_dcntl; /* --> Script execution control */
791 #define CLSE 0x80 /* mod: cache line size enable */
792 #define PFF 0x40 /* cmd: pre-fetch flush */
793 #define PFEN 0x20 /* mod: pre-fetch enable */
794 #define EA 0x20 /* mod: 720 enable-ack */
795 #define SSM 0x10 /* mod: single step mode */
796 #define IRQM 0x08 /* mod: irq mode (1 = totem pole !) */
797 #define STD 0x04 /* cmd: start dma mode */
798 #define IRQD 0x02 /* mod: irq disable */
799 #define NOCOM 0x01 /* cmd: protect sfbr while reselect */
800 /* bits 0-1 rsvd for C1010 */
801
802 /*3c*/ u32 nc_adder;
803
804 /*40*/ u16 nc_sien; /* -->: interrupt enable */
805 /*42*/ u16 nc_sist; /* <--: interrupt status */
806 #define SBMC 0x1000/* sta: SCSI Bus Mode Change (895/6 only) */
807 #define STO 0x0400/* sta: timeout (select) */
808 #define GEN 0x0200/* sta: timeout (general) */
809 #define HTH 0x0100/* sta: timeout (handshake) */
810 #define MA 0x80 /* sta: phase mismatch */
811 #define CMP 0x40 /* sta: arbitration complete */
812 #define SEL 0x20 /* sta: selected by another device */
813 #define RSL 0x10 /* sta: reselected by another device*/
814 #define SGE 0x08 /* sta: gross error (over/underflow)*/
815 #define UDC 0x04 /* sta: unexpected disconnect */
816 #define RST 0x02 /* sta: scsi bus reset detected */
817 #define PAR 0x01 /* sta: scsi parity error */
818
819 /*44*/ u8 nc_slpar;
820 /*45*/ u8 nc_swide;
821 /*46*/ u8 nc_macntl;
822 /*47*/ u8 nc_gpcntl;
823 /*48*/ u8 nc_stime0; /* cmd: timeout for select&handshake*/
824 /*49*/ u8 nc_stime1; /* cmd: timeout user defined */
825 /*4a*/ u16 nc_respid; /* sta: Reselect-IDs */
826
827 /*4c*/ u8 nc_stest0;
828
829 /*4d*/ u8 nc_stest1;
830 #define SCLK 0x80 /* Use the PCI clock as SCSI clock */
831 #define DBLEN 0x08 /* clock doubler running */
832 #define DBLSEL 0x04 /* clock doubler selected */
833
834
835 /*4e*/ u8 nc_stest2;
836 #define ROF 0x40 /* reset scsi offset (after gross error!) */
837 #define DIF 0x20 /* 720 SCSI differential mode */
838 #define EXT 0x02 /* extended filtering */
839
840 /*4f*/ u8 nc_stest3;
841 #define TE 0x80 /* c: tolerAnt enable */
842 #define HSC 0x20 /* c: Halt SCSI Clock */
843 #define CSF 0x02 /* c: clear scsi fifo */
844
845 /*50*/ u16 nc_sidl; /* Lowlevel: latched from scsi data */
846 /*52*/ u8 nc_stest4;
847 #define SMODE 0xc0 /* SCSI bus mode (895/6 only) */
848 #define SMODE_HVD 0x40 /* High Voltage Differential */
849 #define SMODE_SE 0x80 /* Single Ended */
850 #define SMODE_LVD 0xc0 /* Low Voltage Differential */
851 #define LCKFRQ 0x20 /* Frequency Lock (895/6 only) */
852 /* bits 0-5 rsvd for C1010 */
853
854 /*53*/ u8 nc_53_;
855 /*54*/ u16 nc_sodl; /* Lowlevel: data out to scsi data */
856 /*56*/ u8 nc_ccntl0; /* Chip Control 0 (896) */
857 #define ENPMJ 0x80 /* Enable Phase Mismatch Jump */
858 #define PMJCTL 0x40 /* Phase Mismatch Jump Control */
859 #define ENNDJ 0x20 /* Enable Non Data PM Jump */
860 #define DISFC 0x10 /* Disable Auto FIFO Clear */
861 #define DILS 0x02 /* Disable Internal Load/Store */
862 #define DPR 0x01 /* Disable Pipe Req */
863
864 /*57*/ u8 nc_ccntl1; /* Chip Control 1 (896) */
865 #define ZMOD 0x80 /* High Impedance Mode */
866 #define DIC 0x10 /* Disable Internal Cycles */
867 #define DDAC 0x08 /* Disable Dual Address Cycle */
868 #define XTIMOD 0x04 /* 64-bit Table Ind. Indexing Mode */
869 #define EXTIBMV 0x02 /* Enable 64-bit Table Ind. BMOV */
870 #define EXDBMV 0x01 /* Enable 64-bit Direct BMOV */
871
872 /*58*/ u16 nc_sbdl; /* Lowlevel: data from scsi data */
873 /*5a*/ u16 nc_5a_;
874
875 /*5c*/ u8 nc_scr0; /* Working register B */
876 /*5d*/ u8 nc_scr1; /* */
877 /*5e*/ u8 nc_scr2; /* */
878 /*5f*/ u8 nc_scr3; /* */
879
880 /*60*/ u8 nc_scrx[64]; /* Working register C-R */
881 /*a0*/ u32 nc_mmrs; /* Memory Move Read Selector */
882 /*a4*/ u32 nc_mmws; /* Memory Move Write Selector */
883 /*a8*/ u32 nc_sfs; /* Script Fetch Selector */
884 /*ac*/ u32 nc_drs; /* DSA Relative Selector */
885 /*b0*/ u32 nc_sbms; /* Static Block Move Selector */
886 /*b4*/ u32 nc_dbms; /* Dynamic Block Move Selector */
887 /*b8*/ u32 nc_dnad64; /* DMA Next Address 64 */
888 /*bc*/ u16 nc_scntl4; /* C1010 only */
889 #define U3EN 0x80 /* Enable Ultra 3 */
890 #define AIPEN 0x40 /* Allow check upper byte lanes */
891 #define XCLKH_DT 0x08 /* Extra clock of data hold on DT
892 transfer edge */
893 #define XCLKH_ST 0x04 /* Extra clock of data hold on ST
894 transfer edge */
895
896 /*be*/ u8 nc_aipcntl0; /* Epat Control 1 C1010 only */
897 /*bf*/ u8 nc_aipcntl1; /* AIP Control C1010_66 Only */
898
899 /*c0*/ u32 nc_pmjad1; /* Phase Mismatch Jump Address 1 */
900 /*c4*/ u32 nc_pmjad2; /* Phase Mismatch Jump Address 2 */
901 /*c8*/ u8 nc_rbc; /* Remaining Byte Count */
902 /*c9*/ u8 nc_rbc1; /* */
903 /*ca*/ u8 nc_rbc2; /* */
904 /*cb*/ u8 nc_rbc3; /* */
905
906 /*cc*/ u8 nc_ua; /* Updated Address */
907 /*cd*/ u8 nc_ua1; /* */
908 /*ce*/ u8 nc_ua2; /* */
909 /*cf*/ u8 nc_ua3; /* */
910 /*d0*/ u32 nc_esa; /* Entry Storage Address */
911 /*d4*/ u8 nc_ia; /* Instruction Address */
912 /*d5*/ u8 nc_ia1;
913 /*d6*/ u8 nc_ia2;
914 /*d7*/ u8 nc_ia3;
915 /*d8*/ u32 nc_sbc; /* SCSI Byte Count (3 bytes only) */
916 /*dc*/ u32 nc_csbc; /* Cumulative SCSI Byte Count */
917
918 /* Following for C1010 only */
919 /*e0*/ u16 nc_crcpad; /* CRC Value */
920 /*e2*/ u8 nc_crccntl0; /* CRC control register */
921 #define SNDCRC 0x10 /* Send CRC Request */
922 /*e3*/ u8 nc_crccntl1; /* CRC control register */
923 /*e4*/ u32 nc_crcdata; /* CRC data register */
924 /*e8*/ u32 nc_e8_; /* rsvd */
925 /*ec*/ u32 nc_ec_; /* rsvd */
926 /*f0*/ u16 nc_dfbc; /* DMA FIFO byte count */
927
928 };
929
930 /*-----------------------------------------------------------
931 **
932 ** Utility macros for the script.
933 **
934 **-----------------------------------------------------------
935 */
936
937 #define REGJ(p,r) (offsetof(struct ncr_reg, p ## r))
938 #define REG(r) REGJ (nc_, r)
939
940 typedef u32 ncrcmd;
941
942 /*-----------------------------------------------------------
943 **
944 ** SCSI phases
945 **
946 ** DT phases illegal for ncr driver.
947 **
948 **-----------------------------------------------------------
949 */
950
951 #define SCR_DATA_OUT 0x00000000
952 #define SCR_DATA_IN 0x01000000
953 #define SCR_COMMAND 0x02000000
954 #define SCR_STATUS 0x03000000
955 #define SCR_DT_DATA_OUT 0x04000000
956 #define SCR_DT_DATA_IN 0x05000000
957 #define SCR_MSG_OUT 0x06000000
958 #define SCR_MSG_IN 0x07000000
959
960 #define SCR_ILG_OUT 0x04000000
961 #define SCR_ILG_IN 0x05000000
962
963 /*-----------------------------------------------------------
964 **
965 ** Data transfer via SCSI.
966 **
967 **-----------------------------------------------------------
968 **
969 ** MOVE_ABS (LEN)
970 ** <<start address>>
971 **
972 ** MOVE_IND (LEN)
973 ** <<dnad_offset>>
974 **
975 ** MOVE_TBL
976 ** <<dnad_offset>>
977 **
978 **-----------------------------------------------------------
979 */
980
981 #define OPC_MOVE 0x08000000
982
983 #define SCR_MOVE_ABS(l) ((0x00000000 | OPC_MOVE) | (l))
984 #define SCR_MOVE_IND(l) ((0x20000000 | OPC_MOVE) | (l))
985 #define SCR_MOVE_TBL (0x10000000 | OPC_MOVE)
986
987 #define SCR_CHMOV_ABS(l) ((0x00000000) | (l))
988 #define SCR_CHMOV_IND(l) ((0x20000000) | (l))
989 #define SCR_CHMOV_TBL (0x10000000)
990
991 struct scr_tblmove {
992 u32 size;
993 u32 addr;
994 };
995
996 /*-----------------------------------------------------------
997 **
998 ** Selection
999 **
1000 **-----------------------------------------------------------
1001 **
1002 ** SEL_ABS | SCR_ID (0..15) [ | REL_JMP]
1003 ** <<alternate_address>>
1004 **
1005 ** SEL_TBL | << dnad_offset>> [ | REL_JMP]
1006 ** <<alternate_address>>
1007 **
1008 **-----------------------------------------------------------
1009 */
1010
1011 #define SCR_SEL_ABS 0x40000000
1012 #define SCR_SEL_ABS_ATN 0x41000000
1013 #define SCR_SEL_TBL 0x42000000
1014 #define SCR_SEL_TBL_ATN 0x43000000
1015
1016
1017 #ifdef SCSI_NCR_BIG_ENDIAN
1018 struct scr_tblsel {
1019 u8 sel_scntl3;
1020 u8 sel_id;
1021 u8 sel_sxfer;
1022 u8 sel_scntl4;
1023 };
1024 #else
1025 struct scr_tblsel {
1026 u8 sel_scntl4;
1027 u8 sel_sxfer;
1028 u8 sel_id;
1029 u8 sel_scntl3;
1030 };
1031 #endif
1032
1033 #define SCR_JMP_REL 0x04000000
1034 #define SCR_ID(id) (((u32)(id)) << 16)
1035
1036 /*-----------------------------------------------------------
1037 **
1038 ** Waiting for Disconnect or Reselect
1039 **
1040 **-----------------------------------------------------------
1041 **
1042 ** WAIT_DISC
1043 ** dummy: <<alternate_address>>
1044 **
1045 ** WAIT_RESEL
1046 ** <<alternate_address>>
1047 **
1048 **-----------------------------------------------------------
1049 */
1050
1051 #define SCR_WAIT_DISC 0x48000000
1052 #define SCR_WAIT_RESEL 0x50000000
1053
1054 /*-----------------------------------------------------------
1055 **
1056 ** Bit Set / Reset
1057 **
1058 **-----------------------------------------------------------
1059 **
1060 ** SET (flags {|.. })
1061 **
1062 ** CLR (flags {|.. })
1063 **
1064 **-----------------------------------------------------------
1065 */
1066
1067 #define SCR_SET(f) (0x58000000 | (f))
1068 #define SCR_CLR(f) (0x60000000 | (f))
1069
1070 #define SCR_CARRY 0x00000400
1071 #define SCR_TRG 0x00000200
1072 #define SCR_ACK 0x00000040
1073 #define SCR_ATN 0x00000008
1074
1075
1076
1077
1078 /*-----------------------------------------------------------
1079 **
1080 ** Memory to memory move
1081 **
1082 **-----------------------------------------------------------
1083 **
1084 ** COPY (bytecount)
1085 ** << source_address >>
1086 ** << destination_address >>
1087 **
1088 ** SCR_COPY sets the NO FLUSH option by default.
1089 ** SCR_COPY_F does not set this option.
1090 **
1091 ** For chips which do not support this option,
1092 ** ncr_copy_and_bind() will remove this bit.
1093 **-----------------------------------------------------------
1094 */
1095
1096 #define SCR_NO_FLUSH 0x01000000
1097
1098 #define SCR_COPY(n) (0xc0000000 | SCR_NO_FLUSH | (n))
1099 #define SCR_COPY_F(n) (0xc0000000 | (n))
1100
1101 /*-----------------------------------------------------------
1102 **
1103 ** Register move and binary operations
1104 **
1105 **-----------------------------------------------------------
1106 **
1107 ** SFBR_REG (reg, op, data) reg = SFBR op data
1108 ** << 0 >>
1109 **
1110 ** REG_SFBR (reg, op, data) SFBR = reg op data
1111 ** << 0 >>
1112 **
1113 ** REG_REG (reg, op, data) reg = reg op data
1114 ** << 0 >>
1115 **
1116 **-----------------------------------------------------------
1117 ** On 810A, 860, 825A, 875, 895 and 896 chips the content
1118 ** of SFBR register can be used as data (SCR_SFBR_DATA).
1119 ** The 896 has additionnal IO registers starting at
1120 ** offset 0x80. Bit 7 of register offset is stored in
1121 ** bit 7 of the SCRIPTS instruction first DWORD.
1122 **-----------------------------------------------------------
1123 */
1124
1125 #define SCR_REG_OFS(ofs) ((((ofs) & 0x7f) << 16ul) + ((ofs) & 0x80))
1126
1127 #define SCR_SFBR_REG(reg,op,data) \
1128 (0x68000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1129
1130 #define SCR_REG_SFBR(reg,op,data) \
1131 (0x70000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1132
1133 #define SCR_REG_REG(reg,op,data) \
1134 (0x78000000 | (SCR_REG_OFS(REG(reg))) | (op) | (((data)&0xff)<<8ul))
1135
1136
1137 #define SCR_LOAD 0x00000000
1138 #define SCR_SHL 0x01000000
1139 #define SCR_OR 0x02000000
1140 #define SCR_XOR 0x03000000
1141 #define SCR_AND 0x04000000
1142 #define SCR_SHR 0x05000000
1143 #define SCR_ADD 0x06000000
1144 #define SCR_ADDC 0x07000000
1145
1146 #define SCR_SFBR_DATA (0x00800000>>8ul) /* Use SFBR as data */
1147
1148 /*-----------------------------------------------------------
1149 **
1150 ** FROM_REG (reg) SFBR = reg
1151 ** << 0 >>
1152 **
1153 ** TO_REG (reg) reg = SFBR
1154 ** << 0 >>
1155 **
1156 ** LOAD_REG (reg, data) reg = <data>
1157 ** << 0 >>
1158 **
1159 ** LOAD_SFBR(data) SFBR = <data>
1160 ** << 0 >>
1161 **
1162 **-----------------------------------------------------------
1163 */
1164
1165 #define SCR_FROM_REG(reg) \
1166 SCR_REG_SFBR(reg,SCR_OR,0)
1167
1168 #define SCR_TO_REG(reg) \
1169 SCR_SFBR_REG(reg,SCR_OR,0)
1170
1171 #define SCR_LOAD_REG(reg,data) \
1172 SCR_REG_REG(reg,SCR_LOAD,data)
1173
1174 #define SCR_LOAD_SFBR(data) \
1175 (SCR_REG_SFBR (gpreg, SCR_LOAD, data))
1176
1177 /*-----------------------------------------------------------
1178 **
1179 ** LOAD from memory to register.
1180 ** STORE from register to memory.
1181 **
1182 ** Only supported by 810A, 860, 825A, 875, 895 and 896.
1183 **
1184 **-----------------------------------------------------------
1185 **
1186 ** LOAD_ABS (LEN)
1187 ** <<start address>>
1188 **
1189 ** LOAD_REL (LEN) (DSA relative)
1190 ** <<dsa_offset>>
1191 **
1192 **-----------------------------------------------------------
1193 */
1194
1195 #define SCR_REG_OFS2(ofs) (((ofs) & 0xff) << 16ul)
1196 #define SCR_NO_FLUSH2 0x02000000
1197 #define SCR_DSA_REL2 0x10000000
1198
1199 #define SCR_LOAD_R(reg, how, n) \
1200 (0xe1000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
1201
1202 #define SCR_STORE_R(reg, how, n) \
1203 (0xe0000000 | how | (SCR_REG_OFS2(REG(reg))) | (n))
1204
1205 #define SCR_LOAD_ABS(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2, n)
1206 #define SCR_LOAD_REL(reg, n) SCR_LOAD_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2, n)
1207 #define SCR_LOAD_ABS_F(reg, n) SCR_LOAD_R(reg, 0, n)
1208 #define SCR_LOAD_REL_F(reg, n) SCR_LOAD_R(reg, SCR_DSA_REL2, n)
1209
1210 #define SCR_STORE_ABS(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2, n)
1211 #define SCR_STORE_REL(reg, n) SCR_STORE_R(reg, SCR_NO_FLUSH2|SCR_DSA_REL2,n)
1212 #define SCR_STORE_ABS_F(reg, n) SCR_STORE_R(reg, 0, n)
1213 #define SCR_STORE_REL_F(reg, n) SCR_STORE_R(reg, SCR_DSA_REL2, n)
1214
1215
1216 /*-----------------------------------------------------------
1217 **
1218 ** Waiting for Disconnect or Reselect
1219 **
1220 **-----------------------------------------------------------
1221 **
1222 ** JUMP [ | IFTRUE/IFFALSE ( ... ) ]
1223 ** <<address>>
1224 **
1225 ** JUMPR [ | IFTRUE/IFFALSE ( ... ) ]
1226 ** <<distance>>
1227 **
1228 ** CALL [ | IFTRUE/IFFALSE ( ... ) ]
1229 ** <<address>>
1230 **
1231 ** CALLR [ | IFTRUE/IFFALSE ( ... ) ]
1232 ** <<distance>>
1233 **
1234 ** RETURN [ | IFTRUE/IFFALSE ( ... ) ]
1235 ** <<dummy>>
1236 **
1237 ** INT [ | IFTRUE/IFFALSE ( ... ) ]
1238 ** <<ident>>
1239 **
1240 ** INT_FLY [ | IFTRUE/IFFALSE ( ... ) ]
1241 ** <<ident>>
1242 **
1243 ** Conditions:
1244 ** WHEN (phase)
1245 ** IF (phase)
1246 ** CARRYSET
1247 ** DATA (data, mask)
1248 **
1249 **-----------------------------------------------------------
1250 */
1251
1252 #define SCR_NO_OP 0x80000000
1253 #define SCR_JUMP 0x80080000
1254 #define SCR_JUMP64 0x80480000
1255 #define SCR_JUMPR 0x80880000
1256 #define SCR_CALL 0x88080000
1257 #define SCR_CALLR 0x88880000
1258 #define SCR_RETURN 0x90080000
1259 #define SCR_INT 0x98080000
1260 #define SCR_INT_FLY 0x98180000
1261
1262 #define IFFALSE(arg) (0x00080000 | (arg))
1263 #define IFTRUE(arg) (0x00000000 | (arg))
1264
1265 #define WHEN(phase) (0x00030000 | (phase))
1266 #define IF(phase) (0x00020000 | (phase))
1267
1268 #define DATA(D) (0x00040000 | ((D) & 0xff))
1269 #define MASK(D,M) (0x00040000 | (((M ^ 0xff) & 0xff) << 8ul)|((D) & 0xff))
1270
1271 #define CARRYSET (0x00200000)
1272
1273 /*-----------------------------------------------------------
1274 **
1275 ** SCSI constants.
1276 **
1277 **-----------------------------------------------------------
1278 */
1279
1280 /*
1281 ** Messages
1282 */
1283
1284 #define M_COMPLETE COMMAND_COMPLETE
1285 #define M_EXTENDED EXTENDED_MESSAGE
1286 #define M_SAVE_DP SAVE_POINTERS
1287 #define M_RESTORE_DP RESTORE_POINTERS
1288 #define M_DISCONNECT DISCONNECT
1289 #define M_ID_ERROR INITIATOR_ERROR
1290 #define M_ABORT ABORT_TASK_SET
1291 #define M_REJECT MESSAGE_REJECT
1292 #define M_NOOP NOP
1293 #define M_PARITY MSG_PARITY_ERROR
1294 #define M_LCOMPLETE LINKED_CMD_COMPLETE
1295 #define M_FCOMPLETE LINKED_FLG_CMD_COMPLETE
1296 #define M_RESET TARGET_RESET
1297 #define M_ABORT_TAG ABORT_TASK
1298 #define M_CLEAR_QUEUE CLEAR_TASK_SET
1299 #define M_INIT_REC INITIATE_RECOVERY
1300 #define M_REL_REC RELEASE_RECOVERY
1301 #define M_TERMINATE (0x11)
1302 #define M_SIMPLE_TAG SIMPLE_QUEUE_TAG
1303 #define M_HEAD_TAG HEAD_OF_QUEUE_TAG
1304 #define M_ORDERED_TAG ORDERED_QUEUE_TAG
1305 #define M_IGN_RESIDUE IGNORE_WIDE_RESIDUE
1306 #define M_IDENTIFY (0x80)
1307
1308 #define M_X_MODIFY_DP EXTENDED_MODIFY_DATA_POINTER
1309 #define M_X_SYNC_REQ EXTENDED_SDTR
1310 #define M_X_WIDE_REQ EXTENDED_WDTR
1311 #define M_X_PPR_REQ EXTENDED_PPR
1312
1313 /*
1314 ** Status
1315 */
1316
1317 #define S_GOOD (0x00)
1318 #define S_CHECK_COND (0x02)
1319 #define S_COND_MET (0x04)
1320 #define S_BUSY (0x08)
1321 #define S_INT (0x10)
1322 #define S_INT_COND_MET (0x14)
1323 #define S_CONFLICT (0x18)
1324 #define S_TERMINATED (0x20)
1325 #define S_QUEUE_FULL (0x28)
1326 #define S_ILLEGAL (0xff)
1327 #define S_SENSE (0x80)
1328
1329 /*
1330 * End of ncrreg from FreeBSD
1331 */
1332
1333 #endif /* defined SYM53C8XX_DEFS_H */
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