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[PATCH] W1: w1_netlink: New init/fini netlink callbacks.
[linux-2.6/verdex.git] / drivers / serial / 8250_pci.c
blob0e21f583690ebdeffa57f316bd8fba2c67da8e71
1 /*
2 * linux/drivers/char/8250_pci.c
3 *
4 * Probe module for 8250/16550-type PCI serial ports.
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2001 Russell King, All Rights Reserved.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License.
13 *
14 * $Id: 8250_pci.c,v 1.28 2002/11/02 11:14:18 rmk Exp $
15 */
16 #include <linux/module.h>
17 #include <linux/init.h>
18 #include <linux/pci.h>
19 #include <linux/sched.h>
20 #include <linux/string.h>
21 #include <linux/kernel.h>
22 #include <linux/slab.h>
23 #include <linux/delay.h>
24 #include <linux/tty.h>
25 #include <linux/serial_core.h>
26 #include <linux/8250_pci.h>
27 #include <linux/bitops.h>
28
29 #include <asm/byteorder.h>
30 #include <asm/io.h>
31
32 #include "8250.h"
33
34 #undef SERIAL_DEBUG_PCI
35
36 /*
37 * init function returns:
38 * > 0 - number of ports
39 * = 0 - use board->num_ports
40 * < 0 - error
41 */
42 struct pci_serial_quirk {
43 u32 vendor;
44 u32 device;
45 u32 subvendor;
46 u32 subdevice;
47 int (*init)(struct pci_dev *dev);
48 int (*setup)(struct serial_private *, struct pciserial_board *,
49 struct uart_port *, int);
50 void (*exit)(struct pci_dev *dev);
51 };
52
53 #define PCI_NUM_BAR_RESOURCES 6
54
55 struct serial_private {
56 struct pci_dev *dev;
57 unsigned int nr;
58 void __iomem *remapped_bar[PCI_NUM_BAR_RESOURCES];
59 struct pci_serial_quirk *quirk;
60 int line[0];
61 };
62
63 static void moan_device(const char *str, struct pci_dev *dev)
64 {
65 printk(KERN_WARNING "%s: %s\n"
66 KERN_WARNING "Please send the output of lspci -vv, this\n"
67 KERN_WARNING "message (0x%04x,0x%04x,0x%04x,0x%04x), the\n"
68 KERN_WARNING "manufacturer and name of serial board or\n"
69 KERN_WARNING "modem board to rmk+serial@arm.linux.org.uk.\n",
70 pci_name(dev), str, dev->vendor, dev->device,
71 dev->subsystem_vendor, dev->subsystem_device);
72 }
73
74 static int
75 setup_port(struct serial_private *priv, struct uart_port *port,
76 int bar, int offset, int regshift)
77 {
78 struct pci_dev *dev = priv->dev;
79 unsigned long base, len;
80
81 if (bar >= PCI_NUM_BAR_RESOURCES)
82 return -EINVAL;
83
84 base = pci_resource_start(dev, bar);
85
86 if (pci_resource_flags(dev, bar) & IORESOURCE_MEM) {
87 len = pci_resource_len(dev, bar);
88
89 if (!priv->remapped_bar[bar])
90 priv->remapped_bar[bar] = ioremap(base, len);
91 if (!priv->remapped_bar[bar])
92 return -ENOMEM;
93
94 port->iotype = UPIO_MEM;
95 port->iobase = 0;
96 port->mapbase = base + offset;
97 port->membase = priv->remapped_bar[bar] + offset;
98 port->regshift = regshift;
99 } else {
100 port->iotype = UPIO_PORT;
101 port->iobase = base + offset;
102 port->mapbase = 0;
103 port->membase = NULL;
104 port->regshift = 0;
105 }
106 return 0;
107 }
108
109 /*
110 * AFAVLAB uses a different mixture of BARs and offsets
111 * Not that ugly ;) -- HW
112 */
113 static int
114 afavlab_setup(struct serial_private *priv, struct pciserial_board *board,
115 struct uart_port *port, int idx)
116 {
117 unsigned int bar, offset = board->first_offset;
118
119 bar = FL_GET_BASE(board->flags);
120 if (idx < 4)
121 bar += idx;
122 else {
123 bar = 4;
124 offset += (idx - 4) * board->uart_offset;
125 }
126
127 return setup_port(priv, port, bar, offset, board->reg_shift);
128 }
129
130 /*
131 * HP's Remote Management Console. The Diva chip came in several
132 * different versions. N-class, L2000 and A500 have two Diva chips, each
133 * with 3 UARTs (the third UART on the second chip is unused). Superdome
134 * and Keystone have one Diva chip with 3 UARTs. Some later machines have
135 * one Diva chip, but it has been expanded to 5 UARTs.
136 */
137 static int __devinit pci_hp_diva_init(struct pci_dev *dev)
138 {
139 int rc = 0;
140
141 switch (dev->subsystem_device) {
142 case PCI_DEVICE_ID_HP_DIVA_TOSCA1:
143 case PCI_DEVICE_ID_HP_DIVA_HALFDOME:
144 case PCI_DEVICE_ID_HP_DIVA_KEYSTONE:
145 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
146 rc = 3;
147 break;
148 case PCI_DEVICE_ID_HP_DIVA_TOSCA2:
149 rc = 2;
150 break;
151 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
152 rc = 4;
153 break;
154 case PCI_DEVICE_ID_HP_DIVA_POWERBAR:
155 rc = 1;
156 break;
157 }
158
159 return rc;
160 }
161
162 /*
163 * HP's Diva chip puts the 4th/5th serial port further out, and
164 * some serial ports are supposed to be hidden on certain models.
165 */
166 static int
167 pci_hp_diva_setup(struct serial_private *priv, struct pciserial_board *board,
168 struct uart_port *port, int idx)
169 {
170 unsigned int offset = board->first_offset;
171 unsigned int bar = FL_GET_BASE(board->flags);
172
173 switch (priv->dev->subsystem_device) {
174 case PCI_DEVICE_ID_HP_DIVA_MAESTRO:
175 if (idx == 3)
176 idx++;
177 break;
178 case PCI_DEVICE_ID_HP_DIVA_EVEREST:
179 if (idx > 0)
180 idx++;
181 if (idx > 2)
182 idx++;
183 break;
184 }
185 if (idx > 2)
186 offset = 0x18;
187
188 offset += idx * board->uart_offset;
189
190 return setup_port(priv, port, bar, offset, board->reg_shift);
191 }
192
193 /*
194 * Added for EKF Intel i960 serial boards
195 */
196 static int __devinit pci_inteli960ni_init(struct pci_dev *dev)
197 {
198 unsigned long oldval;
199
200 if (!(dev->subsystem_device & 0x1000))
201 return -ENODEV;
202
203 /* is firmware started? */
204 pci_read_config_dword(dev, 0x44, (void*) &oldval);
205 if (oldval == 0x00001000L) { /* RESET value */
206 printk(KERN_DEBUG "Local i960 firmware missing");
207 return -ENODEV;
208 }
209 return 0;
210 }
211
212 /*
213 * Some PCI serial cards using the PLX 9050 PCI interface chip require
214 * that the card interrupt be explicitly enabled or disabled. This
215 * seems to be mainly needed on card using the PLX which also use I/O
216 * mapped memory.
217 */
218 static int __devinit pci_plx9050_init(struct pci_dev *dev)
219 {
220 u8 irq_config;
221 void __iomem *p;
222
223 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0) {
224 moan_device("no memory in bar 0", dev);
225 return 0;
226 }
227
228 irq_config = 0x41;
229 if (dev->vendor == PCI_VENDOR_ID_PANACOM)
230 irq_config = 0x43;
231 if ((dev->vendor == PCI_VENDOR_ID_PLX) &&
232 (dev->device == PCI_DEVICE_ID_PLX_ROMULUS)) {
233 /*
234 * As the megawolf cards have the int pins active
235 * high, and have 2 UART chips, both ints must be
236 * enabled on the 9050. Also, the UARTS are set in
237 * 16450 mode by default, so we have to enable the
238 * 16C950 'enhanced' mode so that we can use the
239 * deep FIFOs
240 */
241 irq_config = 0x5b;
242 }
243
244 /*
245 * enable/disable interrupts
246 */
247 p = ioremap(pci_resource_start(dev, 0), 0x80);
248 if (p == NULL)
249 return -ENOMEM;
250 writel(irq_config, p + 0x4c);
251
252 /*
253 * Read the register back to ensure that it took effect.
254 */
255 readl(p + 0x4c);
256 iounmap(p);
257
258 return 0;
259 }
260
261 static void __devexit pci_plx9050_exit(struct pci_dev *dev)
262 {
263 u8 __iomem *p;
264
265 if ((pci_resource_flags(dev, 0) & IORESOURCE_MEM) == 0)
266 return;
267
268 /*
269 * disable interrupts
270 */
271 p = ioremap(pci_resource_start(dev, 0), 0x80);
272 if (p != NULL) {
273 writel(0, p + 0x4c);
274
275 /*
276 * Read the register back to ensure that it took effect.
277 */
278 readl(p + 0x4c);
279 iounmap(p);
280 }
281 }
282
283 /* SBS Technologies Inc. PMC-OCTPRO and P-OCTAL cards */
284 static int
285 sbs_setup(struct serial_private *priv, struct pciserial_board *board,
286 struct uart_port *port, int idx)
287 {
288 unsigned int bar, offset = board->first_offset;
289
290 bar = 0;
291
292 if (idx < 4) {
293 /* first four channels map to 0, 0x100, 0x200, 0x300 */
294 offset += idx * board->uart_offset;
295 } else if (idx < 8) {
296 /* last four channels map to 0x1000, 0x1100, 0x1200, 0x1300 */
297 offset += idx * board->uart_offset + 0xC00;
298 } else /* we have only 8 ports on PMC-OCTALPRO */
299 return 1;
300
301 return setup_port(priv, port, bar, offset, board->reg_shift);
302 }
303
304 /*
305 * This does initialization for PMC OCTALPRO cards:
306 * maps the device memory, resets the UARTs (needed, bc
307 * if the module is removed and inserted again, the card
308 * is in the sleep mode) and enables global interrupt.
309 */
310
311 /* global control register offset for SBS PMC-OctalPro */
312 #define OCT_REG_CR_OFF 0x500
313
314 static int __devinit sbs_init(struct pci_dev *dev)
315 {
316 u8 __iomem *p;
317
318 p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
319
320 if (p == NULL)
321 return -ENOMEM;
322 /* Set bit-4 Control Register (UART RESET) in to reset the uarts */
323 writeb(0x10,p + OCT_REG_CR_OFF);
324 udelay(50);
325 writeb(0x0,p + OCT_REG_CR_OFF);
326
327 /* Set bit-2 (INTENABLE) of Control Register */
328 writeb(0x4, p + OCT_REG_CR_OFF);
329 iounmap(p);
330
331 return 0;
332 }
333
334 /*
335 * Disables the global interrupt of PMC-OctalPro
336 */
337
338 static void __devexit sbs_exit(struct pci_dev *dev)
339 {
340 u8 __iomem *p;
341
342 p = ioremap(pci_resource_start(dev, 0),pci_resource_len(dev,0));
343 if (p != NULL) {
344 writeb(0, p + OCT_REG_CR_OFF);
345 }
346 iounmap(p);
347 }
348
349 /*
350 * SIIG serial cards have an PCI interface chip which also controls
351 * the UART clocking frequency. Each UART can be clocked independently
352 * (except cards equiped with 4 UARTs) and initial clocking settings
353 * are stored in the EEPROM chip. It can cause problems because this
354 * version of serial driver doesn't support differently clocked UART's
355 * on single PCI card. To prevent this, initialization functions set
356 * high frequency clocking for all UART's on given card. It is safe (I
357 * hope) because it doesn't touch EEPROM settings to prevent conflicts
358 * with other OSes (like M$ DOS).
359 *
360 * SIIG support added by Andrey Panin <pazke@donpac.ru>, 10/1999
361 *
362 * There is two family of SIIG serial cards with different PCI
363 * interface chip and different configuration methods:
364 * - 10x cards have control registers in IO and/or memory space;
365 * - 20x cards have control registers in standard PCI configuration space.
366 *
367 * Note: all 10x cards have PCI device ids 0x10..
368 * all 20x cards have PCI device ids 0x20..
369 *
370 * There are also Quartet Serial cards which use Oxford Semiconductor
371 * 16954 quad UART PCI chip clocked by 18.432 MHz quartz.
372 *
373 * Note: some SIIG cards are probed by the parport_serial object.
374 */
375
376 #define PCI_DEVICE_ID_SIIG_1S_10x (PCI_DEVICE_ID_SIIG_1S_10x_550 & 0xfffc)
377 #define PCI_DEVICE_ID_SIIG_2S_10x (PCI_DEVICE_ID_SIIG_2S_10x_550 & 0xfff8)
378
379 static int pci_siig10x_init(struct pci_dev *dev)
380 {
381 u16 data;
382 void __iomem *p;
383
384 switch (dev->device & 0xfff8) {
385 case PCI_DEVICE_ID_SIIG_1S_10x: /* 1S */
386 data = 0xffdf;
387 break;
388 case PCI_DEVICE_ID_SIIG_2S_10x: /* 2S, 2S1P */
389 data = 0xf7ff;
390 break;
391 default: /* 1S1P, 4S */
392 data = 0xfffb;
393 break;
394 }
395
396 p = ioremap(pci_resource_start(dev, 0), 0x80);
397 if (p == NULL)
398 return -ENOMEM;
399
400 writew(readw(p + 0x28) & data, p + 0x28);
401 readw(p + 0x28);
402 iounmap(p);
403 return 0;
404 }
405
406 #define PCI_DEVICE_ID_SIIG_2S_20x (PCI_DEVICE_ID_SIIG_2S_20x_550 & 0xfffc)
407 #define PCI_DEVICE_ID_SIIG_2S1P_20x (PCI_DEVICE_ID_SIIG_2S1P_20x_550 & 0xfffc)
408
409 static int pci_siig20x_init(struct pci_dev *dev)
410 {
411 u8 data;
412
413 /* Change clock frequency for the first UART. */
414 pci_read_config_byte(dev, 0x6f, &data);
415 pci_write_config_byte(dev, 0x6f, data & 0xef);
416
417 /* If this card has 2 UART, we have to do the same with second UART. */
418 if (((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S_20x) ||
419 ((dev->device & 0xfffc) == PCI_DEVICE_ID_SIIG_2S1P_20x)) {
420 pci_read_config_byte(dev, 0x73, &data);
421 pci_write_config_byte(dev, 0x73, data & 0xef);
422 }
423 return 0;
424 }
425
426 static int pci_siig_init(struct pci_dev *dev)
427 {
428 unsigned int type = dev->device & 0xff00;
429
430 if (type == 0x1000)
431 return pci_siig10x_init(dev);
432 else if (type == 0x2000)
433 return pci_siig20x_init(dev);
434
435 moan_device("Unknown SIIG card", dev);
436 return -ENODEV;
437 }
438
439 /*
440 * Timedia has an explosion of boards, and to avoid the PCI table from
441 * growing *huge*, we use this function to collapse some 70 entries
442 * in the PCI table into one, for sanity's and compactness's sake.
443 */
444 static unsigned short timedia_single_port[] = {
445 0x4025, 0x4027, 0x4028, 0x5025, 0x5027, 0
446 };
447
448 static unsigned short timedia_dual_port[] = {
449 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085,
450 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079,
451 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079,
452 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079,
453 0xD079, 0
454 };
455
456 static unsigned short timedia_quad_port[] = {
457 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157,
458 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159,
459 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056,
460 0xB157, 0
461 };
462
463 static unsigned short timedia_eight_port[] = {
464 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166,
465 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0
466 };
467
468 static struct timedia_struct {
469 int num;
470 unsigned short *ids;
471 } timedia_data[] = {
472 { 1, timedia_single_port },
473 { 2, timedia_dual_port },
474 { 4, timedia_quad_port },
475 { 8, timedia_eight_port },
476 { 0, NULL }
477 };
478
479 static int __devinit pci_timedia_init(struct pci_dev *dev)
480 {
481 unsigned short *ids;
482 int i, j;
483
484 for (i = 0; timedia_data[i].num; i++) {
485 ids = timedia_data[i].ids;
486 for (j = 0; ids[j]; j++)
487 if (dev->subsystem_device == ids[j])
488 return timedia_data[i].num;
489 }
490 return 0;
491 }
492
493 /*
494 * Timedia/SUNIX uses a mixture of BARs and offsets
495 * Ugh, this is ugly as all hell --- TYT
496 */
497 static int
498 pci_timedia_setup(struct serial_private *priv, struct pciserial_board *board,
499 struct uart_port *port, int idx)
500 {
501 unsigned int bar = 0, offset = board->first_offset;
502
503 switch (idx) {
504 case 0:
505 bar = 0;
506 break;
507 case 1:
508 offset = board->uart_offset;
509 bar = 0;
510 break;
511 case 2:
512 bar = 1;
513 break;
514 case 3:
515 offset = board->uart_offset;
516 bar = 1;
517 case 4: /* BAR 2 */
518 case 5: /* BAR 3 */
519 case 6: /* BAR 4 */
520 case 7: /* BAR 5 */
521 bar = idx - 2;
522 }
523
524 return setup_port(priv, port, bar, offset, board->reg_shift);
525 }
526
527 /*
528 * Some Titan cards are also a little weird
529 */
530 static int
531 titan_400l_800l_setup(struct serial_private *priv,
532 struct pciserial_board *board,
533 struct uart_port *port, int idx)
534 {
535 unsigned int bar, offset = board->first_offset;
536
537 switch (idx) {
538 case 0:
539 bar = 1;
540 break;
541 case 1:
542 bar = 2;
543 break;
544 default:
545 bar = 4;
546 offset = (idx - 2) * board->uart_offset;
547 }
548
549 return setup_port(priv, port, bar, offset, board->reg_shift);
550 }
551
552 static int __devinit pci_xircom_init(struct pci_dev *dev)
553 {
554 msleep(100);
555 return 0;
556 }
557
558 static int __devinit pci_netmos_init(struct pci_dev *dev)
559 {
560 /* subdevice 0x00PS means <P> parallel, <S> serial */
561 unsigned int num_serial = dev->subsystem_device & 0xf;
562
563 if (num_serial == 0)
564 return -ENODEV;
565 return num_serial;
566 }
567
568 static int
569 pci_default_setup(struct serial_private *priv, struct pciserial_board *board,
570 struct uart_port *port, int idx)
571 {
572 unsigned int bar, offset = board->first_offset, maxnr;
573
574 bar = FL_GET_BASE(board->flags);
575 if (board->flags & FL_BASE_BARS)
576 bar += idx;
577 else
578 offset += idx * board->uart_offset;
579
580 maxnr = (pci_resource_len(priv->dev, bar) - board->first_offset) /
581 (8 << board->reg_shift);
582
583 if (board->flags & FL_REGION_SZ_CAP && idx >= maxnr)
584 return 1;
585
586 return setup_port(priv, port, bar, offset, board->reg_shift);
587 }
588
589 /* This should be in linux/pci_ids.h */
590 #define PCI_VENDOR_ID_SBSMODULARIO 0x124B
591 #define PCI_SUBVENDOR_ID_SBSMODULARIO 0x124B
592 #define PCI_DEVICE_ID_OCTPRO 0x0001
593 #define PCI_SUBDEVICE_ID_OCTPRO232 0x0108
594 #define PCI_SUBDEVICE_ID_OCTPRO422 0x0208
595 #define PCI_SUBDEVICE_ID_POCTAL232 0x0308
596 #define PCI_SUBDEVICE_ID_POCTAL422 0x0408
597
598 /*
599 * Master list of serial port init/setup/exit quirks.
600 * This does not describe the general nature of the port.
601 * (ie, baud base, number and location of ports, etc)
602 *
603 * This list is ordered alphabetically by vendor then device.
604 * Specific entries must come before more generic entries.
605 */
606 static struct pci_serial_quirk pci_serial_quirks[] = {
607 /*
608 * AFAVLAB cards.
609 * It is not clear whether this applies to all products.
610 */
611 {
612 .vendor = PCI_VENDOR_ID_AFAVLAB,
613 .device = PCI_ANY_ID,
614 .subvendor = PCI_ANY_ID,
615 .subdevice = PCI_ANY_ID,
616 .setup = afavlab_setup,
617 },
618 /*
619 * HP Diva
620 */
621 {
622 .vendor = PCI_VENDOR_ID_HP,
623 .device = PCI_DEVICE_ID_HP_DIVA,
624 .subvendor = PCI_ANY_ID,
625 .subdevice = PCI_ANY_ID,
626 .init = pci_hp_diva_init,
627 .setup = pci_hp_diva_setup,
628 },
629 /*
630 * Intel
631 */
632 {
633 .vendor = PCI_VENDOR_ID_INTEL,
634 .device = PCI_DEVICE_ID_INTEL_80960_RP,
635 .subvendor = 0xe4bf,
636 .subdevice = PCI_ANY_ID,
637 .init = pci_inteli960ni_init,
638 .setup = pci_default_setup,
639 },
640 /*
641 * Panacom
642 */
643 {
644 .vendor = PCI_VENDOR_ID_PANACOM,
645 .device = PCI_DEVICE_ID_PANACOM_QUADMODEM,
646 .subvendor = PCI_ANY_ID,
647 .subdevice = PCI_ANY_ID,
648 .init = pci_plx9050_init,
649 .setup = pci_default_setup,
650 .exit = __devexit_p(pci_plx9050_exit),
651 },
652 {
653 .vendor = PCI_VENDOR_ID_PANACOM,
654 .device = PCI_DEVICE_ID_PANACOM_DUALMODEM,
655 .subvendor = PCI_ANY_ID,
656 .subdevice = PCI_ANY_ID,
657 .init = pci_plx9050_init,
658 .setup = pci_default_setup,
659 .exit = __devexit_p(pci_plx9050_exit),
660 },
661 /*
662 * PLX
663 */
664 {
665 .vendor = PCI_VENDOR_ID_PLX,
666 .device = PCI_DEVICE_ID_PLX_9050,
667 .subvendor = PCI_SUBVENDOR_ID_KEYSPAN,
668 .subdevice = PCI_SUBDEVICE_ID_KEYSPAN_SX2,
669 .init = pci_plx9050_init,
670 .setup = pci_default_setup,
671 .exit = __devexit_p(pci_plx9050_exit),
672 },
673 {
674 .vendor = PCI_VENDOR_ID_PLX,
675 .device = PCI_DEVICE_ID_PLX_ROMULUS,
676 .subvendor = PCI_VENDOR_ID_PLX,
677 .subdevice = PCI_DEVICE_ID_PLX_ROMULUS,
678 .init = pci_plx9050_init,
679 .setup = pci_default_setup,
680 .exit = __devexit_p(pci_plx9050_exit),
681 },
682 /*
683 * SBS Technologies, Inc., PMC-OCTALPRO 232
684 */
685 {
686 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
687 .device = PCI_DEVICE_ID_OCTPRO,
688 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
689 .subdevice = PCI_SUBDEVICE_ID_OCTPRO232,
690 .init = sbs_init,
691 .setup = sbs_setup,
692 .exit = __devexit_p(sbs_exit),
693 },
694 /*
695 * SBS Technologies, Inc., PMC-OCTALPRO 422
696 */
697 {
698 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
699 .device = PCI_DEVICE_ID_OCTPRO,
700 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
701 .subdevice = PCI_SUBDEVICE_ID_OCTPRO422,
702 .init = sbs_init,
703 .setup = sbs_setup,
704 .exit = __devexit_p(sbs_exit),
705 },
706 /*
707 * SBS Technologies, Inc., P-Octal 232
708 */
709 {
710 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
711 .device = PCI_DEVICE_ID_OCTPRO,
712 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
713 .subdevice = PCI_SUBDEVICE_ID_POCTAL232,
714 .init = sbs_init,
715 .setup = sbs_setup,
716 .exit = __devexit_p(sbs_exit),
717 },
718 /*
719 * SBS Technologies, Inc., P-Octal 422
720 */
721 {
722 .vendor = PCI_VENDOR_ID_SBSMODULARIO,
723 .device = PCI_DEVICE_ID_OCTPRO,
724 .subvendor = PCI_SUBVENDOR_ID_SBSMODULARIO,
725 .subdevice = PCI_SUBDEVICE_ID_POCTAL422,
726 .init = sbs_init,
727 .setup = sbs_setup,
728 .exit = __devexit_p(sbs_exit),
729 },
730 /*
731 * SIIG cards.
732 */
733 {
734 .vendor = PCI_VENDOR_ID_SIIG,
735 .device = PCI_ANY_ID,
736 .subvendor = PCI_ANY_ID,
737 .subdevice = PCI_ANY_ID,
738 .init = pci_siig_init,
739 .setup = pci_default_setup,
740 },
741 /*
742 * Titan cards
743 */
744 {
745 .vendor = PCI_VENDOR_ID_TITAN,
746 .device = PCI_DEVICE_ID_TITAN_400L,
747 .subvendor = PCI_ANY_ID,
748 .subdevice = PCI_ANY_ID,
749 .setup = titan_400l_800l_setup,
750 },
751 {
752 .vendor = PCI_VENDOR_ID_TITAN,
753 .device = PCI_DEVICE_ID_TITAN_800L,
754 .subvendor = PCI_ANY_ID,
755 .subdevice = PCI_ANY_ID,
756 .setup = titan_400l_800l_setup,
757 },
758 /*
759 * Timedia cards
760 */
761 {
762 .vendor = PCI_VENDOR_ID_TIMEDIA,
763 .device = PCI_DEVICE_ID_TIMEDIA_1889,
764 .subvendor = PCI_VENDOR_ID_TIMEDIA,
765 .subdevice = PCI_ANY_ID,
766 .init = pci_timedia_init,
767 .setup = pci_timedia_setup,
768 },
769 {
770 .vendor = PCI_VENDOR_ID_TIMEDIA,
771 .device = PCI_ANY_ID,
772 .subvendor = PCI_ANY_ID,
773 .subdevice = PCI_ANY_ID,
774 .setup = pci_timedia_setup,
775 },
776 /*
777 * Xircom cards
778 */
779 {
780 .vendor = PCI_VENDOR_ID_XIRCOM,
781 .device = PCI_DEVICE_ID_XIRCOM_X3201_MDM,
782 .subvendor = PCI_ANY_ID,
783 .subdevice = PCI_ANY_ID,
784 .init = pci_xircom_init,
785 .setup = pci_default_setup,
786 },
787 /*
788 * Netmos cards
789 */
790 {
791 .vendor = PCI_VENDOR_ID_NETMOS,
792 .device = PCI_ANY_ID,
793 .subvendor = PCI_ANY_ID,
794 .subdevice = PCI_ANY_ID,
795 .init = pci_netmos_init,
796 .setup = pci_default_setup,
797 },
798 /*
799 * Default "match everything" terminator entry
800 */
801 {
802 .vendor = PCI_ANY_ID,
803 .device = PCI_ANY_ID,
804 .subvendor = PCI_ANY_ID,
805 .subdevice = PCI_ANY_ID,
806 .setup = pci_default_setup,
807 }
808 };
809
810 static inline int quirk_id_matches(u32 quirk_id, u32 dev_id)
811 {
812 return quirk_id == PCI_ANY_ID || quirk_id == dev_id;
813 }
814
815 static struct pci_serial_quirk *find_quirk(struct pci_dev *dev)
816 {
817 struct pci_serial_quirk *quirk;
818
819 for (quirk = pci_serial_quirks; ; quirk++)
820 if (quirk_id_matches(quirk->vendor, dev->vendor) &&
821 quirk_id_matches(quirk->device, dev->device) &&
822 quirk_id_matches(quirk->subvendor, dev->subsystem_vendor) &&
823 quirk_id_matches(quirk->subdevice, dev->subsystem_device))
824 break;
825 return quirk;
826 }
827
828 static _INLINE_ int
829 get_pci_irq(struct pci_dev *dev, struct pciserial_board *board)
830 {
831 if (board->flags & FL_NOIRQ)
832 return 0;
833 else
834 return dev->irq;
835 }
836
837 /*
838 * This is the configuration table for all of the PCI serial boards
839 * which we support. It is directly indexed by the pci_board_num_t enum
840 * value, which is encoded in the pci_device_id PCI probe table's
841 * driver_data member.
842 *
843 * The makeup of these names are:
844 * pbn_bn{_bt}_n_baud
845 *
846 * bn = PCI BAR number
847 * bt = Index using PCI BARs
848 * n = number of serial ports
849 * baud = baud rate
850 *
851 * This table is sorted by (in order): baud, bt, bn, n.
852 *
853 * Please note: in theory if n = 1, _bt infix should make no difference.
854 * ie, pbn_b0_1_115200 is the same as pbn_b0_bt_1_115200
855 */
856 enum pci_board_num_t {
857 pbn_default = 0,
858
859 pbn_b0_1_115200,
860 pbn_b0_2_115200,
861 pbn_b0_4_115200,
862 pbn_b0_5_115200,
863
864 pbn_b0_1_921600,
865 pbn_b0_2_921600,
866 pbn_b0_4_921600,
867
868 pbn_b0_2_1130000,
869
870 pbn_b0_4_1152000,
871
872 pbn_b0_bt_1_115200,
873 pbn_b0_bt_2_115200,
874 pbn_b0_bt_8_115200,
875
876 pbn_b0_bt_1_460800,
877 pbn_b0_bt_2_460800,
878 pbn_b0_bt_4_460800,
879
880 pbn_b0_bt_1_921600,
881 pbn_b0_bt_2_921600,
882 pbn_b0_bt_4_921600,
883 pbn_b0_bt_8_921600,
884
885 pbn_b1_1_115200,
886 pbn_b1_2_115200,
887 pbn_b1_4_115200,
888 pbn_b1_8_115200,
889
890 pbn_b1_1_921600,
891 pbn_b1_2_921600,
892 pbn_b1_4_921600,
893 pbn_b1_8_921600,
894
895 pbn_b1_bt_2_921600,
896
897 pbn_b1_1_1382400,
898 pbn_b1_2_1382400,
899 pbn_b1_4_1382400,
900 pbn_b1_8_1382400,
901
902 pbn_b2_1_115200,
903 pbn_b2_8_115200,
904
905 pbn_b2_1_460800,
906 pbn_b2_4_460800,
907 pbn_b2_8_460800,
908 pbn_b2_16_460800,
909
910 pbn_b2_1_921600,
911 pbn_b2_4_921600,
912 pbn_b2_8_921600,
913
914 pbn_b2_bt_1_115200,
915 pbn_b2_bt_2_115200,
916 pbn_b2_bt_4_115200,
917
918 pbn_b2_bt_2_921600,
919 pbn_b2_bt_4_921600,
920
921 pbn_b3_4_115200,
922 pbn_b3_8_115200,
923
924 /*
925 * Board-specific versions.
926 */
927 pbn_panacom,
928 pbn_panacom2,
929 pbn_panacom4,
930 pbn_plx_romulus,
931 pbn_oxsemi,
932 pbn_intel_i960,
933 pbn_sgi_ioc3,
934 pbn_nec_nile4,
935 pbn_computone_4,
936 pbn_computone_6,
937 pbn_computone_8,
938 pbn_sbsxrsio,
939 pbn_exar_XR17C152,
940 pbn_exar_XR17C154,
941 pbn_exar_XR17C158,
942 };
943
944 /*
945 * uart_offset - the space between channels
946 * reg_shift - describes how the UART registers are mapped
947 * to PCI memory by the card.
948 * For example IER register on SBS, Inc. PMC-OctPro is located at
949 * offset 0x10 from the UART base, while UART_IER is defined as 1
950 * in include/linux/serial_reg.h,
951 * see first lines of serial_in() and serial_out() in 8250.c
952 */
953
954 static struct pciserial_board pci_boards[] __devinitdata = {
955 [pbn_default] = {
956 .flags = FL_BASE0,
957 .num_ports = 1,
958 .base_baud = 115200,
959 .uart_offset = 8,
960 },
961 [pbn_b0_1_115200] = {
962 .flags = FL_BASE0,
963 .num_ports = 1,
964 .base_baud = 115200,
965 .uart_offset = 8,
966 },
967 [pbn_b0_2_115200] = {
968 .flags = FL_BASE0,
969 .num_ports = 2,
970 .base_baud = 115200,
971 .uart_offset = 8,
972 },
973 [pbn_b0_4_115200] = {
974 .flags = FL_BASE0,
975 .num_ports = 4,
976 .base_baud = 115200,
977 .uart_offset = 8,
978 },
979 [pbn_b0_5_115200] = {
980 .flags = FL_BASE0,
981 .num_ports = 5,
982 .base_baud = 115200,
983 .uart_offset = 8,
984 },
985
986 [pbn_b0_1_921600] = {
987 .flags = FL_BASE0,
988 .num_ports = 1,
989 .base_baud = 921600,
990 .uart_offset = 8,
991 },
992 [pbn_b0_2_921600] = {
993 .flags = FL_BASE0,
994 .num_ports = 2,
995 .base_baud = 921600,
996 .uart_offset = 8,
997 },
998 [pbn_b0_4_921600] = {
999 .flags = FL_BASE0,
1000 .num_ports = 4,
1001 .base_baud = 921600,
1002 .uart_offset = 8,
1003 },
1004
1005 [pbn_b0_2_1130000] = {
1006 .flags = FL_BASE0,
1007 .num_ports = 2,
1008 .base_baud = 1130000,
1009 .uart_offset = 8,
1010 },
1011
1012 [pbn_b0_4_1152000] = {
1013 .flags = FL_BASE0,
1014 .num_ports = 4,
1015 .base_baud = 1152000,
1016 .uart_offset = 8,
1017 },
1018
1019 [pbn_b0_bt_1_115200] = {
1020 .flags = FL_BASE0|FL_BASE_BARS,
1021 .num_ports = 1,
1022 .base_baud = 115200,
1023 .uart_offset = 8,
1024 },
1025 [pbn_b0_bt_2_115200] = {
1026 .flags = FL_BASE0|FL_BASE_BARS,
1027 .num_ports = 2,
1028 .base_baud = 115200,
1029 .uart_offset = 8,
1030 },
1031 [pbn_b0_bt_8_115200] = {
1032 .flags = FL_BASE0|FL_BASE_BARS,
1033 .num_ports = 8,
1034 .base_baud = 115200,
1035 .uart_offset = 8,
1036 },
1037
1038 [pbn_b0_bt_1_460800] = {
1039 .flags = FL_BASE0|FL_BASE_BARS,
1040 .num_ports = 1,
1041 .base_baud = 460800,
1042 .uart_offset = 8,
1043 },
1044 [pbn_b0_bt_2_460800] = {
1045 .flags = FL_BASE0|FL_BASE_BARS,
1046 .num_ports = 2,
1047 .base_baud = 460800,
1048 .uart_offset = 8,
1049 },
1050 [pbn_b0_bt_4_460800] = {
1051 .flags = FL_BASE0|FL_BASE_BARS,
1052 .num_ports = 4,
1053 .base_baud = 460800,
1054 .uart_offset = 8,
1055 },
1056
1057 [pbn_b0_bt_1_921600] = {
1058 .flags = FL_BASE0|FL_BASE_BARS,
1059 .num_ports = 1,
1060 .base_baud = 921600,
1061 .uart_offset = 8,
1062 },
1063 [pbn_b0_bt_2_921600] = {
1064 .flags = FL_BASE0|FL_BASE_BARS,
1065 .num_ports = 2,
1066 .base_baud = 921600,
1067 .uart_offset = 8,
1068 },
1069 [pbn_b0_bt_4_921600] = {
1070 .flags = FL_BASE0|FL_BASE_BARS,
1071 .num_ports = 4,
1072 .base_baud = 921600,
1073 .uart_offset = 8,
1074 },
1075 [pbn_b0_bt_8_921600] = {
1076 .flags = FL_BASE0|FL_BASE_BARS,
1077 .num_ports = 8,
1078 .base_baud = 921600,
1079 .uart_offset = 8,
1080 },
1081
1082 [pbn_b1_1_115200] = {
1083 .flags = FL_BASE1,
1084 .num_ports = 1,
1085 .base_baud = 115200,
1086 .uart_offset = 8,
1087 },
1088 [pbn_b1_2_115200] = {
1089 .flags = FL_BASE1,
1090 .num_ports = 2,
1091 .base_baud = 115200,
1092 .uart_offset = 8,
1093 },
1094 [pbn_b1_4_115200] = {
1095 .flags = FL_BASE1,
1096 .num_ports = 4,
1097 .base_baud = 115200,
1098 .uart_offset = 8,
1099 },
1100 [pbn_b1_8_115200] = {
1101 .flags = FL_BASE1,
1102 .num_ports = 8,
1103 .base_baud = 115200,
1104 .uart_offset = 8,
1105 },
1106
1107 [pbn_b1_1_921600] = {
1108 .flags = FL_BASE1,
1109 .num_ports = 1,
1110 .base_baud = 921600,
1111 .uart_offset = 8,
1112 },
1113 [pbn_b1_2_921600] = {
1114 .flags = FL_BASE1,
1115 .num_ports = 2,
1116 .base_baud = 921600,
1117 .uart_offset = 8,
1118 },
1119 [pbn_b1_4_921600] = {
1120 .flags = FL_BASE1,
1121 .num_ports = 4,
1122 .base_baud = 921600,
1123 .uart_offset = 8,
1124 },
1125 [pbn_b1_8_921600] = {
1126 .flags = FL_BASE1,
1127 .num_ports = 8,
1128 .base_baud = 921600,
1129 .uart_offset = 8,
1130 },
1131
1132 [pbn_b1_bt_2_921600] = {
1133 .flags = FL_BASE1|FL_BASE_BARS,
1134 .num_ports = 2,
1135 .base_baud = 921600,
1136 .uart_offset = 8,
1137 },
1138
1139 [pbn_b1_1_1382400] = {
1140 .flags = FL_BASE1,
1141 .num_ports = 1,
1142 .base_baud = 1382400,
1143 .uart_offset = 8,
1144 },
1145 [pbn_b1_2_1382400] = {
1146 .flags = FL_BASE1,
1147 .num_ports = 2,
1148 .base_baud = 1382400,
1149 .uart_offset = 8,
1150 },
1151 [pbn_b1_4_1382400] = {
1152 .flags = FL_BASE1,
1153 .num_ports = 4,
1154 .base_baud = 1382400,
1155 .uart_offset = 8,
1156 },
1157 [pbn_b1_8_1382400] = {
1158 .flags = FL_BASE1,
1159 .num_ports = 8,
1160 .base_baud = 1382400,
1161 .uart_offset = 8,
1162 },
1163
1164 [pbn_b2_1_115200] = {
1165 .flags = FL_BASE2,
1166 .num_ports = 1,
1167 .base_baud = 115200,
1168 .uart_offset = 8,
1169 },
1170 [pbn_b2_8_115200] = {
1171 .flags = FL_BASE2,
1172 .num_ports = 8,
1173 .base_baud = 115200,
1174 .uart_offset = 8,
1175 },
1176
1177 [pbn_b2_1_460800] = {
1178 .flags = FL_BASE2,
1179 .num_ports = 1,
1180 .base_baud = 460800,
1181 .uart_offset = 8,
1182 },
1183 [pbn_b2_4_460800] = {
1184 .flags = FL_BASE2,
1185 .num_ports = 4,
1186 .base_baud = 460800,
1187 .uart_offset = 8,
1188 },
1189 [pbn_b2_8_460800] = {
1190 .flags = FL_BASE2,
1191 .num_ports = 8,
1192 .base_baud = 460800,
1193 .uart_offset = 8,
1194 },
1195 [pbn_b2_16_460800] = {
1196 .flags = FL_BASE2,
1197 .num_ports = 16,
1198 .base_baud = 460800,
1199 .uart_offset = 8,
1200 },
1201
1202 [pbn_b2_1_921600] = {
1203 .flags = FL_BASE2,
1204 .num_ports = 1,
1205 .base_baud = 921600,
1206 .uart_offset = 8,
1207 },
1208 [pbn_b2_4_921600] = {
1209 .flags = FL_BASE2,
1210 .num_ports = 4,
1211 .base_baud = 921600,
1212 .uart_offset = 8,
1213 },
1214 [pbn_b2_8_921600] = {
1215 .flags = FL_BASE2,
1216 .num_ports = 8,
1217 .base_baud = 921600,
1218 .uart_offset = 8,
1219 },
1220
1221 [pbn_b2_bt_1_115200] = {
1222 .flags = FL_BASE2|FL_BASE_BARS,
1223 .num_ports = 1,
1224 .base_baud = 115200,
1225 .uart_offset = 8,
1226 },
1227 [pbn_b2_bt_2_115200] = {
1228 .flags = FL_BASE2|FL_BASE_BARS,
1229 .num_ports = 2,
1230 .base_baud = 115200,
1231 .uart_offset = 8,
1232 },
1233 [pbn_b2_bt_4_115200] = {
1234 .flags = FL_BASE2|FL_BASE_BARS,
1235 .num_ports = 4,
1236 .base_baud = 115200,
1237 .uart_offset = 8,
1238 },
1239
1240 [pbn_b2_bt_2_921600] = {
1241 .flags = FL_BASE2|FL_BASE_BARS,
1242 .num_ports = 2,
1243 .base_baud = 921600,
1244 .uart_offset = 8,
1245 },
1246 [pbn_b2_bt_4_921600] = {
1247 .flags = FL_BASE2|FL_BASE_BARS,
1248 .num_ports = 4,
1249 .base_baud = 921600,
1250 .uart_offset = 8,
1251 },
1252
1253 [pbn_b3_4_115200] = {
1254 .flags = FL_BASE3,
1255 .num_ports = 4,
1256 .base_baud = 115200,
1257 .uart_offset = 8,
1258 },
1259 [pbn_b3_8_115200] = {
1260 .flags = FL_BASE3,
1261 .num_ports = 8,
1262 .base_baud = 115200,
1263 .uart_offset = 8,
1264 },
1265
1266 /*
1267 * Entries following this are board-specific.
1268 */
1269
1270 /*
1271 * Panacom - IOMEM
1272 */
1273 [pbn_panacom] = {
1274 .flags = FL_BASE2,
1275 .num_ports = 2,
1276 .base_baud = 921600,
1277 .uart_offset = 0x400,
1278 .reg_shift = 7,
1279 },
1280 [pbn_panacom2] = {
1281 .flags = FL_BASE2|FL_BASE_BARS,
1282 .num_ports = 2,
1283 .base_baud = 921600,
1284 .uart_offset = 0x400,
1285 .reg_shift = 7,
1286 },
1287 [pbn_panacom4] = {
1288 .flags = FL_BASE2|FL_BASE_BARS,
1289 .num_ports = 4,
1290 .base_baud = 921600,
1291 .uart_offset = 0x400,
1292 .reg_shift = 7,
1293 },
1294
1295 /* I think this entry is broken - the first_offset looks wrong --rmk */
1296 [pbn_plx_romulus] = {
1297 .flags = FL_BASE2,
1298 .num_ports = 4,
1299 .base_baud = 921600,
1300 .uart_offset = 8 << 2,
1301 .reg_shift = 2,
1302 .first_offset = 0x03,
1303 },
1304
1305 /*
1306 * This board uses the size of PCI Base region 0 to
1307 * signal now many ports are available
1308 */
1309 [pbn_oxsemi] = {
1310 .flags = FL_BASE0|FL_REGION_SZ_CAP,
1311 .num_ports = 32,
1312 .base_baud = 115200,
1313 .uart_offset = 8,
1314 },
1315
1316 /*
1317 * EKF addition for i960 Boards form EKF with serial port.
1318 * Max 256 ports.
1319 */
1320 [pbn_intel_i960] = {
1321 .flags = FL_BASE0,
1322 .num_ports = 32,
1323 .base_baud = 921600,
1324 .uart_offset = 8 << 2,
1325 .reg_shift = 2,
1326 .first_offset = 0x10000,
1327 },
1328 [pbn_sgi_ioc3] = {
1329 .flags = FL_BASE0|FL_NOIRQ,
1330 .num_ports = 1,
1331 .base_baud = 458333,
1332 .uart_offset = 8,
1333 .reg_shift = 0,
1334 .first_offset = 0x20178,
1335 },
1336
1337 /*
1338 * NEC Vrc-5074 (Nile 4) builtin UART.
1339 */
1340 [pbn_nec_nile4] = {
1341 .flags = FL_BASE0,
1342 .num_ports = 1,
1343 .base_baud = 520833,
1344 .uart_offset = 8 << 3,
1345 .reg_shift = 3,
1346 .first_offset = 0x300,
1347 },
1348
1349 /*
1350 * Computone - uses IOMEM.
1351 */
1352 [pbn_computone_4] = {
1353 .flags = FL_BASE0,
1354 .num_ports = 4,
1355 .base_baud = 921600,
1356 .uart_offset = 0x40,
1357 .reg_shift = 2,
1358 .first_offset = 0x200,
1359 },
1360 [pbn_computone_6] = {
1361 .flags = FL_BASE0,
1362 .num_ports = 6,
1363 .base_baud = 921600,
1364 .uart_offset = 0x40,
1365 .reg_shift = 2,
1366 .first_offset = 0x200,
1367 },
1368 [pbn_computone_8] = {
1369 .flags = FL_BASE0,
1370 .num_ports = 8,
1371 .base_baud = 921600,
1372 .uart_offset = 0x40,
1373 .reg_shift = 2,
1374 .first_offset = 0x200,
1375 },
1376 [pbn_sbsxrsio] = {
1377 .flags = FL_BASE0,
1378 .num_ports = 8,
1379 .base_baud = 460800,
1380 .uart_offset = 256,
1381 .reg_shift = 4,
1382 },
1383 /*
1384 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
1385 * Only basic 16550A support.
1386 * XR17C15[24] are not tested, but they should work.
1387 */
1388 [pbn_exar_XR17C152] = {
1389 .flags = FL_BASE0,
1390 .num_ports = 2,
1391 .base_baud = 921600,
1392 .uart_offset = 0x200,
1393 },
1394 [pbn_exar_XR17C154] = {
1395 .flags = FL_BASE0,
1396 .num_ports = 4,
1397 .base_baud = 921600,
1398 .uart_offset = 0x200,
1399 },
1400 [pbn_exar_XR17C158] = {
1401 .flags = FL_BASE0,
1402 .num_ports = 8,
1403 .base_baud = 921600,
1404 .uart_offset = 0x200,
1405 },
1406 };
1407
1408 /*
1409 * Given a complete unknown PCI device, try to use some heuristics to
1410 * guess what the configuration might be, based on the pitiful PCI
1411 * serial specs. Returns 0 on success, 1 on failure.
1412 */
1413 static int __devinit
1414 serial_pci_guess_board(struct pci_dev *dev, struct pciserial_board *board)
1415 {
1416 int num_iomem, num_port, first_port = -1, i;
1417
1418 /*
1419 * If it is not a communications device or the programming
1420 * interface is greater than 6, give up.
1421 *
1422 * (Should we try to make guesses for multiport serial devices
1423 * later?)
1424 */
1425 if ((((dev->class >> 8) != PCI_CLASS_COMMUNICATION_SERIAL) &&
1426 ((dev->class >> 8) != PCI_CLASS_COMMUNICATION_MODEM)) ||
1427 (dev->class & 0xff) > 6)
1428 return -ENODEV;
1429
1430 num_iomem = num_port = 0;
1431 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1432 if (pci_resource_flags(dev, i) & IORESOURCE_IO) {
1433 num_port++;
1434 if (first_port == -1)
1435 first_port = i;
1436 }
1437 if (pci_resource_flags(dev, i) & IORESOURCE_MEM)
1438 num_iomem++;
1439 }
1440
1441 /*
1442 * If there is 1 or 0 iomem regions, and exactly one port,
1443 * use it. We guess the number of ports based on the IO
1444 * region size.
1445 */
1446 if (num_iomem <= 1 && num_port == 1) {
1447 board->flags = first_port;
1448 board->num_ports = pci_resource_len(dev, first_port) / 8;
1449 return 0;
1450 }
1451
1452 /*
1453 * Now guess if we've got a board which indexes by BARs.
1454 * Each IO BAR should be 8 bytes, and they should follow
1455 * consecutively.
1456 */
1457 first_port = -1;
1458 num_port = 0;
1459 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1460 if (pci_resource_flags(dev, i) & IORESOURCE_IO &&
1461 pci_resource_len(dev, i) == 8 &&
1462 (first_port == -1 || (first_port + num_port) == i)) {
1463 num_port++;
1464 if (first_port == -1)
1465 first_port = i;
1466 }
1467 }
1468
1469 if (num_port > 1) {
1470 board->flags = first_port | FL_BASE_BARS;
1471 board->num_ports = num_port;
1472 return 0;
1473 }
1474
1475 return -ENODEV;
1476 }
1477
1478 static inline int
1479 serial_pci_matches(struct pciserial_board *board,
1480 struct pciserial_board *guessed)
1481 {
1482 return
1483 board->num_ports == guessed->num_ports &&
1484 board->base_baud == guessed->base_baud &&
1485 board->uart_offset == guessed->uart_offset &&
1486 board->reg_shift == guessed->reg_shift &&
1487 board->first_offset == guessed->first_offset;
1488 }
1489
1490 struct serial_private *
1491 pciserial_init_ports(struct pci_dev *dev, struct pciserial_board *board)
1492 {
1493 struct uart_port serial_port;
1494 struct serial_private *priv;
1495 struct pci_serial_quirk *quirk;
1496 int rc, nr_ports, i;
1497
1498 nr_ports = board->num_ports;
1499
1500 /*
1501 * Find an init and setup quirks.
1502 */
1503 quirk = find_quirk(dev);
1504
1505 /*
1506 * Run the new-style initialization function.
1507 * The initialization function returns:
1508 * <0 - error
1509 * 0 - use board->num_ports
1510 * >0 - number of ports
1511 */
1512 if (quirk->init) {
1513 rc = quirk->init(dev);
1514 if (rc < 0) {
1515 priv = ERR_PTR(rc);
1516 goto err_out;
1517 }
1518 if (rc)
1519 nr_ports = rc;
1520 }
1521
1522 priv = kmalloc(sizeof(struct serial_private) +
1523 sizeof(unsigned int) * nr_ports,
1524 GFP_KERNEL);
1525 if (!priv) {
1526 priv = ERR_PTR(-ENOMEM);
1527 goto err_deinit;
1528 }
1529
1530 memset(priv, 0, sizeof(struct serial_private) +
1531 sizeof(unsigned int) * nr_ports);
1532
1533 priv->dev = dev;
1534 priv->quirk = quirk;
1535
1536 memset(&serial_port, 0, sizeof(struct uart_port));
1537 serial_port.flags = UPF_SKIP_TEST | UPF_BOOT_AUTOCONF | UPF_SHARE_IRQ;
1538 serial_port.uartclk = board->base_baud * 16;
1539 serial_port.irq = get_pci_irq(dev, board);
1540 serial_port.dev = &dev->dev;
1541
1542 for (i = 0; i < nr_ports; i++) {
1543 if (quirk->setup(priv, board, &serial_port, i))
1544 break;
1545
1546 #ifdef SERIAL_DEBUG_PCI
1547 printk("Setup PCI port: port %x, irq %d, type %d\n",
1548 serial_port.iobase, serial_port.irq, serial_port.iotype);
1549 #endif
1550
1551 priv->line[i] = serial8250_register_port(&serial_port);
1552 if (priv->line[i] < 0) {
1553 printk(KERN_WARNING "Couldn't register serial port %s: %d\n", pci_name(dev), priv->line[i]);
1554 break;
1555 }
1556 }
1557
1558 priv->nr = i;
1559
1560 return priv;
1561
1562 err_deinit:
1563 if (quirk->exit)
1564 quirk->exit(dev);
1565 err_out:
1566 return priv;
1567 }
1568 EXPORT_SYMBOL_GPL(pciserial_init_ports);
1569
1570 void pciserial_remove_ports(struct serial_private *priv)
1571 {
1572 struct pci_serial_quirk *quirk;
1573 int i;
1574
1575 for (i = 0; i < priv->nr; i++)
1576 serial8250_unregister_port(priv->line[i]);
1577
1578 for (i = 0; i < PCI_NUM_BAR_RESOURCES; i++) {
1579 if (priv->remapped_bar[i])
1580 iounmap(priv->remapped_bar[i]);
1581 priv->remapped_bar[i] = NULL;
1582 }
1583
1584 /*
1585 * Find the exit quirks.
1586 */
1587 quirk = find_quirk(priv->dev);
1588 if (quirk->exit)
1589 quirk->exit(priv->dev);
1590
1591 kfree(priv);
1592 }
1593 EXPORT_SYMBOL_GPL(pciserial_remove_ports);
1594
1595 void pciserial_suspend_ports(struct serial_private *priv)
1596 {
1597 int i;
1598
1599 for (i = 0; i < priv->nr; i++)
1600 if (priv->line[i] >= 0)
1601 serial8250_suspend_port(priv->line[i]);
1602 }
1603 EXPORT_SYMBOL_GPL(pciserial_suspend_ports);
1604
1605 void pciserial_resume_ports(struct serial_private *priv)
1606 {
1607 int i;
1608
1609 /*
1610 * Ensure that the board is correctly configured.
1611 */
1612 if (priv->quirk->init)
1613 priv->quirk->init(priv->dev);
1614
1615 for (i = 0; i < priv->nr; i++)
1616 if (priv->line[i] >= 0)
1617 serial8250_resume_port(priv->line[i]);
1618 }
1619 EXPORT_SYMBOL_GPL(pciserial_resume_ports);
1620
1621 /*
1622 * Probe one serial board. Unfortunately, there is no rhyme nor reason
1623 * to the arrangement of serial ports on a PCI card.
1624 */
1625 static int __devinit
1626 pciserial_init_one(struct pci_dev *dev, const struct pci_device_id *ent)
1627 {
1628 struct serial_private *priv;
1629 struct pciserial_board *board, tmp;
1630 int rc;
1631
1632 if (ent->driver_data >= ARRAY_SIZE(pci_boards)) {
1633 printk(KERN_ERR "pci_init_one: invalid driver_data: %ld\n",
1634 ent->driver_data);
1635 return -EINVAL;
1636 }
1637
1638 board = &pci_boards[ent->driver_data];
1639
1640 rc = pci_enable_device(dev);
1641 if (rc)
1642 return rc;
1643
1644 if (ent->driver_data == pbn_default) {
1645 /*
1646 * Use a copy of the pci_board entry for this;
1647 * avoid changing entries in the table.
1648 */
1649 memcpy(&tmp, board, sizeof(struct pciserial_board));
1650 board = &tmp;
1651
1652 /*
1653 * We matched one of our class entries. Try to
1654 * determine the parameters of this board.
1655 */
1656 rc = serial_pci_guess_board(dev, board);
1657 if (rc)
1658 goto disable;
1659 } else {
1660 /*
1661 * We matched an explicit entry. If we are able to
1662 * detect this boards settings with our heuristic,
1663 * then we no longer need this entry.
1664 */
1665 memcpy(&tmp, &pci_boards[pbn_default],
1666 sizeof(struct pciserial_board));
1667 rc = serial_pci_guess_board(dev, &tmp);
1668 if (rc == 0 && serial_pci_matches(board, &tmp))
1669 moan_device("Redundant entry in serial pci_table.",
1670 dev);
1671 }
1672
1673 priv = pciserial_init_ports(dev, board);
1674 if (!IS_ERR(priv)) {
1675 pci_set_drvdata(dev, priv);
1676 return 0;
1677 }
1678
1679 rc = PTR_ERR(priv);
1680
1681 disable:
1682 pci_disable_device(dev);
1683 return rc;
1684 }
1685
1686 static void __devexit pciserial_remove_one(struct pci_dev *dev)
1687 {
1688 struct serial_private *priv = pci_get_drvdata(dev);
1689
1690 pci_set_drvdata(dev, NULL);
1691
1692 pciserial_remove_ports(priv);
1693
1694 pci_disable_device(dev);
1695 }
1696
1697 static int pciserial_suspend_one(struct pci_dev *dev, pm_message_t state)
1698 {
1699 struct serial_private *priv = pci_get_drvdata(dev);
1700
1701 if (priv)
1702 pciserial_suspend_ports(priv);
1703
1704 pci_save_state(dev);
1705 pci_set_power_state(dev, pci_choose_state(dev, state));
1706 return 0;
1707 }
1708
1709 static int pciserial_resume_one(struct pci_dev *dev)
1710 {
1711 struct serial_private *priv = pci_get_drvdata(dev);
1712
1713 pci_set_power_state(dev, PCI_D0);
1714 pci_restore_state(dev);
1715
1716 if (priv) {
1717 /*
1718 * The device may have been disabled. Re-enable it.
1719 */
1720 pci_enable_device(dev);
1721
1722 pciserial_resume_ports(priv);
1723 }
1724 return 0;
1725 }
1726
1727 static struct pci_device_id serial_pci_tbl[] = {
1728 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1729 PCI_SUBVENDOR_ID_CONNECT_TECH,
1730 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1731 pbn_b1_8_1382400 },
1732 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1733 PCI_SUBVENDOR_ID_CONNECT_TECH,
1734 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1735 pbn_b1_4_1382400 },
1736 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V960,
1737 PCI_SUBVENDOR_ID_CONNECT_TECH,
1738 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1739 pbn_b1_2_1382400 },
1740 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1741 PCI_SUBVENDOR_ID_CONNECT_TECH,
1742 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_232, 0, 0,
1743 pbn_b1_8_1382400 },
1744 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1745 PCI_SUBVENDOR_ID_CONNECT_TECH,
1746 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_232, 0, 0,
1747 pbn_b1_4_1382400 },
1748 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1749 PCI_SUBVENDOR_ID_CONNECT_TECH,
1750 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_232, 0, 0,
1751 pbn_b1_2_1382400 },
1752 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1753 PCI_SUBVENDOR_ID_CONNECT_TECH,
1754 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485, 0, 0,
1755 pbn_b1_8_921600 },
1756 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1757 PCI_SUBVENDOR_ID_CONNECT_TECH,
1758 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_4_4, 0, 0,
1759 pbn_b1_8_921600 },
1760 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1761 PCI_SUBVENDOR_ID_CONNECT_TECH,
1762 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485, 0, 0,
1763 pbn_b1_4_921600 },
1764 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1765 PCI_SUBVENDOR_ID_CONNECT_TECH,
1766 PCI_SUBDEVICE_ID_CONNECT_TECH_BH4_485_2_2, 0, 0,
1767 pbn_b1_4_921600 },
1768 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1769 PCI_SUBVENDOR_ID_CONNECT_TECH,
1770 PCI_SUBDEVICE_ID_CONNECT_TECH_BH2_485, 0, 0,
1771 pbn_b1_2_921600 },
1772 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1773 PCI_SUBVENDOR_ID_CONNECT_TECH,
1774 PCI_SUBDEVICE_ID_CONNECT_TECH_BH8_485_2_6, 0, 0,
1775 pbn_b1_8_921600 },
1776 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1777 PCI_SUBVENDOR_ID_CONNECT_TECH,
1778 PCI_SUBDEVICE_ID_CONNECT_TECH_BH081101V1, 0, 0,
1779 pbn_b1_8_921600 },
1780 { PCI_VENDOR_ID_V3, PCI_DEVICE_ID_V3_V351,
1781 PCI_SUBVENDOR_ID_CONNECT_TECH,
1782 PCI_SUBDEVICE_ID_CONNECT_TECH_BH041101V1, 0, 0,
1783 pbn_b1_4_921600 },
1784
1785 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_U530,
1786 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1787 pbn_b2_bt_1_115200 },
1788 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM2,
1789 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1790 pbn_b2_bt_2_115200 },
1791 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM422,
1792 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1793 pbn_b2_bt_4_115200 },
1794 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM232,
1795 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1796 pbn_b2_bt_2_115200 },
1797 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM4,
1798 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1799 pbn_b2_bt_4_115200 },
1800 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_COMM8,
1801 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1802 pbn_b2_8_115200 },
1803 { PCI_VENDOR_ID_SEALEVEL, PCI_DEVICE_ID_SEALEVEL_UCOMM8,
1804 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1805 pbn_b2_8_115200 },
1806
1807 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_GTEK_SERIAL2,
1808 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1809 pbn_b2_bt_2_115200 },
1810 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM200,
1811 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1812 pbn_b2_bt_2_921600 },
1813 /*
1814 * VScom SPCOM800, from sl@s.pl
1815 */
1816 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_SPCOM800,
1817 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1818 pbn_b2_8_921600 },
1819 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_1077,
1820 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1821 pbn_b2_4_921600 },
1822 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1823 PCI_SUBVENDOR_ID_KEYSPAN,
1824 PCI_SUBDEVICE_ID_KEYSPAN_SX2, 0, 0,
1825 pbn_panacom },
1826 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_QUADMODEM,
1827 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1828 pbn_panacom4 },
1829 { PCI_VENDOR_ID_PANACOM, PCI_DEVICE_ID_PANACOM_DUALMODEM,
1830 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1831 pbn_panacom2 },
1832 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1833 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1834 PCI_SUBDEVICE_ID_CHASE_PCIFAST4, 0, 0,
1835 pbn_b2_4_460800 },
1836 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1837 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1838 PCI_SUBDEVICE_ID_CHASE_PCIFAST8, 0, 0,
1839 pbn_b2_8_460800 },
1840 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1841 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1842 PCI_SUBDEVICE_ID_CHASE_PCIFAST16, 0, 0,
1843 pbn_b2_16_460800 },
1844 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1845 PCI_SUBVENDOR_ID_CHASE_PCIFAST,
1846 PCI_SUBDEVICE_ID_CHASE_PCIFAST16FMC, 0, 0,
1847 pbn_b2_16_460800 },
1848 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1849 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
1850 PCI_SUBDEVICE_ID_CHASE_PCIRAS4, 0, 0,
1851 pbn_b2_4_460800 },
1852 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1853 PCI_SUBVENDOR_ID_CHASE_PCIRAS,
1854 PCI_SUBDEVICE_ID_CHASE_PCIRAS8, 0, 0,
1855 pbn_b2_8_460800 },
1856 /*
1857 * Megawolf Romulus PCI Serial Card, from Mike Hudson
1858 * (Exoray@isys.ca)
1859 */
1860 { PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_ROMULUS,
1861 0x10b5, 0x106a, 0, 0,
1862 pbn_plx_romulus },
1863 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_QSC100,
1864 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1865 pbn_b1_4_115200 },
1866 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_DSC100,
1867 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1868 pbn_b1_2_115200 },
1869 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100D,
1870 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1871 pbn_b1_8_115200 },
1872 { PCI_VENDOR_ID_QUATECH, PCI_DEVICE_ID_QUATECH_ESC100M,
1873 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1874 pbn_b1_8_115200 },
1875 { PCI_VENDOR_ID_SPECIALIX, PCI_DEVICE_ID_OXSEMI_16PCI954,
1876 PCI_VENDOR_ID_SPECIALIX, PCI_SUBDEVICE_ID_SPECIALIX_SPEED4, 0, 0,
1877 pbn_b0_4_921600 },
1878 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1879 PCI_SUBVENDOR_ID_SIIG, PCI_SUBDEVICE_ID_SIIG_QUARTET_SERIAL, 0, 0,
1880 pbn_b0_4_1152000 },
1881
1882 /*
1883 * The below card is a little controversial since it is the
1884 * subject of a PCI vendor/device ID clash. (See
1885 * www.ussg.iu.edu/hypermail/linux/kernel/0303.1/0516.html).
1886 * For now just used the hex ID 0x950a.
1887 */
1888 { PCI_VENDOR_ID_OXSEMI, 0x950a,
1889 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1890 pbn_b0_2_1130000 },
1891 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI954,
1892 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1893 pbn_b0_4_115200 },
1894 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI952,
1895 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1896 pbn_b0_bt_2_921600 },
1897
1898 /*
1899 * SBS Technologies, Inc. P-Octal and PMC-OCTPRO cards,
1900 * from skokodyn@yahoo.com
1901 */
1902 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1903 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO232, 0, 0,
1904 pbn_sbsxrsio },
1905 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1906 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_OCTPRO422, 0, 0,
1907 pbn_sbsxrsio },
1908 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1909 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL232, 0, 0,
1910 pbn_sbsxrsio },
1911 { PCI_VENDOR_ID_SBSMODULARIO, PCI_DEVICE_ID_OCTPRO,
1912 PCI_SUBVENDOR_ID_SBSMODULARIO, PCI_SUBDEVICE_ID_POCTAL422, 0, 0,
1913 pbn_sbsxrsio },
1914
1915 /*
1916 * Digitan DS560-558, from jimd@esoft.com
1917 */
1918 { PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_ATT_VENUS_MODEM,
1919 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1920 pbn_b1_1_115200 },
1921
1922 /*
1923 * Titan Electronic cards
1924 * The 400L and 800L have a custom setup quirk.
1925 */
1926 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100,
1927 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1928 pbn_b0_1_921600 },
1929 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200,
1930 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1931 pbn_b0_2_921600 },
1932 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400,
1933 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1934 pbn_b0_4_921600 },
1935 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800B,
1936 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1937 pbn_b0_4_921600 },
1938 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_100L,
1939 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1940 pbn_b1_1_921600 },
1941 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_200L,
1942 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1943 pbn_b1_bt_2_921600 },
1944 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_400L,
1945 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1946 pbn_b0_bt_4_921600 },
1947 { PCI_VENDOR_ID_TITAN, PCI_DEVICE_ID_TITAN_800L,
1948 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1949 pbn_b0_bt_8_921600 },
1950
1951 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_550,
1952 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1953 pbn_b2_1_460800 },
1954 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_650,
1955 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1956 pbn_b2_1_460800 },
1957 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_10x_850,
1958 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1959 pbn_b2_1_460800 },
1960 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_550,
1961 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1962 pbn_b2_bt_2_921600 },
1963 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_650,
1964 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1965 pbn_b2_bt_2_921600 },
1966 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_10x_850,
1967 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1968 pbn_b2_bt_2_921600 },
1969 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_550,
1970 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1971 pbn_b2_bt_4_921600 },
1972 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_650,
1973 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1974 pbn_b2_bt_4_921600 },
1975 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_10x_850,
1976 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1977 pbn_b2_bt_4_921600 },
1978 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_550,
1979 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1980 pbn_b0_1_921600 },
1981 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_650,
1982 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1983 pbn_b0_1_921600 },
1984 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_1S_20x_850,
1985 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1986 pbn_b0_1_921600 },
1987 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_550,
1988 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1989 pbn_b0_bt_2_921600 },
1990 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_650,
1991 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1992 pbn_b0_bt_2_921600 },
1993 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_2S_20x_850,
1994 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1995 pbn_b0_bt_2_921600 },
1996 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_550,
1997 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
1998 pbn_b0_bt_4_921600 },
1999 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_650,
2000 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2001 pbn_b0_bt_4_921600 },
2002 { PCI_VENDOR_ID_SIIG, PCI_DEVICE_ID_SIIG_4S_20x_850,
2003 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2004 pbn_b0_bt_4_921600 },
2005
2006 /*
2007 * Computone devices submitted by Doug McNash dmcnash@computone.com
2008 */
2009 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2010 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG4,
2011 0, 0, pbn_computone_4 },
2012 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2013 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG8,
2014 0, 0, pbn_computone_8 },
2015 { PCI_VENDOR_ID_COMPUTONE, PCI_DEVICE_ID_COMPUTONE_PG,
2016 PCI_SUBVENDOR_ID_COMPUTONE, PCI_SUBDEVICE_ID_COMPUTONE_PG6,
2017 0, 0, pbn_computone_6 },
2018
2019 { PCI_VENDOR_ID_OXSEMI, PCI_DEVICE_ID_OXSEMI_16PCI95N,
2020 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2021 pbn_oxsemi },
2022 { PCI_VENDOR_ID_TIMEDIA, PCI_DEVICE_ID_TIMEDIA_1889,
2023 PCI_VENDOR_ID_TIMEDIA, PCI_ANY_ID, 0, 0,
2024 pbn_b0_bt_1_921600 },
2025
2026 /*
2027 * AFAVLAB serial card, from Harald Welte <laforge@gnumonks.org>
2028 */
2029 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P028,
2030 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2031 pbn_b0_bt_8_115200 },
2032 { PCI_VENDOR_ID_AFAVLAB, PCI_DEVICE_ID_AFAVLAB_P030,
2033 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2034 pbn_b0_bt_8_115200 },
2035
2036 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_DSERIAL,
2037 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2038 pbn_b0_bt_2_115200 },
2039 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_A,
2040 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2041 pbn_b0_bt_2_115200 },
2042 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUATRO_B,
2043 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2044 pbn_b0_bt_2_115200 },
2045 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_A,
2046 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2047 pbn_b0_bt_4_460800 },
2048 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_OCTO_B,
2049 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2050 pbn_b0_bt_4_460800 },
2051 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_PLUS,
2052 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2053 pbn_b0_bt_2_460800 },
2054 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_A,
2055 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2056 pbn_b0_bt_2_460800 },
2057 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_QUAD_B,
2058 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2059 pbn_b0_bt_2_460800 },
2060 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_SSERIAL,
2061 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2062 pbn_b0_bt_1_115200 },
2063 { PCI_VENDOR_ID_LAVA, PCI_DEVICE_ID_LAVA_PORT_650,
2064 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2065 pbn_b0_bt_1_460800 },
2066
2067 /*
2068 * Dell Remote Access Card 4 - Tim_T_Murphy@Dell.com
2069 */
2070 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RAC4,
2071 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2072 pbn_b1_1_1382400 },
2073
2074 /*
2075 * Dell Remote Access Card III - Tim_T_Murphy@Dell.com
2076 */
2077 { PCI_VENDOR_ID_DELL, PCI_DEVICE_ID_DELL_RACIII,
2078 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2079 pbn_b1_1_1382400 },
2080
2081 /*
2082 * RAStel 2 port modem, gerg@moreton.com.au
2083 */
2084 { PCI_VENDOR_ID_MORETON, PCI_DEVICE_ID_RASTEL_2PORT,
2085 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2086 pbn_b2_bt_2_115200 },
2087
2088 /*
2089 * EKF addition for i960 Boards form EKF with serial port
2090 */
2091 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80960_RP,
2092 0xE4BF, PCI_ANY_ID, 0, 0,
2093 pbn_intel_i960 },
2094
2095 /*
2096 * Xircom Cardbus/Ethernet combos
2097 */
2098 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_X3201_MDM,
2099 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2100 pbn_b0_1_115200 },
2101 /*
2102 * Xircom RBM56G cardbus modem - Dirk Arnold (temp entry)
2103 */
2104 { PCI_VENDOR_ID_XIRCOM, PCI_DEVICE_ID_XIRCOM_RBM56G,
2105 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2106 pbn_b0_1_115200 },
2107
2108 /*
2109 * Untested PCI modems, sent in from various folks...
2110 */
2111
2112 /*
2113 * Elsa Model 56K PCI Modem, from Andreas Rath <arh@01019freenet.de>
2114 */
2115 { PCI_VENDOR_ID_ROCKWELL, 0x1004,
2116 0x1048, 0x1500, 0, 0,
2117 pbn_b1_1_115200 },
2118
2119 { PCI_VENDOR_ID_SGI, PCI_DEVICE_ID_SGI_IOC3,
2120 0xFF00, 0, 0, 0,
2121 pbn_sgi_ioc3 },
2122
2123 /*
2124 * HP Diva card
2125 */
2126 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2127 PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_RMP3, 0, 0,
2128 pbn_b1_1_115200 },
2129 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA,
2130 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2131 pbn_b0_5_115200 },
2132 { PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_DIVA_AUX,
2133 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2134 pbn_b2_1_115200 },
2135
2136 /*
2137 * NEC Vrc-5074 (Nile 4) builtin UART.
2138 */
2139 { PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_NILE4,
2140 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2141 pbn_nec_nile4 },
2142
2143 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM4,
2144 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2145 pbn_b3_4_115200 },
2146 { PCI_VENDOR_ID_DCI, PCI_DEVICE_ID_DCI_PCCOM8,
2147 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2148 pbn_b3_8_115200 },
2149
2150 /*
2151 * Exar Corp. XR17C15[248] Dual/Quad/Octal UART
2152 */
2153 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C152,
2154 PCI_ANY_ID, PCI_ANY_ID,
2155 0,
2156 0, pbn_exar_XR17C152 },
2157 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C154,
2158 PCI_ANY_ID, PCI_ANY_ID,
2159 0,
2160 0, pbn_exar_XR17C154 },
2161 { PCI_VENDOR_ID_EXAR, PCI_DEVICE_ID_EXAR_XR17C158,
2162 PCI_ANY_ID, PCI_ANY_ID,
2163 0,
2164 0, pbn_exar_XR17C158 },
2165
2166 /*
2167 * Topic TP560 Data/Fax/Voice 56k modem (reported by Evan Clarke)
2168 */
2169 { PCI_VENDOR_ID_TOPIC, PCI_DEVICE_ID_TOPIC_TP560,
2170 PCI_ANY_ID, PCI_ANY_ID, 0, 0,
2171 pbn_b0_1_115200 },
2172
2173 /*
2174 * These entries match devices with class COMMUNICATION_SERIAL,
2175 * COMMUNICATION_MODEM or COMMUNICATION_MULTISERIAL
2176 */
2177 { PCI_ANY_ID, PCI_ANY_ID,
2178 PCI_ANY_ID, PCI_ANY_ID,
2179 PCI_CLASS_COMMUNICATION_SERIAL << 8,
2180 0xffff00, pbn_default },
2181 { PCI_ANY_ID, PCI_ANY_ID,
2182 PCI_ANY_ID, PCI_ANY_ID,
2183 PCI_CLASS_COMMUNICATION_MODEM << 8,
2184 0xffff00, pbn_default },
2185 { PCI_ANY_ID, PCI_ANY_ID,
2186 PCI_ANY_ID, PCI_ANY_ID,
2187 PCI_CLASS_COMMUNICATION_MULTISERIAL << 8,
2188 0xffff00, pbn_default },
2189 { 0, }
2190 };
2191
2192 static struct pci_driver serial_pci_driver = {
2193 .name = "serial",
2194 .probe = pciserial_init_one,
2195 .remove = __devexit_p(pciserial_remove_one),
2196 .suspend = pciserial_suspend_one,
2197 .resume = pciserial_resume_one,
2198 .id_table = serial_pci_tbl,
2199 };
2200
2201 static int __init serial8250_pci_init(void)
2202 {
2203 return pci_register_driver(&serial_pci_driver);
2204 }
2205
2206 static void __exit serial8250_pci_exit(void)
2207 {
2208 pci_unregister_driver(&serial_pci_driver);
2209 }
2210
2211 module_init(serial8250_pci_init);
2212 module_exit(serial8250_pci_exit);
2213
2214 MODULE_LICENSE("GPL");
2215 MODULE_DESCRIPTION("Generic 8250/16x50 PCI serial probe module");
2216 MODULE_DEVICE_TABLE(pci, serial_pci_tbl);
Verdex Pro support