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[PATCH] W1: w1_netlink: New init/fini netlink callbacks.
[linux-2.6/verdex.git] / drivers / serial / sa1100.c
blob1225b14f6e9d4bb7469bb1f6019bf877936f1b54
1 /*
2 * linux/drivers/char/sa1100.c
3 *
4 * Driver for SA11x0 serial ports
5 *
6 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
7 *
8 * Copyright (C) 2000 Deep Blue Solutions Ltd.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
23 *
24 * $Id: sa1100.c,v 1.50 2002/07/29 14:41:04 rmk Exp $
25 *
26 */
27 #include <linux/config.h>
28
29 #if defined(CONFIG_SERIAL_SA1100_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
30 #define SUPPORT_SYSRQ
31 #endif
32
33 #include <linux/module.h>
34 #include <linux/ioport.h>
35 #include <linux/init.h>
36 #include <linux/console.h>
37 #include <linux/sysrq.h>
38 #include <linux/device.h>
39 #include <linux/tty.h>
40 #include <linux/tty_flip.h>
41 #include <linux/serial_core.h>
42 #include <linux/serial.h>
43
44 #include <asm/io.h>
45 #include <asm/irq.h>
46 #include <asm/hardware.h>
47 #include <asm/mach/serial_sa1100.h>
48
49 /* We've been assigned a range on the "Low-density serial ports" major */
50 #define SERIAL_SA1100_MAJOR 204
51 #define MINOR_START 5
52
53 #define NR_PORTS 3
54
55 #define SA1100_ISR_PASS_LIMIT 256
56
57 /*
58 * Convert from ignore_status_mask or read_status_mask to UTSR[01]
59 */
60 #define SM_TO_UTSR0(x) ((x) & 0xff)
61 #define SM_TO_UTSR1(x) ((x) >> 8)
62 #define UTSR0_TO_SM(x) ((x))
63 #define UTSR1_TO_SM(x) ((x) << 8)
64
65 #define UART_GET_UTCR0(sport) __raw_readl((sport)->port.membase + UTCR0)
66 #define UART_GET_UTCR1(sport) __raw_readl((sport)->port.membase + UTCR1)
67 #define UART_GET_UTCR2(sport) __raw_readl((sport)->port.membase + UTCR2)
68 #define UART_GET_UTCR3(sport) __raw_readl((sport)->port.membase + UTCR3)
69 #define UART_GET_UTSR0(sport) __raw_readl((sport)->port.membase + UTSR0)
70 #define UART_GET_UTSR1(sport) __raw_readl((sport)->port.membase + UTSR1)
71 #define UART_GET_CHAR(sport) __raw_readl((sport)->port.membase + UTDR)
72
73 #define UART_PUT_UTCR0(sport,v) __raw_writel((v),(sport)->port.membase + UTCR0)
74 #define UART_PUT_UTCR1(sport,v) __raw_writel((v),(sport)->port.membase + UTCR1)
75 #define UART_PUT_UTCR2(sport,v) __raw_writel((v),(sport)->port.membase + UTCR2)
76 #define UART_PUT_UTCR3(sport,v) __raw_writel((v),(sport)->port.membase + UTCR3)
77 #define UART_PUT_UTSR0(sport,v) __raw_writel((v),(sport)->port.membase + UTSR0)
78 #define UART_PUT_UTSR1(sport,v) __raw_writel((v),(sport)->port.membase + UTSR1)
79 #define UART_PUT_CHAR(sport,v) __raw_writel((v),(sport)->port.membase + UTDR)
80
81 /*
82 * This is the size of our serial port register set.
83 */
84 #define UART_PORT_SIZE 0x24
85
86 /*
87 * This determines how often we check the modem status signals
88 * for any change. They generally aren't connected to an IRQ
89 * so we have to poll them. We also check immediately before
90 * filling the TX fifo incase CTS has been dropped.
91 */
92 #define MCTRL_TIMEOUT (250*HZ/1000)
93
94 struct sa1100_port {
95 struct uart_port port;
96 struct timer_list timer;
97 unsigned int old_status;
98 };
99
100 /*
101 * Handle any change of modem status signal since we were last called.
102 */
103 static void sa1100_mctrl_check(struct sa1100_port *sport)
104 {
105 unsigned int status, changed;
106
107 status = sport->port.ops->get_mctrl(&sport->port);
108 changed = status ^ sport->old_status;
109
110 if (changed == 0)
111 return;
112
113 sport->old_status = status;
114
115 if (changed & TIOCM_RI)
116 sport->port.icount.rng++;
117 if (changed & TIOCM_DSR)
118 sport->port.icount.dsr++;
119 if (changed & TIOCM_CAR)
120 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
121 if (changed & TIOCM_CTS)
122 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
123
124 wake_up_interruptible(&sport->port.info->delta_msr_wait);
125 }
126
127 /*
128 * This is our per-port timeout handler, for checking the
129 * modem status signals.
130 */
131 static void sa1100_timeout(unsigned long data)
132 {
133 struct sa1100_port *sport = (struct sa1100_port *)data;
134 unsigned long flags;
135
136 if (sport->port.info) {
137 spin_lock_irqsave(&sport->port.lock, flags);
138 sa1100_mctrl_check(sport);
139 spin_unlock_irqrestore(&sport->port.lock, flags);
140
141 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
142 }
143 }
144
145 /*
146 * interrupts disabled on entry
147 */
148 static void sa1100_stop_tx(struct uart_port *port)
149 {
150 struct sa1100_port *sport = (struct sa1100_port *)port;
151 u32 utcr3;
152
153 utcr3 = UART_GET_UTCR3(sport);
154 UART_PUT_UTCR3(sport, utcr3 & ~UTCR3_TIE);
155 sport->port.read_status_mask &= ~UTSR0_TO_SM(UTSR0_TFS);
156 }
157
158 /*
159 * interrupts may not be disabled on entry
160 */
161 static void sa1100_start_tx(struct uart_port *port)
162 {
163 struct sa1100_port *sport = (struct sa1100_port *)port;
164 unsigned long flags;
165 u32 utcr3;
166
167 spin_lock_irqsave(&sport->port.lock, flags);
168 utcr3 = UART_GET_UTCR3(sport);
169 sport->port.read_status_mask |= UTSR0_TO_SM(UTSR0_TFS);
170 UART_PUT_UTCR3(sport, utcr3 | UTCR3_TIE);
171 spin_unlock_irqrestore(&sport->port.lock, flags);
172 }
173
174 /*
175 * Interrupts enabled
176 */
177 static void sa1100_stop_rx(struct uart_port *port)
178 {
179 struct sa1100_port *sport = (struct sa1100_port *)port;
180 u32 utcr3;
181
182 utcr3 = UART_GET_UTCR3(sport);
183 UART_PUT_UTCR3(sport, utcr3 & ~UTCR3_RIE);
184 }
185
186 /*
187 * Set the modem control timer to fire immediately.
188 */
189 static void sa1100_enable_ms(struct uart_port *port)
190 {
191 struct sa1100_port *sport = (struct sa1100_port *)port;
192
193 mod_timer(&sport->timer, jiffies);
194 }
195
196 static void
197 sa1100_rx_chars(struct sa1100_port *sport, struct pt_regs *regs)
198 {
199 struct tty_struct *tty = sport->port.info->tty;
200 unsigned int status, ch, flg;
201
202 status = UTSR1_TO_SM(UART_GET_UTSR1(sport)) |
203 UTSR0_TO_SM(UART_GET_UTSR0(sport));
204 while (status & UTSR1_TO_SM(UTSR1_RNE)) {
205 ch = UART_GET_CHAR(sport);
206
207 if (tty->flip.count >= TTY_FLIPBUF_SIZE)
208 goto ignore_char;
209 sport->port.icount.rx++;
210
211 flg = TTY_NORMAL;
212
213 /*
214 * note that the error handling code is
215 * out of the main execution path
216 */
217 if (status & UTSR1_TO_SM(UTSR1_PRE | UTSR1_FRE | UTSR1_ROR)) {
218 if (status & UTSR1_TO_SM(UTSR1_PRE))
219 sport->port.icount.parity++;
220 else if (status & UTSR1_TO_SM(UTSR1_FRE))
221 sport->port.icount.frame++;
222 if (status & UTSR1_TO_SM(UTSR1_ROR))
223 sport->port.icount.overrun++;
224
225 status &= sport->port.read_status_mask;
226
227 if (status & UTSR1_TO_SM(UTSR1_PRE))
228 flg = TTY_PARITY;
229 else if (status & UTSR1_TO_SM(UTSR1_FRE))
230 flg = TTY_FRAME;
231
232 #ifdef SUPPORT_SYSRQ
233 sport->port.sysrq = 0;
234 #endif
235 }
236
237 if (uart_handle_sysrq_char(&sport->port, ch, regs))
238 goto ignore_char;
239
240 uart_insert_char(&sport->port, status, UTSR1_TO_SM(UTSR1_ROR), ch, flg);
241
242 ignore_char:
243 status = UTSR1_TO_SM(UART_GET_UTSR1(sport)) |
244 UTSR0_TO_SM(UART_GET_UTSR0(sport));
245 }
246 tty_flip_buffer_push(tty);
247 }
248
249 static void sa1100_tx_chars(struct sa1100_port *sport)
250 {
251 struct circ_buf *xmit = &sport->port.info->xmit;
252
253 if (sport->port.x_char) {
254 UART_PUT_CHAR(sport, sport->port.x_char);
255 sport->port.icount.tx++;
256 sport->port.x_char = 0;
257 return;
258 }
259
260 /*
261 * Check the modem control lines before
262 * transmitting anything.
263 */
264 sa1100_mctrl_check(sport);
265
266 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
267 sa1100_stop_tx(&sport->port);
268 return;
269 }
270
271 /*
272 * Tried using FIFO (not checking TNF) for fifo fill:
273 * still had the '4 bytes repeated' problem.
274 */
275 while (UART_GET_UTSR1(sport) & UTSR1_TNF) {
276 UART_PUT_CHAR(sport, xmit->buf[xmit->tail]);
277 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
278 sport->port.icount.tx++;
279 if (uart_circ_empty(xmit))
280 break;
281 }
282
283 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
284 uart_write_wakeup(&sport->port);
285
286 if (uart_circ_empty(xmit))
287 sa1100_stop_tx(&sport->port);
288 }
289
290 static irqreturn_t sa1100_int(int irq, void *dev_id, struct pt_regs *regs)
291 {
292 struct sa1100_port *sport = dev_id;
293 unsigned int status, pass_counter = 0;
294
295 spin_lock(&sport->port.lock);
296 status = UART_GET_UTSR0(sport);
297 status &= SM_TO_UTSR0(sport->port.read_status_mask) | ~UTSR0_TFS;
298 do {
299 if (status & (UTSR0_RFS | UTSR0_RID)) {
300 /* Clear the receiver idle bit, if set */
301 if (status & UTSR0_RID)
302 UART_PUT_UTSR0(sport, UTSR0_RID);
303 sa1100_rx_chars(sport, regs);
304 }
305
306 /* Clear the relevant break bits */
307 if (status & (UTSR0_RBB | UTSR0_REB))
308 UART_PUT_UTSR0(sport, status & (UTSR0_RBB | UTSR0_REB));
309
310 if (status & UTSR0_RBB)
311 sport->port.icount.brk++;
312
313 if (status & UTSR0_REB)
314 uart_handle_break(&sport->port);
315
316 if (status & UTSR0_TFS)
317 sa1100_tx_chars(sport);
318 if (pass_counter++ > SA1100_ISR_PASS_LIMIT)
319 break;
320 status = UART_GET_UTSR0(sport);
321 status &= SM_TO_UTSR0(sport->port.read_status_mask) |
322 ~UTSR0_TFS;
323 } while (status & (UTSR0_TFS | UTSR0_RFS | UTSR0_RID));
324 spin_unlock(&sport->port.lock);
325
326 return IRQ_HANDLED;
327 }
328
329 /*
330 * Return TIOCSER_TEMT when transmitter is not busy.
331 */
332 static unsigned int sa1100_tx_empty(struct uart_port *port)
333 {
334 struct sa1100_port *sport = (struct sa1100_port *)port;
335
336 return UART_GET_UTSR1(sport) & UTSR1_TBY ? 0 : TIOCSER_TEMT;
337 }
338
339 static unsigned int sa1100_get_mctrl(struct uart_port *port)
340 {
341 return TIOCM_CTS | TIOCM_DSR | TIOCM_CAR;
342 }
343
344 static void sa1100_set_mctrl(struct uart_port *port, unsigned int mctrl)
345 {
346 }
347
348 /*
349 * Interrupts always disabled.
350 */
351 static void sa1100_break_ctl(struct uart_port *port, int break_state)
352 {
353 struct sa1100_port *sport = (struct sa1100_port *)port;
354 unsigned long flags;
355 unsigned int utcr3;
356
357 spin_lock_irqsave(&sport->port.lock, flags);
358 utcr3 = UART_GET_UTCR3(sport);
359 if (break_state == -1)
360 utcr3 |= UTCR3_BRK;
361 else
362 utcr3 &= ~UTCR3_BRK;
363 UART_PUT_UTCR3(sport, utcr3);
364 spin_unlock_irqrestore(&sport->port.lock, flags);
365 }
366
367 static int sa1100_startup(struct uart_port *port)
368 {
369 struct sa1100_port *sport = (struct sa1100_port *)port;
370 int retval;
371
372 /*
373 * Allocate the IRQ
374 */
375 retval = request_irq(sport->port.irq, sa1100_int, 0,
376 "sa11x0-uart", sport);
377 if (retval)
378 return retval;
379
380 /*
381 * Finally, clear and enable interrupts
382 */
383 UART_PUT_UTSR0(sport, -1);
384 UART_PUT_UTCR3(sport, UTCR3_RXE | UTCR3_TXE | UTCR3_RIE);
385
386 /*
387 * Enable modem status interrupts
388 */
389 spin_lock_irq(&sport->port.lock);
390 sa1100_enable_ms(&sport->port);
391 spin_unlock_irq(&sport->port.lock);
392
393 return 0;
394 }
395
396 static void sa1100_shutdown(struct uart_port *port)
397 {
398 struct sa1100_port *sport = (struct sa1100_port *)port;
399
400 /*
401 * Stop our timer.
402 */
403 del_timer_sync(&sport->timer);
404
405 /*
406 * Free the interrupt
407 */
408 free_irq(sport->port.irq, sport);
409
410 /*
411 * Disable all interrupts, port and break condition.
412 */
413 UART_PUT_UTCR3(sport, 0);
414 }
415
416 static void
417 sa1100_set_termios(struct uart_port *port, struct termios *termios,
418 struct termios *old)
419 {
420 struct sa1100_port *sport = (struct sa1100_port *)port;
421 unsigned long flags;
422 unsigned int utcr0, old_utcr3, baud, quot;
423 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
424
425 /*
426 * We only support CS7 and CS8.
427 */
428 while ((termios->c_cflag & CSIZE) != CS7 &&
429 (termios->c_cflag & CSIZE) != CS8) {
430 termios->c_cflag &= ~CSIZE;
431 termios->c_cflag |= old_csize;
432 old_csize = CS8;
433 }
434
435 if ((termios->c_cflag & CSIZE) == CS8)
436 utcr0 = UTCR0_DSS;
437 else
438 utcr0 = 0;
439
440 if (termios->c_cflag & CSTOPB)
441 utcr0 |= UTCR0_SBS;
442 if (termios->c_cflag & PARENB) {
443 utcr0 |= UTCR0_PE;
444 if (!(termios->c_cflag & PARODD))
445 utcr0 |= UTCR0_OES;
446 }
447
448 /*
449 * Ask the core to calculate the divisor for us.
450 */
451 baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
452 quot = uart_get_divisor(port, baud);
453
454 spin_lock_irqsave(&sport->port.lock, flags);
455
456 sport->port.read_status_mask &= UTSR0_TO_SM(UTSR0_TFS);
457 sport->port.read_status_mask |= UTSR1_TO_SM(UTSR1_ROR);
458 if (termios->c_iflag & INPCK)
459 sport->port.read_status_mask |=
460 UTSR1_TO_SM(UTSR1_FRE | UTSR1_PRE);
461 if (termios->c_iflag & (BRKINT | PARMRK))
462 sport->port.read_status_mask |=
463 UTSR0_TO_SM(UTSR0_RBB | UTSR0_REB);
464
465 /*
466 * Characters to ignore
467 */
468 sport->port.ignore_status_mask = 0;
469 if (termios->c_iflag & IGNPAR)
470 sport->port.ignore_status_mask |=
471 UTSR1_TO_SM(UTSR1_FRE | UTSR1_PRE);
472 if (termios->c_iflag & IGNBRK) {
473 sport->port.ignore_status_mask |=
474 UTSR0_TO_SM(UTSR0_RBB | UTSR0_REB);
475 /*
476 * If we're ignoring parity and break indicators,
477 * ignore overruns too (for real raw support).
478 */
479 if (termios->c_iflag & IGNPAR)
480 sport->port.ignore_status_mask |=
481 UTSR1_TO_SM(UTSR1_ROR);
482 }
483
484 del_timer_sync(&sport->timer);
485
486 /*
487 * Update the per-port timeout.
488 */
489 uart_update_timeout(port, termios->c_cflag, baud);
490
491 /*
492 * disable interrupts and drain transmitter
493 */
494 old_utcr3 = UART_GET_UTCR3(sport);
495 UART_PUT_UTCR3(sport, old_utcr3 & ~(UTCR3_RIE | UTCR3_TIE));
496
497 while (UART_GET_UTSR1(sport) & UTSR1_TBY)
498 barrier();
499
500 /* then, disable everything */
501 UART_PUT_UTCR3(sport, 0);
502
503 /* set the parity, stop bits and data size */
504 UART_PUT_UTCR0(sport, utcr0);
505
506 /* set the baud rate */
507 quot -= 1;
508 UART_PUT_UTCR1(sport, ((quot & 0xf00) >> 8));
509 UART_PUT_UTCR2(sport, (quot & 0xff));
510
511 UART_PUT_UTSR0(sport, -1);
512
513 UART_PUT_UTCR3(sport, old_utcr3);
514
515 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
516 sa1100_enable_ms(&sport->port);
517
518 spin_unlock_irqrestore(&sport->port.lock, flags);
519 }
520
521 static const char *sa1100_type(struct uart_port *port)
522 {
523 struct sa1100_port *sport = (struct sa1100_port *)port;
524
525 return sport->port.type == PORT_SA1100 ? "SA1100" : NULL;
526 }
527
528 /*
529 * Release the memory region(s) being used by 'port'.
530 */
531 static void sa1100_release_port(struct uart_port *port)
532 {
533 struct sa1100_port *sport = (struct sa1100_port *)port;
534
535 release_mem_region(sport->port.mapbase, UART_PORT_SIZE);
536 }
537
538 /*
539 * Request the memory region(s) being used by 'port'.
540 */
541 static int sa1100_request_port(struct uart_port *port)
542 {
543 struct sa1100_port *sport = (struct sa1100_port *)port;
544
545 return request_mem_region(sport->port.mapbase, UART_PORT_SIZE,
546 "sa11x0-uart") != NULL ? 0 : -EBUSY;
547 }
548
549 /*
550 * Configure/autoconfigure the port.
551 */
552 static void sa1100_config_port(struct uart_port *port, int flags)
553 {
554 struct sa1100_port *sport = (struct sa1100_port *)port;
555
556 if (flags & UART_CONFIG_TYPE &&
557 sa1100_request_port(&sport->port) == 0)
558 sport->port.type = PORT_SA1100;
559 }
560
561 /*
562 * Verify the new serial_struct (for TIOCSSERIAL).
563 * The only change we allow are to the flags and type, and
564 * even then only between PORT_SA1100 and PORT_UNKNOWN
565 */
566 static int
567 sa1100_verify_port(struct uart_port *port, struct serial_struct *ser)
568 {
569 struct sa1100_port *sport = (struct sa1100_port *)port;
570 int ret = 0;
571
572 if (ser->type != PORT_UNKNOWN && ser->type != PORT_SA1100)
573 ret = -EINVAL;
574 if (sport->port.irq != ser->irq)
575 ret = -EINVAL;
576 if (ser->io_type != SERIAL_IO_MEM)
577 ret = -EINVAL;
578 if (sport->port.uartclk / 16 != ser->baud_base)
579 ret = -EINVAL;
580 if ((void *)sport->port.mapbase != ser->iomem_base)
581 ret = -EINVAL;
582 if (sport->port.iobase != ser->port)
583 ret = -EINVAL;
584 if (ser->hub6 != 0)
585 ret = -EINVAL;
586 return ret;
587 }
588
589 static struct uart_ops sa1100_pops = {
590 .tx_empty = sa1100_tx_empty,
591 .set_mctrl = sa1100_set_mctrl,
592 .get_mctrl = sa1100_get_mctrl,
593 .stop_tx = sa1100_stop_tx,
594 .start_tx = sa1100_start_tx,
595 .stop_rx = sa1100_stop_rx,
596 .enable_ms = sa1100_enable_ms,
597 .break_ctl = sa1100_break_ctl,
598 .startup = sa1100_startup,
599 .shutdown = sa1100_shutdown,
600 .set_termios = sa1100_set_termios,
601 .type = sa1100_type,
602 .release_port = sa1100_release_port,
603 .request_port = sa1100_request_port,
604 .config_port = sa1100_config_port,
605 .verify_port = sa1100_verify_port,
606 };
607
608 static struct sa1100_port sa1100_ports[NR_PORTS];
609
610 /*
611 * Setup the SA1100 serial ports. Note that we don't include the IrDA
612 * port here since we have our own SIR/FIR driver (see drivers/net/irda)
613 *
614 * Note also that we support "console=ttySAx" where "x" is either 0 or 1.
615 * Which serial port this ends up being depends on the machine you're
616 * running this kernel on. I'm not convinced that this is a good idea,
617 * but that's the way it traditionally works.
618 *
619 * Note that NanoEngine UART3 becomes UART2, and UART2 is no longer
620 * used here.
621 */
622 static void __init sa1100_init_ports(void)
623 {
624 static int first = 1;
625 int i;
626
627 if (!first)
628 return;
629 first = 0;
630
631 for (i = 0; i < NR_PORTS; i++) {
632 sa1100_ports[i].port.uartclk = 3686400;
633 sa1100_ports[i].port.ops = &sa1100_pops;
634 sa1100_ports[i].port.fifosize = 8;
635 sa1100_ports[i].port.line = i;
636 sa1100_ports[i].port.iotype = SERIAL_IO_MEM;
637 init_timer(&sa1100_ports[i].timer);
638 sa1100_ports[i].timer.function = sa1100_timeout;
639 sa1100_ports[i].timer.data = (unsigned long)&sa1100_ports[i];
640 }
641
642 /*
643 * make transmit lines outputs, so that when the port
644 * is closed, the output is in the MARK state.
645 */
646 PPDR |= PPC_TXD1 | PPC_TXD3;
647 PPSR |= PPC_TXD1 | PPC_TXD3;
648 }
649
650 void __init sa1100_register_uart_fns(struct sa1100_port_fns *fns)
651 {
652 if (fns->get_mctrl)
653 sa1100_pops.get_mctrl = fns->get_mctrl;
654 if (fns->set_mctrl)
655 sa1100_pops.set_mctrl = fns->set_mctrl;
656
657 sa1100_pops.pm = fns->pm;
658 sa1100_pops.set_wake = fns->set_wake;
659 }
660
661 void __init sa1100_register_uart(int idx, int port)
662 {
663 if (idx >= NR_PORTS) {
664 printk(KERN_ERR "%s: bad index number %d\n", __FUNCTION__, idx);
665 return;
666 }
667
668 switch (port) {
669 case 1:
670 sa1100_ports[idx].port.membase = (void __iomem *)&Ser1UTCR0;
671 sa1100_ports[idx].port.mapbase = _Ser1UTCR0;
672 sa1100_ports[idx].port.irq = IRQ_Ser1UART;
673 sa1100_ports[idx].port.flags = ASYNC_BOOT_AUTOCONF;
674 break;
675
676 case 2:
677 sa1100_ports[idx].port.membase = (void __iomem *)&Ser2UTCR0;
678 sa1100_ports[idx].port.mapbase = _Ser2UTCR0;
679 sa1100_ports[idx].port.irq = IRQ_Ser2ICP;
680 sa1100_ports[idx].port.flags = ASYNC_BOOT_AUTOCONF;
681 break;
682
683 case 3:
684 sa1100_ports[idx].port.membase = (void __iomem *)&Ser3UTCR0;
685 sa1100_ports[idx].port.mapbase = _Ser3UTCR0;
686 sa1100_ports[idx].port.irq = IRQ_Ser3UART;
687 sa1100_ports[idx].port.flags = ASYNC_BOOT_AUTOCONF;
688 break;
689
690 default:
691 printk(KERN_ERR "%s: bad port number %d\n", __FUNCTION__, port);
692 }
693 }
694
695
696 #ifdef CONFIG_SERIAL_SA1100_CONSOLE
697
698 /*
699 * Interrupts are disabled on entering
700 */
701 static void
702 sa1100_console_write(struct console *co, const char *s, unsigned int count)
703 {
704 struct sa1100_port *sport = &sa1100_ports[co->index];
705 unsigned int old_utcr3, status, i;
706
707 /*
708 * First, save UTCR3 and then disable interrupts
709 */
710 old_utcr3 = UART_GET_UTCR3(sport);
711 UART_PUT_UTCR3(sport, (old_utcr3 & ~(UTCR3_RIE | UTCR3_TIE)) |
712 UTCR3_TXE);
713
714 /*
715 * Now, do each character
716 */
717 for (i = 0; i < count; i++) {
718 do {
719 status = UART_GET_UTSR1(sport);
720 } while (!(status & UTSR1_TNF));
721 UART_PUT_CHAR(sport, s[i]);
722 if (s[i] == '\n') {
723 do {
724 status = UART_GET_UTSR1(sport);
725 } while (!(status & UTSR1_TNF));
726 UART_PUT_CHAR(sport, '\r');
727 }
728 }
729
730 /*
731 * Finally, wait for transmitter to become empty
732 * and restore UTCR3
733 */
734 do {
735 status = UART_GET_UTSR1(sport);
736 } while (status & UTSR1_TBY);
737 UART_PUT_UTCR3(sport, old_utcr3);
738 }
739
740 /*
741 * If the port was already initialised (eg, by a boot loader),
742 * try to determine the current setup.
743 */
744 static void __init
745 sa1100_console_get_options(struct sa1100_port *sport, int *baud,
746 int *parity, int *bits)
747 {
748 unsigned int utcr3;
749
750 utcr3 = UART_GET_UTCR3(sport) & (UTCR3_RXE | UTCR3_TXE);
751 if (utcr3 == (UTCR3_RXE | UTCR3_TXE)) {
752 /* ok, the port was enabled */
753 unsigned int utcr0, quot;
754
755 utcr0 = UART_GET_UTCR0(sport);
756
757 *parity = 'n';
758 if (utcr0 & UTCR0_PE) {
759 if (utcr0 & UTCR0_OES)
760 *parity = 'e';
761 else
762 *parity = 'o';
763 }
764
765 if (utcr0 & UTCR0_DSS)
766 *bits = 8;
767 else
768 *bits = 7;
769
770 quot = UART_GET_UTCR2(sport) | UART_GET_UTCR1(sport) << 8;
771 quot &= 0xfff;
772 *baud = sport->port.uartclk / (16 * (quot + 1));
773 }
774 }
775
776 static int __init
777 sa1100_console_setup(struct console *co, char *options)
778 {
779 struct sa1100_port *sport;
780 int baud = 9600;
781 int bits = 8;
782 int parity = 'n';
783 int flow = 'n';
784
785 /*
786 * Check whether an invalid uart number has been specified, and
787 * if so, search for the first available port that does have
788 * console support.
789 */
790 if (co->index == -1 || co->index >= NR_PORTS)
791 co->index = 0;
792 sport = &sa1100_ports[co->index];
793
794 if (options)
795 uart_parse_options(options, &baud, &parity, &bits, &flow);
796 else
797 sa1100_console_get_options(sport, &baud, &parity, &bits);
798
799 return uart_set_options(&sport->port, co, baud, parity, bits, flow);
800 }
801
802 extern struct uart_driver sa1100_reg;
803 static struct console sa1100_console = {
804 .name = "ttySA",
805 .write = sa1100_console_write,
806 .device = uart_console_device,
807 .setup = sa1100_console_setup,
808 .flags = CON_PRINTBUFFER,
809 .index = -1,
810 .data = &sa1100_reg,
811 };
812
813 static int __init sa1100_rs_console_init(void)
814 {
815 sa1100_init_ports();
816 register_console(&sa1100_console);
817 return 0;
818 }
819 console_initcall(sa1100_rs_console_init);
820
821 #define SA1100_CONSOLE &sa1100_console
822 #else
823 #define SA1100_CONSOLE NULL
824 #endif
825
826 static struct uart_driver sa1100_reg = {
827 .owner = THIS_MODULE,
828 .driver_name = "ttySA",
829 .dev_name = "ttySA",
830 .devfs_name = "ttySA",
831 .major = SERIAL_SA1100_MAJOR,
832 .minor = MINOR_START,
833 .nr = NR_PORTS,
834 .cons = SA1100_CONSOLE,
835 };
836
837 static int sa1100_serial_suspend(struct device *_dev, pm_message_t state, u32 level)
838 {
839 struct sa1100_port *sport = dev_get_drvdata(_dev);
840
841 if (sport && level == SUSPEND_DISABLE)
842 uart_suspend_port(&sa1100_reg, &sport->port);
843
844 return 0;
845 }
846
847 static int sa1100_serial_resume(struct device *_dev, u32 level)
848 {
849 struct sa1100_port *sport = dev_get_drvdata(_dev);
850
851 if (sport && level == RESUME_ENABLE)
852 uart_resume_port(&sa1100_reg, &sport->port);
853
854 return 0;
855 }
856
857 static int sa1100_serial_probe(struct device *_dev)
858 {
859 struct platform_device *dev = to_platform_device(_dev);
860 struct resource *res = dev->resource;
861 int i;
862
863 for (i = 0; i < dev->num_resources; i++, res++)
864 if (res->flags & IORESOURCE_MEM)
865 break;
866
867 if (i < dev->num_resources) {
868 for (i = 0; i < NR_PORTS; i++) {
869 if (sa1100_ports[i].port.mapbase != res->start)
870 continue;
871
872 sa1100_ports[i].port.dev = _dev;
873 uart_add_one_port(&sa1100_reg, &sa1100_ports[i].port);
874 dev_set_drvdata(_dev, &sa1100_ports[i]);
875 break;
876 }
877 }
878
879 return 0;
880 }
881
882 static int sa1100_serial_remove(struct device *_dev)
883 {
884 struct sa1100_port *sport = dev_get_drvdata(_dev);
885
886 dev_set_drvdata(_dev, NULL);
887
888 if (sport)
889 uart_remove_one_port(&sa1100_reg, &sport->port);
890
891 return 0;
892 }
893
894 static struct device_driver sa11x0_serial_driver = {
895 .name = "sa11x0-uart",
896 .bus = &platform_bus_type,
897 .probe = sa1100_serial_probe,
898 .remove = sa1100_serial_remove,
899 .suspend = sa1100_serial_suspend,
900 .resume = sa1100_serial_resume,
901 };
902
903 static int __init sa1100_serial_init(void)
904 {
905 int ret;
906
907 printk(KERN_INFO "Serial: SA11x0 driver $Revision: 1.50 $\n");
908
909 sa1100_init_ports();
910
911 ret = uart_register_driver(&sa1100_reg);
912 if (ret == 0) {
913 ret = driver_register(&sa11x0_serial_driver);
914 if (ret)
915 uart_unregister_driver(&sa1100_reg);
916 }
917 return ret;
918 }
919
920 static void __exit sa1100_serial_exit(void)
921 {
922 driver_unregister(&sa11x0_serial_driver);
923 uart_unregister_driver(&sa1100_reg);
924 }
925
926 module_init(sa1100_serial_init);
927 module_exit(sa1100_serial_exit);
928
929 MODULE_AUTHOR("Deep Blue Solutions Ltd");
930 MODULE_DESCRIPTION("SA1100 generic serial port driver $Revision: 1.50 $");
931 MODULE_LICENSE("GPL");
932 MODULE_ALIAS_CHARDEV_MAJOR(SERIAL_SA1100_MAJOR);
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