drivers/video/chipsfb.c

   1 /*
   2  *  drivers/video/chipsfb.c -- frame buffer device for
   3  *  Chips & Technologies 65550 chip.
   4  *
   5  *  Copyright (C) 1998-2002 Paul Mackerras
   6  *
   7  *  This file is derived from the Powermac "chips" driver:
   8  *  Copyright (C) 1997 Fabio Riccardi.
   9  *  And from the frame buffer device for Open Firmware-initialized devices:
  10  *  Copyright (C) 1997 Geert Uytterhoeven.
  11  *
  12  *  This file is subject to the terms and conditions of the GNU General Public
  13  *  License. See the file COPYING in the main directory of this archive for
  14  *  more details.
  15  */
  16
  17 #include <linux/config.h>
  18 #include <linux/module.h>
  19 #include <linux/kernel.h>
  20 #include <linux/errno.h>
  21 #include <linux/string.h>
  22 #include <linux/mm.h>
  23 #include <linux/tty.h>
  24 #include <linux/slab.h>
  25 #include <linux/vmalloc.h>
  26 #include <linux/delay.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/fb.h>
  29 #include <linux/init.h>
  30 #include <linux/pci.h>
  31 #include <linux/console.h>
  32 #include <asm/io.h>
  33
  34 #ifdef CONFIG_PMAC_BACKLIGHT
  35 #include <asm/backlight.h>
  36 #endif
  37
  38 /*
  39  * Since we access the display with inb/outb to fixed port numbers,
  40  * we can only handle one 6555x chip.  -- paulus
  41  */
  42 #define write_ind(num, val, ap, dp)     do { \
  43         outb((num), (ap)); outb((val), (dp)); \
  44 } while (0)
  45 #define read_ind(num, var, ap, dp)      do { \
  46         outb((num), (ap)); var = inb((dp)); \
  47 } while (0)
  48
  49 /* extension registers */
  50 #define write_xr(num, val)      write_ind(num, val, 0x3d6, 0x3d7)
  51 #define read_xr(num, var)       read_ind(num, var, 0x3d6, 0x3d7)
  52 /* flat panel registers */
  53 #define write_fr(num, val)      write_ind(num, val, 0x3d0, 0x3d1)
  54 #define read_fr(num, var)       read_ind(num, var, 0x3d0, 0x3d1)
  55 /* CRTC registers */
  56 #define write_cr(num, val)      write_ind(num, val, 0x3d4, 0x3d5)
  57 #define read_cr(num, var)       read_ind(num, var, 0x3d4, 0x3d5)
  58 /* graphics registers */
  59 #define write_gr(num, val)      write_ind(num, val, 0x3ce, 0x3cf)
  60 #define read_gr(num, var)       read_ind(num, var, 0x3ce, 0x3cf)
  61 /* sequencer registers */
  62 #define write_sr(num, val)      write_ind(num, val, 0x3c4, 0x3c5)
  63 #define read_sr(num, var)       read_ind(num, var, 0x3c4, 0x3c5)
  64 /* attribute registers - slightly strange */
  65 #define write_ar(num, val)      do { \
  66         inb(0x3da); write_ind(num, val, 0x3c0, 0x3c0); \
  67 } while (0)
  68 #define read_ar(num, var)       do { \
  69         inb(0x3da); read_ind(num, var, 0x3c0, 0x3c1); \
  70 } while (0)
  71
  72 /*
  73  * Exported functions
  74  */
  75 int chips_init(void);
  76
  77 static int chipsfb_pci_init(struct pci_dev *dp, const struct pci_device_id *);
  78 static int chipsfb_check_var(struct fb_var_screeninfo *var,
  79                              struct fb_info *info);
  80 static int chipsfb_set_par(struct fb_info *info);
  81 static int chipsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
  82                              u_int transp, struct fb_info *info);
  83 static int chipsfb_blank(int blank, struct fb_info *info);
  84
  85 static struct fb_ops chipsfb_ops = {
  86         .owner          = THIS_MODULE,
  87         .fb_check_var   = chipsfb_check_var,
  88         .fb_set_par     = chipsfb_set_par,
  89         .fb_setcolreg   = chipsfb_setcolreg,
  90         .fb_blank       = chipsfb_blank,
  91         .fb_fillrect    = cfb_fillrect,
  92         .fb_copyarea    = cfb_copyarea,
  93         .fb_imageblit   = cfb_imageblit,
  94         .fb_cursor      = soft_cursor,
  95 };
  96
  97 static int chipsfb_check_var(struct fb_var_screeninfo *var,
  98                              struct fb_info *info)
  99 {
 100         if (var->xres > 800 || var->yres > 600
 101             || var->xres_virtual > 800 || var->yres_virtual > 600
 102             || (var->bits_per_pixel != 8 && var->bits_per_pixel != 16)
 103             || var->nonstd
 104             || (var->vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
 105                 return -EINVAL;
 106
 107         var->xres = var->xres_virtual = 800;
 108         var->yres = var->yres_virtual = 600;
 109
 110         return 0;
 111 }
 112
 113 static int chipsfb_set_par(struct fb_info *info)
 114 {
 115         if (info->var.bits_per_pixel == 16) {
 116                 write_cr(0x13, 200);            // Set line length (doublewords)
 117                 write_xr(0x81, 0x14);           // 15 bit (555) color mode
 118                 write_xr(0x82, 0x00);           // Disable palettes
 119                 write_xr(0x20, 0x10);           // 16 bit blitter mode
 120
 121                 info->fix.line_length = 800*2;
 122                 info->fix.visual = FB_VISUAL_TRUECOLOR;
 123
 124                 info->var.red.offset = 10;
 125                 info->var.green.offset = 5;
 126                 info->var.blue.offset = 0;
 127                 info->var.red.length = info->var.green.length =
 128                         info->var.blue.length = 5;
 129
 130         } else {
 131                 /* p->var.bits_per_pixel == 8 */
 132                 write_cr(0x13, 100);            // Set line length (doublewords)
 133                 write_xr(0x81, 0x12);           // 8 bit color mode
 134                 write_xr(0x82, 0x08);           // Graphics gamma enable
 135                 write_xr(0x20, 0x00);           // 8 bit blitter mode
 136
 137                 info->fix.line_length = 800;
 138                 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
 139
 140                 info->var.red.offset = info->var.green.offset =
 141                         info->var.blue.offset = 0;
 142                 info->var.red.length = info->var.green.length =
 143                         info->var.blue.length = 8;
 144
 145         }
 146         return 0;
 147 }
 148
 149 static int chipsfb_blank(int blank, struct fb_info *info)
 150 {
 151 #ifdef CONFIG_PMAC_BACKLIGHT
 152         // used to disable backlight only for blank > 1, but it seems
 153         // useful at blank = 1 too (saves battery, extends backlight life)
 154         set_backlight_enable(!blank);
 155 #endif /* CONFIG_PMAC_BACKLIGHT */
 156
 157         return 1;       /* get fb_blank to set the colormap to all black */
 158 }
 159
 160 static int chipsfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
 161                              u_int transp, struct fb_info *info)
 162 {
 163         if (regno > 255)
 164                 return 1;
 165         red >>= 8;
 166         green >>= 8;
 167         blue >>= 8;
 168         outb(regno, 0x3c8);
 169         udelay(1);
 170         outb(red, 0x3c9);
 171         outb(green, 0x3c9);
 172         outb(blue, 0x3c9);
 173
 174         return 0;
 175 }
 176
 177 struct chips_init_reg {
 178         unsigned char addr;
 179         unsigned char data;
 180 };
 181
 182 #define N_ELTS(x)       (sizeof(x) / sizeof(x[0]))
 183
 184 static struct chips_init_reg chips_init_sr[] = {
 185         { 0x00, 0x03 },
 186         { 0x01, 0x01 },
 187         { 0x02, 0x0f },
 188         { 0x04, 0x0e }
 189 };
 190
 191 static struct chips_init_reg chips_init_gr[] = {
 192         { 0x05, 0x00 },
 193         { 0x06, 0x0d },
 194         { 0x08, 0xff }
 195 };
 196
 197 static struct chips_init_reg chips_init_ar[] = {
 198         { 0x10, 0x01 },
 199         { 0x12, 0x0f },
 200         { 0x13, 0x00 }
 201 };
 202
 203 static struct chips_init_reg chips_init_cr[] = {
 204         { 0x00, 0x7f },
 205         { 0x01, 0x63 },
 206         { 0x02, 0x63 },
 207         { 0x03, 0x83 },
 208         { 0x04, 0x66 },
 209         { 0x05, 0x10 },
 210         { 0x06, 0x72 },
 211         { 0x07, 0x3e },
 212         { 0x08, 0x00 },
 213         { 0x09, 0x40 },
 214         { 0x0c, 0x00 },
 215         { 0x0d, 0x00 },
 216         { 0x10, 0x59 },
 217         { 0x11, 0x0d },
 218         { 0x12, 0x57 },
 219         { 0x13, 0x64 },
 220         { 0x14, 0x00 },
 221         { 0x15, 0x57 },
 222         { 0x16, 0x73 },
 223         { 0x17, 0xe3 },
 224         { 0x18, 0xff },
 225         { 0x30, 0x02 },
 226         { 0x31, 0x02 },
 227         { 0x32, 0x02 },
 228         { 0x33, 0x02 },
 229         { 0x40, 0x00 },
 230         { 0x41, 0x00 },
 231         { 0x40, 0x80 }
 232 };
 233
 234 static struct chips_init_reg chips_init_fr[] = {
 235         { 0x01, 0x02 },
 236         { 0x03, 0x08 },
 237         { 0x04, 0x81 },
 238         { 0x05, 0x21 },
 239         { 0x08, 0x0c },
 240         { 0x0a, 0x74 },
 241         { 0x0b, 0x11 },
 242         { 0x10, 0x0c },
 243         { 0x11, 0xe0 },
 244         /* { 0x12, 0x40 }, -- 3400 needs 40, 2400 needs 48, no way to tell */
 245         { 0x20, 0x63 },
 246         { 0x21, 0x68 },
 247         { 0x22, 0x19 },
 248         { 0x23, 0x7f },
 249         { 0x24, 0x68 },
 250         { 0x26, 0x00 },
 251         { 0x27, 0x0f },
 252         { 0x30, 0x57 },
 253         { 0x31, 0x58 },
 254         { 0x32, 0x0d },
 255         { 0x33, 0x72 },
 256         { 0x34, 0x02 },
 257         { 0x35, 0x22 },
 258         { 0x36, 0x02 },
 259         { 0x37, 0x00 }
 260 };
 261
 262 static struct chips_init_reg chips_init_xr[] = {
 263         { 0xce, 0x00 },         /* set default memory clock */
 264         { 0xcc, 0x43 },         /* memory clock ratio */
 265         { 0xcd, 0x18 },
 266         { 0xce, 0xa1 },
 267         { 0xc8, 0x84 },
 268         { 0xc9, 0x0a },
 269         { 0xca, 0x00 },
 270         { 0xcb, 0x20 },
 271         { 0xcf, 0x06 },
 272         { 0xd0, 0x0e },
 273         { 0x09, 0x01 },
 274         { 0x0a, 0x02 },
 275         { 0x0b, 0x01 },
 276         { 0x20, 0x00 },
 277         { 0x40, 0x03 },
 278         { 0x41, 0x01 },
 279         { 0x42, 0x00 },
 280         { 0x80, 0x82 },
 281         { 0x81, 0x12 },
 282         { 0x82, 0x08 },
 283         { 0xa0, 0x00 },
 284         { 0xa8, 0x00 }
 285 };
 286
 287 static void __init chips_hw_init(void)
 288 {
 289         int i;
 290
 291         for (i = 0; i < N_ELTS(chips_init_xr); ++i)
 292                 write_xr(chips_init_xr[i].addr, chips_init_xr[i].data);
 293         outb(0x29, 0x3c2); /* set misc output reg */
 294         for (i = 0; i < N_ELTS(chips_init_sr); ++i)
 295                 write_sr(chips_init_sr[i].addr, chips_init_sr[i].data);
 296         for (i = 0; i < N_ELTS(chips_init_gr); ++i)
 297                 write_gr(chips_init_gr[i].addr, chips_init_gr[i].data);
 298         for (i = 0; i < N_ELTS(chips_init_ar); ++i)
 299                 write_ar(chips_init_ar[i].addr, chips_init_ar[i].data);
 300         for (i = 0; i < N_ELTS(chips_init_cr); ++i)
 301                 write_cr(chips_init_cr[i].addr, chips_init_cr[i].data);
 302         for (i = 0; i < N_ELTS(chips_init_fr); ++i)
 303                 write_fr(chips_init_fr[i].addr, chips_init_fr[i].data);
 304 }
 305
 306 static struct fb_fix_screeninfo chipsfb_fix __initdata = {
 307         .id =           "C&T 65550",
 308         .type =         FB_TYPE_PACKED_PIXELS,
 309         .visual =       FB_VISUAL_PSEUDOCOLOR,
 310         .accel =        FB_ACCEL_NONE,
 311         .line_length =  800,
 312
 313 // FIXME: Assumes 1MB frame buffer, but 65550 supports 1MB or 2MB.
 314 // * "3500" PowerBook G3 (the original PB G3) has 2MB.
 315 // * 2400 has 1MB composed of 2 Mitsubishi M5M4V4265CTP DRAM chips.
 316 //   Motherboard actually supports 2MB -- there are two blank locations
 317 //   for a second pair of DRAMs.  (Thanks, Apple!)
 318 // * 3400 has 1MB (I think).  Don't know if it's expandable.
 319 // -- Tim Seufert
 320         .smem_len =     0x100000,       /* 1MB */
 321 };
 322
 323 static struct fb_var_screeninfo chipsfb_var __initdata = {
 324         .xres = 800,
 325         .yres = 600,
 326         .xres_virtual = 800,
 327         .yres_virtual = 600,
 328         .bits_per_pixel = 8,
 329         .red = { .length = 8 },
 330         .green = { .length = 8 },
 331         .blue = { .length = 8 },
 332         .height = -1,
 333         .width = -1,
 334         .vmode = FB_VMODE_NONINTERLACED,
 335         .pixclock = 10000,
 336         .left_margin = 16,
 337         .right_margin = 16,
 338         .upper_margin = 16,
 339         .lower_margin = 16,
 340         .hsync_len = 8,
 341         .vsync_len = 8,
 342 };
 343
 344 static void __init init_chips(struct fb_info *p, unsigned long addr)
 345 {
 346         memset(p->screen_base, 0, 0x100000);
 347
 348         p->fix = chipsfb_fix;
 349         p->fix.smem_start = addr;
 350
 351         p->var = chipsfb_var;
 352
 353         p->fbops = &chipsfb_ops;
 354         p->flags = FBINFO_DEFAULT;
 355
 356         fb_alloc_cmap(&p->cmap, 256, 0);
 357
 358         chips_hw_init();
 359 }
 360
 361 static int __devinit
 362 chipsfb_pci_init(struct pci_dev *dp, const struct pci_device_id *ent)
 363 {
 364         struct fb_info *p;
 365         unsigned long addr, size;
 366         unsigned short cmd;
 367         int rc = -ENODEV;
 368
 369         if (pci_enable_device(dp) < 0) {
 370                 dev_err(&dp->dev, "Cannot enable PCI device\n");
 371                 goto err_out;
 372         }
 373
 374         if ((dp->resource[0].flags & IORESOURCE_MEM) == 0)
 375                 goto err_disable;
 376         addr = pci_resource_start(dp, 0);
 377         size = pci_resource_len(dp, 0);
 378         if (addr == 0)
 379                 goto err_disable;
 380
 381         p = framebuffer_alloc(0, &dp->dev);
 382         if (p == NULL) {
 383                 dev_err(&dp->dev, "Cannot allocate framebuffer structure\n");
 384                 rc = -ENOMEM;
 385                 goto err_disable;
 386         }
 387
 388         if (pci_request_region(dp, 0, "chipsfb") != 0) {
 389                 dev_err(&dp->dev, "Cannot request framebuffer\n");
 390                 rc = -EBUSY;
 391                 goto err_release_fb;
 392         }
 393
 394 #ifdef __BIG_ENDIAN
 395         addr += 0x800000;       // Use big-endian aperture
 396 #endif
 397
 398         /* we should use pci_enable_device here, but,
 399            the device doesn't declare its I/O ports in its BARs
 400            so pci_enable_device won't turn on I/O responses */
 401         pci_read_config_word(dp, PCI_COMMAND, &cmd);
 402         cmd |= 3;       /* enable memory and IO space */
 403         pci_write_config_word(dp, PCI_COMMAND, cmd);
 404
 405 #ifdef CONFIG_PMAC_BACKLIGHT
 406         /* turn on the backlight */
 407         set_backlight_enable(1);
 408 #endif /* CONFIG_PMAC_BACKLIGHT */
 409
 410 #ifdef CONFIG_PPC
 411         p->screen_base = __ioremap(addr, 0x200000, _PAGE_NO_CACHE);
 412 #else
 413         p->screen_base = ioremap(addr, 0x200000);
 414 #endif
 415         if (p->screen_base == NULL) {
 416                 dev_err(&dp->dev, "Cannot map framebuffer\n");
 417                 rc = -ENOMEM;
 418                 goto err_release_pci;
 419         }
 420
 421         pci_set_drvdata(dp, p);
 422         p->device = &dp->dev;
 423
 424         init_chips(p, addr);
 425
 426         if (register_framebuffer(p) < 0) {
 427                 dev_err(&dp->dev,"C&T 65550 framebuffer failed to register\n");
 428                 goto err_unmap;
 429         }
 430
 431         dev_info(&dp->dev,"fb%d: Chips 65550 frame buffer"
 432                  " (%dK RAM detected)\n",
 433                  p->node, p->fix.smem_len / 1024);
 434
 435         return 0;
 436
 437  err_unmap:
 438         iounmap(p->screen_base);
 439  err_release_pci:
 440         pci_release_region(dp, 0);
 441  err_release_fb:
 442         framebuffer_release(p);
 443  err_disable:
 444  err_out:
 445         return rc;
 446 }
 447
 448 static void __devexit chipsfb_remove(struct pci_dev *dp)
 449 {
 450         struct fb_info *p = pci_get_drvdata(dp);
 451
 452         if (p->screen_base == NULL)
 453                 return;
 454         unregister_framebuffer(p);
 455         iounmap(p->screen_base);
 456         p->screen_base = NULL;
 457         pci_release_region(dp, 0);
 458 }
 459
 460 #ifdef CONFIG_PM
 461 static int chipsfb_pci_suspend(struct pci_dev *pdev, pm_message_t state)
 462 {
 463         struct fb_info *p = pci_get_drvdata(pdev);
 464
 465         if (state.event == pdev->dev.power.power_state.event)
 466                 return 0;
 467         if (state.event != PM_SUSPEND_MEM)
 468                 goto done;
 469
 470         acquire_console_sem();
 471         chipsfb_blank(1, p);
 472         fb_set_suspend(p, 1);
 473         release_console_sem();
 474  done:
 475         pdev->dev.power.power_state = state;
 476         return 0;
 477 }
 478
 479 static int chipsfb_pci_resume(struct pci_dev *pdev)
 480 {
 481         struct fb_info *p = pci_get_drvdata(pdev);
 482
 483         acquire_console_sem();
 484         fb_set_suspend(p, 0);
 485         chipsfb_blank(0, p);
 486         release_console_sem();
 487
 488         pdev->dev.power.power_state = PMSG_ON;
 489         return 0;
 490 }
 491 #endif /* CONFIG_PM */
 492
 493
 494 static struct pci_device_id chipsfb_pci_tbl[] = {
 495         { PCI_VENDOR_ID_CT, PCI_DEVICE_ID_CT_65550, PCI_ANY_ID, PCI_ANY_ID },
 496         { 0 }
 497 };
 498
 499 MODULE_DEVICE_TABLE(pci, chipsfb_pci_tbl);
 500
 501 static struct pci_driver chipsfb_driver = {
 502         .name =         "chipsfb",
 503         .id_table =     chipsfb_pci_tbl,
 504         .probe =        chipsfb_pci_init,
 505         .remove =       __devexit_p(chipsfb_remove),
 506 #ifdef CONFIG_PM
 507         .suspend =      chipsfb_pci_suspend,
 508         .resume =       chipsfb_pci_resume,
 509 #endif
 510 };
 511
 512 int __init chips_init(void)
 513 {
 514         if (fb_get_options("chipsfb", NULL))
 515                 return -ENODEV;
 516
 517         return pci_register_driver(&chipsfb_driver);
 518 }
 519
 520 module_init(chips_init);
 521
 522 static void __exit chipsfb_exit(void)
 523 {
 524         pci_unregister_driver(&chipsfb_driver);
 525 }
 526
 527 MODULE_LICENSE("GPL");