[PATCH] W1: w1_netlink: New init/fini netlink callbacks.
[linux-2.6/verdex.git] / drivers / video / intelfb / intelfb.h
blob6680ec9ba69eac232cd4cb950f88aa57171b7a47
1 #ifndef _INTELFB_H
2 #define _INTELFB_H
4 /* $DHD: intelfb/intelfb.h,v 1.40 2003/06/27 15:06:25 dawes Exp $ */
6 #include <linux/agp_backend.h>
7 #include <linux/fb.h>
10 /*** Version/name ***/
11 #define INTELFB_VERSION "0.9.2"
12 #define INTELFB_MODULE_NAME "intelfb"
13 #define SUPPORTED_CHIPSETS "830M/845G/852GM/855GM/865G/915G"
16 /*** Debug/feature defines ***/
18 #ifndef DEBUG
19 #define DEBUG 0
20 #endif
22 #ifndef VERBOSE
23 #define VERBOSE 0
24 #endif
26 #ifndef REGDUMP
27 #define REGDUMP 0
28 #endif
30 #ifndef DETECT_VGA_CLASS_ONLY
31 #define DETECT_VGA_CLASS_ONLY 1
32 #endif
34 #ifndef ALLOCATE_FOR_PANNING
35 #define ALLOCATE_FOR_PANNING 1
36 #endif
38 #ifndef PREFERRED_MODE
39 #define PREFERRED_MODE "1024x768-32@70"
40 #endif
42 /*** hw-related values ***/
44 /* PCI ids for supported devices */
45 #define PCI_DEVICE_ID_INTEL_830M 0x3577
46 #define PCI_DEVICE_ID_INTEL_845G 0x2562
47 #define PCI_DEVICE_ID_INTEL_85XGM 0x3582
48 #define PCI_DEVICE_ID_INTEL_865G 0x2572
49 #define PCI_DEVICE_ID_INTEL_915G 0x2582
51 /* Size of MMIO region */
52 #define INTEL_REG_SIZE 0x80000
54 #define STRIDE_ALIGNMENT 16
56 #define PALETTE_8_ENTRIES 256
59 /*** Macros ***/
61 /* basic arithmetic */
62 #define KB(x) ((x) * 1024)
63 #define MB(x) ((x) * 1024 * 1024)
64 #define BtoKB(x) ((x) / 1024)
65 #define BtoMB(x) ((x) / 1024 / 1024)
67 #define GTT_PAGE_SIZE KB(4)
69 #define ROUND_UP_TO(x, y) (((x) + (y) - 1) / (y) * (y))
70 #define ROUND_DOWN_TO(x, y) ((x) / (y) * (y))
71 #define ROUND_UP_TO_PAGE(x) ROUND_UP_TO((x), GTT_PAGE_SIZE)
72 #define ROUND_DOWN_TO_PAGE(x) ROUND_DOWN_TO((x), GTT_PAGE_SIZE)
74 /* messages */
75 #define PFX INTELFB_MODULE_NAME ": "
77 #define ERR_MSG(fmt, args...) printk(KERN_ERR PFX fmt, ## args)
78 #define WRN_MSG(fmt, args...) printk(KERN_WARNING PFX fmt, ## args)
79 #define NOT_MSG(fmt, args...) printk(KERN_NOTICE PFX fmt, ## args)
80 #define INF_MSG(fmt, args...) printk(KERN_INFO PFX fmt, ## args)
81 #if DEBUG
82 #define DBG_MSG(fmt, args...) printk(KERN_DEBUG PFX fmt, ## args)
83 #else
84 #define DBG_MSG(fmt, args...) while (0) printk(fmt, ## args)
85 #endif
87 /* get commonly used pointers */
88 #define GET_DINFO(info) (info)->par
90 /* misc macros */
91 #define ACCEL(d, i) \
92 ((d)->accel && !(d)->ring_lockup && \
93 ((i)->var.accel_flags & FB_ACCELF_TEXT))
95 /*#define NOACCEL_CHIPSET(d) \
96 ((d)->chipset != INTEL_865G)*/
97 #define NOACCEL_CHIPSET(d) \
98 (0)
100 #define FIXED_MODE(d) ((d)->fixed_mode)
102 /*** Driver paramters ***/
104 #define RINGBUFFER_SIZE KB(64)
105 #define HW_CURSOR_SIZE KB(4)
107 /* Intel agpgart driver */
108 #define AGP_PHYSICAL_MEMORY 2
110 /*** Data Types ***/
112 /* supported chipsets */
113 enum intel_chips {
114 INTEL_830M,
115 INTEL_845G,
116 INTEL_85XGM,
117 INTEL_852GM,
118 INTEL_852GME,
119 INTEL_855GM,
120 INTEL_855GME,
121 INTEL_865G,
122 INTEL_915G
125 struct intelfb_hwstate {
126 u32 vga0_divisor;
127 u32 vga1_divisor;
128 u32 vga_pd;
129 u32 dpll_a;
130 u32 dpll_b;
131 u32 fpa0;
132 u32 fpa1;
133 u32 fpb0;
134 u32 fpb1;
135 u32 palette_a[PALETTE_8_ENTRIES];
136 u32 palette_b[PALETTE_8_ENTRIES];
137 u32 htotal_a;
138 u32 hblank_a;
139 u32 hsync_a;
140 u32 vtotal_a;
141 u32 vblank_a;
142 u32 vsync_a;
143 u32 src_size_a;
144 u32 bclrpat_a;
145 u32 htotal_b;
146 u32 hblank_b;
147 u32 hsync_b;
148 u32 vtotal_b;
149 u32 vblank_b;
150 u32 vsync_b;
151 u32 src_size_b;
152 u32 bclrpat_b;
153 u32 adpa;
154 u32 dvoa;
155 u32 dvob;
156 u32 dvoc;
157 u32 dvoa_srcdim;
158 u32 dvob_srcdim;
159 u32 dvoc_srcdim;
160 u32 lvds;
161 u32 pipe_a_conf;
162 u32 pipe_b_conf;
163 u32 disp_arb;
164 u32 cursor_a_control;
165 u32 cursor_b_control;
166 u32 cursor_a_base;
167 u32 cursor_b_base;
168 u32 cursor_size;
169 u32 disp_a_ctrl;
170 u32 disp_b_ctrl;
171 u32 disp_a_base;
172 u32 disp_b_base;
173 u32 cursor_a_palette[4];
174 u32 cursor_b_palette[4];
175 u32 disp_a_stride;
176 u32 disp_b_stride;
177 u32 vgacntrl;
178 u32 add_id;
179 u32 swf0x[7];
180 u32 swf1x[7];
181 u32 swf3x[3];
182 u32 fence[8];
183 u32 instpm;
184 u32 mem_mode;
185 u32 fw_blc_0;
186 u32 fw_blc_1;
189 struct intelfb_heap_data {
190 u32 physical;
191 u8 __iomem *virtual;
192 u32 offset; // in GATT pages
193 u32 size; // in bytes
196 struct intelfb_info {
197 struct fb_info *info;
198 struct fb_ops *fbops;
199 struct pci_dev *pdev;
201 struct intelfb_hwstate save_state;
203 /* agpgart structs */
204 struct agp_memory *gtt_fb_mem; // use all stolen memory or vram
205 struct agp_memory *gtt_ring_mem; // ring buffer
206 struct agp_memory *gtt_cursor_mem; // hw cursor
208 /* use a gart reserved fb mem */
209 u8 fbmem_gart;
211 /* mtrr support */
212 u32 mtrr_reg;
213 u32 has_mtrr;
215 /* heap data */
216 struct intelfb_heap_data aperture;
217 struct intelfb_heap_data fb;
218 struct intelfb_heap_data ring;
219 struct intelfb_heap_data cursor;
221 /* mmio regs */
222 u32 mmio_base_phys;
223 u8 __iomem *mmio_base;
225 /* fb start offset (in bytes) */
226 u32 fb_start;
228 /* ring buffer */
229 u8 __iomem *ring_head;
230 u32 ring_tail;
231 u32 ring_tail_mask;
232 u32 ring_space;
233 u32 ring_lockup;
235 /* palette */
236 u32 pseudo_palette[17];
237 struct { u8 red, green, blue, pad; } palette[256];
239 /* chip info */
240 int pci_chipset;
241 int chipset;
242 const char *name;
243 int mobile;
245 /* current mode */
246 int bpp, depth;
247 u32 visual;
248 int xres, yres, pitch;
249 int pixclock;
251 /* current pipe */
252 int pipe;
254 /* some flags */
255 int accel;
256 int hwcursor;
257 int fixed_mode;
258 int ring_active;
260 /* hw cursor */
261 int cursor_on;
262 int cursor_blanked;
263 u8 cursor_src[64];
265 /* initial parameters */
266 int initial_vga;
267 struct fb_var_screeninfo initial_var;
268 u32 initial_fb_base;
269 u32 initial_video_ram;
270 u32 initial_pitch;
272 /* driver registered */
273 int registered;
276 /*** function prototypes ***/
278 extern int intelfb_var_to_depth(const struct fb_var_screeninfo *var);
280 #endif /* _INTELFB_H */