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[PATCH] W1: w1_netlink: New init/fini netlink callbacks.
[linux-2.6/verdex.git] / drivers / video / matrox / matroxfb_misc.c
bloba18dd024fc86a9384b67c49391c1685ca75e95f3
1 /*
2 *
3 * Hardware accelerated Matrox Millennium I, II, Mystique, G100, G200 and G400
4 *
5 * (c) 1998-2002 Petr Vandrovec <vandrove@vc.cvut.cz>
6 *
7 * Portions Copyright (c) 2001 Matrox Graphics Inc.
8 *
9 * Version: 1.65 2002/08/14
10 *
11 * MTRR stuff: 1998 Tom Rini <trini@kernel.crashing.org>
12 *
13 * Contributors: "menion?" <menion@mindless.com>
14 * Betatesting, fixes, ideas
15 *
16 * "Kurt Garloff" <garloff@suse.de>
17 * Betatesting, fixes, ideas, videomodes, videomodes timmings
18 *
19 * "Tom Rini" <trini@kernel.crashing.org>
20 * MTRR stuff, PPC cleanups, betatesting, fixes, ideas
21 *
22 * "Bibek Sahu" <scorpio@dodds.net>
23 * Access device through readb|w|l and write b|w|l
24 * Extensive debugging stuff
25 *
26 * "Daniel Haun" <haund@usa.net>
27 * Testing, hardware cursor fixes
28 *
29 * "Scott Wood" <sawst46+@pitt.edu>
30 * Fixes
31 *
32 * "Gerd Knorr" <kraxel@goldbach.isdn.cs.tu-berlin.de>
33 * Betatesting
34 *
35 * "Kelly French" <targon@hazmat.com>
36 * "Fernando Herrera" <fherrera@eurielec.etsit.upm.es>
37 * Betatesting, bug reporting
38 *
39 * "Pablo Bianucci" <pbian@pccp.com.ar>
40 * Fixes, ideas, betatesting
41 *
42 * "Inaky Perez Gonzalez" <inaky@peloncho.fis.ucm.es>
43 * Fixes, enhandcements, ideas, betatesting
44 *
45 * "Ryuichi Oikawa" <roikawa@rr.iiij4u.or.jp>
46 * PPC betatesting, PPC support, backward compatibility
47 *
48 * "Paul Womar" <Paul@pwomar.demon.co.uk>
49 * "Owen Waller" <O.Waller@ee.qub.ac.uk>
50 * PPC betatesting
51 *
52 * "Thomas Pornin" <pornin@bolet.ens.fr>
53 * Alpha betatesting
54 *
55 * "Pieter van Leuven" <pvl@iae.nl>
56 * "Ulf Jaenicke-Roessler" <ujr@physik.phy.tu-dresden.de>
57 * G100 testing
58 *
59 * "H. Peter Arvin" <hpa@transmeta.com>
60 * Ideas
61 *
62 * "Cort Dougan" <cort@cs.nmt.edu>
63 * CHRP fixes and PReP cleanup
64 *
65 * "Mark Vojkovich" <mvojkovi@ucsd.edu>
66 * G400 support
67 *
68 * "David C. Hansen" <haveblue@us.ibm.com>
69 * Fixes
70 *
71 * (following author is not in any relation with this code, but his code
72 * is included in this driver)
73 *
74 * Based on framebuffer driver for VBE 2.0 compliant graphic boards
75 * (c) 1998 Gerd Knorr <kraxel@cs.tu-berlin.de>
76 *
77 * (following author is not in any relation with this code, but his ideas
78 * were used when writting this driver)
79 *
80 * FreeVBE/AF (Matrox), "Shawn Hargreaves" <shawn@talula.demon.co.uk>
81 *
82 */
83
84 /* make checkconfig does not check includes for this... */
85 #include <linux/config.h>
86
87 #include "matroxfb_misc.h"
88 #include <linux/interrupt.h>
89 #include <linux/matroxfb.h>
90
91 void matroxfb_DAC_out(CPMINFO int reg, int val) {
92 DBG_REG(__FUNCTION__)
93 mga_outb(M_RAMDAC_BASE+M_X_INDEX, reg);
94 mga_outb(M_RAMDAC_BASE+M_X_DATAREG, val);
95 }
96
97 int matroxfb_DAC_in(CPMINFO int reg) {
98 DBG_REG(__FUNCTION__)
99 mga_outb(M_RAMDAC_BASE+M_X_INDEX, reg);
100 return mga_inb(M_RAMDAC_BASE+M_X_DATAREG);
101 }
102
103 void matroxfb_var2my(struct fb_var_screeninfo* var, struct my_timming* mt) {
104 unsigned int pixclock = var->pixclock;
105
106 DBG(__FUNCTION__)
107
108 if (!pixclock) pixclock = 10000; /* 10ns = 100MHz */
109 mt->pixclock = 1000000000 / pixclock;
110 if (mt->pixclock < 1) mt->pixclock = 1;
111 mt->mnp = -1;
112 mt->dblscan = var->vmode & FB_VMODE_DOUBLE;
113 mt->interlaced = var->vmode & FB_VMODE_INTERLACED;
114 mt->HDisplay = var->xres;
115 mt->HSyncStart = mt->HDisplay + var->right_margin;
116 mt->HSyncEnd = mt->HSyncStart + var->hsync_len;
117 mt->HTotal = mt->HSyncEnd + var->left_margin;
118 mt->VDisplay = var->yres;
119 mt->VSyncStart = mt->VDisplay + var->lower_margin;
120 mt->VSyncEnd = mt->VSyncStart + var->vsync_len;
121 mt->VTotal = mt->VSyncEnd + var->upper_margin;
122 mt->sync = var->sync;
123 }
124
125 int matroxfb_PLL_calcclock(const struct matrox_pll_features* pll, unsigned int freq, unsigned int fmax,
126 unsigned int* in, unsigned int* feed, unsigned int* post) {
127 unsigned int bestdiff = ~0;
128 unsigned int bestvco = 0;
129 unsigned int fxtal = pll->ref_freq;
130 unsigned int fwant;
131 unsigned int p;
132
133 DBG(__FUNCTION__)
134
135 fwant = freq;
136
137 #ifdef DEBUG
138 printk(KERN_ERR "post_shift_max: %d\n", pll->post_shift_max);
139 printk(KERN_ERR "ref_freq: %d\n", pll->ref_freq);
140 printk(KERN_ERR "freq: %d\n", freq);
141 printk(KERN_ERR "vco_freq_min: %d\n", pll->vco_freq_min);
142 printk(KERN_ERR "in_div_min: %d\n", pll->in_div_min);
143 printk(KERN_ERR "in_div_max: %d\n", pll->in_div_max);
144 printk(KERN_ERR "feed_div_min: %d\n", pll->feed_div_min);
145 printk(KERN_ERR "feed_div_max: %d\n", pll->feed_div_max);
146 printk(KERN_ERR "fmax: %d\n", fmax);
147 #endif
148 for (p = 1; p <= pll->post_shift_max; p++) {
149 if (fwant * 2 > fmax)
150 break;
151 fwant *= 2;
152 }
153 if (fwant < pll->vco_freq_min) fwant = pll->vco_freq_min;
154 if (fwant > fmax) fwant = fmax;
155 for (; p-- > 0; fwant >>= 1, bestdiff >>= 1) {
156 unsigned int m;
157
158 if (fwant < pll->vco_freq_min) break;
159 for (m = pll->in_div_min; m <= pll->in_div_max; m++) {
160 unsigned int diff, fvco;
161 unsigned int n;
162
163 n = (fwant * (m + 1) + (fxtal >> 1)) / fxtal - 1;
164 if (n > pll->feed_div_max)
165 break;
166 if (n < pll->feed_div_min)
167 n = pll->feed_div_min;
168 fvco = (fxtal * (n + 1)) / (m + 1);
169 if (fvco < fwant)
170 diff = fwant - fvco;
171 else
172 diff = fvco - fwant;
173 if (diff < bestdiff) {
174 bestdiff = diff;
175 *post = p;
176 *in = m;
177 *feed = n;
178 bestvco = fvco;
179 }
180 }
181 }
182 dprintk(KERN_ERR "clk: %02X %02X %02X %d %d %d\n", *in, *feed, *post, fxtal, bestvco, fwant);
183 return bestvco;
184 }
185
186 int matroxfb_vgaHWinit(WPMINFO struct my_timming* m) {
187 unsigned int hd, hs, he, hbe, ht;
188 unsigned int vd, vs, ve, vt, lc;
189 unsigned int wd;
190 unsigned int divider;
191 int i;
192 int fwidth;
193 struct matrox_hw_state * const hw = &ACCESS_FBINFO(hw);
194
195 fwidth = 8;
196
197 DBG(__FUNCTION__)
198
199 hw->SEQ[0] = 0x00;
200 hw->SEQ[1] = 0x01; /* or 0x09 */
201 hw->SEQ[2] = 0x0F; /* bitplanes */
202 hw->SEQ[3] = 0x00;
203 hw->SEQ[4] = 0x0E;
204 /* CRTC 0..7, 9, 16..19, 21, 22 are reprogrammed by Matrox Millennium code... Hope that by MGA1064 too */
205 if (m->dblscan) {
206 m->VTotal <<= 1;
207 m->VDisplay <<= 1;
208 m->VSyncStart <<= 1;
209 m->VSyncEnd <<= 1;
210 }
211 if (m->interlaced) {
212 m->VTotal >>= 1;
213 m->VDisplay >>= 1;
214 m->VSyncStart >>= 1;
215 m->VSyncEnd >>= 1;
216 }
217
218 /* GCTL is ignored when not using 0xA0000 aperture */
219 hw->GCTL[0] = 0x00;
220 hw->GCTL[1] = 0x00;
221 hw->GCTL[2] = 0x00;
222 hw->GCTL[3] = 0x00;
223 hw->GCTL[4] = 0x00;
224 hw->GCTL[5] = 0x40;
225 hw->GCTL[6] = 0x05;
226 hw->GCTL[7] = 0x0F;
227 hw->GCTL[8] = 0xFF;
228
229 /* Whole ATTR is ignored in PowerGraphics mode */
230 for (i = 0; i < 16; i++)
231 hw->ATTR[i] = i;
232 hw->ATTR[16] = 0x41;
233 hw->ATTR[17] = 0xFF;
234 hw->ATTR[18] = 0x0F;
235 if (fwidth == 9)
236 hw->ATTR[19] = 0x08;
237 else
238 hw->ATTR[19] = 0x00;
239 hw->ATTR[20] = 0x00;
240
241 hd = m->HDisplay >> 3;
242 hs = m->HSyncStart >> 3;
243 he = m->HSyncEnd >> 3;
244 ht = m->HTotal >> 3;
245 /* standard timmings are in 8pixels, but for interleaved we cannot */
246 /* do it for 4bpp (because of (4bpp >> 1(interleaved))/4 == 0) */
247 /* using 16 or more pixels per unit can save us */
248 divider = ACCESS_FBINFO(curr.final_bppShift);
249 while (divider & 3) {
250 hd >>= 1;
251 hs >>= 1;
252 he >>= 1;
253 ht >>= 1;
254 divider <<= 1;
255 }
256 divider = divider / 4;
257 /* divider can be from 1 to 8 */
258 while (divider > 8) {
259 hd <<= 1;
260 hs <<= 1;
261 he <<= 1;
262 ht <<= 1;
263 divider >>= 1;
264 }
265 hd = hd - 1;
266 hs = hs - 1;
267 he = he - 1;
268 ht = ht - 1;
269 vd = m->VDisplay - 1;
270 vs = m->VSyncStart - 1;
271 ve = m->VSyncEnd - 1;
272 vt = m->VTotal - 2;
273 lc = vd;
274 /* G200 cannot work with (ht & 7) == 6 */
275 if (((ht & 0x07) == 0x06) || ((ht & 0x0F) == 0x04))
276 ht++;
277 hbe = ht;
278 wd = ACCESS_FBINFO(fbcon).var.xres_virtual * ACCESS_FBINFO(curr.final_bppShift) / 64;
279
280 hw->CRTCEXT[0] = 0;
281 hw->CRTCEXT[5] = 0;
282 if (m->interlaced) {
283 hw->CRTCEXT[0] = 0x80;
284 hw->CRTCEXT[5] = (hs + he - ht) >> 1;
285 if (!m->dblscan)
286 wd <<= 1;
287 vt &= ~1;
288 }
289 hw->CRTCEXT[0] |= (wd & 0x300) >> 4;
290 hw->CRTCEXT[1] = (((ht - 4) & 0x100) >> 8) |
291 ((hd & 0x100) >> 7) | /* blanking */
292 ((hs & 0x100) >> 6) | /* sync start */
293 (hbe & 0x040); /* end hor. blanking */
294 /* FIXME: Enable vidrst only on G400, and only if TV-out is used */
295 if (ACCESS_FBINFO(outputs[1]).src == MATROXFB_SRC_CRTC1)
296 hw->CRTCEXT[1] |= 0x88; /* enable horizontal and vertical vidrst */
297 hw->CRTCEXT[2] = ((vt & 0xC00) >> 10) |
298 ((vd & 0x400) >> 8) | /* disp end */
299 ((vd & 0xC00) >> 7) | /* vblanking start */
300 ((vs & 0xC00) >> 5) |
301 ((lc & 0x400) >> 3);
302 hw->CRTCEXT[3] = (divider - 1) | 0x80;
303 hw->CRTCEXT[4] = 0;
304
305 hw->CRTC[0] = ht-4;
306 hw->CRTC[1] = hd;
307 hw->CRTC[2] = hd;
308 hw->CRTC[3] = (hbe & 0x1F) | 0x80;
309 hw->CRTC[4] = hs;
310 hw->CRTC[5] = ((hbe & 0x20) << 2) | (he & 0x1F);
311 hw->CRTC[6] = vt & 0xFF;
312 hw->CRTC[7] = ((vt & 0x100) >> 8) |
313 ((vd & 0x100) >> 7) |
314 ((vs & 0x100) >> 6) |
315 ((vd & 0x100) >> 5) |
316 ((lc & 0x100) >> 4) |
317 ((vt & 0x200) >> 4) |
318 ((vd & 0x200) >> 3) |
319 ((vs & 0x200) >> 2);
320 hw->CRTC[8] = 0x00;
321 hw->CRTC[9] = ((vd & 0x200) >> 4) |
322 ((lc & 0x200) >> 3);
323 if (m->dblscan && !m->interlaced)
324 hw->CRTC[9] |= 0x80;
325 for (i = 10; i < 16; i++)
326 hw->CRTC[i] = 0x00;
327 hw->CRTC[16] = vs /* & 0xFF */;
328 hw->CRTC[17] = (ve & 0x0F) | 0x20;
329 hw->CRTC[18] = vd /* & 0xFF */;
330 hw->CRTC[19] = wd /* & 0xFF */;
331 hw->CRTC[20] = 0x00;
332 hw->CRTC[21] = vd /* & 0xFF */;
333 hw->CRTC[22] = (vt + 1) /* & 0xFF */;
334 hw->CRTC[23] = 0xC3;
335 hw->CRTC[24] = lc;
336 return 0;
337 };
338
339 void matroxfb_vgaHWrestore(WPMINFO2) {
340 int i;
341 struct matrox_hw_state * const hw = &ACCESS_FBINFO(hw);
342 CRITFLAGS
343
344 DBG(__FUNCTION__)
345
346 dprintk(KERN_INFO "MiscOutReg: %02X\n", hw->MiscOutReg);
347 dprintk(KERN_INFO "SEQ regs: ");
348 for (i = 0; i < 5; i++)
349 dprintk("%02X:", hw->SEQ[i]);
350 dprintk("\n");
351 dprintk(KERN_INFO "GDC regs: ");
352 for (i = 0; i < 9; i++)
353 dprintk("%02X:", hw->GCTL[i]);
354 dprintk("\n");
355 dprintk(KERN_INFO "CRTC regs: ");
356 for (i = 0; i < 25; i++)
357 dprintk("%02X:", hw->CRTC[i]);
358 dprintk("\n");
359 dprintk(KERN_INFO "ATTR regs: ");
360 for (i = 0; i < 21; i++)
361 dprintk("%02X:", hw->ATTR[i]);
362 dprintk("\n");
363
364 CRITBEGIN
365
366 mga_inb(M_ATTR_RESET);
367 mga_outb(M_ATTR_INDEX, 0);
368 mga_outb(M_MISC_REG, hw->MiscOutReg);
369 for (i = 1; i < 5; i++)
370 mga_setr(M_SEQ_INDEX, i, hw->SEQ[i]);
371 mga_setr(M_CRTC_INDEX, 17, hw->CRTC[17] & 0x7F);
372 for (i = 0; i < 25; i++)
373 mga_setr(M_CRTC_INDEX, i, hw->CRTC[i]);
374 for (i = 0; i < 9; i++)
375 mga_setr(M_GRAPHICS_INDEX, i, hw->GCTL[i]);
376 for (i = 0; i < 21; i++) {
377 mga_inb(M_ATTR_RESET);
378 mga_outb(M_ATTR_INDEX, i);
379 mga_outb(M_ATTR_INDEX, hw->ATTR[i]);
380 }
381 mga_outb(M_PALETTE_MASK, 0xFF);
382 mga_outb(M_DAC_REG, 0x00);
383 for (i = 0; i < 768; i++)
384 mga_outb(M_DAC_VAL, hw->DACpal[i]);
385 mga_inb(M_ATTR_RESET);
386 mga_outb(M_ATTR_INDEX, 0x20);
387
388 CRITEND
389 }
390
391 static void get_pins(unsigned char __iomem* pins, struct matrox_bios* bd) {
392 unsigned int b0 = readb(pins);
393
394 if (b0 == 0x2E && readb(pins+1) == 0x41) {
395 unsigned int pins_len = readb(pins+2);
396 unsigned int i;
397 unsigned char cksum;
398 unsigned char* dst = bd->pins;
399
400 if (pins_len < 3 || pins_len > 128) {
401 return;
402 }
403 *dst++ = 0x2E;
404 *dst++ = 0x41;
405 *dst++ = pins_len;
406 cksum = 0x2E + 0x41 + pins_len;
407 for (i = 3; i < pins_len; i++) {
408 cksum += *dst++ = readb(pins+i);
409 }
410 if (cksum) {
411 return;
412 }
413 bd->pins_len = pins_len;
414 } else if (b0 == 0x40 && readb(pins+1) == 0x00) {
415 unsigned int i;
416 unsigned char* dst = bd->pins;
417
418 *dst++ = 0x40;
419 *dst++ = 0;
420 for (i = 2; i < 0x40; i++) {
421 *dst++ = readb(pins+i);
422 }
423 bd->pins_len = 0x40;
424 }
425 }
426
427 static void get_bios_version(unsigned char __iomem * vbios, struct matrox_bios* bd) {
428 unsigned int pcir_offset;
429
430 pcir_offset = readb(vbios + 24) | (readb(vbios + 25) << 8);
431 if (pcir_offset >= 26 && pcir_offset < 0xFFE0 &&
432 readb(vbios + pcir_offset ) == 'P' &&
433 readb(vbios + pcir_offset + 1) == 'C' &&
434 readb(vbios + pcir_offset + 2) == 'I' &&
435 readb(vbios + pcir_offset + 3) == 'R') {
436 unsigned char h;
437
438 h = readb(vbios + pcir_offset + 0x12);
439 bd->version.vMaj = (h >> 4) & 0xF;
440 bd->version.vMin = h & 0xF;
441 bd->version.vRev = readb(vbios + pcir_offset + 0x13);
442 } else {
443 unsigned char h;
444
445 h = readb(vbios + 5);
446 bd->version.vMaj = (h >> 4) & 0xF;
447 bd->version.vMin = h & 0xF;
448 bd->version.vRev = 0;
449 }
450 }
451
452 static void get_bios_output(unsigned char __iomem* vbios, struct matrox_bios* bd) {
453 unsigned char b;
454
455 b = readb(vbios + 0x7FF1);
456 if (b == 0xFF) {
457 b = 0;
458 }
459 bd->output.state = b;
460 }
461
462 static void get_bios_tvout(unsigned char __iomem* vbios, struct matrox_bios* bd) {
463 unsigned int i;
464
465 /* Check for 'IBM .*(V....TVO' string - it means TVO BIOS */
466 bd->output.tvout = 0;
467 if (readb(vbios + 0x1D) != 'I' ||
468 readb(vbios + 0x1E) != 'B' ||
469 readb(vbios + 0x1F) != 'M' ||
470 readb(vbios + 0x20) != ' ') {
471 return;
472 }
473 for (i = 0x2D; i < 0x2D + 128; i++) {
474 unsigned char b = readb(vbios + i);
475
476 if (b == '(' && readb(vbios + i + 1) == 'V') {
477 if (readb(vbios + i + 6) == 'T' &&
478 readb(vbios + i + 7) == 'V' &&
479 readb(vbios + i + 8) == 'O') {
480 bd->output.tvout = 1;
481 }
482 return;
483 }
484 if (b == 0)
485 break;
486 }
487 }
488
489 static void parse_bios(unsigned char __iomem* vbios, struct matrox_bios* bd) {
490 unsigned int pins_offset;
491
492 if (readb(vbios) != 0x55 || readb(vbios + 1) != 0xAA) {
493 return;
494 }
495 bd->bios_valid = 1;
496 get_bios_version(vbios, bd);
497 get_bios_output(vbios, bd);
498 get_bios_tvout(vbios, bd);
499 pins_offset = readb(vbios + 0x7FFC) | (readb(vbios + 0x7FFD) << 8);
500 if (pins_offset <= 0xFF80) {
501 get_pins(vbios + pins_offset, bd);
502 }
503 }
504
505 #define get_u16(x) (le16_to_cpu(get_unaligned((__u16*)(x))))
506 #define get_u32(x) (le32_to_cpu(get_unaligned((__u32*)(x))))
507 static int parse_pins1(WPMINFO const struct matrox_bios* bd) {
508 unsigned int maxdac;
509
510 switch (bd->pins[22]) {
511 case 0: maxdac = 175000; break;
512 case 1: maxdac = 220000; break;
513 default: maxdac = 240000; break;
514 }
515 if (get_u16(bd->pins + 24)) {
516 maxdac = get_u16(bd->pins + 24) * 10;
517 }
518 MINFO->limits.pixel.vcomax = maxdac;
519 MINFO->values.pll.system = get_u16(bd->pins + 28) ? get_u16(bd->pins + 28) * 10 : 50000;
520 /* ignore 4MB, 8MB, module clocks */
521 MINFO->features.pll.ref_freq = 14318;
522 MINFO->values.reg.mctlwtst = 0x00030101;
523 return 0;
524 }
525
526 static void default_pins1(WPMINFO2) {
527 /* Millennium */
528 MINFO->limits.pixel.vcomax = 220000;
529 MINFO->values.pll.system = 50000;
530 MINFO->features.pll.ref_freq = 14318;
531 MINFO->values.reg.mctlwtst = 0x00030101;
532 }
533
534 static int parse_pins2(WPMINFO const struct matrox_bios* bd) {
535 MINFO->limits.pixel.vcomax =
536 MINFO->limits.system.vcomax = (bd->pins[41] == 0xFF) ? 230000 : ((bd->pins[41] + 100) * 1000);
537 MINFO->values.reg.mctlwtst = ((bd->pins[51] & 0x01) ? 0x00000001 : 0) |
538 ((bd->pins[51] & 0x02) ? 0x00000100 : 0) |
539 ((bd->pins[51] & 0x04) ? 0x00010000 : 0) |
540 ((bd->pins[51] & 0x08) ? 0x00020000 : 0);
541 MINFO->values.pll.system = (bd->pins[43] == 0xFF) ? 50000 : ((bd->pins[43] + 100) * 1000);
542 MINFO->features.pll.ref_freq = 14318;
543 return 0;
544 }
545
546 static void default_pins2(WPMINFO2) {
547 /* Millennium II, Mystique */
548 MINFO->limits.pixel.vcomax =
549 MINFO->limits.system.vcomax = 230000;
550 MINFO->values.reg.mctlwtst = 0x00030101;
551 MINFO->values.pll.system = 50000;
552 MINFO->features.pll.ref_freq = 14318;
553 }
554
555 static int parse_pins3(WPMINFO const struct matrox_bios* bd) {
556 MINFO->limits.pixel.vcomax =
557 MINFO->limits.system.vcomax = (bd->pins[36] == 0xFF) ? 230000 : ((bd->pins[36] + 100) * 1000);
558 MINFO->values.reg.mctlwtst = get_u32(bd->pins + 48) == 0xFFFFFFFF ? 0x01250A21 : get_u32(bd->pins + 48);
559 /* memory config */
560 MINFO->values.reg.memrdbk = ((bd->pins[57] << 21) & 0x1E000000) |
561 ((bd->pins[57] << 22) & 0x00C00000) |
562 ((bd->pins[56] << 1) & 0x000001E0) |
563 ( bd->pins[56] & 0x0000000F);
564 MINFO->values.reg.opt = (bd->pins[54] & 7) << 10;
565 MINFO->values.reg.opt2 = bd->pins[58] << 12;
566 MINFO->features.pll.ref_freq = (bd->pins[52] & 0x20) ? 14318 : 27000;
567 return 0;
568 }
569
570 static void default_pins3(WPMINFO2) {
571 /* G100, G200 */
572 MINFO->limits.pixel.vcomax =
573 MINFO->limits.system.vcomax = 230000;
574 MINFO->values.reg.mctlwtst = 0x01250A21;
575 MINFO->values.reg.memrdbk = 0x00000000;
576 MINFO->values.reg.opt = 0x00000C00;
577 MINFO->values.reg.opt2 = 0x00000000;
578 MINFO->features.pll.ref_freq = 27000;
579 }
580
581 static int parse_pins4(WPMINFO const struct matrox_bios* bd) {
582 MINFO->limits.pixel.vcomax = (bd->pins[ 39] == 0xFF) ? 230000 : bd->pins[ 39] * 4000;
583 MINFO->limits.system.vcomax = (bd->pins[ 38] == 0xFF) ? MINFO->limits.pixel.vcomax : bd->pins[ 38] * 4000;
584 MINFO->values.reg.mctlwtst = get_u32(bd->pins + 71);
585 MINFO->values.reg.memrdbk = ((bd->pins[87] << 21) & 0x1E000000) |
586 ((bd->pins[87] << 22) & 0x00C00000) |
587 ((bd->pins[86] << 1) & 0x000001E0) |
588 ( bd->pins[86] & 0x0000000F);
589 MINFO->values.reg.opt = ((bd->pins[53] << 15) & 0x00400000) |
590 ((bd->pins[53] << 22) & 0x10000000) |
591 ((bd->pins[53] << 7) & 0x00001C00);
592 MINFO->values.reg.opt3 = get_u32(bd->pins + 67);
593 MINFO->values.pll.system = (bd->pins[ 65] == 0xFF) ? 200000 : bd->pins[ 65] * 4000;
594 MINFO->features.pll.ref_freq = (bd->pins[ 92] & 0x01) ? 14318 : 27000;
595 return 0;
596 }
597
598 static void default_pins4(WPMINFO2) {
599 /* G400 */
600 MINFO->limits.pixel.vcomax =
601 MINFO->limits.system.vcomax = 252000;
602 MINFO->values.reg.mctlwtst = 0x04A450A1;
603 MINFO->values.reg.memrdbk = 0x000000E7;
604 MINFO->values.reg.opt = 0x10000400;
605 MINFO->values.reg.opt3 = 0x0190A419;
606 MINFO->values.pll.system = 200000;
607 MINFO->features.pll.ref_freq = 27000;
608 }
609
610 static int parse_pins5(WPMINFO const struct matrox_bios* bd) {
611 unsigned int mult;
612
613 mult = bd->pins[4]?8000:6000;
614
615 MINFO->limits.pixel.vcomax = (bd->pins[ 38] == 0xFF) ? 600000 : bd->pins[ 38] * mult;
616 MINFO->limits.system.vcomax = (bd->pins[ 36] == 0xFF) ? MINFO->limits.pixel.vcomax : bd->pins[ 36] * mult;
617 MINFO->limits.video.vcomax = (bd->pins[ 37] == 0xFF) ? MINFO->limits.system.vcomax : bd->pins[ 37] * mult;
618 MINFO->limits.pixel.vcomin = (bd->pins[123] == 0xFF) ? 256000 : bd->pins[123] * mult;
619 MINFO->limits.system.vcomin = (bd->pins[121] == 0xFF) ? MINFO->limits.pixel.vcomin : bd->pins[121] * mult;
620 MINFO->limits.video.vcomin = (bd->pins[122] == 0xFF) ? MINFO->limits.system.vcomin : bd->pins[122] * mult;
621 MINFO->values.pll.system =
622 MINFO->values.pll.video = (bd->pins[ 92] == 0xFF) ? 284000 : bd->pins[ 92] * 4000;
623 MINFO->values.reg.opt = get_u32(bd->pins+ 48);
624 MINFO->values.reg.opt2 = get_u32(bd->pins+ 52);
625 MINFO->values.reg.opt3 = get_u32(bd->pins+ 94);
626 MINFO->values.reg.mctlwtst = get_u32(bd->pins+ 98);
627 MINFO->values.reg.memmisc = get_u32(bd->pins+102);
628 MINFO->values.reg.memrdbk = get_u32(bd->pins+106);
629 MINFO->features.pll.ref_freq = (bd->pins[110] & 0x01) ? 14318 : 27000;
630 MINFO->values.memory.ddr = (bd->pins[114] & 0x60) == 0x20;
631 MINFO->values.memory.dll = (bd->pins[115] & 0x02) != 0;
632 MINFO->values.memory.emrswen = (bd->pins[115] & 0x01) != 0;
633 MINFO->values.reg.maccess = MINFO->values.memory.emrswen ? 0x00004000 : 0x00000000;
634 if (bd->pins[115] & 4) {
635 MINFO->values.reg.mctlwtst_core = MINFO->values.reg.mctlwtst;
636 } else {
637 u_int32_t wtst_xlat[] = { 0, 1, 5, 6, 7, 5, 2, 3 };
638 MINFO->values.reg.mctlwtst_core = (MINFO->values.reg.mctlwtst & ~7) |
639 wtst_xlat[MINFO->values.reg.mctlwtst & 7];
640 }
641 return 0;
642 }
643
644 static void default_pins5(WPMINFO2) {
645 /* Mine 16MB G450 with SDRAM DDR */
646 MINFO->limits.pixel.vcomax =
647 MINFO->limits.system.vcomax =
648 MINFO->limits.video.vcomax = 600000;
649 MINFO->limits.pixel.vcomin =
650 MINFO->limits.system.vcomin =
651 MINFO->limits.video.vcomin = 256000;
652 MINFO->values.pll.system =
653 MINFO->values.pll.video = 284000;
654 MINFO->values.reg.opt = 0x404A1160;
655 MINFO->values.reg.opt2 = 0x0000AC00;
656 MINFO->values.reg.opt3 = 0x0090A409;
657 MINFO->values.reg.mctlwtst_core =
658 MINFO->values.reg.mctlwtst = 0x0C81462B;
659 MINFO->values.reg.memmisc = 0x80000004;
660 MINFO->values.reg.memrdbk = 0x01001103;
661 MINFO->features.pll.ref_freq = 27000;
662 MINFO->values.memory.ddr = 1;
663 MINFO->values.memory.dll = 1;
664 MINFO->values.memory.emrswen = 1;
665 MINFO->values.reg.maccess = 0x00004000;
666 }
667
668 static int matroxfb_set_limits(WPMINFO const struct matrox_bios* bd) {
669 unsigned int pins_version;
670 static const unsigned int pinslen[] = { 64, 64, 64, 128, 128 };
671
672 switch (ACCESS_FBINFO(chip)) {
673 case MGA_2064: default_pins1(PMINFO2); break;
674 case MGA_2164:
675 case MGA_1064:
676 case MGA_1164: default_pins2(PMINFO2); break;
677 case MGA_G100:
678 case MGA_G200: default_pins3(PMINFO2); break;
679 case MGA_G400: default_pins4(PMINFO2); break;
680 case MGA_G450:
681 case MGA_G550: default_pins5(PMINFO2); break;
682 }
683 if (!bd->bios_valid) {
684 printk(KERN_INFO "matroxfb: Your Matrox device does not have BIOS\n");
685 return -1;
686 }
687 if (bd->pins_len < 64) {
688 printk(KERN_INFO "matroxfb: BIOS on your Matrox device does not contain powerup info\n");
689 return -1;
690 }
691 if (bd->pins[0] == 0x2E && bd->pins[1] == 0x41) {
692 pins_version = bd->pins[5];
693 if (pins_version < 2 || pins_version > 5) {
694 printk(KERN_INFO "matroxfb: Unknown version (%u) of powerup info\n", pins_version);
695 return -1;
696 }
697 } else {
698 pins_version = 1;
699 }
700 if (bd->pins_len != pinslen[pins_version - 1]) {
701 printk(KERN_INFO "matroxfb: Invalid powerup info\n");
702 return -1;
703 }
704 switch (pins_version) {
705 case 1:
706 return parse_pins1(PMINFO bd);
707 case 2:
708 return parse_pins2(PMINFO bd);
709 case 3:
710 return parse_pins3(PMINFO bd);
711 case 4:
712 return parse_pins4(PMINFO bd);
713 case 5:
714 return parse_pins5(PMINFO bd);
715 default:
716 printk(KERN_DEBUG "matroxfb: Powerup info version %u is not yet supported\n", pins_version);
717 return -1;
718 }
719 }
720
721 void matroxfb_read_pins(WPMINFO2) {
722 u32 opt;
723 u32 biosbase;
724 u32 fbbase;
725 struct pci_dev* pdev = ACCESS_FBINFO(pcidev);
726
727 memset(&ACCESS_FBINFO(bios), 0, sizeof(ACCESS_FBINFO(bios)));
728 pci_read_config_dword(pdev, PCI_OPTION_REG, &opt);
729 pci_write_config_dword(pdev, PCI_OPTION_REG, opt | PCI_OPTION_ENABLE_ROM);
730 pci_read_config_dword(pdev, PCI_ROM_ADDRESS, &biosbase);
731 pci_read_config_dword(pdev, ACCESS_FBINFO(devflags.fbResource), &fbbase);
732 pci_write_config_dword(pdev, PCI_ROM_ADDRESS, (fbbase & PCI_ROM_ADDRESS_MASK) | PCI_ROM_ADDRESS_ENABLE);
733 parse_bios(vaddr_va(ACCESS_FBINFO(video).vbase), &ACCESS_FBINFO(bios));
734 pci_write_config_dword(pdev, PCI_ROM_ADDRESS, biosbase);
735 pci_write_config_dword(pdev, PCI_OPTION_REG, opt);
736 #ifdef CONFIG_X86
737 if (!ACCESS_FBINFO(bios).bios_valid) {
738 unsigned char __iomem* b;
739
740 b = ioremap(0x000C0000, 65536);
741 if (!b) {
742 printk(KERN_INFO "matroxfb: Unable to map legacy BIOS\n");
743 } else {
744 unsigned int ven = readb(b+0x64+0) | (readb(b+0x64+1) << 8);
745 unsigned int dev = readb(b+0x64+2) | (readb(b+0x64+3) << 8);
746
747 if (ven != pdev->vendor || dev != pdev->device) {
748 printk(KERN_INFO "matroxfb: Legacy BIOS is for %04X:%04X, while this device is %04X:%04X\n",
749 ven, dev, pdev->vendor, pdev->device);
750 } else {
751 parse_bios(b, &ACCESS_FBINFO(bios));
752 }
753 iounmap(b);
754 }
755 }
756 #endif
757 matroxfb_set_limits(PMINFO &ACCESS_FBINFO(bios));
758 }
759
760 EXPORT_SYMBOL(matroxfb_DAC_in);
761 EXPORT_SYMBOL(matroxfb_DAC_out);
762 EXPORT_SYMBOL(matroxfb_var2my);
763 EXPORT_SYMBOL(matroxfb_PLL_calcclock);
764 #ifndef CONFIG_FB_MATROX_MULTIHEAD
765 struct matrox_fb_info matroxfb_global_mxinfo;
766 EXPORT_SYMBOL(matroxfb_global_mxinfo);
767 #endif
768 EXPORT_SYMBOL(matroxfb_vgaHWinit); /* DAC1064, Ti3026 */
769 EXPORT_SYMBOL(matroxfb_vgaHWrestore); /* DAC1064, Ti3026 */
770 EXPORT_SYMBOL(matroxfb_read_pins);
771
772 MODULE_AUTHOR("(c) 1999-2002 Petr Vandrovec <vandrove@vc.cvut.cz>");
773 MODULE_DESCRIPTION("Miscellaneous support for Matrox video cards");
774 MODULE_LICENSE("GPL");
Verdex Pro support