arch/arm/common/gic.c

   1 /*
   2  *  linux/arch/arm/common/gic.c
   3  *
   4  *  Copyright (C) 2002 ARM Limited, All Rights Reserved.
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * Interrupt architecture for the GIC:
  11  *
  12  * o There is one Interrupt Distributor, which receives interrupts
  13  *   from system devices and sends them to the Interrupt Controllers.
  14  *
  15  * o There is one CPU Interface per CPU, which sends interrupts sent
  16  *   by the Distributor, and interrupts generated locally, to the
  17  *   associated CPU.
  18  *
  19  * Note that IRQs 0-31 are special - they are local to each CPU.
  20  * As such, the enable set/clear, pending set/clear and active bit
  21  * registers are banked per-cpu for these sources.
  22  */
  23 #include <linux/init.h>
  24 #include <linux/kernel.h>
  25 #include <linux/list.h>
  26 #include <linux/smp.h>
  27 #include <linux/cpumask.h>
  28
  29 #include <asm/irq.h>
  30 #include <asm/io.h>
  31 #include <asm/mach/irq.h>
  32 #include <asm/hardware/gic.h>
  33
  34 static void __iomem *gic_dist_base;
  35 static void __iomem *gic_cpu_base;
  36
  37 /*
  38  * Routines to acknowledge, disable and enable interrupts
  39  *
  40  * Linux assumes that when we're done with an interrupt we need to
  41  * unmask it, in the same way we need to unmask an interrupt when
  42  * we first enable it.
  43  *
  44  * The GIC has a seperate notion of "end of interrupt" to re-enable
  45  * an interrupt after handling, in order to support hardware
  46  * prioritisation.
  47  *
  48  * We can make the GIC behave in the way that Linux expects by making
  49  * our "acknowledge" routine disable the interrupt, then mark it as
  50  * complete.
  51  */
  52 static void gic_ack_irq(unsigned int irq)
  53 {
  54         u32 mask = 1 << (irq % 32);
  55         writel(mask, gic_dist_base + GIC_DIST_ENABLE_CLEAR + (irq / 32) * 4);
  56         writel(irq, gic_cpu_base + GIC_CPU_EOI);
  57 }
  58
  59 static void gic_mask_irq(unsigned int irq)
  60 {
  61         u32 mask = 1 << (irq % 32);
  62         writel(mask, gic_dist_base + GIC_DIST_ENABLE_CLEAR + (irq / 32) * 4);
  63 }
  64
  65 static void gic_unmask_irq(unsigned int irq)
  66 {
  67         u32 mask = 1 << (irq % 32);
  68         writel(mask, gic_dist_base + GIC_DIST_ENABLE_SET + (irq / 32) * 4);
  69 }
  70
  71 static void gic_set_cpu(struct irqdesc *desc, unsigned int irq, unsigned int cpu)
  72 {
  73         void __iomem *reg = gic_dist_base + GIC_DIST_TARGET + (irq & ~3);
  74         unsigned int shift = (irq % 4) * 8;
  75         u32 val;
  76
  77         val = readl(reg) & ~(0xff << shift);
  78         val |= 1 << (cpu + shift);
  79         writel(val, reg);
  80 }
  81
  82 static struct irqchip gic_chip = {
  83         .ack            = gic_ack_irq,
  84         .mask           = gic_mask_irq,
  85         .unmask         = gic_unmask_irq,
  86 #ifdef CONFIG_SMP
  87         .set_cpu        = gic_set_cpu,
  88 #endif
  89 };
  90
  91 void __init gic_dist_init(void __iomem *base)
  92 {
  93         unsigned int max_irq, i;
  94         u32 cpumask = 1 << smp_processor_id();
  95
  96         cpumask |= cpumask << 8;
  97         cpumask |= cpumask << 16;
  98
  99         gic_dist_base = base;
 100
 101         writel(0, base + GIC_DIST_CTRL);
 102
 103         /*
 104          * Find out how many interrupts are supported.
 105          */
 106         max_irq = readl(base + GIC_DIST_CTR) & 0x1f;
 107         max_irq = (max_irq + 1) * 32;
 108
 109         /*
 110          * The GIC only supports up to 1020 interrupt sources.
 111          * Limit this to either the architected maximum, or the
 112          * platform maximum.
 113          */
 114         if (max_irq > max(1020, NR_IRQS))
 115                 max_irq = max(1020, NR_IRQS);
 116
 117         /*
 118          * Set all global interrupts to be level triggered, active low.
 119          */
 120         for (i = 32; i < max_irq; i += 16)
 121                 writel(0, base + GIC_DIST_CONFIG + i * 4 / 16);
 122
 123         /*
 124          * Set all global interrupts to this CPU only.
 125          */
 126         for (i = 32; i < max_irq; i += 4)
 127                 writel(cpumask, base + GIC_DIST_TARGET + i * 4 / 4);
 128
 129         /*
 130          * Set priority on all interrupts.
 131          */
 132         for (i = 0; i < max_irq; i += 4)
 133                 writel(0xa0a0a0a0, base + GIC_DIST_PRI + i * 4 / 4);
 134
 135         /*
 136          * Disable all interrupts.
 137          */
 138         for (i = 0; i < max_irq; i += 32)
 139                 writel(0xffffffff, base + GIC_DIST_ENABLE_CLEAR + i * 4 / 32);
 140
 141         /*
 142          * Setup the Linux IRQ subsystem.
 143          */
 144         for (i = 29; i < max_irq; i++) {
 145                 set_irq_chip(i, &gic_chip);
 146                 set_irq_handler(i, do_level_IRQ);
 147                 set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
 148         }
 149
 150         writel(1, base + GIC_DIST_CTRL);
 151 }
 152
 153 void __cpuinit gic_cpu_init(void __iomem *base)
 154 {
 155         gic_cpu_base = base;
 156         writel(0xf0, base + GIC_CPU_PRIMASK);
 157         writel(1, base + GIC_CPU_CTRL);
 158 }
 159
 160 #ifdef CONFIG_SMP
 161 void gic_raise_softirq(cpumask_t cpumask, unsigned int irq)
 162 {
 163         unsigned long map = *cpus_addr(cpumask);
 164
 165         writel(map << 16 | irq, gic_dist_base + GIC_DIST_SOFTINT);
 166 }
 167 #endif