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[PATCH] ppc64: Remove unused code
[linux-2.6/verdex.git] / arch / ppc / kernel / cputable.c
blob546e1ea4cafa31a6bb126dfce2fdcbde2e3fe6d3
1 /*
2 * arch/ppc/kernel/cputable.c
3 *
4 * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version
9 * 2 of the License, or (at your option) any later version.
10 */
11
12 #include <linux/config.h>
13 #include <linux/string.h>
14 #include <linux/sched.h>
15 #include <linux/threads.h>
16 #include <linux/init.h>
17 #include <asm/cputable.h>
18
19 struct cpu_spec* cur_cpu_spec[NR_CPUS];
20
21 extern void __setup_cpu_601(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
22 extern void __setup_cpu_603(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
23 extern void __setup_cpu_604(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
24 extern void __setup_cpu_750(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
25 extern void __setup_cpu_750cx(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
26 extern void __setup_cpu_750fx(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
27 extern void __setup_cpu_7400(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
28 extern void __setup_cpu_7410(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
29 extern void __setup_cpu_745x(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
30 extern void __setup_cpu_power3(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
31 extern void __setup_cpu_power4(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
32 extern void __setup_cpu_ppc970(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
33 extern void __setup_cpu_generic(unsigned long offset, int cpu_nr, struct cpu_spec* spec);
34
35 #define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
36 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
37 !defined(CONFIG_BOOKE))
38
39 /* This table only contains "desktop" CPUs, it need to be filled with embedded
40 * ones as well...
41 */
42 #define COMMON_PPC (PPC_FEATURE_32 | PPC_FEATURE_HAS_FPU | \
43 PPC_FEATURE_HAS_MMU)
44
45 /* We only set the altivec features if the kernel was compiled with altivec
46 * support
47 */
48 #ifdef CONFIG_ALTIVEC
49 #define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
50 #define PPC_FEATURE_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
51 #else
52 #define CPU_FTR_ALTIVEC_COMP 0
53 #define PPC_FEATURE_ALTIVEC_COMP 0
54 #endif
55
56 /* We only set the spe features if the kernel was compiled with
57 * spe support
58 */
59 #ifdef CONFIG_SPE
60 #define PPC_FEATURE_SPE_COMP PPC_FEATURE_HAS_SPE
61 #else
62 #define PPC_FEATURE_SPE_COMP 0
63 #endif
64
65 /* We need to mark all pages as being coherent if we're SMP or we
66 * have a 74[45]x and an MPC107 host bridge.
67 */
68 #if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE)
69 #define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
70 #else
71 #define CPU_FTR_COMMON 0
72 #endif
73
74 /* The powersave features NAP & DOZE seems to confuse BDI when
75 debugging. So if a BDI is used, disable theses
76 */
77 #ifndef CONFIG_BDI_SWITCH
78 #define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
79 #define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
80 #else
81 #define CPU_FTR_MAYBE_CAN_DOZE 0
82 #define CPU_FTR_MAYBE_CAN_NAP 0
83 #endif
84
85 struct cpu_spec cpu_specs[] = {
86 #if CLASSIC_PPC
87 { /* 601 */
88 .pvr_mask = 0xffff0000,
89 .pvr_value = 0x00010000,
90 .cpu_name = "601",
91 .cpu_features = CPU_FTR_COMMON | CPU_FTR_601 |
92 CPU_FTR_HPTE_TABLE,
93 .cpu_user_features = COMMON_PPC | PPC_FEATURE_601_INSTR |
94 PPC_FEATURE_UNIFIED_CACHE,
95 .icache_bsize = 32,
96 .dcache_bsize = 32,
97 .cpu_setup = __setup_cpu_601
98 },
99 { /* 603 */
100 .pvr_mask = 0xffff0000,
101 .pvr_value = 0x00030000,
102 .cpu_name = "603",
103 .cpu_features = CPU_FTR_COMMON |
104 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
105 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP,
106 .cpu_user_features = COMMON_PPC,
107 .icache_bsize = 32,
108 .dcache_bsize = 32,
109 .cpu_setup = __setup_cpu_603
110 },
111 { /* 603e */
112 .pvr_mask = 0xffff0000,
113 .pvr_value = 0x00060000,
114 .cpu_name = "603e",
115 .cpu_features = CPU_FTR_COMMON |
116 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
117 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP,
118 .cpu_user_features = COMMON_PPC,
119 .icache_bsize = 32,
120 .dcache_bsize = 32,
121 .cpu_setup = __setup_cpu_603
122 },
123 { /* 603ev */
124 .pvr_mask = 0xffff0000,
125 .pvr_value = 0x00070000,
126 .cpu_name = "603ev",
127 .cpu_features = CPU_FTR_COMMON |
128 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
129 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP,
130 .cpu_user_features = COMMON_PPC,
131 .icache_bsize = 32,
132 .dcache_bsize = 32,
133 .cpu_setup = __setup_cpu_603
134 },
135 { /* 604 */
136 .pvr_mask = 0xffff0000,
137 .pvr_value = 0x00040000,
138 .cpu_name = "604",
139 .cpu_features = CPU_FTR_COMMON |
140 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
141 CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
142 .cpu_user_features = COMMON_PPC,
143 .icache_bsize = 32,
144 .dcache_bsize = 32,
145 .num_pmcs = 2,
146 .cpu_setup = __setup_cpu_604
147 },
148 { /* 604e */
149 .pvr_mask = 0xfffff000,
150 .pvr_value = 0x00090000,
151 .cpu_name = "604e",
152 .cpu_features = CPU_FTR_COMMON |
153 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
154 CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
155 .cpu_user_features = COMMON_PPC,
156 .icache_bsize = 32,
157 .dcache_bsize = 32,
158 .num_pmcs = 4,
159 .cpu_setup = __setup_cpu_604
160 },
161 { /* 604r */
162 .pvr_mask = 0xffff0000,
163 .pvr_value = 0x00090000,
164 .cpu_name = "604r",
165 .cpu_features = CPU_FTR_COMMON |
166 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
167 CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
168 .cpu_user_features = COMMON_PPC,
169 .icache_bsize = 32,
170 .dcache_bsize = 32,
171 .num_pmcs = 4,
172 .cpu_setup = __setup_cpu_604
173 },
174 { /* 604ev */
175 .pvr_mask = 0xffff0000,
176 .pvr_value = 0x000a0000,
177 .cpu_name = "604ev",
178 .cpu_features = CPU_FTR_COMMON |
179 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
180 CPU_FTR_604_PERF_MON | CPU_FTR_HPTE_TABLE,
181 .cpu_user_features = COMMON_PPC,
182 .icache_bsize = 32,
183 .dcache_bsize = 32,
184 .num_pmcs = 4,
185 .cpu_setup = __setup_cpu_604
186 },
187 { /* 740/750 (0x4202, don't support TAU ?) */
188 .pvr_mask = 0xffffffff,
189 .pvr_value = 0x00084202,
190 .cpu_name = "740/750",
191 .cpu_features = CPU_FTR_COMMON |
192 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
193 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_HPTE_TABLE |
194 CPU_FTR_MAYBE_CAN_NAP,
195 .cpu_user_features = COMMON_PPC,
196 .icache_bsize = 32,
197 .dcache_bsize = 32,
198 .num_pmcs = 4,
199 .cpu_setup = __setup_cpu_750
200 },
201 { /* 750CX (80100 and 8010x?) */
202 .pvr_mask = 0xfffffff0,
203 .pvr_value = 0x00080100,
204 .cpu_name = "750CX",
205 .cpu_features = CPU_FTR_COMMON |
206 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
207 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
208 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
209 .cpu_user_features = COMMON_PPC,
210 .icache_bsize = 32,
211 .dcache_bsize = 32,
212 .num_pmcs = 4,
213 .cpu_setup = __setup_cpu_750cx
214 },
215 { /* 750CX (82201 and 82202) */
216 .pvr_mask = 0xfffffff0,
217 .pvr_value = 0x00082200,
218 .cpu_name = "750CX",
219 .cpu_features = CPU_FTR_COMMON |
220 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
221 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
222 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
223 .cpu_user_features = COMMON_PPC,
224 .icache_bsize = 32,
225 .dcache_bsize = 32,
226 .num_pmcs = 4,
227 .cpu_setup = __setup_cpu_750cx
228 },
229 { /* 750CXe (82214) */
230 .pvr_mask = 0xfffffff0,
231 .pvr_value = 0x00082210,
232 .cpu_name = "750CXe",
233 .cpu_features = CPU_FTR_COMMON |
234 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
235 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
236 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
237 .cpu_user_features = COMMON_PPC,
238 .icache_bsize = 32,
239 .dcache_bsize = 32,
240 .num_pmcs = 4,
241 .cpu_setup = __setup_cpu_750cx
242 },
243 { /* 750CXe "Gekko" (83214) */
244 .pvr_mask = 0xffffffff,
245 .pvr_value = 0x00083214,
246 .cpu_name = "750CXe",
247 .cpu_features = CPU_FTR_COMMON |
248 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
249 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
250 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
251 .cpu_user_features = COMMON_PPC,
252 .icache_bsize = 32,
253 .dcache_bsize = 32,
254 .num_pmcs = 4,
255 .cpu_setup = __setup_cpu_750cx
256 },
257 { /* 745/755 */
258 .pvr_mask = 0xfffff000,
259 .pvr_value = 0x00083000,
260 .cpu_name = "745/755",
261 .cpu_features = CPU_FTR_COMMON |
262 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
263 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
264 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
265 .cpu_user_features = COMMON_PPC,
266 .icache_bsize = 32,
267 .dcache_bsize = 32,
268 .num_pmcs = 4,
269 .cpu_setup = __setup_cpu_750
270 },
271 { /* 750FX rev 1.x */
272 .pvr_mask = 0xffffff00,
273 .pvr_value = 0x70000100,
274 .cpu_name = "750FX",
275 .cpu_features = CPU_FTR_COMMON |
276 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
277 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
278 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
279 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM,
280 .cpu_user_features = COMMON_PPC,
281 .icache_bsize = 32,
282 .dcache_bsize = 32,
283 .num_pmcs = 4,
284 .cpu_setup = __setup_cpu_750
285 },
286 { /* 750FX rev 2.0 must disable HID0[DPM] */
287 .pvr_mask = 0xffffffff,
288 .pvr_value = 0x70000200,
289 .cpu_name = "750FX",
290 .cpu_features = CPU_FTR_COMMON |
291 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
292 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
293 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
294 CPU_FTR_NO_DPM,
295 .cpu_user_features = COMMON_PPC,
296 .icache_bsize = 32,
297 .dcache_bsize = 32,
298 .num_pmcs = 4,
299 .cpu_setup = __setup_cpu_750
300 },
301 { /* 750FX (All revs except 2.0) */
302 .pvr_mask = 0xffff0000,
303 .pvr_value = 0x70000000,
304 .cpu_name = "750FX",
305 .cpu_features = CPU_FTR_COMMON |
306 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
307 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
308 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP |
309 CPU_FTR_DUAL_PLL_750FX | CPU_FTR_HAS_HIGH_BATS,
310 .cpu_user_features = COMMON_PPC,
311 .icache_bsize = 32,
312 .dcache_bsize = 32,
313 .num_pmcs = 4,
314 .cpu_setup = __setup_cpu_750fx
315 },
316 { /* 750GX */
317 .pvr_mask = 0xffff0000,
318 .pvr_value = 0x70020000,
319 .cpu_name = "750GX",
320 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
321 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
322 CPU_FTR_L2CR | CPU_FTR_TAU | CPU_FTR_HPTE_TABLE |
323 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_DUAL_PLL_750FX |
324 CPU_FTR_HAS_HIGH_BATS,
325 .cpu_user_features = COMMON_PPC,
326 .icache_bsize = 32,
327 .dcache_bsize = 32,
328 .num_pmcs = 4,
329 .cpu_setup = __setup_cpu_750fx
330 },
331 { /* 740/750 (L2CR bit need fixup for 740) */
332 .pvr_mask = 0xffff0000,
333 .pvr_value = 0x00080000,
334 .cpu_name = "740/750",
335 .cpu_features = CPU_FTR_COMMON |
336 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
337 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
338 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
339 .cpu_user_features = COMMON_PPC,
340 .icache_bsize = 32,
341 .dcache_bsize = 32,
342 .num_pmcs = 4,
343 .cpu_setup = __setup_cpu_750
344 },
345 { /* 7400 rev 1.1 ? (no TAU) */
346 .pvr_mask = 0xffffffff,
347 .pvr_value = 0x000c1101,
348 .cpu_name = "7400 (1.1)",
349 .cpu_features = CPU_FTR_COMMON |
350 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
351 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP |
352 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP,
353 .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
354 .icache_bsize = 32,
355 .dcache_bsize = 32,
356 .num_pmcs = 4,
357 .cpu_setup = __setup_cpu_7400
358 },
359 { /* 7400 */
360 .pvr_mask = 0xffff0000,
361 .pvr_value = 0x000c0000,
362 .cpu_name = "7400",
363 .cpu_features = CPU_FTR_COMMON |
364 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
365 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
366 CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
367 CPU_FTR_MAYBE_CAN_NAP,
368 .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
369 .icache_bsize = 32,
370 .dcache_bsize = 32,
371 .num_pmcs = 4,
372 .cpu_setup = __setup_cpu_7400
373 },
374 { /* 7410 */
375 .pvr_mask = 0xffff0000,
376 .pvr_value = 0x800c0000,
377 .cpu_name = "7410",
378 .cpu_features = CPU_FTR_COMMON |
379 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
380 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_TAU |
381 CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
382 CPU_FTR_MAYBE_CAN_NAP,
383 .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
384 .icache_bsize = 32,
385 .dcache_bsize = 32,
386 .num_pmcs = 4,
387 .cpu_setup = __setup_cpu_7410
388 },
389 { /* 7450 2.0 - no doze/nap */
390 .pvr_mask = 0xffffffff,
391 .pvr_value = 0x80000200,
392 .cpu_name = "7450",
393 .cpu_features = CPU_FTR_COMMON |
394 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
395 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
396 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
397 CPU_FTR_NEED_COHERENT,
398 .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
399 .icache_bsize = 32,
400 .dcache_bsize = 32,
401 .num_pmcs = 6,
402 .cpu_setup = __setup_cpu_745x
403 },
404 { /* 7450 2.1 */
405 .pvr_mask = 0xffffffff,
406 .pvr_value = 0x80000201,
407 .cpu_name = "7450",
408 .cpu_features = CPU_FTR_COMMON |
409 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
410 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
411 CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
412 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
413 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
414 CPU_FTR_NEED_COHERENT,
415 .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
416 .icache_bsize = 32,
417 .dcache_bsize = 32,
418 .num_pmcs = 6,
419 .cpu_setup = __setup_cpu_745x
420 },
421 { /* 7450 2.3 and newer */
422 .pvr_mask = 0xffff0000,
423 .pvr_value = 0x80000000,
424 .cpu_name = "7450",
425 .cpu_features = CPU_FTR_COMMON |
426 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
427 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
428 CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
429 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
430 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT,
431 .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
432 .icache_bsize = 32,
433 .dcache_bsize = 32,
434 .num_pmcs = 6,
435 .cpu_setup = __setup_cpu_745x
436 },
437 { /* 7455 rev 1.x */
438 .pvr_mask = 0xffffff00,
439 .pvr_value = 0x80010100,
440 .cpu_name = "7455",
441 .cpu_features = CPU_FTR_COMMON |
442 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
443 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
444 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
445 CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
446 .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
447 .icache_bsize = 32,
448 .dcache_bsize = 32,
449 .num_pmcs = 6,
450 .cpu_setup = __setup_cpu_745x
451 },
452 { /* 7455 rev 2.0 */
453 .pvr_mask = 0xffffffff,
454 .pvr_value = 0x80010200,
455 .cpu_name = "7455",
456 .cpu_features = CPU_FTR_COMMON |
457 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
458 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
459 CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
460 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
461 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP |
462 CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS,
463 .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
464 .icache_bsize = 32,
465 .dcache_bsize = 32,
466 .num_pmcs = 6,
467 .cpu_setup = __setup_cpu_745x
468 },
469 { /* 7455 others */
470 .pvr_mask = 0xffff0000,
471 .pvr_value = 0x80010000,
472 .cpu_name = "7455",
473 .cpu_features = CPU_FTR_COMMON |
474 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
475 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
476 CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
477 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
478 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
479 CPU_FTR_NEED_COHERENT,
480 .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
481 .icache_bsize = 32,
482 .dcache_bsize = 32,
483 .num_pmcs = 6,
484 .cpu_setup = __setup_cpu_745x
485 },
486 { /* 7447/7457 Rev 1.0 */
487 .pvr_mask = 0xffffffff,
488 .pvr_value = 0x80020100,
489 .cpu_name = "7447/7457",
490 .cpu_features = CPU_FTR_COMMON |
491 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
492 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
493 CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
494 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
495 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
496 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
497 .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
498 .icache_bsize = 32,
499 .dcache_bsize = 32,
500 .num_pmcs = 6,
501 .cpu_setup = __setup_cpu_745x
502 },
503 { /* 7447/7457 Rev 1.1 */
504 .pvr_mask = 0xffffffff,
505 .pvr_value = 0x80020101,
506 .cpu_name = "7447/7457",
507 .cpu_features = CPU_FTR_COMMON |
508 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
509 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
510 CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
511 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
512 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
513 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC,
514 .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
515 .icache_bsize = 32,
516 .dcache_bsize = 32,
517 .num_pmcs = 6,
518 .cpu_setup = __setup_cpu_745x
519 },
520 { /* 7447/7457 Rev 1.2 and later */
521 .pvr_mask = 0xffff0000,
522 .pvr_value = 0x80020000,
523 .cpu_name = "7447/7457",
524 .cpu_features = CPU_FTR_COMMON |
525 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
526 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
527 CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR |
528 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 |
529 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS |
530 CPU_FTR_NEED_COHERENT,
531 .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
532 .icache_bsize = 32,
533 .dcache_bsize = 32,
534 .num_pmcs = 6,
535 .cpu_setup = __setup_cpu_745x
536 },
537 { /* 7447A */
538 .pvr_mask = 0xffff0000,
539 .pvr_value = 0x80030000,
540 .cpu_name = "7447A",
541 .cpu_features = CPU_FTR_COMMON |
542 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
543 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
544 CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
545 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
546 CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
547 .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
548 .icache_bsize = 32,
549 .dcache_bsize = 32,
550 .num_pmcs = 6,
551 .cpu_setup = __setup_cpu_745x
552 },
553 { /* 7448 */
554 .pvr_mask = 0xffff0000,
555 .pvr_value = 0x80040000,
556 .cpu_name = "7448",
557 .cpu_features = CPU_FTR_COMMON |
558 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
559 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR |
560 CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE |
561 CPU_FTR_SPEC7450 | CPU_FTR_NAP_DISABLE_L2_PR |
562 CPU_FTR_HAS_HIGH_BATS | CPU_FTR_NEED_COHERENT,
563 .cpu_user_features = COMMON_PPC | PPC_FEATURE_ALTIVEC_COMP,
564 .icache_bsize = 32,
565 .dcache_bsize = 32,
566 .num_pmcs = 6,
567 .cpu_setup = __setup_cpu_745x
568 },
569 { /* 82xx (8240, 8245, 8260 are all 603e cores) */
570 .pvr_mask = 0x7fff0000,
571 .pvr_value = 0x00810000,
572 .cpu_name = "82xx",
573 .cpu_features = CPU_FTR_COMMON |
574 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_MAYBE_CAN_DOZE |
575 CPU_FTR_USE_TB,
576 .cpu_user_features = COMMON_PPC,
577 .icache_bsize = 32,
578 .dcache_bsize = 32,
579 .cpu_setup = __setup_cpu_603
580 },
581 { /* All G2_LE (603e core, plus some) have the same pvr */
582 .pvr_mask = 0x7fff0000,
583 .pvr_value = 0x00820000,
584 .cpu_name = "G2_LE",
585 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
586 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
587 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
588 .cpu_user_features = COMMON_PPC,
589 .icache_bsize = 32,
590 .dcache_bsize = 32,
591 .cpu_setup = __setup_cpu_603
592 },
593 { /* e300 (a 603e core, plus some) on 83xx */
594 .pvr_mask = 0x7fff0000,
595 .pvr_value = 0x00830000,
596 .cpu_name = "e300",
597 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
598 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB |
599 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS,
600 .cpu_user_features = COMMON_PPC,
601 .icache_bsize = 32,
602 .dcache_bsize = 32,
603 .cpu_setup = __setup_cpu_603
604 },
605 { /* default match, we assume split I/D cache & TB (non-601)... */
606 .pvr_mask = 0x00000000,
607 .pvr_value = 0x00000000,
608 .cpu_name = "(generic PPC)",
609 .cpu_features = CPU_FTR_COMMON |
610 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
611 CPU_FTR_HPTE_TABLE,
612 .cpu_user_features = COMMON_PPC,
613 .icache_bsize = 32,
614 .dcache_bsize = 32,
615 .cpu_setup = __setup_cpu_generic
616 },
617 #endif /* CLASSIC_PPC */
618 #ifdef CONFIG_PPC64BRIDGE
619 { /* Power3 */
620 .pvr_mask = 0xffff0000,
621 .pvr_value = 0x00400000,
622 .cpu_name = "Power3 (630)",
623 .cpu_features = CPU_FTR_COMMON |
624 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
625 CPU_FTR_HPTE_TABLE,
626 .cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
627 .icache_bsize = 128,
628 .dcache_bsize = 128,
629 .num_pmcs = 8,
630 .cpu_setup = __setup_cpu_power3
631 },
632 { /* Power3+ */
633 .pvr_mask = 0xffff0000,
634 .pvr_value = 0x00410000,
635 .cpu_name = "Power3 (630+)",
636 .cpu_features = CPU_FTR_COMMON |
637 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
638 CPU_FTR_HPTE_TABLE,
639 .cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
640 .icache_bsize = 128,
641 .dcache_bsize = 128,
642 .num_pmcs = 8,
643 .cpu_setup = __setup_cpu_power3
644 },
645 { /* I-star */
646 .pvr_mask = 0xffff0000,
647 .pvr_value = 0x00360000,
648 .cpu_name = "I-star",
649 .cpu_features = CPU_FTR_COMMON |
650 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
651 CPU_FTR_HPTE_TABLE,
652 .cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
653 .icache_bsize = 128,
654 .dcache_bsize = 128,
655 .num_pmcs = 8,
656 .cpu_setup = __setup_cpu_power3
657 },
658 { /* S-star */
659 .pvr_mask = 0xffff0000,
660 .pvr_value = 0x00370000,
661 .cpu_name = "S-star",
662 .cpu_features = CPU_FTR_COMMON |
663 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
664 CPU_FTR_HPTE_TABLE,
665 .cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
666 .icache_bsize = 128,
667 .dcache_bsize = 128,
668 .num_pmcs = 8,
669 .cpu_setup = __setup_cpu_power3
670 },
671 #endif /* CONFIG_PPC64BRIDGE */
672 #ifdef CONFIG_POWER4
673 { /* Power4 */
674 .pvr_mask = 0xffff0000,
675 .pvr_value = 0x00350000,
676 .cpu_name = "Power4",
677 .cpu_features = CPU_FTR_COMMON |
678 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
679 CPU_FTR_HPTE_TABLE,
680 .cpu_user_features = COMMON_PPC | PPC_FEATURE_64,
681 .icache_bsize = 128,
682 .dcache_bsize = 128,
683 .num_pmcs = 8,
684 .cpu_setup = __setup_cpu_power4
685 },
686 { /* PPC970 */
687 .pvr_mask = 0xffff0000,
688 .pvr_value = 0x00390000,
689 .cpu_name = "PPC970",
690 .cpu_features = CPU_FTR_COMMON |
691 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
692 CPU_FTR_HPTE_TABLE |
693 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MAYBE_CAN_NAP,
694 .cpu_user_features = COMMON_PPC | PPC_FEATURE_64 |
695 PPC_FEATURE_ALTIVEC_COMP,
696 .icache_bsize = 128,
697 .dcache_bsize = 128,
698 .num_pmcs = 8,
699 .cpu_setup = __setup_cpu_ppc970
700 },
701 { /* PPC970FX */
702 .pvr_mask = 0xffff0000,
703 .pvr_value = 0x003c0000,
704 .cpu_name = "PPC970FX",
705 .cpu_features = CPU_FTR_COMMON |
706 CPU_FTR_SPLIT_ID_CACHE | CPU_FTR_USE_TB |
707 CPU_FTR_HPTE_TABLE |
708 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MAYBE_CAN_NAP,
709 .cpu_user_features = COMMON_PPC | PPC_FEATURE_64 |
710 PPC_FEATURE_ALTIVEC_COMP,
711 .icache_bsize = 128,
712 .dcache_bsize = 128,
713 .num_pmcs = 8,
714 .cpu_setup = __setup_cpu_ppc970
715 },
716 #endif /* CONFIG_POWER4 */
717 #ifdef CONFIG_8xx
718 { /* 8xx */
719 .pvr_mask = 0xffff0000,
720 .pvr_value = 0x00500000,
721 .cpu_name = "8xx",
722 /* CPU_FTR_MAYBE_CAN_DOZE is possible,
723 * if the 8xx code is there.... */
724 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
725 CPU_FTR_USE_TB,
726 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
727 .icache_bsize = 16,
728 .dcache_bsize = 16,
729 },
730 #endif /* CONFIG_8xx */
731 #ifdef CONFIG_40x
732 { /* 403GC */
733 .pvr_mask = 0xffffff00,
734 .pvr_value = 0x00200200,
735 .cpu_name = "403GC",
736 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
737 CPU_FTR_USE_TB,
738 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
739 .icache_bsize = 16,
740 .dcache_bsize = 16,
741 },
742 { /* 403GCX */
743 .pvr_mask = 0xffffff00,
744 .pvr_value = 0x00201400,
745 .cpu_name = "403GCX",
746 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
747 CPU_FTR_USE_TB,
748 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
749 .icache_bsize = 16,
750 .dcache_bsize = 16,
751 },
752 { /* 403G ?? */
753 .pvr_mask = 0xffff0000,
754 .pvr_value = 0x00200000,
755 .cpu_name = "403G ??",
756 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
757 CPU_FTR_USE_TB,
758 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
759 .icache_bsize = 16,
760 .dcache_bsize = 16,
761 },
762 { /* 405GP */
763 .pvr_mask = 0xffff0000,
764 .pvr_value = 0x40110000,
765 .cpu_name = "405GP",
766 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
767 CPU_FTR_USE_TB,
768 .cpu_user_features = PPC_FEATURE_32 |
769 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
770 .icache_bsize = 32,
771 .dcache_bsize = 32,
772 },
773 { /* STB 03xxx */
774 .pvr_mask = 0xffff0000,
775 .pvr_value = 0x40130000,
776 .cpu_name = "STB03xxx",
777 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
778 CPU_FTR_USE_TB,
779 .cpu_user_features = PPC_FEATURE_32 |
780 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
781 .icache_bsize = 32,
782 .dcache_bsize = 32,
783 },
784 { /* STB 04xxx */
785 .pvr_mask = 0xffff0000,
786 .pvr_value = 0x41810000,
787 .cpu_name = "STB04xxx",
788 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
789 CPU_FTR_USE_TB,
790 .cpu_user_features = PPC_FEATURE_32 |
791 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
792 .icache_bsize = 32,
793 .dcache_bsize = 32,
794 },
795 { /* NP405L */
796 .pvr_mask = 0xffff0000,
797 .pvr_value = 0x41610000,
798 .cpu_name = "NP405L",
799 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
800 CPU_FTR_USE_TB,
801 .cpu_user_features = PPC_FEATURE_32 |
802 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
803 .icache_bsize = 32,
804 .dcache_bsize = 32,
805 },
806 { /* NP4GS3 */
807 .pvr_mask = 0xffff0000,
808 .pvr_value = 0x40B10000,
809 .cpu_name = "NP4GS3",
810 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
811 CPU_FTR_USE_TB,
812 .cpu_user_features = PPC_FEATURE_32 |
813 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
814 .icache_bsize = 32,
815 .dcache_bsize = 32,
816 },
817 { /* NP405H */
818 .pvr_mask = 0xffff0000,
819 .pvr_value = 0x41410000,
820 .cpu_name = "NP405H",
821 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
822 CPU_FTR_USE_TB,
823 .cpu_user_features = PPC_FEATURE_32 |
824 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
825 .icache_bsize = 32,
826 .dcache_bsize = 32,
827 },
828 { /* 405GPr */
829 .pvr_mask = 0xffff0000,
830 .pvr_value = 0x50910000,
831 .cpu_name = "405GPr",
832 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
833 CPU_FTR_USE_TB,
834 .cpu_user_features = PPC_FEATURE_32 |
835 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
836 .icache_bsize = 32,
837 .dcache_bsize = 32,
838 },
839 { /* STBx25xx */
840 .pvr_mask = 0xffff0000,
841 .pvr_value = 0x51510000,
842 .cpu_name = "STBx25xx",
843 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
844 CPU_FTR_USE_TB,
845 .cpu_user_features = PPC_FEATURE_32 |
846 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
847 .icache_bsize = 32,
848 .dcache_bsize = 32,
849 },
850 { /* 405LP */
851 .pvr_mask = 0xffff0000,
852 .pvr_value = 0x41F10000,
853 .cpu_name = "405LP",
854 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
855 CPU_FTR_USE_TB,
856 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
857 .icache_bsize = 32,
858 .dcache_bsize = 32,
859 },
860 { /* Xilinx Virtex-II Pro */
861 .pvr_mask = 0xffff0000,
862 .pvr_value = 0x20010000,
863 .cpu_name = "Virtex-II Pro",
864 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
865 CPU_FTR_USE_TB,
866 .cpu_user_features = PPC_FEATURE_32 |
867 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
868 .icache_bsize = 32,
869 .dcache_bsize = 32,
870 },
871 { /* 405EP */
872 .pvr_mask = 0xffff0000,
873 .pvr_value = 0x51210000,
874 .cpu_name = "405EP",
875 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
876 CPU_FTR_USE_TB,
877 .cpu_user_features = PPC_FEATURE_32 |
878 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_4xxMAC,
879 .icache_bsize = 32,
880 .dcache_bsize = 32,
881 },
882
883 #endif /* CONFIG_40x */
884 #ifdef CONFIG_44x
885 {
886 .pvr_mask = 0xf0000fff,
887 .pvr_value = 0x40000850,
888 .cpu_name = "440EP Rev. A",
889 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
890 CPU_FTR_USE_TB,
891 .cpu_user_features = COMMON_PPC, /* 440EP has an FPU */
892 .icache_bsize = 32,
893 .dcache_bsize = 32,
894 },
895 {
896 .pvr_mask = 0xf0000fff,
897 .pvr_value = 0x400008d3,
898 .cpu_name = "440EP Rev. B",
899 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
900 CPU_FTR_USE_TB,
901 .cpu_user_features = COMMON_PPC, /* 440EP has an FPU */
902 .icache_bsize = 32,
903 .dcache_bsize = 32,
904 },
905 { /* 440GP Rev. B */
906 .pvr_mask = 0xf0000fff,
907 .pvr_value = 0x40000440,
908 .cpu_name = "440GP Rev. B",
909 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
910 CPU_FTR_USE_TB,
911 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
912 .icache_bsize = 32,
913 .dcache_bsize = 32,
914 },
915 { /* 440GP Rev. C */
916 .pvr_mask = 0xf0000fff,
917 .pvr_value = 0x40000481,
918 .cpu_name = "440GP Rev. C",
919 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
920 CPU_FTR_USE_TB,
921 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
922 .icache_bsize = 32,
923 .dcache_bsize = 32,
924 },
925 { /* 440GX Rev. A */
926 .pvr_mask = 0xf0000fff,
927 .pvr_value = 0x50000850,
928 .cpu_name = "440GX Rev. A",
929 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
930 CPU_FTR_USE_TB,
931 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
932 .icache_bsize = 32,
933 .dcache_bsize = 32,
934 },
935 { /* 440GX Rev. B */
936 .pvr_mask = 0xf0000fff,
937 .pvr_value = 0x50000851,
938 .cpu_name = "440GX Rev. B",
939 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
940 CPU_FTR_USE_TB,
941 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
942 .icache_bsize = 32,
943 .dcache_bsize = 32,
944 },
945 { /* 440GX Rev. C */
946 .pvr_mask = 0xf0000fff,
947 .pvr_value = 0x50000892,
948 .cpu_name = "440GX Rev. C",
949 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
950 CPU_FTR_USE_TB,
951 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
952 .icache_bsize = 32,
953 .dcache_bsize = 32,
954 },
955 { /* 440GX Rev. F */
956 .pvr_mask = 0xf0000fff,
957 .pvr_value = 0x50000894,
958 .cpu_name = "440GX Rev. F",
959 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
960 CPU_FTR_USE_TB,
961 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
962 .icache_bsize = 32,
963 .dcache_bsize = 32,
964 },
965 { /* 440SP Rev. A */
966 .pvr_mask = 0xff000fff,
967 .pvr_value = 0x53000891,
968 .cpu_name = "440SP Rev. A",
969 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
970 CPU_FTR_USE_TB,
971 .cpu_user_features = PPC_FEATURE_32 | PPC_FEATURE_HAS_MMU,
972 .icache_bsize = 32,
973 .dcache_bsize = 32,
974 },
975 #endif /* CONFIG_44x */
976 #ifdef CONFIG_FSL_BOOKE
977 { /* e200z5 */
978 .pvr_mask = 0xfff00000,
979 .pvr_value = 0x81000000,
980 .cpu_name = "e200z5",
981 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
982 .cpu_features = CPU_FTR_USE_TB,
983 .cpu_user_features = PPC_FEATURE_32 |
984 PPC_FEATURE_HAS_MMU | PPC_FEATURE_HAS_EFP_SINGLE |
985 PPC_FEATURE_UNIFIED_CACHE,
986 .dcache_bsize = 32,
987 },
988 { /* e200z6 */
989 .pvr_mask = 0xfff00000,
990 .pvr_value = 0x81100000,
991 .cpu_name = "e200z6",
992 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
993 .cpu_features = CPU_FTR_USE_TB,
994 .cpu_user_features = PPC_FEATURE_32 |
995 PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
996 PPC_FEATURE_HAS_EFP_SINGLE |
997 PPC_FEATURE_UNIFIED_CACHE,
998 .dcache_bsize = 32,
999 },
1000 { /* e500 */
1001 .pvr_mask = 0xffff0000,
1002 .pvr_value = 0x80200000,
1003 .cpu_name = "e500",
1004 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
1005 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
1006 CPU_FTR_USE_TB,
1007 .cpu_user_features = PPC_FEATURE_32 |
1008 PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
1009 PPC_FEATURE_HAS_EFP_SINGLE,
1010 .icache_bsize = 32,
1011 .dcache_bsize = 32,
1012 .num_pmcs = 4,
1013 },
1014 { /* e500v2 */
1015 .pvr_mask = 0xffff0000,
1016 .pvr_value = 0x80210000,
1017 .cpu_name = "e500v2",
1018 /* xxx - galak: add CPU_FTR_MAYBE_CAN_DOZE */
1019 .cpu_features = CPU_FTR_SPLIT_ID_CACHE |
1020 CPU_FTR_USE_TB | CPU_FTR_BIG_PHYS,
1021 .cpu_user_features = PPC_FEATURE_32 |
1022 PPC_FEATURE_HAS_MMU | PPC_FEATURE_SPE_COMP |
1023 PPC_FEATURE_HAS_EFP_SINGLE | PPC_FEATURE_HAS_EFP_DOUBLE,
1024 .icache_bsize = 32,
1025 .dcache_bsize = 32,
1026 .num_pmcs = 4,
1027 },
1028 #endif
1029 #if !CLASSIC_PPC
1030 { /* default match */
1031 .pvr_mask = 0x00000000,
1032 .pvr_value = 0x00000000,
1033 .cpu_name = "(generic PPC)",
1034 .cpu_features = CPU_FTR_COMMON,
1035 .cpu_user_features = PPC_FEATURE_32,
1036 .icache_bsize = 32,
1037 .dcache_bsize = 32,
1038 }
1039 #endif /* !CLASSIC_PPC */
1040 };
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