arch/ppc/platforms/4xx/ibmnp405h.c

   1 /*
   2  * arch/ppc/platforms/4xx/ibmnp405h.c
   3  *
   4  * Author: Armin Kuster <akuster@mvista.com>
   5  *
   6  * 2000-2002 (c) MontaVista, Software, Inc.  This file is licensed under
   7  * the terms of the GNU General Public License version 2.  This program
   8  * is licensed "as is" without any warranty of any kind, whether express
   9  * or implied.
  10  */
  11
  12 #include <linux/config.h>
  13 #include <linux/init.h>
  14 #include <asm/ocp.h>
  15 #include <platforms/4xx/ibmnp405h.h>
  16
  17 static struct ocp_func_emac_data ibmnp405h_emac0_def = {
  18         .rgmii_idx      = -1,           /* No RGMII */
  19         .rgmii_mux      = -1,           /* No RGMII */
  20         .zmii_idx       = 0,            /* ZMII device index */
  21         .zmii_mux       = 0,            /* ZMII input of this EMAC */
  22         .mal_idx        = 0,            /* MAL device index */
  23         .mal_rx_chan    = 0,            /* MAL rx channel number */
  24         .mal_tx_chan    = 0,            /* MAL tx channel number */
  25         .wol_irq        = 41,           /* WOL interrupt number */
  26         .mdio_idx       = -1,           /* No shared MDIO */
  27         .tah_idx        = -1,           /* No TAH */
  28 };
  29
  30 static struct ocp_func_emac_data ibmnp405h_emac1_def = {
  31         .rgmii_idx      = -1,           /* No RGMII */
  32         .rgmii_mux      = -1,           /* No RGMII */
  33         .zmii_idx       = 0,            /* ZMII device index */
  34         .zmii_mux       = 1,            /* ZMII input of this EMAC */
  35         .mal_idx        = 0,            /* MAL device index */
  36         .mal_rx_chan    = 1,            /* MAL rx channel number */
  37         .mal_tx_chan    = 2,            /* MAL tx channel number */
  38         .wol_irq        = 41,           /* WOL interrupt number */
  39         .mdio_idx       = -1,           /* No shared MDIO */
  40         .tah_idx        = -1,           /* No TAH */
  41 };
  42 static struct ocp_func_emac_data ibmnp405h_emac2_def = {
  43         .rgmii_idx      = -1,           /* No RGMII */
  44         .rgmii_mux      = -1,           /* No RGMII */
  45         .zmii_idx       = 0,            /* ZMII device index */
  46         .zmii_mux       = 2,            /* ZMII input of this EMAC */
  47         .mal_idx        = 0,            /* MAL device index */
  48         .mal_rx_chan    = 2,            /* MAL rx channel number */
  49         .mal_tx_chan    = 4,            /* MAL tx channel number */
  50         .wol_irq        = 41,           /* WOL interrupt number */
  51         .mdio_idx       = -1,           /* No shared MDIO */
  52         .tah_idx        = -1,           /* No TAH */
  53 };
  54 static struct ocp_func_emac_data ibmnp405h_emac3_def = {
  55         .rgmii_idx      = -1,           /* No RGMII */
  56         .rgmii_mux      = -1,           /* No RGMII */
  57         .zmii_idx       = 0,            /* ZMII device index */
  58         .zmii_mux       = 3,            /* ZMII input of this EMAC */
  59         .mal_idx        = 0,            /* MAL device index */
  60         .mal_rx_chan    = 3,            /* MAL rx channel number */
  61         .mal_tx_chan    = 6,            /* MAL tx channel number */
  62         .wol_irq        = 41,           /* WOL interrupt number */
  63         .mdio_idx       = -1,           /* No shared MDIO */
  64         .tah_idx        = -1,           /* No TAH */
  65 };
  66 OCP_SYSFS_EMAC_DATA()
  67
  68 static struct ocp_func_mal_data ibmnp405h_mal0_def = {
  69         .num_tx_chans   = 8,            /* Number of TX channels */
  70         .num_rx_chans   = 4,            /* Number of RX channels */
  71         .txeob_irq      = 17,           /* TX End Of Buffer IRQ  */
  72         .rxeob_irq      = 18,           /* RX End Of Buffer IRQ  */
  73         .txde_irq       = 46,           /* TX Descriptor Error IRQ */
  74         .rxde_irq       = 47,           /* RX Descriptor Error IRQ */
  75         .serr_irq       = 45,           /* MAL System Error IRQ    */
  76         .dcr_base       = DCRN_MAL_BASE /* MAL0_CFG DCR number */
  77 };
  78 OCP_SYSFS_MAL_DATA()
  79
  80 static struct ocp_func_iic_data ibmnp405h_iic0_def = {
  81         .fast_mode      = 0,            /* Use standad mode (100Khz) */
  82 };
  83 OCP_SYSFS_IIC_DATA()
  84
  85 struct ocp_def core_ocp[] = {
  86         { .vendor       = OCP_VENDOR_IBM,
  87           .function     = OCP_FUNC_OPB,
  88           .index        = 0,
  89           .paddr        = 0xEF600000,
  90           .irq          = OCP_IRQ_NA,
  91           .pm           = OCP_CPM_NA,
  92         },
  93         { .vendor       = OCP_VENDOR_IBM,
  94           .function     = OCP_FUNC_16550,
  95           .index        = 0,
  96           .paddr        = UART0_IO_BASE,
  97           .irq          = UART0_INT,
  98           .pm           = IBM_CPM_UART0
  99         },
 100         { .vendor       = OCP_VENDOR_IBM,
 101           .function     = OCP_FUNC_16550,
 102           .index        = 1,
 103           .paddr        = UART1_IO_BASE,
 104           .irq          = UART1_INT,
 105           .pm           = IBM_CPM_UART1
 106         },
 107         { .vendor       = OCP_VENDOR_IBM,
 108           .function     = OCP_FUNC_IIC,
 109           .paddr        = 0xEF600500,
 110           .irq          = 2,
 111           .pm           = IBM_CPM_IIC0,
 112           .additions    = &ibmnp405h_iic0_def,
 113           .show         = &ocp_show_iic_data
 114         },
 115         { .vendor       = OCP_VENDOR_IBM,
 116           .function     = OCP_FUNC_GPIO,
 117           .paddr        = 0xEF600700,
 118           .irq          = OCP_IRQ_NA,
 119           .pm           = IBM_CPM_GPIO0
 120         },
 121         { .vendor       = OCP_VENDOR_IBM,
 122           .function     = OCP_FUNC_MAL,
 123           .paddr        = OCP_PADDR_NA,
 124           .irq          = OCP_IRQ_NA,
 125           .pm           = OCP_CPM_NA,
 126           .additions    = &ibmnp405h_mal0_def,
 127           .show         = &ocp_show_mal_data,
 128         },
 129         { .vendor       = OCP_VENDOR_IBM,
 130           .function     = OCP_FUNC_EMAC,
 131           .index        = 0,
 132           .paddr        = EMAC0_BASE,
 133           .irq          = 37,
 134           .pm           = IBM_CPM_EMAC0,
 135           .additions    = &ibmnp405h_emac0_def,
 136           .show         = &ocp_show_emac_data,
 137         },
 138         { .vendor       = OCP_VENDOR_IBM,
 139           .function     = OCP_FUNC_EMAC,
 140           .index        = 1,
 141           .paddr        = 0xEF600900,
 142           .irq          = 38,
 143           .pm           = IBM_CPM_EMAC1,
 144           .additions    = &ibmnp405h_emac1_def,
 145           .show         = &ocp_show_emac_data,
 146         },
 147         { .vendor       = OCP_VENDOR_IBM,
 148           .function     = OCP_FUNC_EMAC,
 149           .index        = 2,
 150           .paddr        = 0xEF600a00,
 151           .irq          = 39,
 152           .pm           = IBM_CPM_EMAC2,
 153           .additions    = &ibmnp405h_emac2_def,
 154           .show         = &ocp_show_emac_data,
 155         },
 156         { .vendor       = OCP_VENDOR_IBM,
 157           .function     = OCP_FUNC_EMAC,
 158           .index        = 3,
 159           .paddr        = 0xEF600b00,
 160           .irq          = 40,
 161           .pm           = IBM_CPM_EMAC3,
 162           .additions    = &ibmnp405h_emac3_def,
 163           .show         = &ocp_show_emac_data,
 164         },
 165         { .vendor       = OCP_VENDOR_IBM,
 166           .function     = OCP_FUNC_ZMII,
 167           .paddr        = 0xEF600C10,
 168           .irq          = OCP_IRQ_NA,
 169           .pm           = OCP_CPM_NA,
 170         },
 171         { .vendor       = OCP_VENDOR_INVALID
 172         }
 173 };