arch/ppc/platforms/chrp_pci.c

   1 /*
   2  * CHRP pci routines.
   3  */
   4
   5 #include <linux/config.h>
   6 #include <linux/kernel.h>
   7 #include <linux/pci.h>
   8 #include <linux/delay.h>
   9 #include <linux/string.h>
  10 #include <linux/init.h>
  11 #include <linux/ide.h>
  12
  13 #include <asm/io.h>
  14 #include <asm/pgtable.h>
  15 #include <asm/irq.h>
  16 #include <asm/hydra.h>
  17 #include <asm/prom.h>
  18 #include <asm/gg2.h>
  19 #include <asm/machdep.h>
  20 #include <asm/sections.h>
  21 #include <asm/pci-bridge.h>
  22 #include <asm/open_pic.h>
  23
  24 /* LongTrail */
  25 void __iomem *gg2_pci_config_base;
  26
  27 /*
  28  * The VLSI Golden Gate II has only 512K of PCI configuration space, so we
  29  * limit the bus number to 3 bits
  30  */
  31
  32 int __chrp gg2_read_config(struct pci_bus *bus, unsigned int devfn, int off,
  33                            int len, u32 *val)
  34 {
  35         volatile void __iomem *cfg_data;
  36         struct pci_controller *hose = bus->sysdata;
  37
  38         if (bus->number > 7)
  39                 return PCIBIOS_DEVICE_NOT_FOUND;
  40         /*
  41          * Note: the caller has already checked that off is
  42          * suitably aligned and that len is 1, 2 or 4.
  43          */
  44         cfg_data = hose->cfg_data + ((bus->number<<16) | (devfn<<8) | off);
  45         switch (len) {
  46         case 1:
  47                 *val =  in_8(cfg_data);
  48                 break;
  49         case 2:
  50                 *val = in_le16(cfg_data);
  51                 break;
  52         default:
  53                 *val = in_le32(cfg_data);
  54                 break;
  55         }
  56         return PCIBIOS_SUCCESSFUL;
  57 }
  58
  59 int __chrp gg2_write_config(struct pci_bus *bus, unsigned int devfn, int off,
  60                             int len, u32 val)
  61 {
  62         volatile void __iomem *cfg_data;
  63         struct pci_controller *hose = bus->sysdata;
  64
  65         if (bus->number > 7)
  66                 return PCIBIOS_DEVICE_NOT_FOUND;
  67         /*
  68          * Note: the caller has already checked that off is
  69          * suitably aligned and that len is 1, 2 or 4.
  70          */
  71         cfg_data = hose->cfg_data + ((bus->number<<16) | (devfn<<8) | off);
  72         switch (len) {
  73         case 1:
  74                 out_8(cfg_data, val);
  75                 break;
  76         case 2:
  77                 out_le16(cfg_data, val);
  78                 break;
  79         default:
  80                 out_le32(cfg_data, val);
  81                 break;
  82         }
  83         return PCIBIOS_SUCCESSFUL;
  84 }
  85
  86 static struct pci_ops gg2_pci_ops =
  87 {
  88         gg2_read_config,
  89         gg2_write_config
  90 };
  91
  92 /*
  93  * Access functions for PCI config space using RTAS calls.
  94  */
  95 int __chrp
  96 rtas_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
  97                  int len, u32 *val)
  98 {
  99         struct pci_controller *hose = bus->sysdata;
 100         unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
 101                 | (((bus->number - hose->first_busno) & 0xff) << 16)
 102                 | (hose->index << 24);
 103         unsigned long ret = ~0UL;
 104         int rval;
 105
 106         rval = call_rtas("read-pci-config", 2, 2, &ret, addr, len);
 107         *val = ret;
 108         return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL;
 109 }
 110
 111 int __chrp
 112 rtas_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
 113                   int len, u32 val)
 114 {
 115         struct pci_controller *hose = bus->sysdata;
 116         unsigned long addr = (offset & 0xff) | ((devfn & 0xff) << 8)
 117                 | (((bus->number - hose->first_busno) & 0xff) << 16)
 118                 | (hose->index << 24);
 119         int rval;
 120
 121         rval = call_rtas("write-pci-config", 3, 1, NULL, addr, len, val);
 122         return rval? PCIBIOS_DEVICE_NOT_FOUND: PCIBIOS_SUCCESSFUL;
 123 }
 124
 125 static struct pci_ops rtas_pci_ops =
 126 {
 127         rtas_read_config,
 128         rtas_write_config
 129 };
 130
 131 volatile struct Hydra __iomem *Hydra = NULL;
 132
 133 int __init
 134 hydra_init(void)
 135 {
 136         struct device_node *np;
 137
 138         np = find_devices("mac-io");
 139         if (np == NULL || np->n_addrs == 0)
 140                 return 0;
 141         Hydra = ioremap(np->addrs[0].address, np->addrs[0].size);
 142         printk("Hydra Mac I/O at %x\n", np->addrs[0].address);
 143         printk("Hydra Feature_Control was %x",
 144                in_le32(&Hydra->Feature_Control));
 145         out_le32(&Hydra->Feature_Control, (HYDRA_FC_SCC_CELL_EN |
 146                                            HYDRA_FC_SCSI_CELL_EN |
 147                                            HYDRA_FC_SCCA_ENABLE |
 148                                            HYDRA_FC_SCCB_ENABLE |
 149                                            HYDRA_FC_ARB_BYPASS |
 150                                            HYDRA_FC_MPIC_ENABLE |
 151                                            HYDRA_FC_SLOW_SCC_PCLK |
 152                                            HYDRA_FC_MPIC_IS_MASTER));
 153         printk(", now %x\n", in_le32(&Hydra->Feature_Control));
 154         return 1;
 155 }
 156
 157 void __init
 158 chrp_pcibios_fixup(void)
 159 {
 160         struct pci_dev *dev = NULL;
 161         struct device_node *np;
 162
 163         /* PCI interrupts are controlled by the OpenPIC */
 164         for_each_pci_dev(dev) {
 165                 np = pci_device_to_OF_node(dev);
 166                 if ((np != 0) && (np->n_intrs > 0) && (np->intrs[0].line != 0))
 167                         dev->irq = np->intrs[0].line;
 168                 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, dev->irq);
 169         }
 170 }
 171
 172 #define PRG_CL_RESET_VALID 0x00010000
 173
 174 static void __init
 175 setup_python(struct pci_controller *hose, struct device_node *dev)
 176 {
 177         u32 __iomem *reg;
 178         u32 val;
 179         unsigned long addr = dev->addrs[0].address;
 180
 181         setup_indirect_pci(hose, addr + 0xf8000, addr + 0xf8010);
 182
 183         /* Clear the magic go-slow bit */
 184         reg = ioremap(dev->addrs[0].address + 0xf6000, 0x40);
 185         val = in_be32(&reg[12]);
 186         if (val & PRG_CL_RESET_VALID) {
 187                 out_be32(&reg[12], val & ~PRG_CL_RESET_VALID);
 188                 in_be32(&reg[12]);
 189         }
 190         iounmap(reg);
 191 }
 192
 193 /* Marvell Discovery II based Pegasos 2 */
 194 static void __init setup_peg2(struct pci_controller *hose, struct device_node *dev)
 195 {
 196         struct device_node *root = find_path_device("/");
 197         struct device_node *rtas;
 198
 199         rtas = of_find_node_by_name (root, "rtas");
 200         if (rtas) {
 201                 hose->ops = &rtas_pci_ops;
 202         } else {
 203                 printk ("RTAS supporting Pegasos OF not found, please upgrade"
 204                         " your firmware\n");
 205         }
 206         pci_assign_all_busses = 1;
 207 }
 208
 209 void __init
 210 chrp_find_bridges(void)
 211 {
 212         struct device_node *dev;
 213         int *bus_range;
 214         int len, index = -1;
 215         struct pci_controller *hose;
 216         unsigned int *dma;
 217         char *model, *machine;
 218         int is_longtrail = 0, is_mot = 0, is_pegasos = 0;
 219         struct device_node *root = find_path_device("/");
 220
 221         /*
 222          * The PCI host bridge nodes on some machines don't have
 223          * properties to adequately identify them, so we have to
 224          * look at what sort of machine this is as well.
 225          */
 226         machine = get_property(root, "model", NULL);
 227         if (machine != NULL) {
 228                 is_longtrail = strncmp(machine, "IBM,LongTrail", 13) == 0;
 229                 is_mot = strncmp(machine, "MOT", 3) == 0;
 230                 if (strncmp(machine, "Pegasos2", 8) == 0)
 231                         is_pegasos = 2;
 232                 else if (strncmp(machine, "Pegasos", 7) == 0)
 233                         is_pegasos = 1;
 234         }
 235         for (dev = root->child; dev != NULL; dev = dev->sibling) {
 236                 if (dev->type == NULL || strcmp(dev->type, "pci") != 0)
 237                         continue;
 238                 ++index;
 239                 /* The GG2 bridge on the LongTrail doesn't have an address */
 240                 if (dev->n_addrs < 1 && !is_longtrail) {
 241                         printk(KERN_WARNING "Can't use %s: no address\n",
 242                                dev->full_name);
 243                         continue;
 244                 }
 245                 bus_range = (int *) get_property(dev, "bus-range", &len);
 246                 if (bus_range == NULL || len < 2 * sizeof(int)) {
 247                         printk(KERN_WARNING "Can't get bus-range for %s\n",
 248                                 dev->full_name);
 249                         continue;
 250                 }
 251                 if (bus_range[1] == bus_range[0])
 252                         printk(KERN_INFO "PCI bus %d", bus_range[0]);
 253                 else
 254                         printk(KERN_INFO "PCI buses %d..%d",
 255                                bus_range[0], bus_range[1]);
 256                 printk(" controlled by %s", dev->type);
 257                 if (dev->n_addrs > 0)
 258                         printk(" at %x", dev->addrs[0].address);
 259                 printk("\n");
 260
 261                 hose = pcibios_alloc_controller();
 262                 if (!hose) {
 263                         printk("Can't allocate PCI controller structure for %s\n",
 264                                 dev->full_name);
 265                         continue;
 266                 }
 267                 hose->arch_data = dev;
 268                 hose->first_busno = bus_range[0];
 269                 hose->last_busno = bus_range[1];
 270
 271                 model = get_property(dev, "model", NULL);
 272                 if (model == NULL)
 273                         model = "<none>";
 274                 if (device_is_compatible(dev, "IBM,python")) {
 275                         setup_python(hose, dev);
 276                 } else if (is_mot
 277                            || strncmp(model, "Motorola, Grackle", 17) == 0) {
 278                         setup_grackle(hose);
 279                 } else if (is_longtrail) {
 280                         void __iomem *p = ioremap(GG2_PCI_CONFIG_BASE, 0x80000);
 281                         hose->ops = &gg2_pci_ops;
 282                         hose->cfg_data = p;
 283                         gg2_pci_config_base = p;
 284                 } else if (is_pegasos == 1) {
 285                         setup_indirect_pci(hose, 0xfec00cf8, 0xfee00cfc);
 286                 } else if (is_pegasos == 2) {
 287                         setup_peg2(hose, dev);
 288                 } else {
 289                         printk("No methods for %s (model %s), using RTAS\n",
 290                                dev->full_name, model);
 291                         hose->ops = &rtas_pci_ops;
 292                 }
 293
 294                 pci_process_bridge_OF_ranges(hose, dev, index == 0);
 295
 296                 /* check the first bridge for a property that we can
 297                    use to set pci_dram_offset */
 298                 dma = (unsigned int *)
 299                         get_property(dev, "ibm,dma-ranges", &len);
 300                 if (index == 0 && dma != NULL && len >= 6 * sizeof(*dma)) {
 301                         pci_dram_offset = dma[2] - dma[3];
 302                         printk("pci_dram_offset = %lx\n", pci_dram_offset);
 303                 }
 304         }
 305
 306         /* Do not fixup interrupts from OF tree on pegasos */
 307         if (is_pegasos == 0)
 308                 ppc_md.pcibios_fixup = chrp_pcibios_fixup;
 309 }