3 * Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
4 * Rewritten by Cort Dougan (cort@cs.nmt.edu) for PReP
5 * Copyright (C) 1996 Cort Dougan <cort@cs.nmt.edu>
6 * Adapted for Power Macintosh by Paul Mackerras.
7 * Low-level exception handlers and MMU support
8 * rewritten by Paul Mackerras.
9 * Copyright (C) 1996 Paul Mackerras.
10 * MPC8xx modifications Copyright (C) 1997 Dan Malek (dmalek@jlc.net).
12 * This file contains the system call entry code, context switch
13 * code, and exception/interrupt return code for PowerPC.
15 * This program is free software; you can redistribute it and/or
16 * modify it under the terms of the GNU General Public License
17 * as published by the Free Software Foundation; either version
18 * 2 of the License, or (at your option) any later version.
21 #include <linux/config.h>
22 #include <linux/errno.h>
23 #include <asm/unistd.h>
24 #include <asm/processor.h>
27 #include <asm/thread_info.h>
28 #include <asm/ppc_asm.h>
29 #include <asm/asm-offsets.h>
30 #include <asm/cputable.h>
32 #ifdef CONFIG_PPC_ISERIES
33 #define DO_SOFT_DISABLE
41 .tc .sys_call_table[TC],.sys_call_table
43 /* This value is used to mark exception frames on the stack. */
45 .tc ID_72656773_68657265[TC],0x7265677368657265
52 .globl system_call_common
56 addi r1,r1,-INT_FRAME_SIZE
90 addi r9,r1,STACK_FRAME_OVERHEAD
91 ld r11,exception_marker@toc(r2)
92 std r11,-16(r9) /* "regshere" marker */
93 #ifdef CONFIG_PPC_ISERIES
94 /* Hack for handling interrupts when soft-enabling on iSeries */
95 cmpdi cr1,r0,0x5555 /* syscall 0x5555 */
96 andi. r10,r12,MSR_PR /* from kernel */
97 crand 4*cr0+eq,4*cr1+eq,4*cr0+eq
98 beq hardware_interrupt_entry
99 lbz r10,PACAPROCENABLED(r13)
111 addi r9,r1,STACK_FRAME_OVERHEAD
113 clrrdi r11,r1,THREAD_SHIFT
115 andi. r11,r10,_TIF_SYSCALL_T_OR_A
117 syscall_dotrace_cont:
118 cmpldi 0,r0,NR_syscalls
121 system_call: /* label this so stack traces look sane */
123 * Need to vector to 32 Bit or default sys_call_table here,
124 * based on caller's run-mode / personality.
126 ld r11,.SYS_CALL_TABLE@toc(2)
127 andi. r10,r10,_TIF_32BIT
129 addi r11,r11,8 /* use 32-bit syscall entries */
138 ldx r10,r11,r0 /* Fetch system call handler [ptr] */
140 bctrl /* Call handler */
145 bl .do_show_syscall_exit
148 clrrdi r12,r1,THREAD_SHIFT
150 /* disable interrupts so current_thread_info()->flags can't change,
151 and so that we don't get interrupted after loading SRR0/1. */
161 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP|_TIF_SIGPENDING|_TIF_NEED_RESCHED|_TIF_RESTOREALL|_TIF_SAVE_NVGPRS|_TIF_NOERROR|_TIF_RESTORE_SIGMASK)
162 bne- syscall_exit_work
168 stdcx. r0,0,r1 /* to clear the reservation */
171 beq- 1f /* only restore r13 if */
172 ld r13,GPR13(r1) /* returning to usermode */
176 mtmsrd r11,1 /* clear MSR.RI */
183 b . /* prevent speculative execution */
186 oris r5,r5,0x1000 /* Set SO bit in CR */
191 /* Traced system call support */
194 addi r3,r1,STACK_FRAME_OVERHEAD
195 bl .do_syscall_trace_enter
196 ld r0,GPR0(r1) /* Restore original registers */
203 addi r9,r1,STACK_FRAME_OVERHEAD
204 clrrdi r10,r1,THREAD_SHIFT
206 b syscall_dotrace_cont
213 /* If TIF_RESTOREALL is set, don't scribble on either r3 or ccr.
214 If TIF_NOERROR is set, just save r3 as it is. */
216 andi. r0,r9,_TIF_RESTOREALL
218 cmpld r3,r11 /* r10 is -LAST_ERRNO */
220 andi. r0,r9,_TIF_NOERROR
224 oris r5,r5,0x1000 /* Set SO bit in CR */
227 2: andi. r0,r9,(_TIF_PERSYSCALL_MASK)
230 /* Clear per-syscall TIF flags if any are set, but _leave_
231 _TIF_SAVE_NVGPRS set in r9 since we haven't dealt with that
234 li r11,_TIF_PERSYSCALL_MASK
235 addi r12,r12,TI_FLAGS
240 subi r12,r12,TI_FLAGS
243 /* Anything else left to do? */
244 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP|_TIF_SAVE_NVGPRS)
245 beq .ret_from_except_lite
247 /* Re-enable interrupts */
252 andi. r0,r9,_TIF_SAVE_NVGPRS
255 /* If tracing, re-enable interrupts and do it */
256 save_user_nvgprs_cont:
257 andi. r0,r9,(_TIF_SYSCALL_T_OR_A|_TIF_SINGLESTEP)
260 addi r3,r1,STACK_FRAME_OVERHEAD
261 bl .do_syscall_trace_leave
263 clrrdi r12,r1,THREAD_SHIFT
265 /* Disable interrupts again and handle other work if any */
271 b .ret_from_except_lite
273 /* Save non-volatile GPRs, if not already saved. */
285 ld r10,TI_SIGFRAME(r12)
286 andi. r0,r9,_TIF_32BIT
287 beq- save_user_nvgprs_64
289 /* 32-bit save to userspace */
291 .macro savewords start, end
292 1: stw \start,4*(\start)(r10)
293 .section __ex_table,"a"
295 .llong 1b,save_user_nvgprs_fault
298 savewords "(\start+1)",\end
302 b save_user_nvgprs_cont
305 /* 64-bit save to userspace */
307 .macro savelongs start, end
308 1: std \start,8*(\start)(r10)
309 .section __ex_table,"a"
311 .llong 1b,save_user_nvgprs_fault
314 savelongs "(\start+1)",\end
318 b save_user_nvgprs_cont
320 save_user_nvgprs_fault:
321 li r3,11 /* SIGSEGV */
325 clrrdi r12,r1,THREAD_SHIFT
327 b save_user_nvgprs_cont
330 * The sigsuspend and rt_sigsuspend system calls can call do_signal
331 * and thus put the process into the stopped state where we might
332 * want to examine its user state with ptrace. Therefore we need
333 * to save all the nonvolatile registers (r14 - r31) before calling
334 * the C code. Similarly, fork, vfork and clone need the full
335 * register state on the stack so that it can be copied to the child.
353 _GLOBAL(ret_from_fork)
360 * This routine switches between two different tasks. The process
361 * state of one is saved on its kernel stack. Then the state
362 * of the other is restored from its kernel stack. The memory
363 * management hardware is updated to the second process's state.
364 * Finally, we can return to the second process, via ret_from_except.
365 * On entry, r3 points to the THREAD for the current task, r4
366 * points to the THREAD for the new task.
368 * Note: there are two ways to get to the "going out" portion
369 * of this code; either by coming in via the entry (_switch)
370 * or via "fork" which must set up an environment equivalent
371 * to the "_switch" path. If you change this you'll have to change
372 * the fork code also.
374 * The code which creates the new task context is in 'copy_thread'
375 * in arch/powerpc/kernel/process.c
381 stdu r1,-SWITCH_FRAME_SIZE(r1)
382 /* r3-r13 are caller saved -- Cort */
385 mflr r20 /* Return to switch caller */
388 #ifdef CONFIG_ALTIVEC
390 oris r0,r0,MSR_VEC@h /* Disable altivec */
391 mfspr r24,SPRN_VRSAVE /* save vrsave register value */
392 std r24,THREAD_VRSAVE(r3)
393 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
394 #endif /* CONFIG_ALTIVEC */
403 std r1,KSP(r3) /* Set old stack pointer */
406 /* We need a sync somewhere here to make sure that if the
407 * previous task gets rescheduled on another CPU, it sees all
408 * stores it has performed on this one.
411 #endif /* CONFIG_SMP */
413 addi r6,r4,-THREAD /* Convert THREAD to 'current' */
414 std r6,PACACURRENT(r13) /* Set new 'current' */
416 ld r8,KSP(r4) /* new stack pointer */
418 clrrdi r6,r8,28 /* get its ESID */
419 clrrdi r9,r1,28 /* get current sp ESID */
420 clrldi. r0,r6,2 /* is new ESID c00000000? */
421 cmpd cr1,r6,r9 /* or is new ESID the same as current ESID? */
423 beq 2f /* if yes, don't slbie it */
425 /* Bolt in the new stack SLB entry */
426 ld r7,KSP_VSID(r4) /* Get new stack's VSID */
427 oris r0,r6,(SLB_ESID_V)@h
428 ori r0,r0,(SLB_NUM_BOLTED-1)@l
430 slbie r6 /* Workaround POWER5 < DD2.1 issue */
435 END_FTR_SECTION_IFSET(CPU_FTR_SLB)
436 clrrdi r7,r8,THREAD_SHIFT /* base of new stack */
437 /* Note: this uses SWITCH_FRAME_SIZE rather than INT_FRAME_SIZE
438 because we don't need to leave the 288-byte ABI gap at the
439 top of the kernel stack. */
440 addi r7,r7,THREAD_SIZE-SWITCH_FRAME_SIZE
442 mr r1,r8 /* start using new stack pointer */
443 std r7,PACAKSAVE(r13)
448 #ifdef CONFIG_ALTIVEC
450 ld r0,THREAD_VRSAVE(r4)
451 mtspr SPRN_VRSAVE,r0 /* if G4, restore VRSAVE reg */
452 END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
453 #endif /* CONFIG_ALTIVEC */
455 /* r3-r13 are destroyed -- Cort */
459 /* convert old thread to its task_struct for return value */
461 ld r7,_NIP(r1) /* Return to _switch caller in new task */
463 addi r1,r1,SWITCH_FRAME_SIZE
467 _GLOBAL(ret_from_except)
470 bne .ret_from_except_lite
473 _GLOBAL(ret_from_except_lite)
475 * Disable interrupts so that current_thread_info()->flags
476 * can't change between when we test it and when we return
477 * from the interrupt.
479 mfmsr r10 /* Get current interrupt state */
480 rldicl r9,r10,48,1 /* clear MSR_EE */
482 mtmsrd r9,1 /* Update machine state */
484 #ifdef CONFIG_PREEMPT
485 clrrdi r9,r1,THREAD_SHIFT /* current_thread_info() */
486 li r0,_TIF_NEED_RESCHED /* bits to check */
489 /* Move MSR_PR bit in r3 to _TIF_SIGPENDING position in r0 */
490 rlwimi r0,r3,32+TIF_SIGPENDING-MSR_PR_LG,_TIF_SIGPENDING
491 and. r0,r4,r0 /* check NEED_RESCHED and maybe SIGPENDING */
494 #else /* !CONFIG_PREEMPT */
495 ld r3,_MSR(r1) /* Returning to user mode? */
497 beq restore /* if not, just restore regs and return */
499 /* Check current_thread_info()->flags */
500 clrrdi r9,r1,THREAD_SHIFT
502 andi. r0,r4,_TIF_USER_WORK_MASK
507 #ifdef CONFIG_PPC_ISERIES
511 /* Check for pending interrupts (iSeries) */
512 ld r3,PACALPPACAPTR(r13)
513 ld r3,LPPACAANYINT(r3)
515 beq+ 4f /* skip do_IRQ if no interrupts */
518 stb r3,PACAPROCENABLED(r13) /* ensure we are soft-disabled */
520 mtmsrd r10 /* hard-enable again */
521 addi r3,r1,STACK_FRAME_OVERHEAD
523 b .ret_from_except_lite /* loop back and handle more */
525 4: stb r5,PACAPROCENABLED(r13)
535 * r13 is our per cpu area, only restore it if we are returning to
550 stdcx. r0,0,r1 /* to clear the reservation */
572 b . /* prevent speculative execution */
574 /* Note: this must change if we start using the TIF_NOTIFY_RESUME bit */
576 #ifdef CONFIG_PREEMPT
577 andi. r0,r3,MSR_PR /* Returning to user mode? */
579 /* Check that preempt_count() == 0 and interrupts are enabled */
580 lwz r8,TI_PREEMPT(r9)
582 #ifdef CONFIG_PPC_ISERIES
588 crandc eq,cr1*4+eq,eq
590 /* here we are preempting the current task */
592 #ifdef CONFIG_PPC_ISERIES
594 stb r0,PACAPROCENABLED(r13)
597 mtmsrd r10,1 /* reenable interrupts */
600 clrrdi r9,r1,THREAD_SHIFT
601 rldicl r10,r10,48,1 /* disable interrupts again */
605 andi. r0,r4,_TIF_NEED_RESCHED
611 /* Enable interrupts */
615 andi. r0,r4,_TIF_NEED_RESCHED
618 b .ret_from_except_lite
622 addi r4,r1,STACK_FRAME_OVERHEAD
627 addi r3,r1,STACK_FRAME_OVERHEAD
628 bl .unrecoverable_exception
631 #ifdef CONFIG_PPC_RTAS
633 * On CHRP, the Run-Time Abstraction Services (RTAS) have to be
634 * called with the MMU off.
636 * In addition, we need to be in 32b mode, at least for now.
638 * Note: r3 is an input parameter to rtas, so don't trash it...
643 stdu r1,-RTAS_FRAME_SIZE(r1) /* Save SP and create stack space. */
645 /* Because RTAS is running in 32b mode, it clobbers the high order half
646 * of all registers that it saves. We therefore save those registers
647 * RTAS might touch to the stack. (r0, r3-r13 are caller saved)
649 SAVE_GPR(2, r1) /* Save the TOC */
650 SAVE_GPR(13, r1) /* Save paca */
651 SAVE_8GPRS(14, r1) /* Save the non-volatiles */
652 SAVE_10GPRS(22, r1) /* ditto */
669 /* There is no way it is acceptable to get here with interrupts enabled,
670 * check it with the asm equivalent of WARN_ON
675 .section __bug_table,"a"
676 .llong 1b,__LINE__ + 0x1000000, 1f, 2f
680 2: .asciz "enter_rtas"
683 /* Unfortunately, the stack pointer and the MSR are also clobbered,
684 * so they are saved in the PACA which allows us to restore
685 * our original state after RTAS returns.
688 std r6,PACASAVEDMSR(r13)
690 /* Setup our real return addr */
691 LOAD_REG_ADDR(r4,.rtas_return_loc)
692 clrldi r4,r4,2 /* convert to realmode address */
696 ori r0,r0,MSR_EE|MSR_SE|MSR_BE|MSR_RI
700 rldicr r9,r9,MSR_SF_LG,(63-MSR_SF_LG)
701 ori r9,r9,MSR_IR|MSR_DR|MSR_FE0|MSR_FE1|MSR_FP
704 sync /* disable interrupts so SRR0/1 */
705 mtmsrd r0 /* don't get trashed */
707 LOAD_REG_ADDR(r4, rtas)
708 ld r5,RTASENTRY(r4) /* get the rtas->entry value */
709 ld r4,RTASBASE(r4) /* get the rtas->base value */
714 b . /* prevent speculative execution */
716 _STATIC(rtas_return_loc)
717 /* relocation is off at this point */
718 mfspr r4,SPRN_SPRG3 /* Get PACA */
719 clrldi r4,r4,2 /* convert to realmode address */
727 ld r1,PACAR1(r4) /* Restore our SP */
728 LOAD_REG_IMMEDIATE(r3,.rtas_restore_regs)
729 ld r4,PACASAVEDMSR(r4) /* Restore our MSR */
734 b . /* prevent speculative execution */
736 _STATIC(rtas_restore_regs)
737 /* relocation is on at this point */
738 REST_GPR(2, r1) /* Restore the TOC */
739 REST_GPR(13, r1) /* Restore paca */
740 REST_8GPRS(14, r1) /* Restore the non-volatiles */
741 REST_10GPRS(22, r1) /* ditto */
760 addi r1,r1,RTAS_FRAME_SIZE /* Unstack our frame */
761 ld r0,16(r1) /* get return address */
764 blr /* return to caller */
766 #endif /* CONFIG_PPC_RTAS */
768 #ifdef CONFIG_PPC_MULTIPLATFORM
773 stdu r1,-PROM_FRAME_SIZE(r1) /* Save SP and create stack space */
775 /* Because PROM is running in 32b mode, it clobbers the high order half
776 * of all registers that it saves. We therefore save those registers
777 * PROM might touch to the stack. (r0, r3-r13 are caller saved)
800 /* Get the PROM entrypoint */
804 /* Switch MSR to 32 bits mode
808 rldicr r12,r12,MSR_SF_LG,(63-MSR_SF_LG)
811 rldicr r12,r12,MSR_ISF_LG,(63-MSR_ISF_LG)
816 /* Restore arguments & enter PROM here... */
820 /* Just make sure that r1 top 32 bits didn't get
825 /* Restore the MSR (back to 64 bits) */
830 /* Restore other registers */
850 addi r1,r1,PROM_FRAME_SIZE
855 #endif /* CONFIG_PPC_MULTIPLATFORM */