arch/ppc/platforms/85xx/mpc85xx_ads_common.c

   1 /*
   2  * MPC85xx ADS board common routines
   3  *
   4  * Maintainer: Kumar Gala <galak@kernel.crashing.org>
   5  *
   6  * Copyright 2004 Freescale Semiconductor Inc.
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  */
  13
  14 #include <linux/config.h>
  15 #include <linux/stddef.h>
  16 #include <linux/kernel.h>
  17 #include <linux/init.h>
  18 #include <linux/errno.h>
  19 #include <linux/reboot.h>
  20 #include <linux/pci.h>
  21 #include <linux/kdev_t.h>
  22 #include <linux/major.h>
  23 #include <linux/console.h>
  24 #include <linux/delay.h>
  25 #include <linux/seq_file.h>
  26 #include <linux/serial.h>
  27 #include <linux/module.h>
  28
  29 #include <asm/system.h>
  30 #include <asm/pgtable.h>
  31 #include <asm/page.h>
  32 #include <asm/atomic.h>
  33 #include <asm/time.h>
  34 #include <asm/io.h>
  35 #include <asm/machdep.h>
  36 #include <asm/open_pic.h>
  37 #include <asm/bootinfo.h>
  38 #include <asm/pci-bridge.h>
  39 #include <asm/mpc85xx.h>
  40 #include <asm/irq.h>
  41 #include <asm/immap_85xx.h>
  42 #include <asm/ppc_sys.h>
  43
  44 #include <mm/mmu_decl.h>
  45
  46 #include <syslib/ppc85xx_rio.h>
  47
  48 #include <platforms/85xx/mpc85xx_ads_common.h>
  49
  50 #ifndef CONFIG_PCI
  51 unsigned long isa_io_base = 0;
  52 unsigned long isa_mem_base = 0;
  53 #endif
  54
  55 extern unsigned long total_memory;      /* in mm/init */
  56
  57 unsigned char __res[sizeof (bd_t)];
  58
  59 /* Internal interrupts are all Level Sensitive, and Positive Polarity */
  60 static u_char mpc85xx_ads_openpic_initsenses[] __initdata = {
  61         MPC85XX_INTERNAL_IRQ_SENSES,
  62         0x0,                                            /* External  0: */
  63 #if defined(CONFIG_PCI)
  64         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 1: PCI slot 0 */
  65         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 2: PCI slot 1 */
  66         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 3: PCI slot 2 */
  67         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 4: PCI slot 3 */
  68 #else
  69         0x0,                            /* External  1: */
  70         0x0,                            /* External  2: */
  71         0x0,                            /* External  3: */
  72         0x0,                            /* External  4: */
  73 #endif
  74         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 5: PHY */
  75         0x0,                            /* External  6: */
  76         (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE),      /* External 7: PHY */
  77         0x0,                            /* External  8: */
  78         0x0,                            /* External  9: */
  79         0x0,                            /* External 10: */
  80         0x0,                            /* External 11: */
  81 };
  82
  83 /* ************************************************************************ */
  84 int
  85 mpc85xx_ads_show_cpuinfo(struct seq_file *m)
  86 {
  87         uint pvid, svid, phid1;
  88         uint memsize = total_memory;
  89         bd_t *binfo = (bd_t *) __res;
  90         unsigned int freq;
  91
  92         /* get the core frequency */
  93         freq = binfo->bi_intfreq;
  94
  95         pvid = mfspr(SPRN_PVR);
  96         svid = mfspr(SPRN_SVR);
  97
  98         seq_printf(m, "Vendor\t\t: Freescale Semiconductor\n");
  99         seq_printf(m, "Machine\t\t: mpc%sads\n", cur_ppc_sys_spec->ppc_sys_name);
 100         seq_printf(m, "clock\t\t: %dMHz\n", freq / 1000000);
 101         seq_printf(m, "PVR\t\t: 0x%x\n", pvid);
 102         seq_printf(m, "SVR\t\t: 0x%x\n", svid);
 103
 104         /* Display cpu Pll setting */
 105         phid1 = mfspr(SPRN_HID1);
 106         seq_printf(m, "PLL setting\t: 0x%x\n", ((phid1 >> 24) & 0x3f));
 107
 108         /* Display the amount of memory */
 109         seq_printf(m, "Memory\t\t: %d MB\n", memsize / (1024 * 1024));
 110
 111         return 0;
 112 }
 113
 114 void __init
 115 mpc85xx_ads_init_IRQ(void)
 116 {
 117         bd_t *binfo = (bd_t *) __res;
 118         /* Determine the Physical Address of the OpenPIC regs */
 119         phys_addr_t OpenPIC_PAddr =
 120             binfo->bi_immr_base + MPC85xx_OPENPIC_OFFSET;
 121         OpenPIC_Addr = ioremap(OpenPIC_PAddr, MPC85xx_OPENPIC_SIZE);
 122         OpenPIC_InitSenses = mpc85xx_ads_openpic_initsenses;
 123         OpenPIC_NumInitSenses = sizeof (mpc85xx_ads_openpic_initsenses);
 124
 125         /* Skip reserved space and internal sources */
 126         openpic_set_sources(0, 32, OpenPIC_Addr + 0x10200);
 127         /* Map PIC IRQs 0-11 */
 128         openpic_set_sources(48, 12, OpenPIC_Addr + 0x10000);
 129
 130         /* we let openpic interrupts starting from an offset, to
 131          * leave space for cascading interrupts underneath.
 132          */
 133         openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET);
 134
 135         return;
 136 }
 137
 138 #ifdef CONFIG_PCI
 139 /*
 140  * interrupt routing
 141  */
 142
 143 int
 144 mpc85xx_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
 145 {
 146         static char pci_irq_table[][4] =
 147             /*
 148              * This is little evil, but works around the fact
 149              * that revA boards have IDSEL starting at 18
 150              * and others boards (older) start at 12
 151              *
 152              *      PCI IDSEL/INTPIN->INTLINE
 153              *       A      B      C      D
 154              */
 155         {
 156                 {PIRQA, PIRQB, PIRQC, PIRQD},   /* IDSEL 2 */
 157                 {PIRQD, PIRQA, PIRQB, PIRQC},
 158                 {PIRQC, PIRQD, PIRQA, PIRQB},
 159                 {PIRQB, PIRQC, PIRQD, PIRQA},   /* IDSEL 5 */
 160                 {0, 0, 0, 0},   /* -- */
 161                 {0, 0, 0, 0},   /* -- */
 162                 {0, 0, 0, 0},   /* -- */
 163                 {0, 0, 0, 0},   /* -- */
 164                 {0, 0, 0, 0},   /* -- */
 165                 {0, 0, 0, 0},   /* -- */
 166                 {PIRQA, PIRQB, PIRQC, PIRQD},   /* IDSEL 12 */
 167                 {PIRQD, PIRQA, PIRQB, PIRQC},
 168                 {PIRQC, PIRQD, PIRQA, PIRQB},
 169                 {PIRQB, PIRQC, PIRQD, PIRQA},   /* IDSEL 15 */
 170                 {0, 0, 0, 0},   /* -- */
 171                 {0, 0, 0, 0},   /* -- */
 172                 {PIRQA, PIRQB, PIRQC, PIRQD},   /* IDSEL 18 */
 173                 {PIRQD, PIRQA, PIRQB, PIRQC},
 174                 {PIRQC, PIRQD, PIRQA, PIRQB},
 175                 {PIRQB, PIRQC, PIRQD, PIRQA},   /* IDSEL 21 */
 176         };
 177
 178         const long min_idsel = 2, max_idsel = 21, irqs_per_slot = 4;
 179         return PCI_IRQ_TABLE_LOOKUP;
 180 }
 181
 182 int
 183 mpc85xx_exclude_device(u_char bus, u_char devfn)
 184 {
 185         if (bus == 0 && PCI_SLOT(devfn) == 0)
 186                 return PCIBIOS_DEVICE_NOT_FOUND;
 187         else
 188                 return PCIBIOS_SUCCESSFUL;
 189 }
 190
 191 #endif /* CONFIG_PCI */
 192
 193 #ifdef CONFIG_RAPIDIO
 194 void platform_rio_init(void)
 195 {
 196         /* 512MB RIO LAW at 0xc0000000 */
 197         mpc85xx_rio_setup(0xc0000000, 0x20000000);
 198 }
 199 #endif /* CONFIG_RAPIDIO */