arch/ppc/platforms/85xx/mpc85xx_cds_common.h

   1 /*
   2  * MPC85xx CDS board definitions
   3  *
   4  * Maintainer: Kumar Gala <galak@kernel.crashing.org>
   5  *
   6  * Copyright 2004 Freescale Semiconductor, Inc
   7  *
   8  * This program is free software; you can redistribute  it and/or modify it
   9  * under  the terms of  the GNU General  Public License as published by the
  10  * Free Software Foundation;  either version 2 of the  License, or (at your
  11  * option) any later version.
  12  *
  13  */
  14
  15 #ifndef __MACH_MPC85XX_CDS_H__
  16 #define __MACH_MPC85XX_CDS_H__
  17
  18 #include <linux/config.h>
  19 #include <linux/serial.h>
  20 #include <asm/ppcboot.h>
  21 #include <linux/initrd.h>
  22 #include <syslib/ppc85xx_setup.h>
  23
  24 #define BOARD_CCSRBAR           ((uint)0xe0000000)
  25 #define CCSRBAR_SIZE            ((uint)1024*1024)
  26
  27 /* CADMUS info */
  28 #define CADMUS_BASE (0xf8004000)
  29 #define CADMUS_SIZE (256)
  30 #define CM_VER  (0)
  31 #define CM_CSR  (1)
  32 #define CM_RST  (2)
  33
  34 /* CDS NVRAM/RTC */
  35 #define CDS_RTC_ADDR    (0xf8000000)
  36 #define CDS_RTC_SIZE    (8 * 1024)
  37
  38 /* PCI config */
  39 #define PCI1_CFG_ADDR_OFFSET    (0x8000)
  40 #define PCI1_CFG_DATA_OFFSET    (0x8004)
  41
  42 #define PCI2_CFG_ADDR_OFFSET    (0x9000)
  43 #define PCI2_CFG_DATA_OFFSET    (0x9004)
  44
  45 /* PCI interrupt controller */
  46 #define PIRQ0A                   MPC85xx_IRQ_EXT0
  47 #define PIRQ0B                   MPC85xx_IRQ_EXT1
  48 #define PIRQ0C                   MPC85xx_IRQ_EXT2
  49 #define PIRQ0D                   MPC85xx_IRQ_EXT3
  50 #define PIRQ1A                   MPC85xx_IRQ_EXT11
  51
  52 /* PCI 1 memory map */
  53 #define MPC85XX_PCI1_LOWER_IO        0x00000000
  54 #define MPC85XX_PCI1_UPPER_IO        0x00ffffff
  55
  56 #define MPC85XX_PCI1_LOWER_MEM       0x80000000
  57 #define MPC85XX_PCI1_UPPER_MEM       0x9fffffff
  58
  59 #define MPC85XX_PCI1_IO_BASE         0xe2000000
  60 #define MPC85XX_PCI1_MEM_OFFSET      0x00000000
  61
  62 #define MPC85XX_PCI1_IO_SIZE         0x01000000
  63
  64 /* PCI 2 memory map */
  65 /* Note: the standard PPC fixups will cause IO space to get bumped by
  66  * hose->io_base_virt - isa_io_base => MPC85XX_PCI1_IO_SIZE */
  67 #define MPC85XX_PCI2_LOWER_IO        0x00000000
  68 #define MPC85XX_PCI2_UPPER_IO        0x00ffffff
  69
  70 #define MPC85XX_PCI2_LOWER_MEM       0xa0000000
  71 #define MPC85XX_PCI2_UPPER_MEM       0xbfffffff
  72
  73 #define MPC85XX_PCI2_IO_BASE         0xe3000000
  74 #define MPC85XX_PCI2_MEM_OFFSET      0x00000000
  75
  76 #define MPC85XX_PCI2_IO_SIZE         0x01000000
  77
  78 #define NR_8259_INTS                 16
  79 #define CPM_IRQ_OFFSET               NR_8259_INTS
  80
  81 #endif /* __MACH_MPC85XX_CDS_H__ */