2 * WindRiver PowerQUICC III SBC85xx board common routines
4 * Copyright 2002, 2003 Motorola Inc.
5 * Copyright 2004 Red Hat, Inc.
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License as published by the
9 * Free Software Foundation; either version 2 of the License, or (at your
10 * option) any later version.
13 #include <linux/config.h>
14 #include <linux/stddef.h>
15 #include <linux/kernel.h>
16 #include <linux/init.h>
17 #include <linux/errno.h>
18 #include <linux/reboot.h>
19 #include <linux/pci.h>
20 #include <linux/kdev_t.h>
21 #include <linux/major.h>
22 #include <linux/console.h>
23 #include <linux/delay.h>
24 #include <linux/seq_file.h>
25 #include <linux/serial.h>
26 #include <linux/module.h>
28 #include <asm/system.h>
29 #include <asm/pgtable.h>
31 #include <asm/atomic.h>
34 #include <asm/machdep.h>
35 #include <asm/open_pic.h>
36 #include <asm/bootinfo.h>
37 #include <asm/pci-bridge.h>
38 #include <asm/mpc85xx.h>
40 #include <asm/immap_85xx.h>
41 #include <asm/ppc_sys.h>
43 #include <mm/mmu_decl.h>
45 #include <platforms/85xx/sbc85xx.h>
47 unsigned char __res
[sizeof (bd_t
)];
50 unsigned long isa_io_base
= 0;
51 unsigned long isa_mem_base
= 0;
52 unsigned long pci_dram_offset
= 0;
55 extern unsigned long total_memory
; /* in mm/init */
57 /* Internal interrupts are all Level Sensitive, and Positive Polarity */
58 static u_char sbc8560_openpic_initsenses
[] __initdata
= {
59 MPC85XX_INTERNAL_IRQ_SENSES
,
60 0x0, /* External 0: */
61 0x0, /* External 1: */
62 #if defined(CONFIG_PCI)
63 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_NEGATIVE
), /* External 2: PCI slot 0 */
64 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_NEGATIVE
), /* External 3: PCI slot 1 */
65 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_NEGATIVE
), /* External 4: PCI slot 2 */
66 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_NEGATIVE
), /* External 5: PCI slot 3 */
68 0x0, /* External 2: */
69 0x0, /* External 3: */
70 0x0, /* External 4: */
71 0x0, /* External 5: */
73 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_NEGATIVE
), /* External 6: PHY */
74 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_NEGATIVE
), /* External 7: PHY */
75 0x0, /* External 8: */
76 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* External 9: PHY */
77 (IRQ_SENSE_LEVEL
| IRQ_POLARITY_POSITIVE
), /* External 10: PHY */
78 0x0, /* External 11: */
81 /* ************************************************************************ */
83 sbc8560_show_cpuinfo(struct seq_file
*m
)
85 uint pvid
, svid
, phid1
;
86 uint memsize
= total_memory
;
87 bd_t
*binfo
= (bd_t
*) __res
;
90 /* get the core frequency */
91 freq
= binfo
->bi_intfreq
;
93 pvid
= mfspr(SPRN_PVR
);
94 svid
= mfspr(SPRN_SVR
);
96 seq_printf(m
, "Vendor\t\t: Wind River\n");
97 seq_printf(m
, "Machine\t\t: SBC%s\n", cur_ppc_sys_spec
->ppc_sys_name
);
98 seq_printf(m
, "clock\t\t: %dMHz\n", freq
/ 1000000);
99 seq_printf(m
, "PVR\t\t: 0x%x\n", pvid
);
100 seq_printf(m
, "SVR\t\t: 0x%x\n", svid
);
102 /* Display cpu Pll setting */
103 phid1
= mfspr(SPRN_HID1
);
104 seq_printf(m
, "PLL setting\t: 0x%x\n", ((phid1
>> 24) & 0x3f));
106 /* Display the amount of memory */
107 seq_printf(m
, "Memory\t\t: %d MB\n", memsize
/ (1024 * 1024));
113 sbc8560_init_IRQ(void)
115 bd_t
*binfo
= (bd_t
*) __res
;
116 /* Determine the Physical Address of the OpenPIC regs */
117 phys_addr_t OpenPIC_PAddr
=
118 binfo
->bi_immr_base
+ MPC85xx_OPENPIC_OFFSET
;
119 OpenPIC_Addr
= ioremap(OpenPIC_PAddr
, MPC85xx_OPENPIC_SIZE
);
120 OpenPIC_InitSenses
= sbc8560_openpic_initsenses
;
121 OpenPIC_NumInitSenses
= sizeof (sbc8560_openpic_initsenses
);
123 /* Skip reserved space and internal sources */
124 openpic_set_sources(0, 32, OpenPIC_Addr
+ 0x10200);
125 /* Map PIC IRQs 0-11 */
126 openpic_set_sources(48, 12, OpenPIC_Addr
+ 0x10000);
128 /* we let openpic interrupts starting from an offset, to
129 * leave space for cascading interrupts underneath.
131 openpic_init(MPC85xx_OPENPIC_IRQ_OFFSET
);
141 int mpc85xx_map_irq(struct pci_dev
*dev
, unsigned char idsel
,
144 static char pci_irq_table
[][4] =
146 * PCI IDSEL/INTPIN->INTLINE
150 {PIRQA
, PIRQB
, PIRQC
, PIRQD
},
151 {PIRQD
, PIRQA
, PIRQB
, PIRQC
},
152 {PIRQC
, PIRQD
, PIRQA
, PIRQB
},
153 {PIRQB
, PIRQC
, PIRQD
, PIRQA
},
156 const long min_idsel
= 12, max_idsel
= 15, irqs_per_slot
= 4;
157 return PCI_IRQ_TABLE_LOOKUP
;
160 int mpc85xx_exclude_device(u_char bus
, u_char devfn
)
162 if (bus
== 0 && PCI_SLOT(devfn
) == 0)
163 return PCIBIOS_DEVICE_NOT_FOUND
;
165 return PCIBIOS_SUCCESSFUL
;
167 #endif /* CONFIG_PCI */