2 * linux/arch/arm/mach-pxa/pxa3xx.c
4 * code specific to pxa3xx aka Monahans
6 * Copyright (C) 2006 Marvell International Ltd.
8 * 2007-09-02: eric miao <eric.miao@marvell.com>
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License version 2 as
13 * published by the Free Software Foundation.
16 #include <linux/module.h>
17 #include <linux/kernel.h>
18 #include <linux/init.h>
20 #include <linux/platform_device.h>
21 #include <linux/irq.h>
23 #include <asm/hardware.h>
24 #include <asm/arch/pxa3xx-regs.h>
25 #include <asm/arch/ohci.h>
26 #include <asm/arch/pm.h>
27 #include <asm/arch/dma.h>
28 #include <asm/arch/ssp.h>
34 /* Crystal clock: 13MHz */
35 #define BASE_CLK 13000000
37 /* Ring Oscillator Clock: 60MHz */
38 #define RO_CLK 60000000
40 #define ACCR_D0CS (1 << 26)
42 /* crystal frequency to static memory controller multiplier (SMCFS) */
43 static unsigned char smcfs_mult
[8] = { 6, 0, 8, 0, 0, 16, };
45 /* crystal frequency to HSIO bus frequency multiplier (HSS) */
46 static unsigned char hss_mult
[4] = { 8, 12, 16, 0 };
49 * Get the clock frequency as reflected by CCSR and the turbo flag.
50 * We assume these values have been applied via a fcs.
51 * If info is not 0 we also display the current settings.
53 unsigned int pxa3xx_get_clk_frequency_khz(int info
)
55 unsigned long acsr
, xclkcfg
;
56 unsigned int t
, xl
, xn
, hss
, ro
, XL
, XN
, CLK
, HSS
;
58 /* Read XCLKCFG register turbo bit */
59 __asm__
__volatile__("mrc\tp14, 0, %0, c6, c0, 0" : "=r"(xclkcfg
));
65 xn
= (acsr
>> 8) & 0x7;
66 hss
= (acsr
>> 14) & 0x3;
71 ro
= acsr
& ACCR_D0CS
;
73 CLK
= (ro
) ? RO_CLK
: ((t
) ? XN
: XL
);
74 HSS
= (ro
) ? RO_CLK
: hss_mult
[hss
] * BASE_CLK
;
77 pr_info("RO Mode clock: %d.%02dMHz (%sactive)\n",
78 RO_CLK
/ 1000000, (RO_CLK
% 1000000) / 10000,
80 pr_info("Run Mode clock: %d.%02dMHz (*%d)\n",
81 XL
/ 1000000, (XL
% 1000000) / 10000, xl
);
82 pr_info("Turbo Mode clock: %d.%02dMHz (*%d, %sactive)\n",
83 XN
/ 1000000, (XN
% 1000000) / 10000, xn
,
85 pr_info("HSIO bus clock: %d.%02dMHz\n",
86 HSS
/ 1000000, (HSS
% 1000000) / 10000);
93 * Return the current static memory controller clock frequency
96 unsigned int pxa3xx_get_memclk_frequency_10khz(void)
99 unsigned int smcfs
, clk
= 0;
103 smcfs
= (acsr
>> 23) & 0x7;
104 clk
= (acsr
& ACCR_D0CS
) ? RO_CLK
: smcfs_mult
[smcfs
] * BASE_CLK
;
106 return (clk
/ 10000);
110 * Return the current HSIO bus clock frequency
112 static unsigned long clk_pxa3xx_hsio_getrate(struct clk
*clk
)
115 unsigned int hss
, hsio_clk
;
119 hss
= (acsr
>> 14) & 0x3;
120 hsio_clk
= (acsr
& ACCR_D0CS
) ? RO_CLK
: hss_mult
[hss
] * BASE_CLK
;
125 static void clk_pxa3xx_cken_enable(struct clk
*clk
)
127 unsigned long mask
= 1ul << (clk
->cken
& 0x1f);
139 static void clk_pxa3xx_cken_disable(struct clk
*clk
)
141 unsigned long mask
= 1ul << (clk
->cken
& 0x1f);
153 static const struct clkops clk_pxa3xx_cken_ops
= {
154 .enable
= clk_pxa3xx_cken_enable
,
155 .disable
= clk_pxa3xx_cken_disable
,
158 static const struct clkops clk_pxa3xx_hsio_ops
= {
159 .enable
= clk_pxa3xx_cken_enable
,
160 .disable
= clk_pxa3xx_cken_disable
,
161 .getrate
= clk_pxa3xx_hsio_getrate
,
164 #define PXA3xx_CKEN(_name, _cken, _rate, _delay, _dev) \
168 .ops = &clk_pxa3xx_cken_ops, \
170 .cken = CKEN_##_cken, \
174 #define PXA3xx_CK(_name, _cken, _ops, _dev) \
179 .cken = CKEN_##_cken, \
182 static struct clk pxa3xx_clks
[] = {
183 PXA3xx_CK("LCDCLK", LCD
, &clk_pxa3xx_hsio_ops
, &pxa_device_fb
.dev
),
184 PXA3xx_CK("CAMCLK", CAMERA
, &clk_pxa3xx_hsio_ops
, NULL
),
186 PXA3xx_CKEN("UARTCLK", FFUART
, 14857000, 1, &pxa_device_ffuart
.dev
),
187 PXA3xx_CKEN("UARTCLK", BTUART
, 14857000, 1, &pxa_device_btuart
.dev
),
188 PXA3xx_CKEN("UARTCLK", STUART
, 14857000, 1, NULL
),
190 PXA3xx_CKEN("I2CCLK", I2C
, 32842000, 0, &pxa_device_i2c
.dev
),
191 PXA3xx_CKEN("UDCCLK", UDC
, 48000000, 5, &pxa_device_udc
.dev
),
194 void __init
pxa3xx_init_irq(void)
196 /* enable CP6 access */
198 __asm__
__volatile__("mrc p15, 0, %0, c15, c1, 0\n": "=r"(value
));
200 __asm__
__volatile__("mcr p15, 0, %0, c15, c1, 0\n": :"r"(value
));
204 pxa_init_irq_gpio(128);
208 * device registration specific to PXA3xx.
211 static struct platform_device
*devices
[] __initdata
= {
224 static int __init
pxa3xx_init(void)
228 if (cpu_is_pxa3xx()) {
229 clks_register(pxa3xx_clks
, ARRAY_SIZE(pxa3xx_clks
));
231 if ((ret
= pxa_init_dma(32)))
234 return platform_add_devices(devices
, ARRAY_SIZE(devices
));
239 subsys_initcall(pxa3xx_init
);