arch/arm/mach-pxa/time.c

   1 /*
   2  * arch/arm/mach-pxa/time.c
   3  *
   4  * PXA clocksource, clockevents, and OST interrupt handlers.
   5  * Copyright (c) 2007 by Bill Gatliff <bgat@billgatliff.com>.
   6  *
   7  * Derived from Nicolas Pitre's PXA timer handler Copyright (c) 2001
   8  * by MontaVista Software, Inc.  (Nico, your code rocks!)
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License version 2 as
  12  * published by the Free Software Foundation.
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/interrupt.h>
  18 #include <linux/clockchips.h>
  19 #include <linux/sched.h>
  20
  21 #include <asm/div64.h>
  22 #include <asm/cnt32_to_63.h>
  23 #include <asm/mach/irq.h>
  24 #include <asm/mach/time.h>
  25 #include <asm/arch/pxa-regs.h>
  26 #include <asm/mach-types.h>
  27
  28 /*
  29  * This is PXA's sched_clock implementation. This has a resolution
  30  * of at least 308 ns and a maximum value of 208 days.
  31  *
  32  * The return value is guaranteed to be monotonic in that range as
  33  * long as there is always less than 582 seconds between successive
  34  * calls to sched_clock() which should always be the case in practice.
  35  */
  36
  37 #define OSCR2NS_SCALE_FACTOR 10
  38
  39 static unsigned long oscr2ns_scale;
  40
  41 static void __init set_oscr2ns_scale(unsigned long oscr_rate)
  42 {
  43         unsigned long long v = 1000000000ULL << OSCR2NS_SCALE_FACTOR;
  44         do_div(v, oscr_rate);
  45         oscr2ns_scale = v;
  46         /*
  47          * We want an even value to automatically clear the top bit
  48          * returned by cnt32_to_63() without an additional run time
  49          * instruction. So if the LSB is 1 then round it up.
  50          */
  51         if (oscr2ns_scale & 1)
  52                 oscr2ns_scale++;
  53 }
  54
  55 unsigned long long sched_clock(void)
  56 {
  57         unsigned long long v = cnt32_to_63(OSCR);
  58         return (v * oscr2ns_scale) >> OSCR2NS_SCALE_FACTOR;
  59 }
  60
  61
  62 static irqreturn_t
  63 pxa_ost0_interrupt(int irq, void *dev_id)
  64 {
  65         int next_match;
  66         struct clock_event_device *c = dev_id;
  67
  68         if (c->mode == CLOCK_EVT_MODE_ONESHOT) {
  69                 /* Disarm the compare/match, signal the event. */
  70                 OIER &= ~OIER_E0;
  71                 OSSR = OSSR_M0;
  72                 c->event_handler(c);
  73         } else if (c->mode == CLOCK_EVT_MODE_PERIODIC) {
  74                 /* Call the event handler as many times as necessary
  75                  * to recover missed events, if any (if we update
  76                  * OSMR0 and OSCR0 is still ahead of us, we've missed
  77                  * the event).  As we're dealing with that, re-arm the
  78                  * compare/match for the next event.
  79                  *
  80                  * HACK ALERT:
  81                  *
  82                  * There's a latency between the instruction that
  83                  * writes to OSMR0 and the actual commit to the
  84                  * physical hardware, because the CPU doesn't (have
  85                  * to) run at bus speed, there's a write buffer
  86                  * between the CPU and the bus, etc. etc.  So if the
  87                  * target OSCR0 is "very close", to the OSMR0 load
  88                  * value, the update to OSMR0 might not get to the
  89                  * hardware in time and we'll miss that interrupt.
  90                  *
  91                  * To be safe, if the new OSMR0 is "very close" to the
  92                  * target OSCR0 value, we call the event_handler as
  93                  * though the event actually happened.  According to
  94                  * Nico's comment in the previous version of this
  95                  * code, experience has shown that 6 OSCR ticks is
  96                  * "very close" but he went with 8.  We will use 16,
  97                  * based on the results of testing on PXA270.
  98                  *
  99                  * To be doubly sure, we also tell clkevt via
 100                  * clockevents_register_device() not to ask for
 101                  * anything that might put us "very close".
 102          */
 103 #define MIN_OSCR_DELTA 16
 104                 do {
 105                         OSSR = OSSR_M0;
 106                         next_match = (OSMR0 += LATCH);
 107                         c->event_handler(c);
 108                 } while (((signed long)(next_match - OSCR) <= MIN_OSCR_DELTA)
 109                          && (c->mode == CLOCK_EVT_MODE_PERIODIC));
 110         }
 111
 112         return IRQ_HANDLED;
 113 }
 114
 115 static int
 116 pxa_osmr0_set_next_event(unsigned long delta, struct clock_event_device *dev)
 117 {
 118         unsigned long flags, next, oscr;
 119
 120         raw_local_irq_save(flags);
 121         OIER |= OIER_E0;
 122         next = OSCR + delta;
 123         OSMR0 = next;
 124         oscr = OSCR;
 125         raw_local_irq_restore(flags);
 126
 127         return (signed)(next - oscr) <= MIN_OSCR_DELTA ? -ETIME : 0;
 128 }
 129
 130 static void
 131 pxa_osmr0_set_mode(enum clock_event_mode mode, struct clock_event_device *dev)
 132 {
 133         unsigned long irqflags;
 134
 135         switch (mode) {
 136         case CLOCK_EVT_MODE_PERIODIC:
 137                 raw_local_irq_save(irqflags);
 138                 OSSR = OSSR_M0;
 139                 OIER |= OIER_E0;
 140                 OSMR0 = OSCR + LATCH;
 141                 raw_local_irq_restore(irqflags);
 142                 break;
 143
 144         case CLOCK_EVT_MODE_ONESHOT:
 145                 raw_local_irq_save(irqflags);
 146                 OIER &= ~OIER_E0;
 147                 OSSR = OSSR_M0;
 148                 raw_local_irq_restore(irqflags);
 149                 break;
 150
 151         case CLOCK_EVT_MODE_UNUSED:
 152         case CLOCK_EVT_MODE_SHUTDOWN:
 153                 /* initializing, released, or preparing for suspend */
 154                 raw_local_irq_save(irqflags);
 155                 OIER &= ~OIER_E0;
 156                 OSSR = OSSR_M0;
 157                 raw_local_irq_restore(irqflags);
 158                 break;
 159
 160         case CLOCK_EVT_MODE_RESUME:
 161                 break;
 162         }
 163 }
 164
 165 static struct clock_event_device ckevt_pxa_osmr0 = {
 166         .name           = "osmr0",
 167         .features       = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
 168         .shift          = 32,
 169         .rating         = 200,
 170         .cpumask        = CPU_MASK_CPU0,
 171         .set_next_event = pxa_osmr0_set_next_event,
 172         .set_mode       = pxa_osmr0_set_mode,
 173 };
 174
 175 static cycle_t pxa_read_oscr(void)
 176 {
 177         return OSCR;
 178 }
 179
 180 static struct clocksource cksrc_pxa_oscr0 = {
 181         .name           = "oscr0",
 182         .rating         = 200,
 183         .read           = pxa_read_oscr,
 184         .mask           = CLOCKSOURCE_MASK(32),
 185         .shift          = 20,
 186         .flags          = CLOCK_SOURCE_IS_CONTINUOUS,
 187 };
 188
 189 static struct irqaction pxa_ost0_irq = {
 190         .name           = "ost0",
 191         .flags          = IRQF_DISABLED | IRQF_TIMER | IRQF_IRQPOLL,
 192         .handler        = pxa_ost0_interrupt,
 193         .dev_id         = &ckevt_pxa_osmr0,
 194 };
 195
 196 static void __init pxa_timer_init(void)
 197 {
 198         unsigned long clock_tick_rate;
 199
 200         OIER = 0;
 201         OSSR = OSSR_M0 | OSSR_M1 | OSSR_M2 | OSSR_M3;
 202
 203         if (cpu_is_pxa21x() || cpu_is_pxa25x())
 204                 clock_tick_rate = 3686400;
 205         else if (machine_is_mainstone())
 206                 clock_tick_rate = 3249600;
 207         else
 208                 clock_tick_rate = 3250000;
 209
 210         set_oscr2ns_scale(clock_tick_rate);
 211
 212         ckevt_pxa_osmr0.mult =
 213                 div_sc(clock_tick_rate, NSEC_PER_SEC, ckevt_pxa_osmr0.shift);
 214         ckevt_pxa_osmr0.max_delta_ns =
 215                 clockevent_delta2ns(0x7fffffff, &ckevt_pxa_osmr0);
 216         ckevt_pxa_osmr0.min_delta_ns =
 217                 clockevent_delta2ns(MIN_OSCR_DELTA, &ckevt_pxa_osmr0) + 1;
 218
 219         cksrc_pxa_oscr0.mult =
 220                 clocksource_hz2mult(clock_tick_rate, cksrc_pxa_oscr0.shift);
 221
 222         setup_irq(IRQ_OST0, &pxa_ost0_irq);
 223
 224         clocksource_register(&cksrc_pxa_oscr0);
 225         clockevents_register_device(&ckevt_pxa_osmr0);
 226 }
 227
 228 #ifdef CONFIG_PM
 229 static unsigned long osmr[4], oier;
 230
 231 static void pxa_timer_suspend(void)
 232 {
 233         osmr[0] = OSMR0;
 234         osmr[1] = OSMR1;
 235         osmr[2] = OSMR2;
 236         osmr[3] = OSMR3;
 237         oier = OIER;
 238 }
 239
 240 static void pxa_timer_resume(void)
 241 {
 242         OSMR0 = osmr[0];
 243         OSMR1 = osmr[1];
 244         OSMR2 = osmr[2];
 245         OSMR3 = osmr[3];
 246         OIER = oier;
 247
 248         /*
 249          * OSCR0 is the system timer, which has to increase
 250          * monotonically until it rolls over in hardware.  The value
 251          * (OSMR0 - LATCH) is OSCR0 at the most recent system tick,
 252          * which is a handy value to restore to OSCR0.
 253          */
 254         OSCR = OSMR0 - LATCH;
 255 }
 256 #else
 257 #define pxa_timer_suspend NULL
 258 #define pxa_timer_resume NULL
 259 #endif
 260
 261 struct sys_timer pxa_timer = {
 262         .init           = pxa_timer_init,
 263         .suspend        = pxa_timer_suspend,
 264         .resume         = pxa_timer_resume,
 265 };