arch/ppc/syslib/harrier.c

   1 /*
   2  * Motorola MCG Harrier northbridge/memory controller support
   3  *
   4  * Author: Dale Farnsworth
   5  *         dale.farnsworth@mvista.com
   6  *
   7  * 2001 (c) MontaVista, Software, Inc.  This file is licensed under
   8  * the terms of the GNU General Public License version 2.  This program
   9  * is licensed "as is" without any warranty of any kind, whether express
  10  * or implied.
  11  */
  12 #include <linux/kernel.h>
  13 #include <linux/init.h>
  14 #include <linux/pci.h>
  15 #include <linux/harrier_defs.h>
  16
  17 #include <asm/byteorder.h>
  18 #include <asm/io.h>
  19 #include <asm/irq.h>
  20 #include <asm/pci.h>
  21 #include <asm/pci-bridge.h>
  22 #include <asm/open_pic.h>
  23 #include <asm/harrier.h>
  24
  25 /* define defaults for inbound windows */
  26 #define HARRIER_ITAT_DEFAULT            (HARRIER_ITAT_ENA | \
  27                                          HARRIER_ITAT_MEM | \
  28                                          HARRIER_ITAT_WPE | \
  29                                          HARRIER_ITAT_GBL)
  30
  31 #define HARRIER_MPAT_DEFAULT            (HARRIER_ITAT_ENA | \
  32                                          HARRIER_ITAT_MEM | \
  33                                          HARRIER_ITAT_WPE | \
  34                                          HARRIER_ITAT_GBL)
  35
  36 /*
  37  * Initialize the inbound window size on a non-monarch harrier.
  38  */
  39 void __init harrier_setup_nonmonarch(uint ppc_reg_base, uint in0_size)
  40 {
  41         u16 temps;
  42         u32 temp;
  43
  44         if (in0_size > HARRIER_ITSZ_2GB) {
  45                 printk
  46                     ("harrier_setup_nonmonarch: Invalid window size code %d\n",
  47                      in0_size);
  48                 return;
  49         }
  50
  51         /* Clear the PCI memory enable bit. If we don't, then when the
  52          * inbound windows are enabled below, the corresponding BARs will be
  53          * "live" and start answering to PCI memory reads from their default
  54          * addresses (0x0), which overlap with system RAM.
  55          */
  56         temps = in_le16((u16 *) (ppc_reg_base +
  57                                  HARRIER_XCSR_CONFIG(PCI_COMMAND)));
  58         temps &= ~(PCI_COMMAND_MEMORY);
  59         out_le16((u16 *) (ppc_reg_base + HARRIER_XCSR_CONFIG(PCI_COMMAND)),
  60                  temps);
  61
  62         /* Setup a non-prefetchable inbound window */
  63         out_le32((u32 *) (ppc_reg_base +
  64                           HARRIER_XCSR_CONFIG(HARRIER_ITSZ0_OFF)), in0_size);
  65
  66         temp = in_le32((u32 *) (ppc_reg_base +
  67                                 HARRIER_XCSR_CONFIG(HARRIER_ITAT0_OFF)));
  68         temp &= ~HARRIER_ITAT_PRE;
  69         temp |= HARRIER_ITAT_DEFAULT;
  70         out_le32((u32 *) (ppc_reg_base +
  71                           HARRIER_XCSR_CONFIG(HARRIER_ITAT0_OFF)), temp);
  72
  73         /* Enable the message passing block */
  74         temp = in_le32((u32 *) (ppc_reg_base +
  75                                 HARRIER_XCSR_CONFIG(HARRIER_MPAT_OFF)));
  76         temp |= HARRIER_MPAT_DEFAULT;
  77         out_le32((u32 *) (ppc_reg_base +
  78                           HARRIER_XCSR_CONFIG(HARRIER_MPAT_OFF)), temp);
  79 }
  80
  81 void __init harrier_release_eready(uint ppc_reg_base)
  82 {
  83         ulong temp;
  84
  85         /*
  86          * Set EREADY to allow the line to be pulled up after everyone is
  87          * ready.
  88          */
  89         temp = in_be32((uint *) (ppc_reg_base + HARRIER_MISC_CSR_OFF));
  90         temp |= HARRIER_EREADY;
  91         out_be32((uint *) (ppc_reg_base + HARRIER_MISC_CSR_OFF), temp);
  92 }
  93
  94 void __init harrier_wait_eready(uint ppc_reg_base)
  95 {
  96         ulong temp;
  97
  98         /*
  99          * Poll the ERDYS line until it goes high to indicate that all
 100          * non-monarch PrPMCs are ready for bus enumeration (or that there are
 101          * no PrPMCs present).
 102          */
 103
 104         /* FIXME: Add a timeout of some kind to prevent endless waits. */
 105         do {
 106
 107                 temp = in_be32((uint *) (ppc_reg_base + HARRIER_MISC_CSR_OFF));
 108
 109         } while (!(temp & HARRIER_ERDYS));
 110 }
 111
 112 /*
 113  * Initialize the Motorola MCG Harrier host bridge.
 114  *
 115  * This means setting up the PPC bus to PCI memory and I/O space mappings,
 116  * setting the PCI memory space address of the MPIC (mapped straight
 117  * through), and ioremap'ing the mpic registers.
 118  * 'OpenPIC_Addr' will be set correctly by this routine.
 119  * This routine will not change the PCI_CONFIG_ADDR or PCI_CONFIG_DATA
 120  * addresses and assumes that the mapping of PCI memory space back to system
 121  * memory is set up correctly by PPCBug.
 122  */
 123 int __init
 124 harrier_init(struct pci_controller *hose,
 125              uint ppc_reg_base,
 126              ulong processor_pci_mem_start,
 127              ulong processor_pci_mem_end,
 128              ulong processor_pci_io_start,
 129              ulong processor_pci_io_end, ulong processor_mpic_base)
 130 {
 131         uint addr, offset;
 132
 133         /*
 134          * Some sanity checks...
 135          */
 136         if (((processor_pci_mem_start & 0xffff0000) != processor_pci_mem_start)
 137             || ((processor_pci_io_start & 0xffff0000) !=
 138                 processor_pci_io_start)) {
 139                 printk("harrier_init: %s\n",
 140                        "PPC to PCI mappings must start on 64 KB boundaries");
 141                 return -1;
 142         }
 143
 144         if (((processor_pci_mem_end & 0x0000ffff) != 0x0000ffff) ||
 145             ((processor_pci_io_end & 0x0000ffff) != 0x0000ffff)) {
 146                 printk("harrier_init: PPC to PCI mappings %s\n",
 147                        "must end just before a 64 KB boundaries");
 148                 return -1;
 149         }
 150
 151         if (((processor_pci_mem_end - processor_pci_mem_start) !=
 152              (hose->mem_space.end - hose->mem_space.start)) ||
 153             ((processor_pci_io_end - processor_pci_io_start) !=
 154              (hose->io_space.end - hose->io_space.start))) {
 155                 printk("harrier_init: %s\n",
 156                        "PPC and PCI memory or I/O space sizes don't match");
 157                 return -1;
 158         }
 159
 160         if ((processor_mpic_base & 0xfffc0000) != processor_mpic_base) {
 161                 printk("harrier_init: %s\n",
 162                        "MPIC address must start on 256 KB boundary");
 163                 return -1;
 164         }
 165
 166         if ((pci_dram_offset & 0xffff0000) != pci_dram_offset) {
 167                 printk("harrier_init: %s\n",
 168                        "pci_dram_offset must be multiple of 64 KB");
 169                 return -1;
 170         }
 171
 172         /*
 173          * Program the OTAD/OTOF registers to set up the PCI Mem & I/O
 174          * space mappings.  These are the mappings going from the processor to
 175          * the PCI bus.
 176          *
 177          * Note: Don't need to 'AND' start/end addresses with 0xffff0000
 178          *       because sanity check above ensures that they are properly
 179          *       aligned.
 180          */
 181
 182         /* Set up PPC->PCI Mem mapping */
 183         addr = processor_pci_mem_start | (processor_pci_mem_end >> 16);
 184 #ifdef CONFIG_HARRIER_STORE_GATHERING
 185         offset = (hose->mem_space.start - processor_pci_mem_start) | 0x9a;
 186 #else
 187         offset = (hose->mem_space.start - processor_pci_mem_start) | 0x92;
 188 #endif
 189         out_be32((uint *) (ppc_reg_base + HARRIER_OTAD0_OFF), addr);
 190         out_be32((uint *) (ppc_reg_base + HARRIER_OTOF0_OFF), offset);
 191
 192         /* Set up PPC->PCI I/O mapping -- Contiguous I/O space */
 193         addr = processor_pci_io_start | (processor_pci_io_end >> 16);
 194         offset = (hose->io_space.start - processor_pci_io_start) | 0x80;
 195         out_be32((uint *) (ppc_reg_base + HARRIER_OTAD1_OFF), addr);
 196         out_be32((uint *) (ppc_reg_base + HARRIER_OTOF1_OFF), offset);
 197
 198         /* Enable MPIC */
 199         OpenPIC_Addr = (void *)processor_mpic_base;
 200         addr = (processor_mpic_base >> 16) | 1;
 201         out_be16((ushort *) (ppc_reg_base + HARRIER_MBAR_OFF), addr);
 202         out_8((u_char *) (ppc_reg_base + HARRIER_MPIC_CSR_OFF),
 203               HARRIER_MPIC_OPI_ENABLE);
 204
 205         return 0;
 206 }
 207
 208 /*
 209  * Find the amount of RAM present.
 210  * This assumes that PPCBug has initialized the memory controller (SMC)
 211  * on the Harrier correctly (i.e., it does no sanity checking).
 212  * It also assumes that the memory base registers are set to configure the
 213  * memory as contiguous starting with "RAM A BASE", "RAM B BASE", etc.
 214  * however, RAM base registers can be skipped (e.g. A, B, C are set,
 215  * D is skipped but E is set is okay).
 216  */
 217 #define MB      (1024*1024UL)
 218
 219 static uint harrier_size_table[] __initdata = {
 220         0 * MB,                 /* 0 ==>    0 MB */
 221         32 * MB,                /* 1 ==>   32 MB */
 222         64 * MB,                /* 2 ==>   64 MB */
 223         64 * MB,                /* 3 ==>   64 MB */
 224         128 * MB,               /* 4 ==>  128 MB */
 225         128 * MB,               /* 5 ==>  128 MB */
 226         128 * MB,               /* 6 ==>  128 MB */
 227         256 * MB,               /* 7 ==>  256 MB */
 228         256 * MB,               /* 8 ==>  256 MB */
 229         256 * MB,               /* 9 ==>  256 MB */
 230         512 * MB,               /* a ==>  512 MB */
 231         512 * MB,               /* b ==>  512 MB */
 232         512 * MB,               /* c ==>  512 MB */
 233         1024 * MB,              /* d ==> 1024 MB */
 234         1024 * MB,              /* e ==> 1024 MB */
 235         2048 * MB,              /* f ==> 2048 MB */
 236 };
 237
 238 /*
 239  * *** WARNING: You MUST have a BAT set up to map in the XCSR regs ***
 240  *
 241  * Read the memory controller's registers to determine the amount of system
 242  * memory.  Assumes that the memory controller registers are already mapped
 243  * into virtual memory--too early to use ioremap().
 244  */
 245 unsigned long __init harrier_get_mem_size(uint xcsr_base)
 246 {
 247         ulong last_addr;
 248         int i;
 249         uint vend_dev_id;
 250         uint *size_table;
 251         uint val;
 252         uint *csrp;
 253         uint size;
 254         int size_table_entries;
 255
 256         vend_dev_id = in_be32((uint *) xcsr_base + PCI_VENDOR_ID);
 257
 258         if (((vend_dev_id & 0xffff0000) >> 16) != PCI_VENDOR_ID_MOTOROLA) {
 259                 printk("harrier_get_mem_size: %s (0x%x)\n",
 260                        "Not a Motorola Memory Controller", vend_dev_id);
 261                 return 0;
 262         }
 263
 264         vend_dev_id &= 0x0000ffff;
 265
 266         if (vend_dev_id == PCI_DEVICE_ID_MOTOROLA_HARRIER) {
 267                 size_table = harrier_size_table;
 268                 size_table_entries = sizeof(harrier_size_table) /
 269                     sizeof(harrier_size_table[0]);
 270         } else {
 271                 printk("harrier_get_mem_size: %s (0x%x)\n",
 272                        "Not a Harrier", vend_dev_id);
 273                 return 0;
 274         }
 275
 276         last_addr = 0;
 277
 278         csrp = (uint *) (xcsr_base + HARRIER_SDBA_OFF);
 279         for (i = 0; i < 8; i++) {
 280                 val = in_be32(csrp++);
 281
 282                 if (val & 0x100) {      /* If enabled */
 283                         size = val >> HARRIER_SDB_SIZE_SHIFT;
 284                         size &= HARRIER_SDB_SIZE_MASK;
 285                         if (size >= size_table_entries) {
 286                                 break;  /* Register not set correctly */
 287                         }
 288                         size = size_table[size];
 289
 290                         val &= ~(size - 1);
 291                         val += size;
 292
 293                         if (val > last_addr) {
 294                                 last_addr = val;
 295                         }
 296                 }
 297         }
 298
 299         return last_addr;
 300 }