2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/init.h>
20 #include <linux/delay.h>
21 #include <linux/bootmem.h>
22 #include <linux/smp_lock.h>
23 #include <linux/interrupt.h>
24 #include <linux/mc146818rtc.h>
25 #include <linux/kernel_stat.h>
26 #include <linux/sysdev.h>
27 #include <linux/cpu.h>
28 #include <linux/module.h>
30 #include <asm/atomic.h>
33 #include <asm/mpspec.h>
35 #include <asm/arch_hooks.h>
37 #include <asm/i8253.h>
40 #include <mach_apic.h>
41 #include <mach_apicdef.h>
47 * cpu_mask that denotes the CPUs that needs timer interrupt coming in as
48 * IPIs in place of local APIC timers
50 static cpumask_t timer_bcast_ipi
;
53 * Knob to control our willingness to enable the local APIC.
55 int enable_local_apic __initdata
= 0; /* -1=force-disable, +1=force-enable */
63 static void apic_pm_activate(void);
65 static int modern_apic(void)
67 unsigned int lvr
, version
;
68 /* AMD systems use old APIC versions, so check the CPU */
69 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_AMD
&&
70 boot_cpu_data
.x86
>= 0xf)
72 lvr
= apic_read(APIC_LVR
);
73 version
= GET_APIC_VERSION(lvr
);
74 return version
>= 0x14;
78 * 'what should we do if we get a hw irq event on an illegal vector'.
79 * each architecture has to answer this themselves.
81 void ack_bad_irq(unsigned int irq
)
83 printk("unexpected IRQ trap at vector %02x\n", irq
);
85 * Currently unexpected vectors happen only on SMP and APIC.
86 * We _must_ ack these because every local APIC has only N
87 * irq slots per priority level, and a 'hanging, unacked' IRQ
88 * holds up an irq slot - in excessive cases (when multiple
89 * unexpected vectors occur) that might lock up the APIC
91 * But only ack when the APIC is enabled -AK
97 void __init
apic_intr_init(void)
102 /* self generated IPI for local APIC timer */
103 set_intr_gate(LOCAL_TIMER_VECTOR
, apic_timer_interrupt
);
105 /* IPI vectors for APIC spurious and error interrupts */
106 set_intr_gate(SPURIOUS_APIC_VECTOR
, spurious_interrupt
);
107 set_intr_gate(ERROR_APIC_VECTOR
, error_interrupt
);
109 /* thermal monitor LVT interrupt */
110 #ifdef CONFIG_X86_MCE_P4THERMAL
111 set_intr_gate(THERMAL_APIC_VECTOR
, thermal_interrupt
);
115 /* Using APIC to generate smp_local_timer_interrupt? */
116 int using_apic_timer __read_mostly
= 0;
118 static int enabled_via_apicbase
;
120 void enable_NMI_through_LVT0 (void * dummy
)
124 ver
= apic_read(APIC_LVR
);
125 ver
= GET_APIC_VERSION(ver
);
126 v
= APIC_DM_NMI
; /* unmask and set to NMI */
127 if (!APIC_INTEGRATED(ver
)) /* 82489DX */
128 v
|= APIC_LVT_LEVEL_TRIGGER
;
129 apic_write_around(APIC_LVT0
, v
);
132 int get_physical_broadcast(void)
142 unsigned int v
, ver
, maxlvt
;
144 v
= apic_read(APIC_LVR
);
145 ver
= GET_APIC_VERSION(v
);
146 /* 82489DXs do not report # of LVT entries. */
147 maxlvt
= APIC_INTEGRATED(ver
) ? GET_APIC_MAXLVT(v
) : 2;
151 void clear_local_APIC(void)
156 maxlvt
= get_maxlvt();
159 * Masking an LVT entry can trigger a local APIC error
160 * if the vector is zero. Mask LVTERR first to prevent this.
163 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
164 apic_write_around(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
167 * Careful: we have to set masks only first to deassert
168 * any level-triggered sources.
170 v
= apic_read(APIC_LVTT
);
171 apic_write_around(APIC_LVTT
, v
| APIC_LVT_MASKED
);
172 v
= apic_read(APIC_LVT0
);
173 apic_write_around(APIC_LVT0
, v
| APIC_LVT_MASKED
);
174 v
= apic_read(APIC_LVT1
);
175 apic_write_around(APIC_LVT1
, v
| APIC_LVT_MASKED
);
177 v
= apic_read(APIC_LVTPC
);
178 apic_write_around(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
181 /* lets not touch this if we didn't frob it */
182 #ifdef CONFIG_X86_MCE_P4THERMAL
184 v
= apic_read(APIC_LVTTHMR
);
185 apic_write_around(APIC_LVTTHMR
, v
| APIC_LVT_MASKED
);
189 * Clean APIC state for other OSs:
191 apic_write_around(APIC_LVTT
, APIC_LVT_MASKED
);
192 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
);
193 apic_write_around(APIC_LVT1
, APIC_LVT_MASKED
);
195 apic_write_around(APIC_LVTERR
, APIC_LVT_MASKED
);
197 apic_write_around(APIC_LVTPC
, APIC_LVT_MASKED
);
199 #ifdef CONFIG_X86_MCE_P4THERMAL
201 apic_write_around(APIC_LVTTHMR
, APIC_LVT_MASKED
);
203 v
= GET_APIC_VERSION(apic_read(APIC_LVR
));
204 if (APIC_INTEGRATED(v
)) { /* !82489DX */
205 if (maxlvt
> 3) /* Due to Pentium errata 3AP and 11AP. */
206 apic_write(APIC_ESR
, 0);
211 void __init
connect_bsp_APIC(void)
215 * Do not trust the local APIC being empty at bootup.
219 * PIC mode, enable APIC mode in the IMCR, i.e.
220 * connect BSP's local APIC to INT and NMI lines.
222 apic_printk(APIC_VERBOSE
, "leaving PIC mode, "
223 "enabling APIC mode.\n");
230 void disconnect_bsp_APIC(int virt_wire_setup
)
234 * Put the board back into PIC mode (has an effect
235 * only on certain older boards). Note that APIC
236 * interrupts, including IPIs, won't work beyond
237 * this point! The only exception are INIT IPIs.
239 apic_printk(APIC_VERBOSE
, "disabling APIC mode, "
240 "entering PIC mode.\n");
245 /* Go back to Virtual Wire compatibility mode */
248 /* For the spurious interrupt use vector F, and enable it */
249 value
= apic_read(APIC_SPIV
);
250 value
&= ~APIC_VECTOR_MASK
;
251 value
|= APIC_SPIV_APIC_ENABLED
;
253 apic_write_around(APIC_SPIV
, value
);
255 if (!virt_wire_setup
) {
256 /* For LVT0 make it edge triggered, active high, external and enabled */
257 value
= apic_read(APIC_LVT0
);
258 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
259 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
260 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
261 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
262 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
263 apic_write_around(APIC_LVT0
, value
);
267 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
);
270 /* For LVT1 make it edge triggered, active high, nmi and enabled */
271 value
= apic_read(APIC_LVT1
);
273 APIC_MODE_MASK
| APIC_SEND_PENDING
|
274 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
275 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
276 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
277 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
278 apic_write_around(APIC_LVT1
, value
);
282 void disable_local_APIC(void)
289 * Disable APIC (implies clearing of registers
292 value
= apic_read(APIC_SPIV
);
293 value
&= ~APIC_SPIV_APIC_ENABLED
;
294 apic_write_around(APIC_SPIV
, value
);
296 if (enabled_via_apicbase
) {
298 rdmsr(MSR_IA32_APICBASE
, l
, h
);
299 l
&= ~MSR_IA32_APICBASE_ENABLE
;
300 wrmsr(MSR_IA32_APICBASE
, l
, h
);
305 * This is to verify that we're looking at a real local APIC.
306 * Check these against your board if the CPUs aren't getting
307 * started for no apparent reason.
309 int __init
verify_local_APIC(void)
311 unsigned int reg0
, reg1
;
314 * The version register is read-only in a real APIC.
316 reg0
= apic_read(APIC_LVR
);
317 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
318 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
319 reg1
= apic_read(APIC_LVR
);
320 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
323 * The two version reads above should print the same
324 * numbers. If the second one is different, then we
325 * poke at a non-APIC.
331 * Check if the version looks reasonably.
333 reg1
= GET_APIC_VERSION(reg0
);
334 if (reg1
== 0x00 || reg1
== 0xff)
337 if (reg1
< 0x02 || reg1
== 0xff)
341 * The ID register is read/write in a real APIC.
343 reg0
= apic_read(APIC_ID
);
344 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
347 * The next two are just to see if we have sane values.
348 * They're only really relevant if we're in Virtual Wire
349 * compatibility mode, but most boxes are anymore.
351 reg0
= apic_read(APIC_LVT0
);
352 apic_printk(APIC_DEBUG
, "Getting LVT0: %x\n", reg0
);
353 reg1
= apic_read(APIC_LVT1
);
354 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
359 void __init
sync_Arb_IDs(void)
361 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1
362 And not needed on AMD */
368 apic_wait_icr_idle();
370 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
371 apic_write_around(APIC_ICR
, APIC_DEST_ALLINC
| APIC_INT_LEVELTRIG
375 extern void __error_in_apic_c (void);
378 * An initial setup of the virtual wire mode.
380 void __init
init_bsp_APIC(void)
382 unsigned long value
, ver
;
385 * Don't do the setup now if we have a SMP BIOS as the
386 * through-I/O-APIC virtual wire mode might be active.
388 if (smp_found_config
|| !cpu_has_apic
)
391 value
= apic_read(APIC_LVR
);
392 ver
= GET_APIC_VERSION(value
);
395 * Do not trust the local APIC being empty at bootup.
402 value
= apic_read(APIC_SPIV
);
403 value
&= ~APIC_VECTOR_MASK
;
404 value
|= APIC_SPIV_APIC_ENABLED
;
406 /* This bit is reserved on P4/Xeon and should be cleared */
407 if ((boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) && (boot_cpu_data
.x86
== 15))
408 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
410 value
|= APIC_SPIV_FOCUS_DISABLED
;
411 value
|= SPURIOUS_APIC_VECTOR
;
412 apic_write_around(APIC_SPIV
, value
);
415 * Set up the virtual wire mode.
417 apic_write_around(APIC_LVT0
, APIC_DM_EXTINT
);
419 if (!APIC_INTEGRATED(ver
)) /* 82489DX */
420 value
|= APIC_LVT_LEVEL_TRIGGER
;
421 apic_write_around(APIC_LVT1
, value
);
424 void __devinit
setup_local_APIC(void)
426 unsigned long oldvalue
, value
, ver
, maxlvt
;
429 /* Pound the ESR really hard over the head with a big hammer - mbligh */
431 apic_write(APIC_ESR
, 0);
432 apic_write(APIC_ESR
, 0);
433 apic_write(APIC_ESR
, 0);
434 apic_write(APIC_ESR
, 0);
437 value
= apic_read(APIC_LVR
);
438 ver
= GET_APIC_VERSION(value
);
440 if ((SPURIOUS_APIC_VECTOR
& 0x0f) != 0x0f)
444 * Double-check whether this APIC is really registered.
446 if (!apic_id_registered())
450 * Intel recommends to set DFR, LDR and TPR before enabling
451 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
452 * document number 292116). So here it goes...
457 * Set Task Priority to 'accept all'. We never change this
460 value
= apic_read(APIC_TASKPRI
);
461 value
&= ~APIC_TPRI_MASK
;
462 apic_write_around(APIC_TASKPRI
, value
);
465 * After a crash, we no longer service the interrupts and a pending
466 * interrupt from previous kernel might still have ISR bit set.
468 * Most probably by now CPU has serviced that pending interrupt and
469 * it might not have done the ack_APIC_irq() because it thought,
470 * interrupt came from i8259 as ExtInt. LAPIC did not get EOI so it
471 * does not clear the ISR bit and cpu thinks it has already serivced
472 * the interrupt. Hence a vector might get locked. It was noticed
473 * for timer irq (vector 0x31). Issue an extra EOI to clear ISR.
475 for (i
= APIC_ISR_NR
- 1; i
>= 0; i
--) {
476 value
= apic_read(APIC_ISR
+ i
*0x10);
477 for (j
= 31; j
>= 0; j
--) {
484 * Now that we are all set up, enable the APIC
486 value
= apic_read(APIC_SPIV
);
487 value
&= ~APIC_VECTOR_MASK
;
491 value
|= APIC_SPIV_APIC_ENABLED
;
494 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
495 * certain networking cards. If high frequency interrupts are
496 * happening on a particular IOAPIC pin, plus the IOAPIC routing
497 * entry is masked/unmasked at a high rate as well then sooner or
498 * later IOAPIC line gets 'stuck', no more interrupts are received
499 * from the device. If focus CPU is disabled then the hang goes
502 * [ This bug can be reproduced easily with a level-triggered
503 * PCI Ne2000 networking cards and PII/PIII processors, dual
507 * Actually disabling the focus CPU check just makes the hang less
508 * frequent as it makes the interrupt distributon model be more
509 * like LRU than MRU (the short-term load is more even across CPUs).
510 * See also the comment in end_level_ioapic_irq(). --macro
513 /* Enable focus processor (bit==0) */
514 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
516 /* Disable focus processor (bit==1) */
517 value
|= APIC_SPIV_FOCUS_DISABLED
;
520 * Set spurious IRQ vector
522 value
|= SPURIOUS_APIC_VECTOR
;
523 apic_write_around(APIC_SPIV
, value
);
528 * set up through-local-APIC on the BP's LINT0. This is not
529 * strictly necessery in pure symmetric-IO mode, but sometimes
530 * we delegate interrupts to the 8259A.
533 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
535 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
536 if (!smp_processor_id() && (pic_mode
|| !value
)) {
537 value
= APIC_DM_EXTINT
;
538 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n",
541 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
542 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n",
545 apic_write_around(APIC_LVT0
, value
);
548 * only the BP should see the LINT1 NMI signal, obviously.
550 if (!smp_processor_id())
553 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
554 if (!APIC_INTEGRATED(ver
)) /* 82489DX */
555 value
|= APIC_LVT_LEVEL_TRIGGER
;
556 apic_write_around(APIC_LVT1
, value
);
558 if (APIC_INTEGRATED(ver
) && !esr_disable
) { /* !82489DX */
559 maxlvt
= get_maxlvt();
560 if (maxlvt
> 3) /* Due to the Pentium erratum 3AP. */
561 apic_write(APIC_ESR
, 0);
562 oldvalue
= apic_read(APIC_ESR
);
564 value
= ERROR_APIC_VECTOR
; // enables sending errors
565 apic_write_around(APIC_LVTERR
, value
);
567 * spec says clear errors after enabling vector.
570 apic_write(APIC_ESR
, 0);
571 value
= apic_read(APIC_ESR
);
572 if (value
!= oldvalue
)
573 apic_printk(APIC_VERBOSE
, "ESR value before enabling "
574 "vector: 0x%08lx after: 0x%08lx\n",
579 * Something untraceble is creating bad interrupts on
580 * secondary quads ... for the moment, just leave the
581 * ESR disabled - we can't do anything useful with the
582 * errors anyway - mbligh
584 printk("Leaving ESR disabled.\n");
586 printk("No ESR for 82489DX.\n");
589 setup_apic_nmi_watchdog(NULL
);
594 * If Linux enabled the LAPIC against the BIOS default
595 * disable it down before re-entering the BIOS on shutdown.
596 * Otherwise the BIOS may get confused and not power-off.
597 * Additionally clear all LVT entries before disable_local_APIC
598 * for the case where Linux didn't enable the LAPIC.
600 void lapic_shutdown(void)
607 local_irq_save(flags
);
610 if (enabled_via_apicbase
)
611 disable_local_APIC();
613 local_irq_restore(flags
);
620 /* r/w apic fields */
621 unsigned int apic_id
;
622 unsigned int apic_taskpri
;
623 unsigned int apic_ldr
;
624 unsigned int apic_dfr
;
625 unsigned int apic_spiv
;
626 unsigned int apic_lvtt
;
627 unsigned int apic_lvtpc
;
628 unsigned int apic_lvt0
;
629 unsigned int apic_lvt1
;
630 unsigned int apic_lvterr
;
631 unsigned int apic_tmict
;
632 unsigned int apic_tdcr
;
633 unsigned int apic_thmr
;
636 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
640 if (!apic_pm_state
.active
)
643 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
644 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
645 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
646 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
647 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
648 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
649 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
650 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
651 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
652 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
653 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
654 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
655 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
657 local_irq_save(flags
);
658 disable_local_APIC();
659 local_irq_restore(flags
);
663 static int lapic_resume(struct sys_device
*dev
)
668 if (!apic_pm_state
.active
)
671 local_irq_save(flags
);
674 * Make sure the APICBASE points to the right address
676 * FIXME! This will be wrong if we ever support suspend on
677 * SMP! We'll need to do this as part of the CPU restore!
679 rdmsr(MSR_IA32_APICBASE
, l
, h
);
680 l
&= ~MSR_IA32_APICBASE_BASE
;
681 l
|= MSR_IA32_APICBASE_ENABLE
| mp_lapic_addr
;
682 wrmsr(MSR_IA32_APICBASE
, l
, h
);
684 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
685 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
686 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
687 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
688 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
689 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
690 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
691 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
692 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
693 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
694 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
695 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
696 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
697 apic_write(APIC_ESR
, 0);
699 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
700 apic_write(APIC_ESR
, 0);
702 local_irq_restore(flags
);
707 * This device has no shutdown method - fully functioning local APICs
708 * are needed on every CPU up until machine_halt/restart/poweroff.
711 static struct sysdev_class lapic_sysclass
= {
712 set_kset_name("lapic"),
713 .resume
= lapic_resume
,
714 .suspend
= lapic_suspend
,
717 static struct sys_device device_lapic
= {
719 .cls
= &lapic_sysclass
,
722 static void __devinit
apic_pm_activate(void)
724 apic_pm_state
.active
= 1;
727 static int __init
init_lapic_sysfs(void)
733 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
735 error
= sysdev_class_register(&lapic_sysclass
);
737 error
= sysdev_register(&device_lapic
);
740 device_initcall(init_lapic_sysfs
);
742 #else /* CONFIG_PM */
744 static void apic_pm_activate(void) { }
746 #endif /* CONFIG_PM */
749 * Detect and enable local APICs on non-SMP boards.
750 * Original code written by Keir Fraser.
753 static int __init
apic_set_verbosity(char *str
)
755 if (strcmp("debug", str
) == 0)
756 apic_verbosity
= APIC_DEBUG
;
757 else if (strcmp("verbose", str
) == 0)
758 apic_verbosity
= APIC_VERBOSE
;
762 __setup("apic=", apic_set_verbosity
);
764 static int __init
detect_init_APIC (void)
768 /* Disabled by kernel option? */
769 if (enable_local_apic
< 0)
772 switch (boot_cpu_data
.x86_vendor
) {
774 if ((boot_cpu_data
.x86
== 6 && boot_cpu_data
.x86_model
> 1) ||
775 (boot_cpu_data
.x86
== 15))
778 case X86_VENDOR_INTEL
:
779 if (boot_cpu_data
.x86
== 6 || boot_cpu_data
.x86
== 15 ||
780 (boot_cpu_data
.x86
== 5 && cpu_has_apic
))
789 * Over-ride BIOS and try to enable the local
790 * APIC only if "lapic" specified.
792 if (enable_local_apic
<= 0) {
793 printk("Local APIC disabled by BIOS -- "
794 "you can enable it with \"lapic\"\n");
798 * Some BIOSes disable the local APIC in the
799 * APIC_BASE MSR. This can only be done in
800 * software for Intel P6 or later and AMD K7
801 * (Model > 1) or later.
803 rdmsr(MSR_IA32_APICBASE
, l
, h
);
804 if (!(l
& MSR_IA32_APICBASE_ENABLE
)) {
805 printk("Local APIC disabled by BIOS -- reenabling.\n");
806 l
&= ~MSR_IA32_APICBASE_BASE
;
807 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
808 wrmsr(MSR_IA32_APICBASE
, l
, h
);
809 enabled_via_apicbase
= 1;
813 * The APIC feature bit should now be enabled
816 features
= cpuid_edx(1);
817 if (!(features
& (1 << X86_FEATURE_APIC
))) {
818 printk("Could not enable APIC!\n");
821 set_bit(X86_FEATURE_APIC
, boot_cpu_data
.x86_capability
);
822 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
824 /* The BIOS may have set up the APIC at some other address */
825 rdmsr(MSR_IA32_APICBASE
, l
, h
);
826 if (l
& MSR_IA32_APICBASE_ENABLE
)
827 mp_lapic_addr
= l
& MSR_IA32_APICBASE_BASE
;
829 if (nmi_watchdog
!= NMI_NONE
)
830 nmi_watchdog
= NMI_LOCAL_APIC
;
832 printk("Found and enabled local APIC!\n");
839 printk("No local APIC present or hardware disabled\n");
843 void __init
init_apic_mappings(void)
845 unsigned long apic_phys
;
848 * If no local APIC can be found then set up a fake all
849 * zeroes page to simulate the local APIC and another
850 * one for the IO-APIC.
852 if (!smp_found_config
&& detect_init_APIC()) {
853 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
854 apic_phys
= __pa(apic_phys
);
856 apic_phys
= mp_lapic_addr
;
858 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
859 printk(KERN_DEBUG
"mapped APIC to %08lx (%08lx)\n", APIC_BASE
,
863 * Fetch the APIC ID of the BSP in case we have a
864 * default configuration (or the MP table is broken).
866 if (boot_cpu_physical_apicid
== -1U)
867 boot_cpu_physical_apicid
= GET_APIC_ID(apic_read(APIC_ID
));
869 #ifdef CONFIG_X86_IO_APIC
871 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
874 for (i
= 0; i
< nr_ioapics
; i
++) {
875 if (smp_found_config
) {
876 ioapic_phys
= mp_ioapics
[i
].mpc_apicaddr
;
879 "WARNING: bogus zero IO-APIC "
880 "address found in MPTABLE, "
881 "disabling IO/APIC support!\n");
882 smp_found_config
= 0;
883 skip_ioapic_setup
= 1;
884 goto fake_ioapic_page
;
888 ioapic_phys
= (unsigned long)
889 alloc_bootmem_pages(PAGE_SIZE
);
890 ioapic_phys
= __pa(ioapic_phys
);
892 set_fixmap_nocache(idx
, ioapic_phys
);
893 printk(KERN_DEBUG
"mapped IOAPIC to %08lx (%08lx)\n",
894 __fix_to_virt(idx
), ioapic_phys
);
902 * This part sets up the APIC 32 bit clock in LVTT1, with HZ interrupts
903 * per second. We assume that the caller has already set up the local
906 * The APIC timer is not exactly sync with the external timer chip, it
907 * closely follows bus clocks.
911 * The timer chip is already set up at HZ interrupts per second here,
912 * but we do not accept timer interrupts yet. We only allow the BP
915 static unsigned int __devinit
get_8254_timer_count(void)
921 spin_lock_irqsave(&i8253_lock
, flags
);
923 outb_p(0x00, PIT_MODE
);
924 count
= inb_p(PIT_CH0
);
925 count
|= inb_p(PIT_CH0
) << 8;
927 spin_unlock_irqrestore(&i8253_lock
, flags
);
932 /* next tick in 8254 can be caught by catching timer wraparound */
933 static void __devinit
wait_8254_wraparound(void)
935 unsigned int curr_count
, prev_count
;
937 curr_count
= get_8254_timer_count();
939 prev_count
= curr_count
;
940 curr_count
= get_8254_timer_count();
942 /* workaround for broken Mercury/Neptune */
943 if (prev_count
>= curr_count
+ 0x100)
944 curr_count
= get_8254_timer_count();
946 } while (prev_count
>= curr_count
);
950 * Default initialization for 8254 timers. If we use other timers like HPET,
951 * we override this later
953 void (*wait_timer_tick
)(void) __devinitdata
= wait_8254_wraparound
;
956 * This function sets up the local APIC timer, with a timeout of
957 * 'clocks' APIC bus clock. During calibration we actually call
958 * this function twice on the boot CPU, once with a bogus timeout
959 * value, second time for real. The other (noncalibrating) CPUs
960 * call this function only once, with the real, calibrated value.
962 * We do reads before writes even if unnecessary, to get around the
963 * P5 APIC double write bug.
966 #define APIC_DIVISOR 16
968 static void __setup_APIC_LVTT(unsigned int clocks
)
970 unsigned int lvtt_value
, tmp_value
, ver
;
971 int cpu
= smp_processor_id();
973 ver
= GET_APIC_VERSION(apic_read(APIC_LVR
));
974 lvtt_value
= APIC_LVT_TIMER_PERIODIC
| LOCAL_TIMER_VECTOR
;
975 if (!APIC_INTEGRATED(ver
))
976 lvtt_value
|= SET_APIC_TIMER_BASE(APIC_TIMER_BASE_DIV
);
978 if (cpu_isset(cpu
, timer_bcast_ipi
))
979 lvtt_value
|= APIC_LVT_MASKED
;
981 apic_write_around(APIC_LVTT
, lvtt_value
);
986 tmp_value
= apic_read(APIC_TDCR
);
987 apic_write_around(APIC_TDCR
, (tmp_value
988 & ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
))
991 apic_write_around(APIC_TMICT
, clocks
/APIC_DIVISOR
);
994 static void __devinit
setup_APIC_timer(unsigned int clocks
)
998 local_irq_save(flags
);
1001 * Wait for IRQ0's slice:
1005 __setup_APIC_LVTT(clocks
);
1007 local_irq_restore(flags
);
1011 * In this function we calibrate APIC bus clocks to the external
1012 * timer. Unfortunately we cannot use jiffies and the timer irq
1013 * to calibrate, since some later bootup code depends on getting
1014 * the first irq? Ugh.
1016 * We want to do the calibration only once since we
1017 * want to have local timer irqs syncron. CPUs connected
1018 * by the same APIC bus have the very same bus frequency.
1019 * And we want to have irqs off anyways, no accidental
1020 * APIC irq that way.
1023 static int __init
calibrate_APIC_clock(void)
1025 unsigned long long t1
= 0, t2
= 0;
1029 const int LOOPS
= HZ
/10;
1031 apic_printk(APIC_VERBOSE
, "calibrating APIC timer ...\n");
1034 * Put whatever arbitrary (but long enough) timeout
1035 * value into the APIC clock, we just want to get the
1036 * counter running for calibration.
1038 __setup_APIC_LVTT(1000000000);
1041 * The timer chip counts down to zero. Let's wait
1042 * for a wraparound to start exact measurement:
1043 * (the current tick might have been already half done)
1049 * We wrapped around just now. Let's start:
1053 tt1
= apic_read(APIC_TMCCT
);
1056 * Let's wait LOOPS wraprounds:
1058 for (i
= 0; i
< LOOPS
; i
++)
1061 tt2
= apic_read(APIC_TMCCT
);
1066 * The APIC bus clock counter is 32 bits only, it
1067 * might have overflown, but note that we use signed
1068 * longs, thus no extra care needed.
1070 * underflown to be exact, as the timer counts down ;)
1073 result
= (tt1
-tt2
)*APIC_DIVISOR
/LOOPS
;
1076 apic_printk(APIC_VERBOSE
, "..... CPU clock speed is "
1078 ((long)(t2
-t1
)/LOOPS
)/(1000000/HZ
),
1079 ((long)(t2
-t1
)/LOOPS
)%(1000000/HZ
));
1081 apic_printk(APIC_VERBOSE
, "..... host bus clock speed is "
1083 result
/(1000000/HZ
),
1084 result
%(1000000/HZ
));
1089 static unsigned int calibration_result
;
1091 void __init
setup_boot_APIC_clock(void)
1093 unsigned long flags
;
1094 apic_printk(APIC_VERBOSE
, "Using local APIC timer interrupts.\n");
1095 using_apic_timer
= 1;
1097 local_irq_save(flags
);
1099 calibration_result
= calibrate_APIC_clock();
1101 * Now set up the timer for real.
1103 setup_APIC_timer(calibration_result
);
1105 local_irq_restore(flags
);
1108 void __devinit
setup_secondary_APIC_clock(void)
1110 setup_APIC_timer(calibration_result
);
1113 void disable_APIC_timer(void)
1115 if (using_apic_timer
) {
1118 v
= apic_read(APIC_LVTT
);
1120 * When an illegal vector value (0-15) is written to an LVT
1121 * entry and delivery mode is Fixed, the APIC may signal an
1122 * illegal vector error, with out regard to whether the mask
1123 * bit is set or whether an interrupt is actually seen on input.
1125 * Boot sequence might call this function when the LVTT has
1126 * '0' vector value. So make sure vector field is set to
1129 v
|= (APIC_LVT_MASKED
| LOCAL_TIMER_VECTOR
);
1130 apic_write_around(APIC_LVTT
, v
);
1134 void enable_APIC_timer(void)
1136 int cpu
= smp_processor_id();
1138 if (using_apic_timer
&&
1139 !cpu_isset(cpu
, timer_bcast_ipi
)) {
1142 v
= apic_read(APIC_LVTT
);
1143 apic_write_around(APIC_LVTT
, v
& ~APIC_LVT_MASKED
);
1147 void switch_APIC_timer_to_ipi(void *cpumask
)
1149 cpumask_t mask
= *(cpumask_t
*)cpumask
;
1150 int cpu
= smp_processor_id();
1152 if (cpu_isset(cpu
, mask
) &&
1153 !cpu_isset(cpu
, timer_bcast_ipi
)) {
1154 disable_APIC_timer();
1155 cpu_set(cpu
, timer_bcast_ipi
);
1158 EXPORT_SYMBOL(switch_APIC_timer_to_ipi
);
1160 void switch_ipi_to_APIC_timer(void *cpumask
)
1162 cpumask_t mask
= *(cpumask_t
*)cpumask
;
1163 int cpu
= smp_processor_id();
1165 if (cpu_isset(cpu
, mask
) &&
1166 cpu_isset(cpu
, timer_bcast_ipi
)) {
1167 cpu_clear(cpu
, timer_bcast_ipi
);
1168 enable_APIC_timer();
1171 EXPORT_SYMBOL(switch_ipi_to_APIC_timer
);
1176 * Local timer interrupt handler. It does both profiling and
1177 * process statistics/rescheduling.
1179 * We do profiling in every local tick, statistics/rescheduling
1180 * happen only every 'profiling multiplier' ticks. The default
1181 * multiplier is 1 and it can be changed by writing the new multiplier
1182 * value into /proc/profile.
1185 inline void smp_local_timer_interrupt(struct pt_regs
* regs
)
1187 profile_tick(CPU_PROFILING
, regs
);
1189 update_process_times(user_mode_vm(regs
));
1193 * We take the 'long' return path, and there every subsystem
1194 * grabs the apropriate locks (kernel lock/ irq lock).
1196 * we might want to decouple profiling from the 'long path',
1197 * and do the profiling totally in assembly.
1199 * Currently this isn't too much of an issue (performance wise),
1200 * we can take more than 100K local irqs per second on a 100 MHz P5.
1205 * Local APIC timer interrupt. This is the most natural way for doing
1206 * local interrupts, but local timer interrupts can be emulated by
1207 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
1209 * [ if a single-CPU system runs an SMP kernel then we call the local
1210 * interrupt as well. Thus we cannot inline the local irq ... ]
1213 fastcall
void smp_apic_timer_interrupt(struct pt_regs
*regs
)
1215 int cpu
= smp_processor_id();
1218 * the NMI deadlock-detector uses this.
1220 per_cpu(irq_stat
, cpu
).apic_timer_irqs
++;
1223 * NOTE! We'd better ACK the irq immediately,
1224 * because timer handling can be slow.
1228 * update_process_times() expects us to have done irq_enter().
1229 * Besides, if we don't timer interrupts ignore the global
1230 * interrupt lock, which is the WrongThing (tm) to do.
1233 smp_local_timer_interrupt(regs
);
1238 static void up_apic_timer_interrupt_call(struct pt_regs
*regs
)
1240 int cpu
= smp_processor_id();
1243 * the NMI deadlock-detector uses this.
1245 per_cpu(irq_stat
, cpu
).apic_timer_irqs
++;
1247 smp_local_timer_interrupt(regs
);
1251 void smp_send_timer_broadcast_ipi(struct pt_regs
*regs
)
1255 cpus_and(mask
, cpu_online_map
, timer_bcast_ipi
);
1256 if (!cpus_empty(mask
)) {
1258 send_IPI_mask(mask
, LOCAL_TIMER_VECTOR
);
1261 * We can directly call the apic timer interrupt handler
1262 * in UP case. Minus all irq related functions
1264 up_apic_timer_interrupt_call(regs
);
1269 int setup_profiling_timer(unsigned int multiplier
)
1275 * This interrupt should _never_ happen with our APIC/SMP architecture
1277 fastcall
void smp_spurious_interrupt(struct pt_regs
*regs
)
1283 * Check if this really is a spurious interrupt and ACK it
1284 * if it is a vectored one. Just in case...
1285 * Spurious interrupts should not be ACKed.
1287 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
1288 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
1291 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
1292 printk(KERN_INFO
"spurious APIC interrupt on CPU#%d, should never happen.\n",
1293 smp_processor_id());
1298 * This interrupt should never happen with our APIC/SMP architecture
1301 fastcall
void smp_error_interrupt(struct pt_regs
*regs
)
1303 unsigned long v
, v1
;
1306 /* First tickle the hardware, only then report what went on. -- REW */
1307 v
= apic_read(APIC_ESR
);
1308 apic_write(APIC_ESR
, 0);
1309 v1
= apic_read(APIC_ESR
);
1311 atomic_inc(&irq_err_count
);
1313 /* Here is what the APIC error bits mean:
1316 2: Send accept error
1317 3: Receive accept error
1319 5: Send illegal vector
1320 6: Received illegal vector
1321 7: Illegal register address
1323 printk (KERN_DEBUG
"APIC error on CPU%d: %02lx(%02lx)\n",
1324 smp_processor_id(), v
, v1
);
1329 * This initializes the IO-APIC and APIC hardware if this is
1332 int __init
APIC_init_uniprocessor (void)
1334 if (enable_local_apic
< 0)
1335 clear_bit(X86_FEATURE_APIC
, boot_cpu_data
.x86_capability
);
1337 if (!smp_found_config
&& !cpu_has_apic
)
1341 * Complain if the BIOS pretends there is one.
1343 if (!cpu_has_apic
&& APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
])) {
1344 printk(KERN_ERR
"BIOS bug, local APIC #%d not detected!...\n",
1345 boot_cpu_physical_apicid
);
1346 clear_bit(X86_FEATURE_APIC
, boot_cpu_data
.x86_capability
);
1350 verify_local_APIC();
1355 * Hack: In case of kdump, after a crash, kernel might be booting
1356 * on a cpu with non-zero lapic id. But boot_cpu_physical_apicid
1357 * might be zero if read from MP tables. Get it from LAPIC.
1359 #ifdef CONFIG_CRASH_DUMP
1360 boot_cpu_physical_apicid
= GET_APIC_ID(apic_read(APIC_ID
));
1362 phys_cpu_present_map
= physid_mask_of_physid(boot_cpu_physical_apicid
);
1366 #ifdef CONFIG_X86_IO_APIC
1367 if (smp_found_config
)
1368 if (!skip_ioapic_setup
&& nr_ioapics
)
1371 setup_boot_APIC_clock();