2 * linux/arch/i386/nmi.c
4 * NMI watchdog support on APIC systems
6 * Started by Ingo Molnar <mingo@redhat.com>
9 * Mikael Pettersson : AMD K7 support for local APIC NMI watchdog.
10 * Mikael Pettersson : Power Management for local APIC NMI watchdog.
11 * Mikael Pettersson : Pentium 4 support for local APIC NMI watchdog.
13 * Mikael Pettersson : PM converted to driver model. Disable/enable API.
16 #include <linux/config.h>
17 #include <linux/delay.h>
18 #include <linux/interrupt.h>
19 #include <linux/module.h>
20 #include <linux/nmi.h>
21 #include <linux/sysdev.h>
22 #include <linux/sysctl.h>
23 #include <linux/percpu.h>
27 #include <asm/kdebug.h>
29 #include "mach_traps.h"
31 /* perfctr_nmi_owner tracks the ownership of the perfctr registers:
32 * evtsel_nmi_owner tracks the ownership of the event selection
33 * - different performance counters/ event selection may be reserved for
34 * different subsystems this reservation system just tries to coordinate
37 static DEFINE_PER_CPU(unsigned long, perfctr_nmi_owner
);
38 static DEFINE_PER_CPU(unsigned long, evntsel_nmi_owner
[3]);
40 /* this number is calculated from Intel's MSR_P4_CRU_ESCR5 register and it's
41 * offset from MSR_P4_BSU_ESCR0. It will be the max for all platforms (for now)
43 #define NMI_MAX_COUNTER_BITS 66
46 * >0: the lapic NMI watchdog is active, but can be disabled
47 * <0: the lapic NMI watchdog has not been set up, and cannot
49 * 0: the lapic NMI watchdog is disabled, but can be enabled
51 atomic_t nmi_active
= ATOMIC_INIT(0); /* oprofile uses this */
53 unsigned int nmi_watchdog
= NMI_DEFAULT
;
54 static unsigned int nmi_hz
= HZ
;
56 struct nmi_watchdog_ctlblk
{
59 unsigned int cccr_msr
;
60 unsigned int perfctr_msr
; /* the MSR to reset in NMI handler */
61 unsigned int evntsel_msr
; /* the MSR to select the events to handle */
63 static DEFINE_PER_CPU(struct nmi_watchdog_ctlblk
, nmi_watchdog_ctlblk
);
65 /* local prototypes */
66 static void stop_apic_nmi_watchdog(void *unused
);
67 static int unknown_nmi_panic_callback(struct pt_regs
*regs
, int cpu
);
69 extern void show_registers(struct pt_regs
*regs
);
70 extern int unknown_nmi_panic
;
72 /* converts an msr to an appropriate reservation bit */
73 static inline unsigned int nmi_perfctr_msr_to_bit(unsigned int msr
)
75 /* returns the bit offset of the performance counter register */
76 switch (boot_cpu_data
.x86_vendor
) {
78 return (msr
- MSR_K7_PERFCTR0
);
79 case X86_VENDOR_INTEL
:
80 switch (boot_cpu_data
.x86
) {
82 return (msr
- MSR_P6_PERFCTR0
);
84 return (msr
- MSR_P4_BPU_PERFCTR0
);
90 /* converts an msr to an appropriate reservation bit */
91 static inline unsigned int nmi_evntsel_msr_to_bit(unsigned int msr
)
93 /* returns the bit offset of the event selection register */
94 switch (boot_cpu_data
.x86_vendor
) {
96 return (msr
- MSR_K7_EVNTSEL0
);
97 case X86_VENDOR_INTEL
:
98 switch (boot_cpu_data
.x86
) {
100 return (msr
- MSR_P6_EVNTSEL0
);
102 return (msr
- MSR_P4_BSU_ESCR0
);
108 /* checks for a bit availability (hack for oprofile) */
109 int avail_to_resrv_perfctr_nmi_bit(unsigned int counter
)
111 BUG_ON(counter
> NMI_MAX_COUNTER_BITS
);
113 return (!test_bit(counter
, &__get_cpu_var(perfctr_nmi_owner
)));
116 /* checks the an msr for availability */
117 int avail_to_resrv_perfctr_nmi(unsigned int msr
)
119 unsigned int counter
;
121 counter
= nmi_perfctr_msr_to_bit(msr
);
122 BUG_ON(counter
> NMI_MAX_COUNTER_BITS
);
124 return (!test_bit(counter
, &__get_cpu_var(perfctr_nmi_owner
)));
127 int reserve_perfctr_nmi(unsigned int msr
)
129 unsigned int counter
;
131 counter
= nmi_perfctr_msr_to_bit(msr
);
132 BUG_ON(counter
> NMI_MAX_COUNTER_BITS
);
134 if (!test_and_set_bit(counter
, &__get_cpu_var(perfctr_nmi_owner
)))
139 void release_perfctr_nmi(unsigned int msr
)
141 unsigned int counter
;
143 counter
= nmi_perfctr_msr_to_bit(msr
);
144 BUG_ON(counter
> NMI_MAX_COUNTER_BITS
);
146 clear_bit(counter
, &__get_cpu_var(perfctr_nmi_owner
));
149 int reserve_evntsel_nmi(unsigned int msr
)
151 unsigned int counter
;
153 counter
= nmi_evntsel_msr_to_bit(msr
);
154 BUG_ON(counter
> NMI_MAX_COUNTER_BITS
);
156 if (!test_and_set_bit(counter
, &__get_cpu_var(evntsel_nmi_owner
)[0]))
161 void release_evntsel_nmi(unsigned int msr
)
163 unsigned int counter
;
165 counter
= nmi_evntsel_msr_to_bit(msr
);
166 BUG_ON(counter
> NMI_MAX_COUNTER_BITS
);
168 clear_bit(counter
, &__get_cpu_var(evntsel_nmi_owner
)[0]);
171 static __cpuinit
inline int nmi_known_cpu(void)
173 switch (boot_cpu_data
.x86_vendor
) {
175 return ((boot_cpu_data
.x86
== 15) || (boot_cpu_data
.x86
== 6));
176 case X86_VENDOR_INTEL
:
177 return ((boot_cpu_data
.x86
== 15) || (boot_cpu_data
.x86
== 6));
183 /* The performance counters used by NMI_LOCAL_APIC don't trigger when
184 * the CPU is idle. To make sure the NMI watchdog really ticks on all
185 * CPUs during the test make them busy.
187 static __init
void nmi_cpu_busy(void *data
)
189 volatile int *endflag
= data
;
190 local_irq_enable_in_hardirq();
191 /* Intentionally don't use cpu_relax here. This is
192 to make sure that the performance counter really ticks,
193 even if there is a simulator or similar that catches the
194 pause instruction. On a real HT machine this is fine because
195 all other CPUs are busy with "useless" delay loops and don't
196 care if they get somewhat less cycles. */
197 while (*endflag
== 0)
202 static int __init
check_nmi_watchdog(void)
204 volatile int endflag
= 0;
205 unsigned int *prev_nmi_count
;
208 if ((nmi_watchdog
== NMI_NONE
) || (nmi_watchdog
== NMI_DEFAULT
))
211 if (!atomic_read(&nmi_active
))
214 prev_nmi_count
= kmalloc(NR_CPUS
* sizeof(int), GFP_KERNEL
);
218 printk(KERN_INFO
"Testing NMI watchdog ... ");
220 if (nmi_watchdog
== NMI_LOCAL_APIC
)
221 smp_call_function(nmi_cpu_busy
, (void *)&endflag
, 0, 0);
223 for_each_possible_cpu(cpu
)
224 prev_nmi_count
[cpu
] = per_cpu(irq_stat
, cpu
).__nmi_count
;
226 mdelay((10*1000)/nmi_hz
); // wait 10 ticks
228 for_each_possible_cpu(cpu
) {
230 /* Check cpu_callin_map here because that is set
231 after the timer is started. */
232 if (!cpu_isset(cpu
, cpu_callin_map
))
235 if (!per_cpu(nmi_watchdog_ctlblk
, cpu
).enabled
)
237 if (nmi_count(cpu
) - prev_nmi_count
[cpu
] <= 5) {
238 printk("CPU#%d: NMI appears to be stuck (%d->%d)!\n",
242 per_cpu(nmi_watchdog_ctlblk
, cpu
).enabled
= 0;
243 atomic_dec(&nmi_active
);
246 if (!atomic_read(&nmi_active
)) {
247 kfree(prev_nmi_count
);
248 atomic_set(&nmi_active
, -1);
254 /* now that we know it works we can reduce NMI frequency to
255 something more reasonable; makes a difference in some configs */
256 if (nmi_watchdog
== NMI_LOCAL_APIC
)
259 kfree(prev_nmi_count
);
262 /* This needs to happen later in boot so counters are working */
263 late_initcall(check_nmi_watchdog
);
265 static int __init
setup_nmi_watchdog(char *str
)
269 get_option(&str
, &nmi
);
271 if ((nmi
>= NMI_INVALID
) || (nmi
< NMI_NONE
))
274 * If any other x86 CPU has a local APIC, then
275 * please test the NMI stuff there and send me the
276 * missing bits. Right now Intel P6/P4 and AMD K7 only.
278 if ((nmi
== NMI_LOCAL_APIC
) && (nmi_known_cpu() == 0))
279 return 0; /* no lapic support */
284 __setup("nmi_watchdog=", setup_nmi_watchdog
);
286 static void disable_lapic_nmi_watchdog(void)
288 BUG_ON(nmi_watchdog
!= NMI_LOCAL_APIC
);
290 if (atomic_read(&nmi_active
) <= 0)
293 on_each_cpu(stop_apic_nmi_watchdog
, NULL
, 0, 1);
295 BUG_ON(atomic_read(&nmi_active
) != 0);
298 static void enable_lapic_nmi_watchdog(void)
300 BUG_ON(nmi_watchdog
!= NMI_LOCAL_APIC
);
302 /* are we already enabled */
303 if (atomic_read(&nmi_active
) != 0)
306 /* are we lapic aware */
307 if (nmi_known_cpu() <= 0)
310 on_each_cpu(setup_apic_nmi_watchdog
, NULL
, 0, 1);
311 touch_nmi_watchdog();
314 void disable_timer_nmi_watchdog(void)
316 BUG_ON(nmi_watchdog
!= NMI_IO_APIC
);
318 if (atomic_read(&nmi_active
) <= 0)
322 on_each_cpu(stop_apic_nmi_watchdog
, NULL
, 0, 1);
324 BUG_ON(atomic_read(&nmi_active
) != 0);
327 void enable_timer_nmi_watchdog(void)
329 BUG_ON(nmi_watchdog
!= NMI_IO_APIC
);
331 if (atomic_read(&nmi_active
) == 0) {
332 touch_nmi_watchdog();
333 on_each_cpu(setup_apic_nmi_watchdog
, NULL
, 0, 1);
340 static int nmi_pm_active
; /* nmi_active before suspend */
342 static int lapic_nmi_suspend(struct sys_device
*dev
, pm_message_t state
)
344 nmi_pm_active
= atomic_read(&nmi_active
);
345 disable_lapic_nmi_watchdog();
349 static int lapic_nmi_resume(struct sys_device
*dev
)
351 if (nmi_pm_active
> 0)
352 enable_lapic_nmi_watchdog();
357 static struct sysdev_class nmi_sysclass
= {
358 set_kset_name("lapic_nmi"),
359 .resume
= lapic_nmi_resume
,
360 .suspend
= lapic_nmi_suspend
,
363 static struct sys_device device_lapic_nmi
= {
365 .cls
= &nmi_sysclass
,
368 static int __init
init_lapic_nmi_sysfs(void)
372 /* should really be a BUG_ON but b/c this is an
373 * init call, it just doesn't work. -dcz
375 if (nmi_watchdog
!= NMI_LOCAL_APIC
)
378 if ( atomic_read(&nmi_active
) < 0 )
381 error
= sysdev_class_register(&nmi_sysclass
);
383 error
= sysdev_register(&device_lapic_nmi
);
386 /* must come after the local APIC's device_initcall() */
387 late_initcall(init_lapic_nmi_sysfs
);
389 #endif /* CONFIG_PM */
392 * Activate the NMI watchdog via the local APIC.
393 * Original code written by Keith Owens.
396 static void write_watchdog_counter(unsigned int perfctr_msr
, const char *descr
)
398 u64 count
= (u64
)cpu_khz
* 1000;
400 do_div(count
, nmi_hz
);
402 Dprintk("setting %s to -0x%08Lx\n", descr
, count
);
403 wrmsrl(perfctr_msr
, 0 - count
);
406 /* Note that these events don't tick when the CPU idles. This means
407 the frequency varies with CPU load. */
409 #define K7_EVNTSEL_ENABLE (1 << 22)
410 #define K7_EVNTSEL_INT (1 << 20)
411 #define K7_EVNTSEL_OS (1 << 17)
412 #define K7_EVNTSEL_USR (1 << 16)
413 #define K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING 0x76
414 #define K7_NMI_EVENT K7_EVENT_CYCLES_PROCESSOR_IS_RUNNING
416 static int setup_k7_watchdog(void)
418 unsigned int perfctr_msr
, evntsel_msr
;
419 unsigned int evntsel
;
420 struct nmi_watchdog_ctlblk
*wd
= &__get_cpu_var(nmi_watchdog_ctlblk
);
422 perfctr_msr
= MSR_K7_PERFCTR0
;
423 evntsel_msr
= MSR_K7_EVNTSEL0
;
424 if (!reserve_perfctr_nmi(perfctr_msr
))
427 if (!reserve_evntsel_nmi(evntsel_msr
))
430 wrmsrl(perfctr_msr
, 0UL);
432 evntsel
= K7_EVNTSEL_INT
437 /* setup the timer */
438 wrmsr(evntsel_msr
, evntsel
, 0);
439 write_watchdog_counter(perfctr_msr
, "K7_PERFCTR0");
440 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
441 evntsel
|= K7_EVNTSEL_ENABLE
;
442 wrmsr(evntsel_msr
, evntsel
, 0);
444 wd
->perfctr_msr
= perfctr_msr
;
445 wd
->evntsel_msr
= evntsel_msr
;
446 wd
->cccr_msr
= 0; //unused
447 wd
->check_bit
= 1ULL<<63;
450 release_perfctr_nmi(perfctr_msr
);
455 static void stop_k7_watchdog(void)
457 struct nmi_watchdog_ctlblk
*wd
= &__get_cpu_var(nmi_watchdog_ctlblk
);
459 wrmsr(wd
->evntsel_msr
, 0, 0);
461 release_evntsel_nmi(wd
->evntsel_msr
);
462 release_perfctr_nmi(wd
->perfctr_msr
);
465 #define P6_EVNTSEL0_ENABLE (1 << 22)
466 #define P6_EVNTSEL_INT (1 << 20)
467 #define P6_EVNTSEL_OS (1 << 17)
468 #define P6_EVNTSEL_USR (1 << 16)
469 #define P6_EVENT_CPU_CLOCKS_NOT_HALTED 0x79
470 #define P6_NMI_EVENT P6_EVENT_CPU_CLOCKS_NOT_HALTED
472 static int setup_p6_watchdog(void)
474 unsigned int perfctr_msr
, evntsel_msr
;
475 unsigned int evntsel
;
476 struct nmi_watchdog_ctlblk
*wd
= &__get_cpu_var(nmi_watchdog_ctlblk
);
478 perfctr_msr
= MSR_P6_PERFCTR0
;
479 evntsel_msr
= MSR_P6_EVNTSEL0
;
480 if (!reserve_perfctr_nmi(perfctr_msr
))
483 if (!reserve_evntsel_nmi(evntsel_msr
))
486 wrmsrl(perfctr_msr
, 0UL);
488 evntsel
= P6_EVNTSEL_INT
493 /* setup the timer */
494 wrmsr(evntsel_msr
, evntsel
, 0);
495 write_watchdog_counter(perfctr_msr
, "P6_PERFCTR0");
496 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
497 evntsel
|= P6_EVNTSEL0_ENABLE
;
498 wrmsr(evntsel_msr
, evntsel
, 0);
500 wd
->perfctr_msr
= perfctr_msr
;
501 wd
->evntsel_msr
= evntsel_msr
;
502 wd
->cccr_msr
= 0; //unused
503 wd
->check_bit
= 1ULL<<39;
506 release_perfctr_nmi(perfctr_msr
);
511 static void stop_p6_watchdog(void)
513 struct nmi_watchdog_ctlblk
*wd
= &__get_cpu_var(nmi_watchdog_ctlblk
);
515 wrmsr(wd
->evntsel_msr
, 0, 0);
517 release_evntsel_nmi(wd
->evntsel_msr
);
518 release_perfctr_nmi(wd
->perfctr_msr
);
521 /* Note that these events don't tick when the CPU idles. This means
522 the frequency varies with CPU load. */
524 #define MSR_P4_MISC_ENABLE_PERF_AVAIL (1<<7)
525 #define P4_ESCR_EVENT_SELECT(N) ((N)<<25)
526 #define P4_ESCR_OS (1<<3)
527 #define P4_ESCR_USR (1<<2)
528 #define P4_CCCR_OVF_PMI0 (1<<26)
529 #define P4_CCCR_OVF_PMI1 (1<<27)
530 #define P4_CCCR_THRESHOLD(N) ((N)<<20)
531 #define P4_CCCR_COMPLEMENT (1<<19)
532 #define P4_CCCR_COMPARE (1<<18)
533 #define P4_CCCR_REQUIRED (3<<16)
534 #define P4_CCCR_ESCR_SELECT(N) ((N)<<13)
535 #define P4_CCCR_ENABLE (1<<12)
536 #define P4_CCCR_OVF (1<<31)
537 /* Set up IQ_COUNTER0 to behave like a clock, by having IQ_CCCR0 filter
538 CRU_ESCR0 (with any non-null event selector) through a complemented
539 max threshold. [IA32-Vol3, Section 14.9.9] */
541 static int setup_p4_watchdog(void)
543 unsigned int perfctr_msr
, evntsel_msr
, cccr_msr
;
544 unsigned int evntsel
, cccr_val
;
545 unsigned int misc_enable
, dummy
;
547 struct nmi_watchdog_ctlblk
*wd
= &__get_cpu_var(nmi_watchdog_ctlblk
);
549 rdmsr(MSR_IA32_MISC_ENABLE
, misc_enable
, dummy
);
550 if (!(misc_enable
& MSR_P4_MISC_ENABLE_PERF_AVAIL
))
554 /* detect which hyperthread we are on */
555 if (smp_num_siblings
== 2) {
556 unsigned int ebx
, apicid
;
559 apicid
= (ebx
>> 24) & 0xff;
565 /* performance counters are shared resources
566 * assign each hyperthread its own set
567 * (re-use the ESCR0 register, seems safe
568 * and keeps the cccr_val the same)
572 perfctr_msr
= MSR_P4_IQ_PERFCTR0
;
573 evntsel_msr
= MSR_P4_CRU_ESCR0
;
574 cccr_msr
= MSR_P4_IQ_CCCR0
;
575 cccr_val
= P4_CCCR_OVF_PMI0
| P4_CCCR_ESCR_SELECT(4);
578 perfctr_msr
= MSR_P4_IQ_PERFCTR1
;
579 evntsel_msr
= MSR_P4_CRU_ESCR0
;
580 cccr_msr
= MSR_P4_IQ_CCCR1
;
581 cccr_val
= P4_CCCR_OVF_PMI1
| P4_CCCR_ESCR_SELECT(4);
584 if (!reserve_perfctr_nmi(perfctr_msr
))
587 if (!reserve_evntsel_nmi(evntsel_msr
))
590 evntsel
= P4_ESCR_EVENT_SELECT(0x3F)
594 cccr_val
|= P4_CCCR_THRESHOLD(15)
599 wrmsr(evntsel_msr
, evntsel
, 0);
600 wrmsr(cccr_msr
, cccr_val
, 0);
601 write_watchdog_counter(perfctr_msr
, "P4_IQ_COUNTER0");
602 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
603 cccr_val
|= P4_CCCR_ENABLE
;
604 wrmsr(cccr_msr
, cccr_val
, 0);
605 wd
->perfctr_msr
= perfctr_msr
;
606 wd
->evntsel_msr
= evntsel_msr
;
607 wd
->cccr_msr
= cccr_msr
;
608 wd
->check_bit
= 1ULL<<39;
611 release_perfctr_nmi(perfctr_msr
);
616 static void stop_p4_watchdog(void)
618 struct nmi_watchdog_ctlblk
*wd
= &__get_cpu_var(nmi_watchdog_ctlblk
);
620 wrmsr(wd
->cccr_msr
, 0, 0);
621 wrmsr(wd
->evntsel_msr
, 0, 0);
623 release_evntsel_nmi(wd
->evntsel_msr
);
624 release_perfctr_nmi(wd
->perfctr_msr
);
627 void setup_apic_nmi_watchdog (void *unused
)
629 /* only support LOCAL and IO APICs for now */
630 if ((nmi_watchdog
!= NMI_LOCAL_APIC
) &&
631 (nmi_watchdog
!= NMI_IO_APIC
))
634 if (nmi_watchdog
== NMI_LOCAL_APIC
) {
635 switch (boot_cpu_data
.x86_vendor
) {
637 if (boot_cpu_data
.x86
!= 6 && boot_cpu_data
.x86
!= 15)
639 if (!setup_k7_watchdog())
642 case X86_VENDOR_INTEL
:
643 switch (boot_cpu_data
.x86
) {
645 if (boot_cpu_data
.x86_model
> 0xd)
648 if (!setup_p6_watchdog())
652 if (boot_cpu_data
.x86_model
> 0x4)
655 if (!setup_p4_watchdog())
666 __get_cpu_var(nmi_watchdog_ctlblk
.enabled
) = 1;
667 atomic_inc(&nmi_active
);
670 static void stop_apic_nmi_watchdog(void *unused
)
672 /* only support LOCAL and IO APICs for now */
673 if ((nmi_watchdog
!= NMI_LOCAL_APIC
) &&
674 (nmi_watchdog
!= NMI_IO_APIC
))
677 if (nmi_watchdog
== NMI_LOCAL_APIC
) {
678 switch (boot_cpu_data
.x86_vendor
) {
682 case X86_VENDOR_INTEL
:
683 switch (boot_cpu_data
.x86
) {
685 if (boot_cpu_data
.x86_model
> 0xd)
690 if (boot_cpu_data
.x86_model
> 0x4)
700 __get_cpu_var(nmi_watchdog_ctlblk
.enabled
) = 0;
701 atomic_dec(&nmi_active
);
705 * the best way to detect whether a CPU has a 'hard lockup' problem
706 * is to check it's local APIC timer IRQ counts. If they are not
707 * changing then that CPU has some problem.
709 * as these watchdog NMI IRQs are generated on every CPU, we only
710 * have to check the current processor.
712 * since NMIs don't listen to _any_ locks, we have to be extremely
713 * careful not to rely on unsafe variables. The printk might lock
714 * up though, so we have to break up any console locks first ...
715 * [when there will be more tty-related locks, break them up
720 last_irq_sums
[NR_CPUS
],
721 alert_counter
[NR_CPUS
];
723 void touch_nmi_watchdog (void)
728 * Just reset the alert counters, (other CPUs might be
729 * spinning on locks we hold):
731 for_each_possible_cpu(i
)
732 alert_counter
[i
] = 0;
735 * Tickle the softlockup detector too:
737 touch_softlockup_watchdog();
739 EXPORT_SYMBOL(touch_nmi_watchdog
);
741 extern void die_nmi(struct pt_regs
*, const char *msg
);
743 int nmi_watchdog_tick (struct pt_regs
* regs
, unsigned reason
)
747 * Since current_thread_info()-> is always on the stack, and we
748 * always switch the stack NMI-atomically, it's safe to use
749 * smp_processor_id().
753 int cpu
= smp_processor_id();
754 struct nmi_watchdog_ctlblk
*wd
= &__get_cpu_var(nmi_watchdog_ctlblk
);
758 /* check for other users first */
759 if (notify_die(DIE_NMI
, "nmi", regs
, reason
, 2, SIGINT
)
765 sum
= per_cpu(irq_stat
, cpu
).apic_timer_irqs
;
767 /* if the apic timer isn't firing, this cpu isn't doing much */
768 if (!touched
&& last_irq_sums
[cpu
] == sum
) {
770 * Ayiee, looks like this CPU is stuck ...
771 * wait a few IRQs (5 seconds) before doing the oops ...
773 alert_counter
[cpu
]++;
774 if (alert_counter
[cpu
] == 5*nmi_hz
)
776 * die_nmi will return ONLY if NOTIFY_STOP happens..
778 die_nmi(regs
, "BUG: NMI Watchdog detected LOCKUP");
780 last_irq_sums
[cpu
] = sum
;
781 alert_counter
[cpu
] = 0;
783 /* see if the nmi watchdog went off */
785 if (nmi_watchdog
== NMI_LOCAL_APIC
) {
786 rdmsrl(wd
->perfctr_msr
, dummy
);
787 if (dummy
& wd
->check_bit
){
788 /* this wasn't a watchdog timer interrupt */
792 /* only Intel P4 uses the cccr msr */
793 if (wd
->cccr_msr
!= 0) {
796 * - An overflown perfctr will assert its interrupt
797 * until the OVF flag in its CCCR is cleared.
798 * - LVTPC is masked on interrupt and must be
799 * unmasked by the LVTPC handler.
801 rdmsrl(wd
->cccr_msr
, dummy
);
802 dummy
&= ~P4_CCCR_OVF
;
803 wrmsrl(wd
->cccr_msr
, dummy
);
804 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
806 else if (wd
->perfctr_msr
== MSR_P6_PERFCTR0
) {
807 /* Only P6 based Pentium M need to re-unmask
808 * the apic vector but it doesn't hurt
809 * other P6 variant */
810 apic_write(APIC_LVTPC
, APIC_DM_NMI
);
812 /* start the cycle over again */
813 write_watchdog_counter(wd
->perfctr_msr
, NULL
);
815 } else if (nmi_watchdog
== NMI_IO_APIC
) {
816 /* don't know how to accurately check for this.
817 * just assume it was a watchdog timer interrupt
818 * This matches the old behaviour.
822 printk(KERN_WARNING
"Unknown enabled NMI hardware?!\n");
828 int do_nmi_callback(struct pt_regs
* regs
, int cpu
)
831 if (unknown_nmi_panic
)
832 return unknown_nmi_panic_callback(regs
, cpu
);
839 static int unknown_nmi_panic_callback(struct pt_regs
*regs
, int cpu
)
841 unsigned char reason
= get_nmi_reason();
844 sprintf(buf
, "NMI received for unknown reason %02x\n", reason
);
851 EXPORT_SYMBOL(nmi_active
);
852 EXPORT_SYMBOL(nmi_watchdog
);
853 EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi
);
854 EXPORT_SYMBOL(avail_to_resrv_perfctr_nmi_bit
);
855 EXPORT_SYMBOL(reserve_perfctr_nmi
);
856 EXPORT_SYMBOL(release_perfctr_nmi
);
857 EXPORT_SYMBOL(reserve_evntsel_nmi
);
858 EXPORT_SYMBOL(release_evntsel_nmi
);
859 EXPORT_SYMBOL(disable_timer_nmi_watchdog
);
860 EXPORT_SYMBOL(enable_timer_nmi_watchdog
);