arch/powerpc/platforms/chrp/setup.c

   1 /*
   2  *  Copyright (C) 1995  Linus Torvalds
   3  *  Adapted from 'alpha' version by Gary Thomas
   4  *  Modified by Cort Dougan (cort@cs.nmt.edu)
   5  */
   6
   7 /*
   8  * bootup setup stuff..
   9  */
  10
  11 #include <linux/errno.h>
  12 #include <linux/sched.h>
  13 #include <linux/kernel.h>
  14 #include <linux/mm.h>
  15 #include <linux/stddef.h>
  16 #include <linux/unistd.h>
  17 #include <linux/ptrace.h>
  18 #include <linux/slab.h>
  19 #include <linux/user.h>
  20 #include <linux/a.out.h>
  21 #include <linux/tty.h>
  22 #include <linux/major.h>
  23 #include <linux/interrupt.h>
  24 #include <linux/reboot.h>
  25 #include <linux/init.h>
  26 #include <linux/pci.h>
  27 #include <linux/utsrelease.h>
  28 #include <linux/adb.h>
  29 #include <linux/module.h>
  30 #include <linux/delay.h>
  31 #include <linux/console.h>
  32 #include <linux/seq_file.h>
  33 #include <linux/root_dev.h>
  34 #include <linux/initrd.h>
  35 #include <linux/module.h>
  36 #include <linux/timer.h>
  37
  38 #include <asm/io.h>
  39 #include <asm/pgtable.h>
  40 #include <asm/prom.h>
  41 #include <asm/gg2.h>
  42 #include <asm/pci-bridge.h>
  43 #include <asm/dma.h>
  44 #include <asm/machdep.h>
  45 #include <asm/irq.h>
  46 #include <asm/hydra.h>
  47 #include <asm/sections.h>
  48 #include <asm/time.h>
  49 #include <asm/i8259.h>
  50 #include <asm/mpic.h>
  51 #include <asm/rtas.h>
  52 #include <asm/xmon.h>
  53
  54 #include "chrp.h"
  55
  56 void rtas_indicator_progress(char *, unsigned short);
  57
  58 int _chrp_type;
  59 EXPORT_SYMBOL(_chrp_type);
  60
  61 static struct mpic *chrp_mpic;
  62
  63 /* Used for doing CHRP event-scans */
  64 DEFINE_PER_CPU(struct timer_list, heartbeat_timer);
  65 unsigned long event_scan_interval;
  66
  67 /*
  68  * XXX this should be in xmon.h, but putting it there means xmon.h
  69  * has to include <linux/interrupt.h> (to get irqreturn_t), which
  70  * causes all sorts of problems.  -- paulus
  71  */
  72 extern irqreturn_t xmon_irq(int, void *);
  73
  74 extern unsigned long loops_per_jiffy;
  75
  76 /* To be replaced by RTAS when available */
  77 static unsigned int __iomem *briq_SPOR;
  78
  79 #ifdef CONFIG_SMP
  80 extern struct smp_ops_t chrp_smp_ops;
  81 #endif
  82
  83 static const char *gg2_memtypes[4] = {
  84         "FPM", "SDRAM", "EDO", "BEDO"
  85 };
  86 static const char *gg2_cachesizes[4] = {
  87         "256 KB", "512 KB", "1 MB", "Reserved"
  88 };
  89 static const char *gg2_cachetypes[4] = {
  90         "Asynchronous", "Reserved", "Flow-Through Synchronous",
  91         "Pipelined Synchronous"
  92 };
  93 static const char *gg2_cachemodes[4] = {
  94         "Disabled", "Write-Through", "Copy-Back", "Transparent Mode"
  95 };
  96
  97 static const char *chrp_names[] = {
  98         "Unknown",
  99         "","","",
 100         "Motorola",
 101         "IBM or Longtrail",
 102         "Genesi Pegasos",
 103         "Total Impact Briq"
 104 };
 105
 106 void chrp_show_cpuinfo(struct seq_file *m)
 107 {
 108         int i, sdramen;
 109         unsigned int t;
 110         struct device_node *root;
 111         const char *model = "";
 112
 113         root = of_find_node_by_path("/");
 114         if (root)
 115                 model = of_get_property(root, "model", NULL);
 116         seq_printf(m, "machine\t\t: CHRP %s\n", model);
 117
 118         /* longtrail (goldengate) stuff */
 119         if (!strncmp(model, "IBM,LongTrail", 13)) {
 120                 /* VLSI VAS96011/12 `Golden Gate 2' */
 121                 /* Memory banks */
 122                 sdramen = (in_le32(gg2_pci_config_base + GG2_PCI_DRAM_CTRL)
 123                            >>31) & 1;
 124                 for (i = 0; i < (sdramen ? 4 : 6); i++) {
 125                         t = in_le32(gg2_pci_config_base+
 126                                                  GG2_PCI_DRAM_BANK0+
 127                                                  i*4);
 128                         if (!(t & 1))
 129                                 continue;
 130                         switch ((t>>8) & 0x1f) {
 131                         case 0x1f:
 132                                 model = "4 MB";
 133                                 break;
 134                         case 0x1e:
 135                                 model = "8 MB";
 136                                 break;
 137                         case 0x1c:
 138                                 model = "16 MB";
 139                                 break;
 140                         case 0x18:
 141                                 model = "32 MB";
 142                                 break;
 143                         case 0x10:
 144                                 model = "64 MB";
 145                                 break;
 146                         case 0x00:
 147                                 model = "128 MB";
 148                                 break;
 149                         default:
 150                                 model = "Reserved";
 151                                 break;
 152                         }
 153                         seq_printf(m, "memory bank %d\t: %s %s\n", i, model,
 154                                    gg2_memtypes[sdramen ? 1 : ((t>>1) & 3)]);
 155                 }
 156                 /* L2 cache */
 157                 t = in_le32(gg2_pci_config_base+GG2_PCI_CC_CTRL);
 158                 seq_printf(m, "board l2\t: %s %s (%s)\n",
 159                            gg2_cachesizes[(t>>7) & 3],
 160                            gg2_cachetypes[(t>>2) & 3],
 161                            gg2_cachemodes[t & 3]);
 162         }
 163         of_node_put(root);
 164 }
 165
 166 /*
 167  *  Fixes for the National Semiconductor PC78308VUL SuperI/O
 168  *
 169  *  Some versions of Open Firmware incorrectly initialize the IRQ settings
 170  *  for keyboard and mouse
 171  */
 172 static inline void __init sio_write(u8 val, u8 index)
 173 {
 174         outb(index, 0x15c);
 175         outb(val, 0x15d);
 176 }
 177
 178 static inline u8 __init sio_read(u8 index)
 179 {
 180         outb(index, 0x15c);
 181         return inb(0x15d);
 182 }
 183
 184 static void __init sio_fixup_irq(const char *name, u8 device, u8 level,
 185                                      u8 type)
 186 {
 187         u8 level0, type0, active;
 188
 189         /* select logical device */
 190         sio_write(device, 0x07);
 191         active = sio_read(0x30);
 192         level0 = sio_read(0x70);
 193         type0 = sio_read(0x71);
 194         if (level0 != level || type0 != type || !active) {
 195                 printk(KERN_WARNING "sio: %s irq level %d, type %d, %sactive: "
 196                        "remapping to level %d, type %d, active\n",
 197                        name, level0, type0, !active ? "in" : "", level, type);
 198                 sio_write(0x01, 0x30);
 199                 sio_write(level, 0x70);
 200                 sio_write(type, 0x71);
 201         }
 202 }
 203
 204 static void __init sio_init(void)
 205 {
 206         struct device_node *root;
 207
 208         if ((root = of_find_node_by_path("/")) &&
 209             !strncmp(of_get_property(root, "model", NULL),
 210                         "IBM,LongTrail", 13)) {
 211                 /* logical device 0 (KBC/Keyboard) */
 212                 sio_fixup_irq("keyboard", 0, 1, 2);
 213                 /* select logical device 1 (KBC/Mouse) */
 214                 sio_fixup_irq("mouse", 1, 12, 2);
 215         }
 216         of_node_put(root);
 217 }
 218
 219
 220 static void __init pegasos_set_l2cr(void)
 221 {
 222         struct device_node *np;
 223
 224         /* On Pegasos, enable the l2 cache if needed, as the OF forgets it */
 225         if (_chrp_type != _CHRP_Pegasos)
 226                 return;
 227
 228         /* Enable L2 cache if needed */
 229         np = of_find_node_by_type(NULL, "cpu");
 230         if (np != NULL) {
 231                 const unsigned int *l2cr = of_get_property(np, "l2cr", NULL);
 232                 if (l2cr == NULL) {
 233                         printk ("Pegasos l2cr : no cpu l2cr property found\n");
 234                         goto out;
 235                 }
 236                 if (!((*l2cr) & 0x80000000)) {
 237                         printk ("Pegasos l2cr : L2 cache was not active, "
 238                                 "activating\n");
 239                         _set_L2CR(0);
 240                         _set_L2CR((*l2cr) | 0x80000000);
 241                 }
 242         }
 243 out:
 244         of_node_put(np);
 245 }
 246
 247 static void briq_restart(char *cmd)
 248 {
 249         local_irq_disable();
 250         if (briq_SPOR)
 251                 out_be32(briq_SPOR, 0);
 252         for(;;);
 253 }
 254
 255 void __init chrp_setup_arch(void)
 256 {
 257         struct device_node *root = of_find_node_by_path("/");
 258         const char *machine = NULL;
 259
 260         /* init to some ~sane value until calibrate_delay() runs */
 261         loops_per_jiffy = 50000000/HZ;
 262
 263         if (root)
 264                 machine = of_get_property(root, "model", NULL);
 265         if (machine && strncmp(machine, "Pegasos", 7) == 0) {
 266                 _chrp_type = _CHRP_Pegasos;
 267         } else if (machine && strncmp(machine, "IBM", 3) == 0) {
 268                 _chrp_type = _CHRP_IBM;
 269         } else if (machine && strncmp(machine, "MOT", 3) == 0) {
 270                 _chrp_type = _CHRP_Motorola;
 271         } else if (machine && strncmp(machine, "TotalImpact,BRIQ-1", 18) == 0) {
 272                 _chrp_type = _CHRP_briq;
 273                 /* Map the SPOR register on briq and change the restart hook */
 274                 briq_SPOR = ioremap(0xff0000e8, 4);
 275                 ppc_md.restart = briq_restart;
 276         } else {
 277                 /* Let's assume it is an IBM chrp if all else fails */
 278                 _chrp_type = _CHRP_IBM;
 279         }
 280         of_node_put(root);
 281         printk("chrp type = %x [%s]\n", _chrp_type, chrp_names[_chrp_type]);
 282
 283         rtas_initialize();
 284         if (rtas_token("display-character") >= 0)
 285                 ppc_md.progress = rtas_progress;
 286
 287         /* use RTAS time-of-day routines if available */
 288         if (rtas_token("get-time-of-day") != RTAS_UNKNOWN_SERVICE) {
 289                 ppc_md.get_boot_time    = rtas_get_boot_time;
 290                 ppc_md.get_rtc_time     = rtas_get_rtc_time;
 291                 ppc_md.set_rtc_time     = rtas_set_rtc_time;
 292         }
 293
 294 #ifdef CONFIG_BLK_DEV_INITRD
 295         /* this is fine for chrp */
 296         initrd_below_start_ok = 1;
 297
 298         if (initrd_start)
 299                 ROOT_DEV = Root_RAM0;
 300         else
 301 #endif
 302                 ROOT_DEV = Root_SDA2; /* sda2 (sda1 is for the kernel) */
 303
 304         /* On pegasos, enable the L2 cache if not already done by OF */
 305         pegasos_set_l2cr();
 306
 307         /* Lookup PCI host bridges */
 308         chrp_find_bridges();
 309
 310         /*
 311          *  Temporary fixes for PCI devices.
 312          *  -- Geert
 313          */
 314         hydra_init();           /* Mac I/O */
 315
 316         /*
 317          *  Fix the Super I/O configuration
 318          */
 319         sio_init();
 320
 321         pci_create_OF_bus_map();
 322
 323         /*
 324          * Print the banner, then scroll down so boot progress
 325          * can be printed.  -- Cort
 326          */
 327         if (ppc_md.progress) ppc_md.progress("Linux/PPC "UTS_RELEASE"\n", 0x0);
 328 }
 329
 330 void
 331 chrp_event_scan(unsigned long unused)
 332 {
 333         unsigned char log[1024];
 334         int ret = 0;
 335
 336         /* XXX: we should loop until the hardware says no more error logs -- Cort */
 337         rtas_call(rtas_token("event-scan"), 4, 1, &ret, 0xffffffff, 0,
 338                   __pa(log), 1024);
 339         mod_timer(&__get_cpu_var(heartbeat_timer),
 340                   jiffies + event_scan_interval);
 341 }
 342
 343 static void chrp_8259_cascade(unsigned int irq, struct irq_desc *desc)
 344 {
 345         unsigned int cascade_irq = i8259_irq();
 346         if (cascade_irq != NO_IRQ)
 347                 generic_handle_irq(cascade_irq);
 348         desc->chip->eoi(irq);
 349 }
 350
 351 /*
 352  * Finds the open-pic node and sets up the mpic driver.
 353  */
 354 static void __init chrp_find_openpic(void)
 355 {
 356         struct device_node *np, *root;
 357         int len, i, j;
 358         int isu_size, idu_size;
 359         const unsigned int *iranges, *opprop = NULL;
 360         int oplen = 0;
 361         unsigned long opaddr;
 362         int na = 1;
 363
 364         np = of_find_node_by_type(NULL, "open-pic");
 365         if (np == NULL)
 366                 return;
 367         root = of_find_node_by_path("/");
 368         if (root) {
 369                 opprop = of_get_property(root, "platform-open-pic", &oplen);
 370                 na = of_n_addr_cells(root);
 371         }
 372         if (opprop && oplen >= na * sizeof(unsigned int)) {
 373                 opaddr = opprop[na-1];  /* assume 32-bit */
 374                 oplen /= na * sizeof(unsigned int);
 375         } else {
 376                 struct resource r;
 377                 if (of_address_to_resource(np, 0, &r)) {
 378                         goto bail;
 379                 }
 380                 opaddr = r.start;
 381                 oplen = 0;
 382         }
 383
 384         printk(KERN_INFO "OpenPIC at %lx\n", opaddr);
 385
 386         iranges = of_get_property(np, "interrupt-ranges", &len);
 387         if (iranges == NULL)
 388                 len = 0;        /* non-distributed mpic */
 389         else
 390                 len /= 2 * sizeof(unsigned int);
 391
 392         /*
 393          * The first pair of cells in interrupt-ranges refers to the
 394          * IDU; subsequent pairs refer to the ISUs.
 395          */
 396         if (oplen < len) {
 397                 printk(KERN_ERR "Insufficient addresses for distributed"
 398                        " OpenPIC (%d < %d)\n", oplen, len);
 399                 len = oplen;
 400         }
 401
 402         isu_size = 0;
 403         idu_size = 0;
 404         if (len > 0 && iranges[1] != 0) {
 405                 printk(KERN_INFO "OpenPIC irqs %d..%d in IDU\n",
 406                        iranges[0], iranges[0] + iranges[1] - 1);
 407                 idu_size = iranges[1];
 408         }
 409         if (len > 1)
 410                 isu_size = iranges[3];
 411
 412         chrp_mpic = mpic_alloc(np, opaddr, MPIC_PRIMARY,
 413                                isu_size, 0, " MPIC    ");
 414         if (chrp_mpic == NULL) {
 415                 printk(KERN_ERR "Failed to allocate MPIC structure\n");
 416                 goto bail;
 417         }
 418         j = na - 1;
 419         for (i = 1; i < len; ++i) {
 420                 iranges += 2;
 421                 j += na;
 422                 printk(KERN_INFO "OpenPIC irqs %d..%d in ISU at %x\n",
 423                        iranges[0], iranges[0] + iranges[1] - 1,
 424                        opprop[j]);
 425                 mpic_assign_isu(chrp_mpic, i - 1, opprop[j]);
 426         }
 427
 428         mpic_init(chrp_mpic);
 429         ppc_md.get_irq = mpic_get_irq;
 430  bail:
 431         of_node_put(root);
 432         of_node_put(np);
 433 }
 434
 435 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON)
 436 static struct irqaction xmon_irqaction = {
 437         .handler = xmon_irq,
 438         .mask = CPU_MASK_NONE,
 439         .name = "XMON break",
 440 };
 441 #endif
 442
 443 static void __init chrp_find_8259(void)
 444 {
 445         struct device_node *np, *pic = NULL;
 446         unsigned long chrp_int_ack = 0;
 447         unsigned int cascade_irq;
 448
 449         /* Look for cascade */
 450         for_each_node_by_type(np, "interrupt-controller")
 451                 if (of_device_is_compatible(np, "chrp,iic")) {
 452                         pic = np;
 453                         break;
 454                 }
 455         /* Ok, 8259 wasn't found. We need to handle the case where
 456          * we have a pegasos that claims to be chrp but doesn't have
 457          * a proper interrupt tree
 458          */
 459         if (pic == NULL && chrp_mpic != NULL) {
 460                 printk(KERN_ERR "i8259: Not found in device-tree"
 461                        " assuming no legacy interrupts\n");
 462                 return;
 463         }
 464
 465         /* Look for intack. In a perfect world, we would look for it on
 466          * the ISA bus that holds the 8259 but heh... Works that way. If
 467          * we ever see a problem, we can try to re-use the pSeries code here.
 468          * Also, Pegasos-type platforms don't have a proper node to start
 469          * from anyway
 470          */
 471         for_each_node_by_name(np, "pci") {
 472                 const unsigned int *addrp = of_get_property(np,
 473                                 "8259-interrupt-acknowledge", NULL);
 474
 475                 if (addrp == NULL)
 476                         continue;
 477                 chrp_int_ack = addrp[of_n_addr_cells(np)-1];
 478                 break;
 479         }
 480         of_node_put(np);
 481         if (np == NULL)
 482                 printk(KERN_WARNING "Cannot find PCI interrupt acknowledge"
 483                        " address, polling\n");
 484
 485         i8259_init(pic, chrp_int_ack);
 486         if (ppc_md.get_irq == NULL) {
 487                 ppc_md.get_irq = i8259_irq;
 488                 irq_set_default_host(i8259_get_host());
 489         }
 490         if (chrp_mpic != NULL) {
 491                 cascade_irq = irq_of_parse_and_map(pic, 0);
 492                 if (cascade_irq == NO_IRQ)
 493                         printk(KERN_ERR "i8259: failed to map cascade irq\n");
 494                 else
 495                         set_irq_chained_handler(cascade_irq,
 496                                                 chrp_8259_cascade);
 497         }
 498 }
 499
 500 void __init chrp_init_IRQ(void)
 501 {
 502 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON)
 503         struct device_node *kbd;
 504 #endif
 505         chrp_find_openpic();
 506         chrp_find_8259();
 507
 508 #ifdef CONFIG_SMP
 509         /* Pegasos has no MPIC, those ops would make it crash. It might be an
 510          * option to move setting them to after we probe the PIC though
 511          */
 512         if (chrp_mpic != NULL)
 513                 smp_ops = &chrp_smp_ops;
 514 #endif /* CONFIG_SMP */
 515
 516         if (_chrp_type == _CHRP_Pegasos)
 517                 ppc_md.get_irq        = i8259_irq;
 518
 519 #if defined(CONFIG_VT) && defined(CONFIG_INPUT_ADBHID) && defined(CONFIG_XMON)
 520         /* see if there is a keyboard in the device tree
 521            with a parent of type "adb" */
 522         for_each_node_by_name(kbd, "keyboard")
 523                 if (kbd->parent && kbd->parent->type
 524                     && strcmp(kbd->parent->type, "adb") == 0)
 525                         break;
 526         of_node_put(kbd);
 527         if (kbd)
 528                 setup_irq(HYDRA_INT_ADB_NMI, &xmon_irqaction);
 529 #endif
 530 }
 531
 532 void __init
 533 chrp_init2(void)
 534 {
 535         struct device_node *device;
 536         const unsigned int *p = NULL;
 537
 538 #ifdef CONFIG_NVRAM
 539         chrp_nvram_init();
 540 #endif
 541
 542         request_region(0x20,0x20,"pic1");
 543         request_region(0xa0,0x20,"pic2");
 544         request_region(0x00,0x20,"dma1");
 545         request_region(0x40,0x20,"timer");
 546         request_region(0x80,0x10,"dma page reg");
 547         request_region(0xc0,0x20,"dma2");
 548
 549         /* Get the event scan rate for the rtas so we know how
 550          * often it expects a heartbeat. -- Cort
 551          */
 552         device = of_find_node_by_name(NULL, "rtas");
 553         if (device)
 554                 p = of_get_property(device, "rtas-event-scan-rate", NULL);
 555         if (p && *p) {
 556                 /*
 557                  * Arrange to call chrp_event_scan at least *p times
 558                  * per minute.  We use 59 rather than 60 here so that
 559                  * the rate will be slightly higher than the minimum.
 560                  * This all assumes we don't do hotplug CPU on any
 561                  * machine that needs the event scans done.
 562                  */
 563                 unsigned long interval, offset;
 564                 int cpu, ncpus;
 565                 struct timer_list *timer;
 566
 567                 interval = HZ * 59 / *p;
 568                 offset = HZ;
 569                 ncpus = num_online_cpus();
 570                 event_scan_interval = ncpus * interval;
 571                 for (cpu = 0; cpu < ncpus; ++cpu) {
 572                         timer = &per_cpu(heartbeat_timer, cpu);
 573                         setup_timer(timer, chrp_event_scan, 0);
 574                         timer->expires = jiffies + offset;
 575                         add_timer_on(timer, cpu);
 576                         offset += interval;
 577                 }
 578                 printk("RTAS Event Scan Rate: %u (%lu jiffies)\n",
 579                        *p, interval);
 580         }
 581         of_node_put(device);
 582
 583         if (ppc_md.progress)
 584                 ppc_md.progress("  Have fun!    ", 0x7777);
 585 }
 586
 587 static int __init chrp_probe(void)
 588 {
 589         char *dtype = of_get_flat_dt_prop(of_get_flat_dt_root(),
 590                                           "device_type", NULL);
 591         if (dtype == NULL)
 592                 return 0;
 593         if (strcmp(dtype, "chrp"))
 594                 return 0;
 595
 596         ISA_DMA_THRESHOLD = ~0L;
 597         DMA_MODE_READ = 0x44;
 598         DMA_MODE_WRITE = 0x48;
 599
 600         return 1;
 601 }
 602
 603 define_machine(chrp) {
 604         .name                   = "CHRP",
 605         .probe                  = chrp_probe,
 606         .setup_arch             = chrp_setup_arch,
 607         .init                   = chrp_init2,
 608         .show_cpuinfo           = chrp_show_cpuinfo,
 609         .init_IRQ               = chrp_init_IRQ,
 610         .restart                = rtas_restart,
 611         .power_off              = rtas_power_off,
 612         .halt                   = rtas_halt,
 613         .time_init              = chrp_time_init,
 614         .set_rtc_time           = chrp_set_rtc_time,
 615         .get_rtc_time           = chrp_get_rtc_time,
 616         .calibrate_decr         = generic_calibrate_decr,
 617         .phys_mem_access_prot   = pci_phys_mem_access_prot,
 618 };