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[TCP]: TCP_CONG_YEAH requires TCP_CONG_VEGAS
[linux-2.6/verdex.git] / drivers / net / skge.c
blob776692946562090527838259d780db424b9afc11
1 /*
2 * New driver for Marvell Yukon chipset and SysKonnect Gigabit
3 * Ethernet adapters. Based on earlier sk98lin, e100 and
4 * FreeBSD if_sk drivers.
5 *
6 * This driver intentionally does not support all the features
7 * of the original driver such as link fail-over and link management because
8 * those should be done at higher levels.
9 *
10 * Copyright (C) 2004, 2005 Stephen Hemminger <shemminger@osdl.org>
11 *
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 */
25
26 #include <linux/in.h>
27 #include <linux/kernel.h>
28 #include <linux/module.h>
29 #include <linux/moduleparam.h>
30 #include <linux/netdevice.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
34 #include <linux/if_vlan.h>
35 #include <linux/ip.h>
36 #include <linux/delay.h>
37 #include <linux/crc32.h>
38 #include <linux/dma-mapping.h>
39 #include <linux/mii.h>
40 #include <asm/irq.h>
41
42 #include "skge.h"
43
44 #define DRV_NAME "skge"
45 #define DRV_VERSION "1.11"
46 #define PFX DRV_NAME " "
47
48 #define DEFAULT_TX_RING_SIZE 128
49 #define DEFAULT_RX_RING_SIZE 512
50 #define MAX_TX_RING_SIZE 1024
51 #define TX_LOW_WATER (MAX_SKB_FRAGS + 1)
52 #define MAX_RX_RING_SIZE 4096
53 #define RX_COPY_THRESHOLD 128
54 #define RX_BUF_SIZE 1536
55 #define PHY_RETRIES 1000
56 #define ETH_JUMBO_MTU 9000
57 #define TX_WATCHDOG (5 * HZ)
58 #define NAPI_WEIGHT 64
59 #define BLINK_MS 250
60 #define LINK_HZ (HZ/2)
61
62 MODULE_DESCRIPTION("SysKonnect Gigabit Ethernet driver");
63 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
64 MODULE_LICENSE("GPL");
65 MODULE_VERSION(DRV_VERSION);
66
67 static const u32 default_msg
68 = NETIF_MSG_DRV| NETIF_MSG_PROBE| NETIF_MSG_LINK
69 | NETIF_MSG_IFUP| NETIF_MSG_IFDOWN;
70
71 static int debug = -1; /* defaults above */
72 module_param(debug, int, 0);
73 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
74
75 static const struct pci_device_id skge_id_table[] = {
76 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940) },
77 { PCI_DEVICE(PCI_VENDOR_ID_3COM, PCI_DEVICE_ID_3COM_3C940B) },
78 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_GE) },
79 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, PCI_DEVICE_ID_SYSKONNECT_YU) },
80 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, PCI_DEVICE_ID_DLINK_DGE510T) },
81 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b01) }, /* DGE-530T */
82 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4320) },
83 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x5005) }, /* Belkin */
84 { PCI_DEVICE(PCI_VENDOR_ID_CNET, PCI_DEVICE_ID_CNET_GIGACARD) },
85 { PCI_DEVICE(PCI_VENDOR_ID_LINKSYS, PCI_DEVICE_ID_LINKSYS_EG1064) },
86 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0015 },
87 { 0 }
88 };
89 MODULE_DEVICE_TABLE(pci, skge_id_table);
90
91 static int skge_up(struct net_device *dev);
92 static int skge_down(struct net_device *dev);
93 static void skge_phy_reset(struct skge_port *skge);
94 static void skge_tx_clean(struct net_device *dev);
95 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
96 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val);
97 static void genesis_get_stats(struct skge_port *skge, u64 *data);
98 static void yukon_get_stats(struct skge_port *skge, u64 *data);
99 static void yukon_init(struct skge_hw *hw, int port);
100 static void genesis_mac_init(struct skge_hw *hw, int port);
101 static void genesis_link_up(struct skge_port *skge);
102
103 /* Avoid conditionals by using array */
104 static const int txqaddr[] = { Q_XA1, Q_XA2 };
105 static const int rxqaddr[] = { Q_R1, Q_R2 };
106 static const u32 rxirqmask[] = { IS_R1_F, IS_R2_F };
107 static const u32 txirqmask[] = { IS_XA1_F, IS_XA2_F };
108 static const u32 napimask[] = { IS_R1_F|IS_XA1_F, IS_R2_F|IS_XA2_F };
109 static const u32 portmask[] = { IS_PORT_1, IS_PORT_2 };
110
111 static int skge_get_regs_len(struct net_device *dev)
112 {
113 return 0x4000;
114 }
115
116 /*
117 * Returns copy of whole control register region
118 * Note: skip RAM address register because accessing it will
119 * cause bus hangs!
120 */
121 static void skge_get_regs(struct net_device *dev, struct ethtool_regs *regs,
122 void *p)
123 {
124 const struct skge_port *skge = netdev_priv(dev);
125 const void __iomem *io = skge->hw->regs;
126
127 regs->version = 1;
128 memset(p, 0, regs->len);
129 memcpy_fromio(p, io, B3_RAM_ADDR);
130
131 memcpy_fromio(p + B3_RI_WTO_R1, io + B3_RI_WTO_R1,
132 regs->len - B3_RI_WTO_R1);
133 }
134
135 /* Wake on Lan only supported on Yukon chips with rev 1 or above */
136 static u32 wol_supported(const struct skge_hw *hw)
137 {
138 if (hw->chip_id == CHIP_ID_GENESIS)
139 return 0;
140
141 if (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
142 return 0;
143
144 return WAKE_MAGIC | WAKE_PHY;
145 }
146
147 static u32 pci_wake_enabled(struct pci_dev *dev)
148 {
149 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
150 u16 value;
151
152 /* If device doesn't support PM Capabilities, but request is to disable
153 * wake events, it's a nop; otherwise fail */
154 if (!pm)
155 return 0;
156
157 pci_read_config_word(dev, pm + PCI_PM_PMC, &value);
158
159 value &= PCI_PM_CAP_PME_MASK;
160 value >>= ffs(PCI_PM_CAP_PME_MASK) - 1; /* First bit of mask */
161
162 return value != 0;
163 }
164
165 static void skge_wol_init(struct skge_port *skge)
166 {
167 struct skge_hw *hw = skge->hw;
168 int port = skge->port;
169 u16 ctrl;
170
171 skge_write16(hw, B0_CTST, CS_RST_CLR);
172 skge_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
173
174 /* Turn on Vaux */
175 skge_write8(hw, B0_POWER_CTRL,
176 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_ON | PC_VCC_OFF);
177
178 /* WA code for COMA mode -- clear PHY reset */
179 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
180 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
181 u32 reg = skge_read32(hw, B2_GP_IO);
182 reg |= GP_DIR_9;
183 reg &= ~GP_IO_9;
184 skge_write32(hw, B2_GP_IO, reg);
185 }
186
187 skge_write32(hw, SK_REG(port, GPHY_CTRL),
188 GPC_DIS_SLEEP |
189 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
190 GPC_ANEG_1 | GPC_RST_SET);
191
192 skge_write32(hw, SK_REG(port, GPHY_CTRL),
193 GPC_DIS_SLEEP |
194 GPC_HWCFG_M_3 | GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0 |
195 GPC_ANEG_1 | GPC_RST_CLR);
196
197 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
198
199 /* Force to 10/100 skge_reset will re-enable on resume */
200 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV,
201 PHY_AN_100FULL | PHY_AN_100HALF |
202 PHY_AN_10FULL | PHY_AN_10HALF| PHY_AN_CSMA);
203 /* no 1000 HD/FD */
204 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, 0);
205 gm_phy_write(hw, port, PHY_MARV_CTRL,
206 PHY_CT_RESET | PHY_CT_SPS_LSB | PHY_CT_ANE |
207 PHY_CT_RE_CFG | PHY_CT_DUP_MD);
208
209
210 /* Set GMAC to no flow control and auto update for speed/duplex */
211 gma_write16(hw, port, GM_GP_CTRL,
212 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
213 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
214
215 /* Set WOL address */
216 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
217 skge->netdev->dev_addr, ETH_ALEN);
218
219 /* Turn on appropriate WOL control bits */
220 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
221 ctrl = 0;
222 if (skge->wol & WAKE_PHY)
223 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
224 else
225 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
226
227 if (skge->wol & WAKE_MAGIC)
228 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
229 else
230 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
231
232 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
233 skge_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
234
235 /* block receiver */
236 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
237 }
238
239 static void skge_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
240 {
241 struct skge_port *skge = netdev_priv(dev);
242
243 wol->supported = wol_supported(skge->hw);
244 wol->wolopts = skge->wol;
245 }
246
247 static int skge_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
248 {
249 struct skge_port *skge = netdev_priv(dev);
250 struct skge_hw *hw = skge->hw;
251
252 if (wol->wolopts & ~wol_supported(hw))
253 return -EOPNOTSUPP;
254
255 skge->wol = wol->wolopts;
256 return 0;
257 }
258
259 /* Determine supported/advertised modes based on hardware.
260 * Note: ethtool ADVERTISED_xxx == SUPPORTED_xxx
261 */
262 static u32 skge_supported_modes(const struct skge_hw *hw)
263 {
264 u32 supported;
265
266 if (hw->copper) {
267 supported = SUPPORTED_10baseT_Half
268 | SUPPORTED_10baseT_Full
269 | SUPPORTED_100baseT_Half
270 | SUPPORTED_100baseT_Full
271 | SUPPORTED_1000baseT_Half
272 | SUPPORTED_1000baseT_Full
273 | SUPPORTED_Autoneg| SUPPORTED_TP;
274
275 if (hw->chip_id == CHIP_ID_GENESIS)
276 supported &= ~(SUPPORTED_10baseT_Half
277 | SUPPORTED_10baseT_Full
278 | SUPPORTED_100baseT_Half
279 | SUPPORTED_100baseT_Full);
280
281 else if (hw->chip_id == CHIP_ID_YUKON)
282 supported &= ~SUPPORTED_1000baseT_Half;
283 } else
284 supported = SUPPORTED_1000baseT_Full | SUPPORTED_1000baseT_Half
285 | SUPPORTED_FIBRE | SUPPORTED_Autoneg;
286
287 return supported;
288 }
289
290 static int skge_get_settings(struct net_device *dev,
291 struct ethtool_cmd *ecmd)
292 {
293 struct skge_port *skge = netdev_priv(dev);
294 struct skge_hw *hw = skge->hw;
295
296 ecmd->transceiver = XCVR_INTERNAL;
297 ecmd->supported = skge_supported_modes(hw);
298
299 if (hw->copper) {
300 ecmd->port = PORT_TP;
301 ecmd->phy_address = hw->phy_addr;
302 } else
303 ecmd->port = PORT_FIBRE;
304
305 ecmd->advertising = skge->advertising;
306 ecmd->autoneg = skge->autoneg;
307 ecmd->speed = skge->speed;
308 ecmd->duplex = skge->duplex;
309 return 0;
310 }
311
312 static int skge_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
313 {
314 struct skge_port *skge = netdev_priv(dev);
315 const struct skge_hw *hw = skge->hw;
316 u32 supported = skge_supported_modes(hw);
317
318 if (ecmd->autoneg == AUTONEG_ENABLE) {
319 ecmd->advertising = supported;
320 skge->duplex = -1;
321 skge->speed = -1;
322 } else {
323 u32 setting;
324
325 switch (ecmd->speed) {
326 case SPEED_1000:
327 if (ecmd->duplex == DUPLEX_FULL)
328 setting = SUPPORTED_1000baseT_Full;
329 else if (ecmd->duplex == DUPLEX_HALF)
330 setting = SUPPORTED_1000baseT_Half;
331 else
332 return -EINVAL;
333 break;
334 case SPEED_100:
335 if (ecmd->duplex == DUPLEX_FULL)
336 setting = SUPPORTED_100baseT_Full;
337 else if (ecmd->duplex == DUPLEX_HALF)
338 setting = SUPPORTED_100baseT_Half;
339 else
340 return -EINVAL;
341 break;
342
343 case SPEED_10:
344 if (ecmd->duplex == DUPLEX_FULL)
345 setting = SUPPORTED_10baseT_Full;
346 else if (ecmd->duplex == DUPLEX_HALF)
347 setting = SUPPORTED_10baseT_Half;
348 else
349 return -EINVAL;
350 break;
351 default:
352 return -EINVAL;
353 }
354
355 if ((setting & supported) == 0)
356 return -EINVAL;
357
358 skge->speed = ecmd->speed;
359 skge->duplex = ecmd->duplex;
360 }
361
362 skge->autoneg = ecmd->autoneg;
363 skge->advertising = ecmd->advertising;
364
365 if (netif_running(dev))
366 skge_phy_reset(skge);
367
368 return (0);
369 }
370
371 static void skge_get_drvinfo(struct net_device *dev,
372 struct ethtool_drvinfo *info)
373 {
374 struct skge_port *skge = netdev_priv(dev);
375
376 strcpy(info->driver, DRV_NAME);
377 strcpy(info->version, DRV_VERSION);
378 strcpy(info->fw_version, "N/A");
379 strcpy(info->bus_info, pci_name(skge->hw->pdev));
380 }
381
382 static const struct skge_stat {
383 char name[ETH_GSTRING_LEN];
384 u16 xmac_offset;
385 u16 gma_offset;
386 } skge_stats[] = {
387 { "tx_bytes", XM_TXO_OK_HI, GM_TXO_OK_HI },
388 { "rx_bytes", XM_RXO_OK_HI, GM_RXO_OK_HI },
389
390 { "tx_broadcast", XM_TXF_BC_OK, GM_TXF_BC_OK },
391 { "rx_broadcast", XM_RXF_BC_OK, GM_RXF_BC_OK },
392 { "tx_multicast", XM_TXF_MC_OK, GM_TXF_MC_OK },
393 { "rx_multicast", XM_RXF_MC_OK, GM_RXF_MC_OK },
394 { "tx_unicast", XM_TXF_UC_OK, GM_TXF_UC_OK },
395 { "rx_unicast", XM_RXF_UC_OK, GM_RXF_UC_OK },
396 { "tx_mac_pause", XM_TXF_MPAUSE, GM_TXF_MPAUSE },
397 { "rx_mac_pause", XM_RXF_MPAUSE, GM_RXF_MPAUSE },
398
399 { "collisions", XM_TXF_SNG_COL, GM_TXF_SNG_COL },
400 { "multi_collisions", XM_TXF_MUL_COL, GM_TXF_MUL_COL },
401 { "aborted", XM_TXF_ABO_COL, GM_TXF_ABO_COL },
402 { "late_collision", XM_TXF_LAT_COL, GM_TXF_LAT_COL },
403 { "fifo_underrun", XM_TXE_FIFO_UR, GM_TXE_FIFO_UR },
404 { "fifo_overflow", XM_RXE_FIFO_OV, GM_RXE_FIFO_OV },
405
406 { "rx_toolong", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
407 { "rx_jabber", XM_RXF_JAB_PKT, GM_RXF_JAB_PKT },
408 { "rx_runt", XM_RXE_RUNT, GM_RXE_FRAG },
409 { "rx_too_long", XM_RXF_LNG_ERR, GM_RXF_LNG_ERR },
410 { "rx_fcs_error", XM_RXF_FCS_ERR, GM_RXF_FCS_ERR },
411 };
412
413 static int skge_get_stats_count(struct net_device *dev)
414 {
415 return ARRAY_SIZE(skge_stats);
416 }
417
418 static void skge_get_ethtool_stats(struct net_device *dev,
419 struct ethtool_stats *stats, u64 *data)
420 {
421 struct skge_port *skge = netdev_priv(dev);
422
423 if (skge->hw->chip_id == CHIP_ID_GENESIS)
424 genesis_get_stats(skge, data);
425 else
426 yukon_get_stats(skge, data);
427 }
428
429 /* Use hardware MIB variables for critical path statistics and
430 * transmit feedback not reported at interrupt.
431 * Other errors are accounted for in interrupt handler.
432 */
433 static struct net_device_stats *skge_get_stats(struct net_device *dev)
434 {
435 struct skge_port *skge = netdev_priv(dev);
436 u64 data[ARRAY_SIZE(skge_stats)];
437
438 if (skge->hw->chip_id == CHIP_ID_GENESIS)
439 genesis_get_stats(skge, data);
440 else
441 yukon_get_stats(skge, data);
442
443 skge->net_stats.tx_bytes = data[0];
444 skge->net_stats.rx_bytes = data[1];
445 skge->net_stats.tx_packets = data[2] + data[4] + data[6];
446 skge->net_stats.rx_packets = data[3] + data[5] + data[7];
447 skge->net_stats.multicast = data[3] + data[5];
448 skge->net_stats.collisions = data[10];
449 skge->net_stats.tx_aborted_errors = data[12];
450
451 return &skge->net_stats;
452 }
453
454 static void skge_get_strings(struct net_device *dev, u32 stringset, u8 *data)
455 {
456 int i;
457
458 switch (stringset) {
459 case ETH_SS_STATS:
460 for (i = 0; i < ARRAY_SIZE(skge_stats); i++)
461 memcpy(data + i * ETH_GSTRING_LEN,
462 skge_stats[i].name, ETH_GSTRING_LEN);
463 break;
464 }
465 }
466
467 static void skge_get_ring_param(struct net_device *dev,
468 struct ethtool_ringparam *p)
469 {
470 struct skge_port *skge = netdev_priv(dev);
471
472 p->rx_max_pending = MAX_RX_RING_SIZE;
473 p->tx_max_pending = MAX_TX_RING_SIZE;
474 p->rx_mini_max_pending = 0;
475 p->rx_jumbo_max_pending = 0;
476
477 p->rx_pending = skge->rx_ring.count;
478 p->tx_pending = skge->tx_ring.count;
479 p->rx_mini_pending = 0;
480 p->rx_jumbo_pending = 0;
481 }
482
483 static int skge_set_ring_param(struct net_device *dev,
484 struct ethtool_ringparam *p)
485 {
486 struct skge_port *skge = netdev_priv(dev);
487 int err;
488
489 if (p->rx_pending == 0 || p->rx_pending > MAX_RX_RING_SIZE ||
490 p->tx_pending < TX_LOW_WATER || p->tx_pending > MAX_TX_RING_SIZE)
491 return -EINVAL;
492
493 skge->rx_ring.count = p->rx_pending;
494 skge->tx_ring.count = p->tx_pending;
495
496 if (netif_running(dev)) {
497 skge_down(dev);
498 err = skge_up(dev);
499 if (err)
500 dev_close(dev);
501 }
502
503 return 0;
504 }
505
506 static u32 skge_get_msglevel(struct net_device *netdev)
507 {
508 struct skge_port *skge = netdev_priv(netdev);
509 return skge->msg_enable;
510 }
511
512 static void skge_set_msglevel(struct net_device *netdev, u32 value)
513 {
514 struct skge_port *skge = netdev_priv(netdev);
515 skge->msg_enable = value;
516 }
517
518 static int skge_nway_reset(struct net_device *dev)
519 {
520 struct skge_port *skge = netdev_priv(dev);
521
522 if (skge->autoneg != AUTONEG_ENABLE || !netif_running(dev))
523 return -EINVAL;
524
525 skge_phy_reset(skge);
526 return 0;
527 }
528
529 static int skge_set_sg(struct net_device *dev, u32 data)
530 {
531 struct skge_port *skge = netdev_priv(dev);
532 struct skge_hw *hw = skge->hw;
533
534 if (hw->chip_id == CHIP_ID_GENESIS && data)
535 return -EOPNOTSUPP;
536 return ethtool_op_set_sg(dev, data);
537 }
538
539 static int skge_set_tx_csum(struct net_device *dev, u32 data)
540 {
541 struct skge_port *skge = netdev_priv(dev);
542 struct skge_hw *hw = skge->hw;
543
544 if (hw->chip_id == CHIP_ID_GENESIS && data)
545 return -EOPNOTSUPP;
546
547 return ethtool_op_set_tx_csum(dev, data);
548 }
549
550 static u32 skge_get_rx_csum(struct net_device *dev)
551 {
552 struct skge_port *skge = netdev_priv(dev);
553
554 return skge->rx_csum;
555 }
556
557 /* Only Yukon supports checksum offload. */
558 static int skge_set_rx_csum(struct net_device *dev, u32 data)
559 {
560 struct skge_port *skge = netdev_priv(dev);
561
562 if (skge->hw->chip_id == CHIP_ID_GENESIS && data)
563 return -EOPNOTSUPP;
564
565 skge->rx_csum = data;
566 return 0;
567 }
568
569 static void skge_get_pauseparam(struct net_device *dev,
570 struct ethtool_pauseparam *ecmd)
571 {
572 struct skge_port *skge = netdev_priv(dev);
573
574 ecmd->rx_pause = (skge->flow_control == FLOW_MODE_SYMMETRIC)
575 || (skge->flow_control == FLOW_MODE_SYM_OR_REM);
576 ecmd->tx_pause = ecmd->rx_pause || (skge->flow_control == FLOW_MODE_LOC_SEND);
577
578 ecmd->autoneg = ecmd->rx_pause || ecmd->tx_pause;
579 }
580
581 static int skge_set_pauseparam(struct net_device *dev,
582 struct ethtool_pauseparam *ecmd)
583 {
584 struct skge_port *skge = netdev_priv(dev);
585 struct ethtool_pauseparam old;
586
587 skge_get_pauseparam(dev, &old);
588
589 if (ecmd->autoneg != old.autoneg)
590 skge->flow_control = ecmd->autoneg ? FLOW_MODE_NONE : FLOW_MODE_SYMMETRIC;
591 else {
592 if (ecmd->rx_pause && ecmd->tx_pause)
593 skge->flow_control = FLOW_MODE_SYMMETRIC;
594 else if (ecmd->rx_pause && !ecmd->tx_pause)
595 skge->flow_control = FLOW_MODE_SYM_OR_REM;
596 else if (!ecmd->rx_pause && ecmd->tx_pause)
597 skge->flow_control = FLOW_MODE_LOC_SEND;
598 else
599 skge->flow_control = FLOW_MODE_NONE;
600 }
601
602 if (netif_running(dev))
603 skge_phy_reset(skge);
604
605 return 0;
606 }
607
608 /* Chip internal frequency for clock calculations */
609 static inline u32 hwkhz(const struct skge_hw *hw)
610 {
611 return (hw->chip_id == CHIP_ID_GENESIS) ? 53125 : 78125;
612 }
613
614 /* Chip HZ to microseconds */
615 static inline u32 skge_clk2usec(const struct skge_hw *hw, u32 ticks)
616 {
617 return (ticks * 1000) / hwkhz(hw);
618 }
619
620 /* Microseconds to chip HZ */
621 static inline u32 skge_usecs2clk(const struct skge_hw *hw, u32 usec)
622 {
623 return hwkhz(hw) * usec / 1000;
624 }
625
626 static int skge_get_coalesce(struct net_device *dev,
627 struct ethtool_coalesce *ecmd)
628 {
629 struct skge_port *skge = netdev_priv(dev);
630 struct skge_hw *hw = skge->hw;
631 int port = skge->port;
632
633 ecmd->rx_coalesce_usecs = 0;
634 ecmd->tx_coalesce_usecs = 0;
635
636 if (skge_read32(hw, B2_IRQM_CTRL) & TIM_START) {
637 u32 delay = skge_clk2usec(hw, skge_read32(hw, B2_IRQM_INI));
638 u32 msk = skge_read32(hw, B2_IRQM_MSK);
639
640 if (msk & rxirqmask[port])
641 ecmd->rx_coalesce_usecs = delay;
642 if (msk & txirqmask[port])
643 ecmd->tx_coalesce_usecs = delay;
644 }
645
646 return 0;
647 }
648
649 /* Note: interrupt timer is per board, but can turn on/off per port */
650 static int skge_set_coalesce(struct net_device *dev,
651 struct ethtool_coalesce *ecmd)
652 {
653 struct skge_port *skge = netdev_priv(dev);
654 struct skge_hw *hw = skge->hw;
655 int port = skge->port;
656 u32 msk = skge_read32(hw, B2_IRQM_MSK);
657 u32 delay = 25;
658
659 if (ecmd->rx_coalesce_usecs == 0)
660 msk &= ~rxirqmask[port];
661 else if (ecmd->rx_coalesce_usecs < 25 ||
662 ecmd->rx_coalesce_usecs > 33333)
663 return -EINVAL;
664 else {
665 msk |= rxirqmask[port];
666 delay = ecmd->rx_coalesce_usecs;
667 }
668
669 if (ecmd->tx_coalesce_usecs == 0)
670 msk &= ~txirqmask[port];
671 else if (ecmd->tx_coalesce_usecs < 25 ||
672 ecmd->tx_coalesce_usecs > 33333)
673 return -EINVAL;
674 else {
675 msk |= txirqmask[port];
676 delay = min(delay, ecmd->rx_coalesce_usecs);
677 }
678
679 skge_write32(hw, B2_IRQM_MSK, msk);
680 if (msk == 0)
681 skge_write32(hw, B2_IRQM_CTRL, TIM_STOP);
682 else {
683 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, delay));
684 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
685 }
686 return 0;
687 }
688
689 enum led_mode { LED_MODE_OFF, LED_MODE_ON, LED_MODE_TST };
690 static void skge_led(struct skge_port *skge, enum led_mode mode)
691 {
692 struct skge_hw *hw = skge->hw;
693 int port = skge->port;
694
695 spin_lock_bh(&hw->phy_lock);
696 if (hw->chip_id == CHIP_ID_GENESIS) {
697 switch (mode) {
698 case LED_MODE_OFF:
699 if (hw->phy_type == SK_PHY_BCOM)
700 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_OFF);
701 else {
702 skge_write32(hw, SK_REG(port, TX_LED_VAL), 0);
703 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_T_OFF);
704 }
705 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
706 skge_write32(hw, SK_REG(port, RX_LED_VAL), 0);
707 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_T_OFF);
708 break;
709
710 case LED_MODE_ON:
711 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_ON);
712 skge_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_LINKSYNC_ON);
713
714 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
715 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
716
717 break;
718
719 case LED_MODE_TST:
720 skge_write8(hw, SK_REG(port, RX_LED_TST), LED_T_ON);
721 skge_write32(hw, SK_REG(port, RX_LED_VAL), 100);
722 skge_write8(hw, SK_REG(port, RX_LED_CTRL), LED_START);
723
724 if (hw->phy_type == SK_PHY_BCOM)
725 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, PHY_B_PEC_LED_ON);
726 else {
727 skge_write8(hw, SK_REG(port, TX_LED_TST), LED_T_ON);
728 skge_write32(hw, SK_REG(port, TX_LED_VAL), 100);
729 skge_write8(hw, SK_REG(port, TX_LED_CTRL), LED_START);
730 }
731
732 }
733 } else {
734 switch (mode) {
735 case LED_MODE_OFF:
736 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
737 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
738 PHY_M_LED_MO_DUP(MO_LED_OFF) |
739 PHY_M_LED_MO_10(MO_LED_OFF) |
740 PHY_M_LED_MO_100(MO_LED_OFF) |
741 PHY_M_LED_MO_1000(MO_LED_OFF) |
742 PHY_M_LED_MO_RX(MO_LED_OFF));
743 break;
744 case LED_MODE_ON:
745 gm_phy_write(hw, port, PHY_MARV_LED_CTRL,
746 PHY_M_LED_PULS_DUR(PULS_170MS) |
747 PHY_M_LED_BLINK_RT(BLINK_84MS) |
748 PHY_M_LEDC_TX_CTRL |
749 PHY_M_LEDC_DP_CTRL);
750
751 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
752 PHY_M_LED_MO_RX(MO_LED_OFF) |
753 (skge->speed == SPEED_100 ?
754 PHY_M_LED_MO_100(MO_LED_ON) : 0));
755 break;
756 case LED_MODE_TST:
757 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
758 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
759 PHY_M_LED_MO_DUP(MO_LED_ON) |
760 PHY_M_LED_MO_10(MO_LED_ON) |
761 PHY_M_LED_MO_100(MO_LED_ON) |
762 PHY_M_LED_MO_1000(MO_LED_ON) |
763 PHY_M_LED_MO_RX(MO_LED_ON));
764 }
765 }
766 spin_unlock_bh(&hw->phy_lock);
767 }
768
769 /* blink LED's for finding board */
770 static int skge_phys_id(struct net_device *dev, u32 data)
771 {
772 struct skge_port *skge = netdev_priv(dev);
773 unsigned long ms;
774 enum led_mode mode = LED_MODE_TST;
775
776 if (!data || data > (u32)(MAX_SCHEDULE_TIMEOUT / HZ))
777 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT / HZ) * 1000;
778 else
779 ms = data * 1000;
780
781 while (ms > 0) {
782 skge_led(skge, mode);
783 mode ^= LED_MODE_TST;
784
785 if (msleep_interruptible(BLINK_MS))
786 break;
787 ms -= BLINK_MS;
788 }
789
790 /* back to regular LED state */
791 skge_led(skge, netif_running(dev) ? LED_MODE_ON : LED_MODE_OFF);
792
793 return 0;
794 }
795
796 static const struct ethtool_ops skge_ethtool_ops = {
797 .get_settings = skge_get_settings,
798 .set_settings = skge_set_settings,
799 .get_drvinfo = skge_get_drvinfo,
800 .get_regs_len = skge_get_regs_len,
801 .get_regs = skge_get_regs,
802 .get_wol = skge_get_wol,
803 .set_wol = skge_set_wol,
804 .get_msglevel = skge_get_msglevel,
805 .set_msglevel = skge_set_msglevel,
806 .nway_reset = skge_nway_reset,
807 .get_link = ethtool_op_get_link,
808 .get_ringparam = skge_get_ring_param,
809 .set_ringparam = skge_set_ring_param,
810 .get_pauseparam = skge_get_pauseparam,
811 .set_pauseparam = skge_set_pauseparam,
812 .get_coalesce = skge_get_coalesce,
813 .set_coalesce = skge_set_coalesce,
814 .get_sg = ethtool_op_get_sg,
815 .set_sg = skge_set_sg,
816 .get_tx_csum = ethtool_op_get_tx_csum,
817 .set_tx_csum = skge_set_tx_csum,
818 .get_rx_csum = skge_get_rx_csum,
819 .set_rx_csum = skge_set_rx_csum,
820 .get_strings = skge_get_strings,
821 .phys_id = skge_phys_id,
822 .get_stats_count = skge_get_stats_count,
823 .get_ethtool_stats = skge_get_ethtool_stats,
824 .get_perm_addr = ethtool_op_get_perm_addr,
825 };
826
827 /*
828 * Allocate ring elements and chain them together
829 * One-to-one association of board descriptors with ring elements
830 */
831 static int skge_ring_alloc(struct skge_ring *ring, void *vaddr, u32 base)
832 {
833 struct skge_tx_desc *d;
834 struct skge_element *e;
835 int i;
836
837 ring->start = kcalloc(ring->count, sizeof(*e), GFP_KERNEL);
838 if (!ring->start)
839 return -ENOMEM;
840
841 for (i = 0, e = ring->start, d = vaddr; i < ring->count; i++, e++, d++) {
842 e->desc = d;
843 if (i == ring->count - 1) {
844 e->next = ring->start;
845 d->next_offset = base;
846 } else {
847 e->next = e + 1;
848 d->next_offset = base + (i+1) * sizeof(*d);
849 }
850 }
851 ring->to_use = ring->to_clean = ring->start;
852
853 return 0;
854 }
855
856 /* Allocate and setup a new buffer for receiving */
857 static void skge_rx_setup(struct skge_port *skge, struct skge_element *e,
858 struct sk_buff *skb, unsigned int bufsize)
859 {
860 struct skge_rx_desc *rd = e->desc;
861 u64 map;
862
863 map = pci_map_single(skge->hw->pdev, skb->data, bufsize,
864 PCI_DMA_FROMDEVICE);
865
866 rd->dma_lo = map;
867 rd->dma_hi = map >> 32;
868 e->skb = skb;
869 rd->csum1_start = ETH_HLEN;
870 rd->csum2_start = ETH_HLEN;
871 rd->csum1 = 0;
872 rd->csum2 = 0;
873
874 wmb();
875
876 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | bufsize;
877 pci_unmap_addr_set(e, mapaddr, map);
878 pci_unmap_len_set(e, maplen, bufsize);
879 }
880
881 /* Resume receiving using existing skb,
882 * Note: DMA address is not changed by chip.
883 * MTU not changed while receiver active.
884 */
885 static inline void skge_rx_reuse(struct skge_element *e, unsigned int size)
886 {
887 struct skge_rx_desc *rd = e->desc;
888
889 rd->csum2 = 0;
890 rd->csum2_start = ETH_HLEN;
891
892 wmb();
893
894 rd->control = BMU_OWN | BMU_STF | BMU_IRQ_EOF | BMU_TCP_CHECK | size;
895 }
896
897
898 /* Free all buffers in receive ring, assumes receiver stopped */
899 static void skge_rx_clean(struct skge_port *skge)
900 {
901 struct skge_hw *hw = skge->hw;
902 struct skge_ring *ring = &skge->rx_ring;
903 struct skge_element *e;
904
905 e = ring->start;
906 do {
907 struct skge_rx_desc *rd = e->desc;
908 rd->control = 0;
909 if (e->skb) {
910 pci_unmap_single(hw->pdev,
911 pci_unmap_addr(e, mapaddr),
912 pci_unmap_len(e, maplen),
913 PCI_DMA_FROMDEVICE);
914 dev_kfree_skb(e->skb);
915 e->skb = NULL;
916 }
917 } while ((e = e->next) != ring->start);
918 }
919
920
921 /* Allocate buffers for receive ring
922 * For receive: to_clean is next received frame.
923 */
924 static int skge_rx_fill(struct net_device *dev)
925 {
926 struct skge_port *skge = netdev_priv(dev);
927 struct skge_ring *ring = &skge->rx_ring;
928 struct skge_element *e;
929
930 e = ring->start;
931 do {
932 struct sk_buff *skb;
933
934 skb = __netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN,
935 GFP_KERNEL);
936 if (!skb)
937 return -ENOMEM;
938
939 skb_reserve(skb, NET_IP_ALIGN);
940 skge_rx_setup(skge, e, skb, skge->rx_buf_size);
941 } while ( (e = e->next) != ring->start);
942
943 ring->to_clean = ring->start;
944 return 0;
945 }
946
947 static const char *skge_pause(enum pause_status status)
948 {
949 switch(status) {
950 case FLOW_STAT_NONE:
951 return "none";
952 case FLOW_STAT_REM_SEND:
953 return "rx only";
954 case FLOW_STAT_LOC_SEND:
955 return "tx_only";
956 case FLOW_STAT_SYMMETRIC: /* Both station may send PAUSE */
957 return "both";
958 default:
959 return "indeterminated";
960 }
961 }
962
963
964 static void skge_link_up(struct skge_port *skge)
965 {
966 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG),
967 LED_BLK_OFF|LED_SYNC_OFF|LED_ON);
968
969 netif_carrier_on(skge->netdev);
970 netif_wake_queue(skge->netdev);
971
972 if (netif_msg_link(skge)) {
973 printk(KERN_INFO PFX
974 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
975 skge->netdev->name, skge->speed,
976 skge->duplex == DUPLEX_FULL ? "full" : "half",
977 skge_pause(skge->flow_status));
978 }
979 }
980
981 static void skge_link_down(struct skge_port *skge)
982 {
983 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
984 netif_carrier_off(skge->netdev);
985 netif_stop_queue(skge->netdev);
986
987 if (netif_msg_link(skge))
988 printk(KERN_INFO PFX "%s: Link is down.\n", skge->netdev->name);
989 }
990
991
992 static void xm_link_down(struct skge_hw *hw, int port)
993 {
994 struct net_device *dev = hw->dev[port];
995 struct skge_port *skge = netdev_priv(dev);
996 u16 cmd, msk;
997
998 if (hw->phy_type == SK_PHY_XMAC) {
999 msk = xm_read16(hw, port, XM_IMSK);
1000 msk |= XM_IS_INP_ASS | XM_IS_LIPA_RC | XM_IS_RX_PAGE | XM_IS_AND;
1001 xm_write16(hw, port, XM_IMSK, msk);
1002 }
1003
1004 cmd = xm_read16(hw, port, XM_MMU_CMD);
1005 cmd &= ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1006 xm_write16(hw, port, XM_MMU_CMD, cmd);
1007 /* dummy read to ensure writing */
1008 (void) xm_read16(hw, port, XM_MMU_CMD);
1009
1010 if (netif_carrier_ok(dev))
1011 skge_link_down(skge);
1012 }
1013
1014 static int __xm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1015 {
1016 int i;
1017
1018 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1019 *val = xm_read16(hw, port, XM_PHY_DATA);
1020
1021 if (hw->phy_type == SK_PHY_XMAC)
1022 goto ready;
1023
1024 for (i = 0; i < PHY_RETRIES; i++) {
1025 if (xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_RDY)
1026 goto ready;
1027 udelay(1);
1028 }
1029
1030 return -ETIMEDOUT;
1031 ready:
1032 *val = xm_read16(hw, port, XM_PHY_DATA);
1033
1034 return 0;
1035 }
1036
1037 static u16 xm_phy_read(struct skge_hw *hw, int port, u16 reg)
1038 {
1039 u16 v = 0;
1040 if (__xm_phy_read(hw, port, reg, &v))
1041 printk(KERN_WARNING PFX "%s: phy read timed out\n",
1042 hw->dev[port]->name);
1043 return v;
1044 }
1045
1046 static int xm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1047 {
1048 int i;
1049
1050 xm_write16(hw, port, XM_PHY_ADDR, reg | hw->phy_addr);
1051 for (i = 0; i < PHY_RETRIES; i++) {
1052 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1053 goto ready;
1054 udelay(1);
1055 }
1056 return -EIO;
1057
1058 ready:
1059 xm_write16(hw, port, XM_PHY_DATA, val);
1060 for (i = 0; i < PHY_RETRIES; i++) {
1061 if (!(xm_read16(hw, port, XM_MMU_CMD) & XM_MMU_PHY_BUSY))
1062 return 0;
1063 udelay(1);
1064 }
1065 return -ETIMEDOUT;
1066 }
1067
1068 static void genesis_init(struct skge_hw *hw)
1069 {
1070 /* set blink source counter */
1071 skge_write32(hw, B2_BSC_INI, (SK_BLK_DUR * SK_FACT_53) / 100);
1072 skge_write8(hw, B2_BSC_CTRL, BSC_START);
1073
1074 /* configure mac arbiter */
1075 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1076
1077 /* configure mac arbiter timeout values */
1078 skge_write8(hw, B3_MA_TOINI_RX1, SK_MAC_TO_53);
1079 skge_write8(hw, B3_MA_TOINI_RX2, SK_MAC_TO_53);
1080 skge_write8(hw, B3_MA_TOINI_TX1, SK_MAC_TO_53);
1081 skge_write8(hw, B3_MA_TOINI_TX2, SK_MAC_TO_53);
1082
1083 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1084 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1085 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1086 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1087
1088 /* configure packet arbiter timeout */
1089 skge_write16(hw, B3_PA_CTRL, PA_RST_CLR);
1090 skge_write16(hw, B3_PA_TOINI_RX1, SK_PKT_TO_MAX);
1091 skge_write16(hw, B3_PA_TOINI_TX1, SK_PKT_TO_MAX);
1092 skge_write16(hw, B3_PA_TOINI_RX2, SK_PKT_TO_MAX);
1093 skge_write16(hw, B3_PA_TOINI_TX2, SK_PKT_TO_MAX);
1094 }
1095
1096 static void genesis_reset(struct skge_hw *hw, int port)
1097 {
1098 const u8 zero[8] = { 0 };
1099
1100 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
1101
1102 /* reset the statistics module */
1103 xm_write32(hw, port, XM_GP_PORT, XM_GP_RES_STAT);
1104 xm_write16(hw, port, XM_IMSK, 0xffff); /* disable XMAC IRQs */
1105 xm_write32(hw, port, XM_MODE, 0); /* clear Mode Reg */
1106 xm_write16(hw, port, XM_TX_CMD, 0); /* reset TX CMD Reg */
1107 xm_write16(hw, port, XM_RX_CMD, 0); /* reset RX CMD Reg */
1108
1109 /* disable Broadcom PHY IRQ */
1110 if (hw->phy_type == SK_PHY_BCOM)
1111 xm_write16(hw, port, PHY_BCOM_INT_MASK, 0xffff);
1112
1113 xm_outhash(hw, port, XM_HSM, zero);
1114 }
1115
1116
1117 /* Convert mode to MII values */
1118 static const u16 phy_pause_map[] = {
1119 [FLOW_MODE_NONE] = 0,
1120 [FLOW_MODE_LOC_SEND] = PHY_AN_PAUSE_ASYM,
1121 [FLOW_MODE_SYMMETRIC] = PHY_AN_PAUSE_CAP,
1122 [FLOW_MODE_SYM_OR_REM] = PHY_AN_PAUSE_CAP | PHY_AN_PAUSE_ASYM,
1123 };
1124
1125 /* special defines for FIBER (88E1011S only) */
1126 static const u16 fiber_pause_map[] = {
1127 [FLOW_MODE_NONE] = PHY_X_P_NO_PAUSE,
1128 [FLOW_MODE_LOC_SEND] = PHY_X_P_ASYM_MD,
1129 [FLOW_MODE_SYMMETRIC] = PHY_X_P_SYM_MD,
1130 [FLOW_MODE_SYM_OR_REM] = PHY_X_P_BOTH_MD,
1131 };
1132
1133
1134 /* Check status of Broadcom phy link */
1135 static void bcom_check_link(struct skge_hw *hw, int port)
1136 {
1137 struct net_device *dev = hw->dev[port];
1138 struct skge_port *skge = netdev_priv(dev);
1139 u16 status;
1140
1141 /* read twice because of latch */
1142 (void) xm_phy_read(hw, port, PHY_BCOM_STAT);
1143 status = xm_phy_read(hw, port, PHY_BCOM_STAT);
1144
1145 if ((status & PHY_ST_LSYNC) == 0) {
1146 xm_link_down(hw, port);
1147 return;
1148 }
1149
1150 if (skge->autoneg == AUTONEG_ENABLE) {
1151 u16 lpa, aux;
1152
1153 if (!(status & PHY_ST_AN_OVER))
1154 return;
1155
1156 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1157 if (lpa & PHY_B_AN_RF) {
1158 printk(KERN_NOTICE PFX "%s: remote fault\n",
1159 dev->name);
1160 return;
1161 }
1162
1163 aux = xm_phy_read(hw, port, PHY_BCOM_AUX_STAT);
1164
1165 /* Check Duplex mismatch */
1166 switch (aux & PHY_B_AS_AN_RES_MSK) {
1167 case PHY_B_RES_1000FD:
1168 skge->duplex = DUPLEX_FULL;
1169 break;
1170 case PHY_B_RES_1000HD:
1171 skge->duplex = DUPLEX_HALF;
1172 break;
1173 default:
1174 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1175 dev->name);
1176 return;
1177 }
1178
1179 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1180 switch (aux & PHY_B_AS_PAUSE_MSK) {
1181 case PHY_B_AS_PAUSE_MSK:
1182 skge->flow_status = FLOW_STAT_SYMMETRIC;
1183 break;
1184 case PHY_B_AS_PRR:
1185 skge->flow_status = FLOW_STAT_REM_SEND;
1186 break;
1187 case PHY_B_AS_PRT:
1188 skge->flow_status = FLOW_STAT_LOC_SEND;
1189 break;
1190 default:
1191 skge->flow_status = FLOW_STAT_NONE;
1192 }
1193 skge->speed = SPEED_1000;
1194 }
1195
1196 if (!netif_carrier_ok(dev))
1197 genesis_link_up(skge);
1198 }
1199
1200 /* Broadcom 5400 only supports giagabit! SysKonnect did not put an additional
1201 * Phy on for 100 or 10Mbit operation
1202 */
1203 static void bcom_phy_init(struct skge_port *skge)
1204 {
1205 struct skge_hw *hw = skge->hw;
1206 int port = skge->port;
1207 int i;
1208 u16 id1, r, ext, ctl;
1209
1210 /* magic workaround patterns for Broadcom */
1211 static const struct {
1212 u16 reg;
1213 u16 val;
1214 } A1hack[] = {
1215 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1104 },
1216 { 0x17, 0x0013 }, { 0x15, 0x0404 }, { 0x17, 0x8006 },
1217 { 0x15, 0x0132 }, { 0x17, 0x8006 }, { 0x15, 0x0232 },
1218 { 0x17, 0x800D }, { 0x15, 0x000F }, { 0x18, 0x0420 },
1219 }, C0hack[] = {
1220 { 0x18, 0x0c20 }, { 0x17, 0x0012 }, { 0x15, 0x1204 },
1221 { 0x17, 0x0013 }, { 0x15, 0x0A04 }, { 0x18, 0x0420 },
1222 };
1223
1224 /* read Id from external PHY (all have the same address) */
1225 id1 = xm_phy_read(hw, port, PHY_XMAC_ID1);
1226
1227 /* Optimize MDIO transfer by suppressing preamble. */
1228 r = xm_read16(hw, port, XM_MMU_CMD);
1229 r |= XM_MMU_NO_PRE;
1230 xm_write16(hw, port, XM_MMU_CMD,r);
1231
1232 switch (id1) {
1233 case PHY_BCOM_ID1_C0:
1234 /*
1235 * Workaround BCOM Errata for the C0 type.
1236 * Write magic patterns to reserved registers.
1237 */
1238 for (i = 0; i < ARRAY_SIZE(C0hack); i++)
1239 xm_phy_write(hw, port,
1240 C0hack[i].reg, C0hack[i].val);
1241
1242 break;
1243 case PHY_BCOM_ID1_A1:
1244 /*
1245 * Workaround BCOM Errata for the A1 type.
1246 * Write magic patterns to reserved registers.
1247 */
1248 for (i = 0; i < ARRAY_SIZE(A1hack); i++)
1249 xm_phy_write(hw, port,
1250 A1hack[i].reg, A1hack[i].val);
1251 break;
1252 }
1253
1254 /*
1255 * Workaround BCOM Errata (#10523) for all BCom PHYs.
1256 * Disable Power Management after reset.
1257 */
1258 r = xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL);
1259 r |= PHY_B_AC_DIS_PM;
1260 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL, r);
1261
1262 /* Dummy read */
1263 xm_read16(hw, port, XM_ISRC);
1264
1265 ext = PHY_B_PEC_EN_LTR; /* enable tx led */
1266 ctl = PHY_CT_SP1000; /* always 1000mbit */
1267
1268 if (skge->autoneg == AUTONEG_ENABLE) {
1269 /*
1270 * Workaround BCOM Errata #1 for the C5 type.
1271 * 1000Base-T Link Acquisition Failure in Slave Mode
1272 * Set Repeater/DTE bit 10 of the 1000Base-T Control Register
1273 */
1274 u16 adv = PHY_B_1000C_RD;
1275 if (skge->advertising & ADVERTISED_1000baseT_Half)
1276 adv |= PHY_B_1000C_AHD;
1277 if (skge->advertising & ADVERTISED_1000baseT_Full)
1278 adv |= PHY_B_1000C_AFD;
1279 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, adv);
1280
1281 ctl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1282 } else {
1283 if (skge->duplex == DUPLEX_FULL)
1284 ctl |= PHY_CT_DUP_MD;
1285 /* Force to slave */
1286 xm_phy_write(hw, port, PHY_BCOM_1000T_CTRL, PHY_B_1000C_MSE);
1287 }
1288
1289 /* Set autonegotiation pause parameters */
1290 xm_phy_write(hw, port, PHY_BCOM_AUNE_ADV,
1291 phy_pause_map[skge->flow_control] | PHY_AN_CSMA);
1292
1293 /* Handle Jumbo frames */
1294 if (hw->dev[port]->mtu > ETH_DATA_LEN) {
1295 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1296 PHY_B_AC_TX_TST | PHY_B_AC_LONG_PACK);
1297
1298 ext |= PHY_B_PEC_HIGH_LA;
1299
1300 }
1301
1302 xm_phy_write(hw, port, PHY_BCOM_P_EXT_CTRL, ext);
1303 xm_phy_write(hw, port, PHY_BCOM_CTRL, ctl);
1304
1305 /* Use link status change interrupt */
1306 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1307 }
1308
1309 static void xm_phy_init(struct skge_port *skge)
1310 {
1311 struct skge_hw *hw = skge->hw;
1312 int port = skge->port;
1313 u16 ctrl = 0;
1314
1315 if (skge->autoneg == AUTONEG_ENABLE) {
1316 if (skge->advertising & ADVERTISED_1000baseT_Half)
1317 ctrl |= PHY_X_AN_HD;
1318 if (skge->advertising & ADVERTISED_1000baseT_Full)
1319 ctrl |= PHY_X_AN_FD;
1320
1321 ctrl |= fiber_pause_map[skge->flow_control];
1322
1323 xm_phy_write(hw, port, PHY_XMAC_AUNE_ADV, ctrl);
1324
1325 /* Restart Auto-negotiation */
1326 ctrl = PHY_CT_ANE | PHY_CT_RE_CFG;
1327 } else {
1328 /* Set DuplexMode in Config register */
1329 if (skge->duplex == DUPLEX_FULL)
1330 ctrl |= PHY_CT_DUP_MD;
1331 /*
1332 * Do NOT enable Auto-negotiation here. This would hold
1333 * the link down because no IDLEs are transmitted
1334 */
1335 }
1336
1337 xm_phy_write(hw, port, PHY_XMAC_CTRL, ctrl);
1338
1339 /* Poll PHY for status changes */
1340 mod_timer(&skge->link_timer, jiffies + LINK_HZ);
1341 }
1342
1343 static void xm_check_link(struct net_device *dev)
1344 {
1345 struct skge_port *skge = netdev_priv(dev);
1346 struct skge_hw *hw = skge->hw;
1347 int port = skge->port;
1348 u16 status;
1349
1350 /* read twice because of latch */
1351 (void) xm_phy_read(hw, port, PHY_XMAC_STAT);
1352 status = xm_phy_read(hw, port, PHY_XMAC_STAT);
1353
1354 if ((status & PHY_ST_LSYNC) == 0) {
1355 xm_link_down(hw, port);
1356 return;
1357 }
1358
1359 if (skge->autoneg == AUTONEG_ENABLE) {
1360 u16 lpa, res;
1361
1362 if (!(status & PHY_ST_AN_OVER))
1363 return;
1364
1365 lpa = xm_phy_read(hw, port, PHY_XMAC_AUNE_LP);
1366 if (lpa & PHY_B_AN_RF) {
1367 printk(KERN_NOTICE PFX "%s: remote fault\n",
1368 dev->name);
1369 return;
1370 }
1371
1372 res = xm_phy_read(hw, port, PHY_XMAC_RES_ABI);
1373
1374 /* Check Duplex mismatch */
1375 switch (res & (PHY_X_RS_HD | PHY_X_RS_FD)) {
1376 case PHY_X_RS_FD:
1377 skge->duplex = DUPLEX_FULL;
1378 break;
1379 case PHY_X_RS_HD:
1380 skge->duplex = DUPLEX_HALF;
1381 break;
1382 default:
1383 printk(KERN_NOTICE PFX "%s: duplex mismatch\n",
1384 dev->name);
1385 return;
1386 }
1387
1388 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
1389 if ((skge->flow_control == FLOW_MODE_SYMMETRIC ||
1390 skge->flow_control == FLOW_MODE_SYM_OR_REM) &&
1391 (lpa & PHY_X_P_SYM_MD))
1392 skge->flow_status = FLOW_STAT_SYMMETRIC;
1393 else if (skge->flow_control == FLOW_MODE_SYM_OR_REM &&
1394 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_ASYM_MD)
1395 /* Enable PAUSE receive, disable PAUSE transmit */
1396 skge->flow_status = FLOW_STAT_REM_SEND;
1397 else if (skge->flow_control == FLOW_MODE_LOC_SEND &&
1398 (lpa & PHY_X_RS_PAUSE) == PHY_X_P_BOTH_MD)
1399 /* Disable PAUSE receive, enable PAUSE transmit */
1400 skge->flow_status = FLOW_STAT_LOC_SEND;
1401 else
1402 skge->flow_status = FLOW_STAT_NONE;
1403
1404 skge->speed = SPEED_1000;
1405 }
1406
1407 if (!netif_carrier_ok(dev))
1408 genesis_link_up(skge);
1409 }
1410
1411 /* Poll to check for link coming up.
1412 * Since internal PHY is wired to a level triggered pin, can't
1413 * get an interrupt when carrier is detected.
1414 */
1415 static void xm_link_timer(unsigned long arg)
1416 {
1417 struct skge_port *skge = (struct skge_port *) arg;
1418 struct net_device *dev = skge->netdev;
1419 struct skge_hw *hw = skge->hw;
1420 int port = skge->port;
1421
1422 if (!netif_running(dev))
1423 return;
1424
1425 if (netif_carrier_ok(dev)) {
1426 xm_read16(hw, port, XM_ISRC);
1427 if (!(xm_read16(hw, port, XM_ISRC) & XM_IS_INP_ASS))
1428 goto nochange;
1429 } else {
1430 if (xm_read32(hw, port, XM_GP_PORT) & XM_GP_INP_ASS)
1431 goto nochange;
1432 xm_read16(hw, port, XM_ISRC);
1433 if (xm_read16(hw, port, XM_ISRC) & XM_IS_INP_ASS)
1434 goto nochange;
1435 }
1436
1437 spin_lock(&hw->phy_lock);
1438 xm_check_link(dev);
1439 spin_unlock(&hw->phy_lock);
1440
1441 nochange:
1442 if (netif_running(dev))
1443 mod_timer(&skge->link_timer, jiffies + LINK_HZ);
1444 }
1445
1446 static void genesis_mac_init(struct skge_hw *hw, int port)
1447 {
1448 struct net_device *dev = hw->dev[port];
1449 struct skge_port *skge = netdev_priv(dev);
1450 int jumbo = hw->dev[port]->mtu > ETH_DATA_LEN;
1451 int i;
1452 u32 r;
1453 const u8 zero[6] = { 0 };
1454
1455 for (i = 0; i < 10; i++) {
1456 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
1457 MFF_SET_MAC_RST);
1458 if (skge_read16(hw, SK_REG(port, TX_MFF_CTRL1)) & MFF_SET_MAC_RST)
1459 goto reset_ok;
1460 udelay(1);
1461 }
1462
1463 printk(KERN_WARNING PFX "%s: genesis reset failed\n", dev->name);
1464
1465 reset_ok:
1466 /* Unreset the XMAC. */
1467 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_CLR_MAC_RST);
1468
1469 /*
1470 * Perform additional initialization for external PHYs,
1471 * namely for the 1000baseTX cards that use the XMAC's
1472 * GMII mode.
1473 */
1474 if (hw->phy_type != SK_PHY_XMAC) {
1475 /* Take external Phy out of reset */
1476 r = skge_read32(hw, B2_GP_IO);
1477 if (port == 0)
1478 r |= GP_DIR_0|GP_IO_0;
1479 else
1480 r |= GP_DIR_2|GP_IO_2;
1481
1482 skge_write32(hw, B2_GP_IO, r);
1483
1484 /* Enable GMII interface */
1485 xm_write16(hw, port, XM_HW_CFG, XM_HW_GMII_MD);
1486 }
1487
1488
1489 switch(hw->phy_type) {
1490 case SK_PHY_XMAC:
1491 xm_phy_init(skge);
1492 break;
1493 case SK_PHY_BCOM:
1494 bcom_phy_init(skge);
1495 bcom_check_link(hw, port);
1496 }
1497
1498 /* Set Station Address */
1499 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
1500
1501 /* We don't use match addresses so clear */
1502 for (i = 1; i < 16; i++)
1503 xm_outaddr(hw, port, XM_EXM(i), zero);
1504
1505 /* Clear MIB counters */
1506 xm_write16(hw, port, XM_STAT_CMD,
1507 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1508 /* Clear two times according to Errata #3 */
1509 xm_write16(hw, port, XM_STAT_CMD,
1510 XM_SC_CLR_RXC | XM_SC_CLR_TXC);
1511
1512 /* configure Rx High Water Mark (XM_RX_HI_WM) */
1513 xm_write16(hw, port, XM_RX_HI_WM, 1450);
1514
1515 /* We don't need the FCS appended to the packet. */
1516 r = XM_RX_LENERR_OK | XM_RX_STRIP_FCS;
1517 if (jumbo)
1518 r |= XM_RX_BIG_PK_OK;
1519
1520 if (skge->duplex == DUPLEX_HALF) {
1521 /*
1522 * If in manual half duplex mode the other side might be in
1523 * full duplex mode, so ignore if a carrier extension is not seen
1524 * on frames received
1525 */
1526 r |= XM_RX_DIS_CEXT;
1527 }
1528 xm_write16(hw, port, XM_RX_CMD, r);
1529
1530
1531 /* We want short frames padded to 60 bytes. */
1532 xm_write16(hw, port, XM_TX_CMD, XM_TX_AUTO_PAD);
1533
1534 /*
1535 * Bump up the transmit threshold. This helps hold off transmit
1536 * underruns when we're blasting traffic from both ports at once.
1537 */
1538 xm_write16(hw, port, XM_TX_THR, 512);
1539
1540 /*
1541 * Enable the reception of all error frames. This is is
1542 * a necessary evil due to the design of the XMAC. The
1543 * XMAC's receive FIFO is only 8K in size, however jumbo
1544 * frames can be up to 9000 bytes in length. When bad
1545 * frame filtering is enabled, the XMAC's RX FIFO operates
1546 * in 'store and forward' mode. For this to work, the
1547 * entire frame has to fit into the FIFO, but that means
1548 * that jumbo frames larger than 8192 bytes will be
1549 * truncated. Disabling all bad frame filtering causes
1550 * the RX FIFO to operate in streaming mode, in which
1551 * case the XMAC will start transferring frames out of the
1552 * RX FIFO as soon as the FIFO threshold is reached.
1553 */
1554 xm_write32(hw, port, XM_MODE, XM_DEF_MODE);
1555
1556
1557 /*
1558 * Initialize the Receive Counter Event Mask (XM_RX_EV_MSK)
1559 * - Enable all bits excepting 'Octets Rx OK Low CntOv'
1560 * and 'Octets Rx OK Hi Cnt Ov'.
1561 */
1562 xm_write32(hw, port, XM_RX_EV_MSK, XMR_DEF_MSK);
1563
1564 /*
1565 * Initialize the Transmit Counter Event Mask (XM_TX_EV_MSK)
1566 * - Enable all bits excepting 'Octets Tx OK Low CntOv'
1567 * and 'Octets Tx OK Hi Cnt Ov'.
1568 */
1569 xm_write32(hw, port, XM_TX_EV_MSK, XMT_DEF_MSK);
1570
1571 /* Configure MAC arbiter */
1572 skge_write16(hw, B3_MA_TO_CTRL, MA_RST_CLR);
1573
1574 /* configure timeout values */
1575 skge_write8(hw, B3_MA_TOINI_RX1, 72);
1576 skge_write8(hw, B3_MA_TOINI_RX2, 72);
1577 skge_write8(hw, B3_MA_TOINI_TX1, 72);
1578 skge_write8(hw, B3_MA_TOINI_TX2, 72);
1579
1580 skge_write8(hw, B3_MA_RCINI_RX1, 0);
1581 skge_write8(hw, B3_MA_RCINI_RX2, 0);
1582 skge_write8(hw, B3_MA_RCINI_TX1, 0);
1583 skge_write8(hw, B3_MA_RCINI_TX2, 0);
1584
1585 /* Configure Rx MAC FIFO */
1586 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_CLR);
1587 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_TIM_PAT);
1588 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_ENA_OP_MD);
1589
1590 /* Configure Tx MAC FIFO */
1591 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_CLR);
1592 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_TX_CTRL_DEF);
1593 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_ENA_OP_MD);
1594
1595 if (jumbo) {
1596 /* Enable frame flushing if jumbo frames used */
1597 skge_write16(hw, SK_REG(port,RX_MFF_CTRL1), MFF_ENA_FLUSH);
1598 } else {
1599 /* enable timeout timers if normal frames */
1600 skge_write16(hw, B3_PA_CTRL,
1601 (port == 0) ? PA_ENA_TO_TX1 : PA_ENA_TO_TX2);
1602 }
1603 }
1604
1605 static void genesis_stop(struct skge_port *skge)
1606 {
1607 struct skge_hw *hw = skge->hw;
1608 int port = skge->port;
1609 u32 reg;
1610
1611 genesis_reset(hw, port);
1612
1613 /* Clear Tx packet arbiter timeout IRQ */
1614 skge_write16(hw, B3_PA_CTRL,
1615 port == 0 ? PA_CLR_TO_TX1 : PA_CLR_TO_TX2);
1616
1617 /*
1618 * If the transfer sticks at the MAC the STOP command will not
1619 * terminate if we don't flush the XMAC's transmit FIFO !
1620 */
1621 xm_write32(hw, port, XM_MODE,
1622 xm_read32(hw, port, XM_MODE)|XM_MD_FTF);
1623
1624
1625 /* Reset the MAC */
1626 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1), MFF_SET_MAC_RST);
1627
1628 /* For external PHYs there must be special handling */
1629 if (hw->phy_type != SK_PHY_XMAC) {
1630 reg = skge_read32(hw, B2_GP_IO);
1631 if (port == 0) {
1632 reg |= GP_DIR_0;
1633 reg &= ~GP_IO_0;
1634 } else {
1635 reg |= GP_DIR_2;
1636 reg &= ~GP_IO_2;
1637 }
1638 skge_write32(hw, B2_GP_IO, reg);
1639 skge_read32(hw, B2_GP_IO);
1640 }
1641
1642 xm_write16(hw, port, XM_MMU_CMD,
1643 xm_read16(hw, port, XM_MMU_CMD)
1644 & ~(XM_MMU_ENA_RX | XM_MMU_ENA_TX));
1645
1646 xm_read16(hw, port, XM_MMU_CMD);
1647 }
1648
1649
1650 static void genesis_get_stats(struct skge_port *skge, u64 *data)
1651 {
1652 struct skge_hw *hw = skge->hw;
1653 int port = skge->port;
1654 int i;
1655 unsigned long timeout = jiffies + HZ;
1656
1657 xm_write16(hw, port,
1658 XM_STAT_CMD, XM_SC_SNP_TXC | XM_SC_SNP_RXC);
1659
1660 /* wait for update to complete */
1661 while (xm_read16(hw, port, XM_STAT_CMD)
1662 & (XM_SC_SNP_TXC | XM_SC_SNP_RXC)) {
1663 if (time_after(jiffies, timeout))
1664 break;
1665 udelay(10);
1666 }
1667
1668 /* special case for 64 bit octet counter */
1669 data[0] = (u64) xm_read32(hw, port, XM_TXO_OK_HI) << 32
1670 | xm_read32(hw, port, XM_TXO_OK_LO);
1671 data[1] = (u64) xm_read32(hw, port, XM_RXO_OK_HI) << 32
1672 | xm_read32(hw, port, XM_RXO_OK_LO);
1673
1674 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
1675 data[i] = xm_read32(hw, port, skge_stats[i].xmac_offset);
1676 }
1677
1678 static void genesis_mac_intr(struct skge_hw *hw, int port)
1679 {
1680 struct skge_port *skge = netdev_priv(hw->dev[port]);
1681 u16 status = xm_read16(hw, port, XM_ISRC);
1682
1683 if (netif_msg_intr(skge))
1684 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
1685 skge->netdev->name, status);
1686
1687 if (hw->phy_type == SK_PHY_XMAC &&
1688 (status & (XM_IS_INP_ASS | XM_IS_LIPA_RC)))
1689 xm_link_down(hw, port);
1690
1691 if (status & XM_IS_TXF_UR) {
1692 xm_write32(hw, port, XM_MODE, XM_MD_FTF);
1693 ++skge->net_stats.tx_fifo_errors;
1694 }
1695 if (status & XM_IS_RXF_OV) {
1696 xm_write32(hw, port, XM_MODE, XM_MD_FRF);
1697 ++skge->net_stats.rx_fifo_errors;
1698 }
1699 }
1700
1701 static void genesis_link_up(struct skge_port *skge)
1702 {
1703 struct skge_hw *hw = skge->hw;
1704 int port = skge->port;
1705 u16 cmd, msk;
1706 u32 mode;
1707
1708 cmd = xm_read16(hw, port, XM_MMU_CMD);
1709
1710 /*
1711 * enabling pause frame reception is required for 1000BT
1712 * because the XMAC is not reset if the link is going down
1713 */
1714 if (skge->flow_status == FLOW_STAT_NONE ||
1715 skge->flow_status == FLOW_STAT_LOC_SEND)
1716 /* Disable Pause Frame Reception */
1717 cmd |= XM_MMU_IGN_PF;
1718 else
1719 /* Enable Pause Frame Reception */
1720 cmd &= ~XM_MMU_IGN_PF;
1721
1722 xm_write16(hw, port, XM_MMU_CMD, cmd);
1723
1724 mode = xm_read32(hw, port, XM_MODE);
1725 if (skge->flow_status== FLOW_STAT_SYMMETRIC ||
1726 skge->flow_status == FLOW_STAT_LOC_SEND) {
1727 /*
1728 * Configure Pause Frame Generation
1729 * Use internal and external Pause Frame Generation.
1730 * Sending pause frames is edge triggered.
1731 * Send a Pause frame with the maximum pause time if
1732 * internal oder external FIFO full condition occurs.
1733 * Send a zero pause time frame to re-start transmission.
1734 */
1735 /* XM_PAUSE_DA = '010000C28001' (default) */
1736 /* XM_MAC_PTIME = 0xffff (maximum) */
1737 /* remember this value is defined in big endian (!) */
1738 xm_write16(hw, port, XM_MAC_PTIME, 0xffff);
1739
1740 mode |= XM_PAUSE_MODE;
1741 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_ENA_PAUSE);
1742 } else {
1743 /*
1744 * disable pause frame generation is required for 1000BT
1745 * because the XMAC is not reset if the link is going down
1746 */
1747 /* Disable Pause Mode in Mode Register */
1748 mode &= ~XM_PAUSE_MODE;
1749
1750 skge_write16(hw, SK_REG(port, RX_MFF_CTRL1), MFF_DIS_PAUSE);
1751 }
1752
1753 xm_write32(hw, port, XM_MODE, mode);
1754 msk = XM_DEF_MSK;
1755 if (hw->phy_type != SK_PHY_XMAC)
1756 msk |= XM_IS_INP_ASS; /* disable GP0 interrupt bit */
1757
1758 xm_write16(hw, port, XM_IMSK, msk);
1759 xm_read16(hw, port, XM_ISRC);
1760
1761 /* get MMU Command Reg. */
1762 cmd = xm_read16(hw, port, XM_MMU_CMD);
1763 if (hw->phy_type != SK_PHY_XMAC && skge->duplex == DUPLEX_FULL)
1764 cmd |= XM_MMU_GMII_FD;
1765
1766 /*
1767 * Workaround BCOM Errata (#10523) for all BCom Phys
1768 * Enable Power Management after link up
1769 */
1770 if (hw->phy_type == SK_PHY_BCOM) {
1771 xm_phy_write(hw, port, PHY_BCOM_AUX_CTRL,
1772 xm_phy_read(hw, port, PHY_BCOM_AUX_CTRL)
1773 & ~PHY_B_AC_DIS_PM);
1774 xm_phy_write(hw, port, PHY_BCOM_INT_MASK, PHY_B_DEF_MSK);
1775 }
1776
1777 /* enable Rx/Tx */
1778 xm_write16(hw, port, XM_MMU_CMD,
1779 cmd | XM_MMU_ENA_RX | XM_MMU_ENA_TX);
1780 skge_link_up(skge);
1781 }
1782
1783
1784 static inline void bcom_phy_intr(struct skge_port *skge)
1785 {
1786 struct skge_hw *hw = skge->hw;
1787 int port = skge->port;
1788 u16 isrc;
1789
1790 isrc = xm_phy_read(hw, port, PHY_BCOM_INT_STAT);
1791 if (netif_msg_intr(skge))
1792 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x\n",
1793 skge->netdev->name, isrc);
1794
1795 if (isrc & PHY_B_IS_PSE)
1796 printk(KERN_ERR PFX "%s: uncorrectable pair swap error\n",
1797 hw->dev[port]->name);
1798
1799 /* Workaround BCom Errata:
1800 * enable and disable loopback mode if "NO HCD" occurs.
1801 */
1802 if (isrc & PHY_B_IS_NO_HDCL) {
1803 u16 ctrl = xm_phy_read(hw, port, PHY_BCOM_CTRL);
1804 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1805 ctrl | PHY_CT_LOOP);
1806 xm_phy_write(hw, port, PHY_BCOM_CTRL,
1807 ctrl & ~PHY_CT_LOOP);
1808 }
1809
1810 if (isrc & (PHY_B_IS_AN_PR | PHY_B_IS_LST_CHANGE))
1811 bcom_check_link(hw, port);
1812
1813 }
1814
1815 static int gm_phy_write(struct skge_hw *hw, int port, u16 reg, u16 val)
1816 {
1817 int i;
1818
1819 gma_write16(hw, port, GM_SMI_DATA, val);
1820 gma_write16(hw, port, GM_SMI_CTRL,
1821 GM_SMI_CT_PHY_AD(hw->phy_addr) | GM_SMI_CT_REG_AD(reg));
1822 for (i = 0; i < PHY_RETRIES; i++) {
1823 udelay(1);
1824
1825 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
1826 return 0;
1827 }
1828
1829 printk(KERN_WARNING PFX "%s: phy write timeout\n",
1830 hw->dev[port]->name);
1831 return -EIO;
1832 }
1833
1834 static int __gm_phy_read(struct skge_hw *hw, int port, u16 reg, u16 *val)
1835 {
1836 int i;
1837
1838 gma_write16(hw, port, GM_SMI_CTRL,
1839 GM_SMI_CT_PHY_AD(hw->phy_addr)
1840 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
1841
1842 for (i = 0; i < PHY_RETRIES; i++) {
1843 udelay(1);
1844 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL)
1845 goto ready;
1846 }
1847
1848 return -ETIMEDOUT;
1849 ready:
1850 *val = gma_read16(hw, port, GM_SMI_DATA);
1851 return 0;
1852 }
1853
1854 static u16 gm_phy_read(struct skge_hw *hw, int port, u16 reg)
1855 {
1856 u16 v = 0;
1857 if (__gm_phy_read(hw, port, reg, &v))
1858 printk(KERN_WARNING PFX "%s: phy read timeout\n",
1859 hw->dev[port]->name);
1860 return v;
1861 }
1862
1863 /* Marvell Phy Initialization */
1864 static void yukon_init(struct skge_hw *hw, int port)
1865 {
1866 struct skge_port *skge = netdev_priv(hw->dev[port]);
1867 u16 ctrl, ct1000, adv;
1868
1869 if (skge->autoneg == AUTONEG_ENABLE) {
1870 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
1871
1872 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
1873 PHY_M_EC_MAC_S_MSK);
1874 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
1875
1876 ectrl |= PHY_M_EC_M_DSC(0) | PHY_M_EC_S_DSC(1);
1877
1878 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
1879 }
1880
1881 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
1882 if (skge->autoneg == AUTONEG_DISABLE)
1883 ctrl &= ~PHY_CT_ANE;
1884
1885 ctrl |= PHY_CT_RESET;
1886 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1887
1888 ctrl = 0;
1889 ct1000 = 0;
1890 adv = PHY_AN_CSMA;
1891
1892 if (skge->autoneg == AUTONEG_ENABLE) {
1893 if (hw->copper) {
1894 if (skge->advertising & ADVERTISED_1000baseT_Full)
1895 ct1000 |= PHY_M_1000C_AFD;
1896 if (skge->advertising & ADVERTISED_1000baseT_Half)
1897 ct1000 |= PHY_M_1000C_AHD;
1898 if (skge->advertising & ADVERTISED_100baseT_Full)
1899 adv |= PHY_M_AN_100_FD;
1900 if (skge->advertising & ADVERTISED_100baseT_Half)
1901 adv |= PHY_M_AN_100_HD;
1902 if (skge->advertising & ADVERTISED_10baseT_Full)
1903 adv |= PHY_M_AN_10_FD;
1904 if (skge->advertising & ADVERTISED_10baseT_Half)
1905 adv |= PHY_M_AN_10_HD;
1906
1907 /* Set Flow-control capabilities */
1908 adv |= phy_pause_map[skge->flow_control];
1909 } else {
1910 if (skge->advertising & ADVERTISED_1000baseT_Full)
1911 adv |= PHY_M_AN_1000X_AFD;
1912 if (skge->advertising & ADVERTISED_1000baseT_Half)
1913 adv |= PHY_M_AN_1000X_AHD;
1914
1915 adv |= fiber_pause_map[skge->flow_control];
1916 }
1917
1918 /* Restart Auto-negotiation */
1919 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
1920 } else {
1921 /* forced speed/duplex settings */
1922 ct1000 = PHY_M_1000C_MSE;
1923
1924 if (skge->duplex == DUPLEX_FULL)
1925 ctrl |= PHY_CT_DUP_MD;
1926
1927 switch (skge->speed) {
1928 case SPEED_1000:
1929 ctrl |= PHY_CT_SP1000;
1930 break;
1931 case SPEED_100:
1932 ctrl |= PHY_CT_SP100;
1933 break;
1934 }
1935
1936 ctrl |= PHY_CT_RESET;
1937 }
1938
1939 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
1940
1941 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
1942 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
1943
1944 /* Enable phy interrupt on autonegotiation complete (or link up) */
1945 if (skge->autoneg == AUTONEG_ENABLE)
1946 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_MSK);
1947 else
1948 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
1949 }
1950
1951 static void yukon_reset(struct skge_hw *hw, int port)
1952 {
1953 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);/* disable PHY IRQs */
1954 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
1955 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
1956 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
1957 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
1958
1959 gma_write16(hw, port, GM_RX_CTRL,
1960 gma_read16(hw, port, GM_RX_CTRL)
1961 | GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
1962 }
1963
1964 /* Apparently, early versions of Yukon-Lite had wrong chip_id? */
1965 static int is_yukon_lite_a0(struct skge_hw *hw)
1966 {
1967 u32 reg;
1968 int ret;
1969
1970 if (hw->chip_id != CHIP_ID_YUKON)
1971 return 0;
1972
1973 reg = skge_read32(hw, B2_FAR);
1974 skge_write8(hw, B2_FAR + 3, 0xff);
1975 ret = (skge_read8(hw, B2_FAR + 3) != 0);
1976 skge_write32(hw, B2_FAR, reg);
1977 return ret;
1978 }
1979
1980 static void yukon_mac_init(struct skge_hw *hw, int port)
1981 {
1982 struct skge_port *skge = netdev_priv(hw->dev[port]);
1983 int i;
1984 u32 reg;
1985 const u8 *addr = hw->dev[port]->dev_addr;
1986
1987 /* WA code for COMA mode -- set PHY reset */
1988 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
1989 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
1990 reg = skge_read32(hw, B2_GP_IO);
1991 reg |= GP_DIR_9 | GP_IO_9;
1992 skge_write32(hw, B2_GP_IO, reg);
1993 }
1994
1995 /* hard reset */
1996 skge_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1997 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1998
1999 /* WA code for COMA mode -- clear PHY reset */
2000 if (hw->chip_id == CHIP_ID_YUKON_LITE &&
2001 hw->chip_rev >= CHIP_REV_YU_LITE_A3) {
2002 reg = skge_read32(hw, B2_GP_IO);
2003 reg |= GP_DIR_9;
2004 reg &= ~GP_IO_9;
2005 skge_write32(hw, B2_GP_IO, reg);
2006 }
2007
2008 /* Set hardware config mode */
2009 reg = GPC_INT_POL_HI | GPC_DIS_FC | GPC_DIS_SLEEP |
2010 GPC_ENA_XC | GPC_ANEG_ADV_ALL_M | GPC_ENA_PAUSE;
2011 reg |= hw->copper ? GPC_HWCFG_GMII_COP : GPC_HWCFG_GMII_FIB;
2012
2013 /* Clear GMC reset */
2014 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_SET);
2015 skge_write32(hw, SK_REG(port, GPHY_CTRL), reg | GPC_RST_CLR);
2016 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON | GMC_RST_CLR);
2017
2018 if (skge->autoneg == AUTONEG_DISABLE) {
2019 reg = GM_GPCR_AU_ALL_DIS;
2020 gma_write16(hw, port, GM_GP_CTRL,
2021 gma_read16(hw, port, GM_GP_CTRL) | reg);
2022
2023 switch (skge->speed) {
2024 case SPEED_1000:
2025 reg &= ~GM_GPCR_SPEED_100;
2026 reg |= GM_GPCR_SPEED_1000;
2027 break;
2028 case SPEED_100:
2029 reg &= ~GM_GPCR_SPEED_1000;
2030 reg |= GM_GPCR_SPEED_100;
2031 break;
2032 case SPEED_10:
2033 reg &= ~(GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100);
2034 break;
2035 }
2036
2037 if (skge->duplex == DUPLEX_FULL)
2038 reg |= GM_GPCR_DUP_FULL;
2039 } else
2040 reg = GM_GPCR_SPEED_1000 | GM_GPCR_SPEED_100 | GM_GPCR_DUP_FULL;
2041
2042 switch (skge->flow_control) {
2043 case FLOW_MODE_NONE:
2044 skge_write32(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2045 reg |= GM_GPCR_FC_TX_DIS | GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2046 break;
2047 case FLOW_MODE_LOC_SEND:
2048 /* disable Rx flow-control */
2049 reg |= GM_GPCR_FC_RX_DIS | GM_GPCR_AU_FCT_DIS;
2050 break;
2051 case FLOW_MODE_SYMMETRIC:
2052 case FLOW_MODE_SYM_OR_REM:
2053 /* enable Tx & Rx flow-control */
2054 break;
2055 }
2056
2057 gma_write16(hw, port, GM_GP_CTRL, reg);
2058 skge_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
2059
2060 yukon_init(hw, port);
2061
2062 /* MIB clear */
2063 reg = gma_read16(hw, port, GM_PHY_ADDR);
2064 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
2065
2066 for (i = 0; i < GM_MIB_CNT_SIZE; i++)
2067 gma_read16(hw, port, GM_MIB_CNT_BASE + 8*i);
2068 gma_write16(hw, port, GM_PHY_ADDR, reg);
2069
2070 /* transmit control */
2071 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
2072
2073 /* receive control reg: unicast + multicast + no FCS */
2074 gma_write16(hw, port, GM_RX_CTRL,
2075 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
2076
2077 /* transmit flow control */
2078 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
2079
2080 /* transmit parameter */
2081 gma_write16(hw, port, GM_TX_PARAM,
2082 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
2083 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
2084 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF));
2085
2086 /* serial mode register */
2087 reg = GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
2088 if (hw->dev[port]->mtu > 1500)
2089 reg |= GM_SMOD_JUMBO_ENA;
2090
2091 gma_write16(hw, port, GM_SERIAL_MODE, reg);
2092
2093 /* physical address: used for pause frames */
2094 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
2095 /* virtual address for data */
2096 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
2097
2098 /* enable interrupt mask for counter overflows */
2099 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
2100 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
2101 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
2102
2103 /* Initialize Mac Fifo */
2104
2105 /* Configure Rx MAC FIFO */
2106 skge_write16(hw, SK_REG(port, RX_GMF_FL_MSK), RX_FF_FL_DEF_MSK);
2107 reg = GMF_OPER_ON | GMF_RX_F_FL_ON;
2108
2109 /* disable Rx GMAC FIFO Flush for YUKON-Lite Rev. A0 only */
2110 if (is_yukon_lite_a0(hw))
2111 reg &= ~GMF_RX_F_FL_ON;
2112
2113 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
2114 skge_write16(hw, SK_REG(port, RX_GMF_CTRL_T), reg);
2115 /*
2116 * because Pause Packet Truncation in GMAC is not working
2117 * we have to increase the Flush Threshold to 64 bytes
2118 * in order to flush pause packets in Rx FIFO on Yukon-1
2119 */
2120 skge_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
2121
2122 /* Configure Tx MAC FIFO */
2123 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
2124 skge_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
2125 }
2126
2127 /* Go into power down mode */
2128 static void yukon_suspend(struct skge_hw *hw, int port)
2129 {
2130 u16 ctrl;
2131
2132 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
2133 ctrl |= PHY_M_PC_POL_R_DIS;
2134 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
2135
2136 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2137 ctrl |= PHY_CT_RESET;
2138 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2139
2140 /* switch IEEE compatible power down mode on */
2141 ctrl = gm_phy_read(hw, port, PHY_MARV_CTRL);
2142 ctrl |= PHY_CT_PDOWN;
2143 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
2144 }
2145
2146 static void yukon_stop(struct skge_port *skge)
2147 {
2148 struct skge_hw *hw = skge->hw;
2149 int port = skge->port;
2150
2151 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
2152 yukon_reset(hw, port);
2153
2154 gma_write16(hw, port, GM_GP_CTRL,
2155 gma_read16(hw, port, GM_GP_CTRL)
2156 & ~(GM_GPCR_TX_ENA|GM_GPCR_RX_ENA));
2157 gma_read16(hw, port, GM_GP_CTRL);
2158
2159 yukon_suspend(hw, port);
2160
2161 /* set GPHY Control reset */
2162 skge_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
2163 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
2164 }
2165
2166 static void yukon_get_stats(struct skge_port *skge, u64 *data)
2167 {
2168 struct skge_hw *hw = skge->hw;
2169 int port = skge->port;
2170 int i;
2171
2172 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2173 | gma_read32(hw, port, GM_TXO_OK_LO);
2174 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2175 | gma_read32(hw, port, GM_RXO_OK_LO);
2176
2177 for (i = 2; i < ARRAY_SIZE(skge_stats); i++)
2178 data[i] = gma_read32(hw, port,
2179 skge_stats[i].gma_offset);
2180 }
2181
2182 static void yukon_mac_intr(struct skge_hw *hw, int port)
2183 {
2184 struct net_device *dev = hw->dev[port];
2185 struct skge_port *skge = netdev_priv(dev);
2186 u8 status = skge_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2187
2188 if (netif_msg_intr(skge))
2189 printk(KERN_DEBUG PFX "%s: mac interrupt status 0x%x\n",
2190 dev->name, status);
2191
2192 if (status & GM_IS_RX_FF_OR) {
2193 ++skge->net_stats.rx_fifo_errors;
2194 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2195 }
2196
2197 if (status & GM_IS_TX_FF_UR) {
2198 ++skge->net_stats.tx_fifo_errors;
2199 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2200 }
2201
2202 }
2203
2204 static u16 yukon_speed(const struct skge_hw *hw, u16 aux)
2205 {
2206 switch (aux & PHY_M_PS_SPEED_MSK) {
2207 case PHY_M_PS_SPEED_1000:
2208 return SPEED_1000;
2209 case PHY_M_PS_SPEED_100:
2210 return SPEED_100;
2211 default:
2212 return SPEED_10;
2213 }
2214 }
2215
2216 static void yukon_link_up(struct skge_port *skge)
2217 {
2218 struct skge_hw *hw = skge->hw;
2219 int port = skge->port;
2220 u16 reg;
2221
2222 /* Enable Transmit FIFO Underrun */
2223 skge_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
2224
2225 reg = gma_read16(hw, port, GM_GP_CTRL);
2226 if (skge->duplex == DUPLEX_FULL || skge->autoneg == AUTONEG_ENABLE)
2227 reg |= GM_GPCR_DUP_FULL;
2228
2229 /* enable Rx/Tx */
2230 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
2231 gma_write16(hw, port, GM_GP_CTRL, reg);
2232
2233 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_DEF_MSK);
2234 skge_link_up(skge);
2235 }
2236
2237 static void yukon_link_down(struct skge_port *skge)
2238 {
2239 struct skge_hw *hw = skge->hw;
2240 int port = skge->port;
2241 u16 ctrl;
2242
2243 ctrl = gma_read16(hw, port, GM_GP_CTRL);
2244 ctrl &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
2245 gma_write16(hw, port, GM_GP_CTRL, ctrl);
2246
2247 if (skge->flow_status == FLOW_STAT_REM_SEND) {
2248 ctrl = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
2249 ctrl |= PHY_M_AN_ASP;
2250 /* restore Asymmetric Pause bit */
2251 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, ctrl);
2252 }
2253
2254 skge_link_down(skge);
2255
2256 yukon_init(hw, port);
2257 }
2258
2259 static void yukon_phy_intr(struct skge_port *skge)
2260 {
2261 struct skge_hw *hw = skge->hw;
2262 int port = skge->port;
2263 const char *reason = NULL;
2264 u16 istatus, phystat;
2265
2266 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
2267 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
2268
2269 if (netif_msg_intr(skge))
2270 printk(KERN_DEBUG PFX "%s: phy interrupt status 0x%x 0x%x\n",
2271 skge->netdev->name, istatus, phystat);
2272
2273 if (istatus & PHY_M_IS_AN_COMPL) {
2274 if (gm_phy_read(hw, port, PHY_MARV_AUNE_LP)
2275 & PHY_M_AN_RF) {
2276 reason = "remote fault";
2277 goto failed;
2278 }
2279
2280 if (gm_phy_read(hw, port, PHY_MARV_1000T_STAT) & PHY_B_1000S_MSF) {
2281 reason = "master/slave fault";
2282 goto failed;
2283 }
2284
2285 if (!(phystat & PHY_M_PS_SPDUP_RES)) {
2286 reason = "speed/duplex";
2287 goto failed;
2288 }
2289
2290 skge->duplex = (phystat & PHY_M_PS_FULL_DUP)
2291 ? DUPLEX_FULL : DUPLEX_HALF;
2292 skge->speed = yukon_speed(hw, phystat);
2293
2294 /* We are using IEEE 802.3z/D5.0 Table 37-4 */
2295 switch (phystat & PHY_M_PS_PAUSE_MSK) {
2296 case PHY_M_PS_PAUSE_MSK:
2297 skge->flow_status = FLOW_STAT_SYMMETRIC;
2298 break;
2299 case PHY_M_PS_RX_P_EN:
2300 skge->flow_status = FLOW_STAT_REM_SEND;
2301 break;
2302 case PHY_M_PS_TX_P_EN:
2303 skge->flow_status = FLOW_STAT_LOC_SEND;
2304 break;
2305 default:
2306 skge->flow_status = FLOW_STAT_NONE;
2307 }
2308
2309 if (skge->flow_status == FLOW_STAT_NONE ||
2310 (skge->speed < SPEED_1000 && skge->duplex == DUPLEX_HALF))
2311 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
2312 else
2313 skge_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
2314 yukon_link_up(skge);
2315 return;
2316 }
2317
2318 if (istatus & PHY_M_IS_LSP_CHANGE)
2319 skge->speed = yukon_speed(hw, phystat);
2320
2321 if (istatus & PHY_M_IS_DUP_CHANGE)
2322 skge->duplex = (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
2323 if (istatus & PHY_M_IS_LST_CHANGE) {
2324 if (phystat & PHY_M_PS_LINK_UP)
2325 yukon_link_up(skge);
2326 else
2327 yukon_link_down(skge);
2328 }
2329 return;
2330 failed:
2331 printk(KERN_ERR PFX "%s: autonegotiation failed (%s)\n",
2332 skge->netdev->name, reason);
2333
2334 /* XXX restart autonegotiation? */
2335 }
2336
2337 static void skge_phy_reset(struct skge_port *skge)
2338 {
2339 struct skge_hw *hw = skge->hw;
2340 int port = skge->port;
2341 struct net_device *dev = hw->dev[port];
2342
2343 netif_stop_queue(skge->netdev);
2344 netif_carrier_off(skge->netdev);
2345
2346 spin_lock_bh(&hw->phy_lock);
2347 if (hw->chip_id == CHIP_ID_GENESIS) {
2348 genesis_reset(hw, port);
2349 genesis_mac_init(hw, port);
2350 } else {
2351 yukon_reset(hw, port);
2352 yukon_init(hw, port);
2353 }
2354 spin_unlock_bh(&hw->phy_lock);
2355
2356 dev->set_multicast_list(dev);
2357 }
2358
2359 /* Basic MII support */
2360 static int skge_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
2361 {
2362 struct mii_ioctl_data *data = if_mii(ifr);
2363 struct skge_port *skge = netdev_priv(dev);
2364 struct skge_hw *hw = skge->hw;
2365 int err = -EOPNOTSUPP;
2366
2367 if (!netif_running(dev))
2368 return -ENODEV; /* Phy still in reset */
2369
2370 switch(cmd) {
2371 case SIOCGMIIPHY:
2372 data->phy_id = hw->phy_addr;
2373
2374 /* fallthru */
2375 case SIOCGMIIREG: {
2376 u16 val = 0;
2377 spin_lock_bh(&hw->phy_lock);
2378 if (hw->chip_id == CHIP_ID_GENESIS)
2379 err = __xm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2380 else
2381 err = __gm_phy_read(hw, skge->port, data->reg_num & 0x1f, &val);
2382 spin_unlock_bh(&hw->phy_lock);
2383 data->val_out = val;
2384 break;
2385 }
2386
2387 case SIOCSMIIREG:
2388 if (!capable(CAP_NET_ADMIN))
2389 return -EPERM;
2390
2391 spin_lock_bh(&hw->phy_lock);
2392 if (hw->chip_id == CHIP_ID_GENESIS)
2393 err = xm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2394 data->val_in);
2395 else
2396 err = gm_phy_write(hw, skge->port, data->reg_num & 0x1f,
2397 data->val_in);
2398 spin_unlock_bh(&hw->phy_lock);
2399 break;
2400 }
2401 return err;
2402 }
2403
2404 static void skge_ramset(struct skge_hw *hw, u16 q, u32 start, size_t len)
2405 {
2406 u32 end;
2407
2408 start /= 8;
2409 len /= 8;
2410 end = start + len - 1;
2411
2412 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
2413 skge_write32(hw, RB_ADDR(q, RB_START), start);
2414 skge_write32(hw, RB_ADDR(q, RB_WP), start);
2415 skge_write32(hw, RB_ADDR(q, RB_RP), start);
2416 skge_write32(hw, RB_ADDR(q, RB_END), end);
2417
2418 if (q == Q_R1 || q == Q_R2) {
2419 /* Set thresholds on receive queue's */
2420 skge_write32(hw, RB_ADDR(q, RB_RX_UTPP),
2421 start + (2*len)/3);
2422 skge_write32(hw, RB_ADDR(q, RB_RX_LTPP),
2423 start + (len/3));
2424 } else {
2425 /* Enable store & forward on Tx queue's because
2426 * Tx FIFO is only 4K on Genesis and 1K on Yukon
2427 */
2428 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
2429 }
2430
2431 skge_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
2432 }
2433
2434 /* Setup Bus Memory Interface */
2435 static void skge_qset(struct skge_port *skge, u16 q,
2436 const struct skge_element *e)
2437 {
2438 struct skge_hw *hw = skge->hw;
2439 u32 watermark = 0x600;
2440 u64 base = skge->dma + (e->desc - skge->mem);
2441
2442 /* optimization to reduce window on 32bit/33mhz */
2443 if ((skge_read16(hw, B0_CTST) & (CS_BUS_CLOCK | CS_BUS_SLOT_SZ)) == 0)
2444 watermark /= 2;
2445
2446 skge_write32(hw, Q_ADDR(q, Q_CSR), CSR_CLR_RESET);
2447 skge_write32(hw, Q_ADDR(q, Q_F), watermark);
2448 skge_write32(hw, Q_ADDR(q, Q_DA_H), (u32)(base >> 32));
2449 skge_write32(hw, Q_ADDR(q, Q_DA_L), (u32)base);
2450 }
2451
2452 static int skge_up(struct net_device *dev)
2453 {
2454 struct skge_port *skge = netdev_priv(dev);
2455 struct skge_hw *hw = skge->hw;
2456 int port = skge->port;
2457 u32 chunk, ram_addr;
2458 size_t rx_size, tx_size;
2459 int err;
2460
2461 if (!is_valid_ether_addr(dev->dev_addr))
2462 return -EINVAL;
2463
2464 if (netif_msg_ifup(skge))
2465 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
2466
2467 if (dev->mtu > RX_BUF_SIZE)
2468 skge->rx_buf_size = dev->mtu + ETH_HLEN;
2469 else
2470 skge->rx_buf_size = RX_BUF_SIZE;
2471
2472
2473 rx_size = skge->rx_ring.count * sizeof(struct skge_rx_desc);
2474 tx_size = skge->tx_ring.count * sizeof(struct skge_tx_desc);
2475 skge->mem_size = tx_size + rx_size;
2476 skge->mem = pci_alloc_consistent(hw->pdev, skge->mem_size, &skge->dma);
2477 if (!skge->mem)
2478 return -ENOMEM;
2479
2480 BUG_ON(skge->dma & 7);
2481
2482 if ((u64)skge->dma >> 32 != ((u64) skge->dma + skge->mem_size) >> 32) {
2483 dev_err(&hw->pdev->dev, "pci_alloc_consistent region crosses 4G boundary\n");
2484 err = -EINVAL;
2485 goto free_pci_mem;
2486 }
2487
2488 memset(skge->mem, 0, skge->mem_size);
2489
2490 err = skge_ring_alloc(&skge->rx_ring, skge->mem, skge->dma);
2491 if (err)
2492 goto free_pci_mem;
2493
2494 err = skge_rx_fill(dev);
2495 if (err)
2496 goto free_rx_ring;
2497
2498 err = skge_ring_alloc(&skge->tx_ring, skge->mem + rx_size,
2499 skge->dma + rx_size);
2500 if (err)
2501 goto free_rx_ring;
2502
2503 /* Initialize MAC */
2504 spin_lock_bh(&hw->phy_lock);
2505 if (hw->chip_id == CHIP_ID_GENESIS)
2506 genesis_mac_init(hw, port);
2507 else
2508 yukon_mac_init(hw, port);
2509 spin_unlock_bh(&hw->phy_lock);
2510
2511 /* Configure RAMbuffers */
2512 chunk = hw->ram_size / ((hw->ports + 1)*2);
2513 ram_addr = hw->ram_offset + 2 * chunk * port;
2514
2515 skge_ramset(hw, rxqaddr[port], ram_addr, chunk);
2516 skge_qset(skge, rxqaddr[port], skge->rx_ring.to_clean);
2517
2518 BUG_ON(skge->tx_ring.to_use != skge->tx_ring.to_clean);
2519 skge_ramset(hw, txqaddr[port], ram_addr+chunk, chunk);
2520 skge_qset(skge, txqaddr[port], skge->tx_ring.to_use);
2521
2522 /* Start receiver BMU */
2523 wmb();
2524 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_START | CSR_IRQ_CL_F);
2525 skge_led(skge, LED_MODE_ON);
2526
2527 spin_lock_irq(&hw->hw_lock);
2528 hw->intr_mask |= portmask[port];
2529 skge_write32(hw, B0_IMSK, hw->intr_mask);
2530 spin_unlock_irq(&hw->hw_lock);
2531
2532 netif_poll_enable(dev);
2533 return 0;
2534
2535 free_rx_ring:
2536 skge_rx_clean(skge);
2537 kfree(skge->rx_ring.start);
2538 free_pci_mem:
2539 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2540 skge->mem = NULL;
2541
2542 return err;
2543 }
2544
2545 static int skge_down(struct net_device *dev)
2546 {
2547 struct skge_port *skge = netdev_priv(dev);
2548 struct skge_hw *hw = skge->hw;
2549 int port = skge->port;
2550
2551 if (skge->mem == NULL)
2552 return 0;
2553
2554 if (netif_msg_ifdown(skge))
2555 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
2556
2557 netif_stop_queue(dev);
2558
2559 if (hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC)
2560 del_timer_sync(&skge->link_timer);
2561
2562 netif_poll_disable(dev);
2563 netif_carrier_off(dev);
2564
2565 spin_lock_irq(&hw->hw_lock);
2566 hw->intr_mask &= ~portmask[port];
2567 skge_write32(hw, B0_IMSK, hw->intr_mask);
2568 spin_unlock_irq(&hw->hw_lock);
2569
2570 skge_write8(skge->hw, SK_REG(skge->port, LNK_LED_REG), LED_OFF);
2571 if (hw->chip_id == CHIP_ID_GENESIS)
2572 genesis_stop(skge);
2573 else
2574 yukon_stop(skge);
2575
2576 /* Stop transmitter */
2577 skge_write8(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_STOP);
2578 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
2579 RB_RST_SET|RB_DIS_OP_MD);
2580
2581
2582 /* Disable Force Sync bit and Enable Alloc bit */
2583 skge_write8(hw, SK_REG(port, TXA_CTRL),
2584 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
2585
2586 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
2587 skge_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
2588 skge_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
2589
2590 /* Reset PCI FIFO */
2591 skge_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), CSR_SET_RESET);
2592 skge_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
2593
2594 /* Reset the RAM Buffer async Tx queue */
2595 skge_write8(hw, RB_ADDR(port == 0 ? Q_XA1 : Q_XA2, RB_CTRL), RB_RST_SET);
2596 /* stop receiver */
2597 skge_write8(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_STOP);
2598 skge_write32(hw, RB_ADDR(port ? Q_R2 : Q_R1, RB_CTRL),
2599 RB_RST_SET|RB_DIS_OP_MD);
2600 skge_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), CSR_SET_RESET);
2601
2602 if (hw->chip_id == CHIP_ID_GENESIS) {
2603 skge_write8(hw, SK_REG(port, TX_MFF_CTRL2), MFF_RST_SET);
2604 skge_write8(hw, SK_REG(port, RX_MFF_CTRL2), MFF_RST_SET);
2605 } else {
2606 skge_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
2607 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
2608 }
2609
2610 skge_led(skge, LED_MODE_OFF);
2611
2612 netif_tx_lock_bh(dev);
2613 skge_tx_clean(dev);
2614 netif_tx_unlock_bh(dev);
2615
2616 skge_rx_clean(skge);
2617
2618 kfree(skge->rx_ring.start);
2619 kfree(skge->tx_ring.start);
2620 pci_free_consistent(hw->pdev, skge->mem_size, skge->mem, skge->dma);
2621 skge->mem = NULL;
2622 return 0;
2623 }
2624
2625 static inline int skge_avail(const struct skge_ring *ring)
2626 {
2627 smp_mb();
2628 return ((ring->to_clean > ring->to_use) ? 0 : ring->count)
2629 + (ring->to_clean - ring->to_use) - 1;
2630 }
2631
2632 static int skge_xmit_frame(struct sk_buff *skb, struct net_device *dev)
2633 {
2634 struct skge_port *skge = netdev_priv(dev);
2635 struct skge_hw *hw = skge->hw;
2636 struct skge_element *e;
2637 struct skge_tx_desc *td;
2638 int i;
2639 u32 control, len;
2640 u64 map;
2641
2642 if (skb_padto(skb, ETH_ZLEN))
2643 return NETDEV_TX_OK;
2644
2645 if (unlikely(skge_avail(&skge->tx_ring) < skb_shinfo(skb)->nr_frags + 1))
2646 return NETDEV_TX_BUSY;
2647
2648 e = skge->tx_ring.to_use;
2649 td = e->desc;
2650 BUG_ON(td->control & BMU_OWN);
2651 e->skb = skb;
2652 len = skb_headlen(skb);
2653 map = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
2654 pci_unmap_addr_set(e, mapaddr, map);
2655 pci_unmap_len_set(e, maplen, len);
2656
2657 td->dma_lo = map;
2658 td->dma_hi = map >> 32;
2659
2660 if (skb->ip_summed == CHECKSUM_PARTIAL) {
2661 const int offset = skb_transport_offset(skb);
2662
2663 /* This seems backwards, but it is what the sk98lin
2664 * does. Looks like hardware is wrong?
2665 */
2666 if (ipip_hdr(skb)->protocol == IPPROTO_UDP
2667 && hw->chip_rev == 0 && hw->chip_id == CHIP_ID_YUKON)
2668 control = BMU_TCP_CHECK;
2669 else
2670 control = BMU_UDP_CHECK;
2671
2672 td->csum_offs = 0;
2673 td->csum_start = offset;
2674 td->csum_write = offset + skb->csum_offset;
2675 } else
2676 control = BMU_CHECK;
2677
2678 if (!skb_shinfo(skb)->nr_frags) /* single buffer i.e. no fragments */
2679 control |= BMU_EOF| BMU_IRQ_EOF;
2680 else {
2681 struct skge_tx_desc *tf = td;
2682
2683 control |= BMU_STFWD;
2684 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2685 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2686
2687 map = pci_map_page(hw->pdev, frag->page, frag->page_offset,
2688 frag->size, PCI_DMA_TODEVICE);
2689
2690 e = e->next;
2691 e->skb = skb;
2692 tf = e->desc;
2693 BUG_ON(tf->control & BMU_OWN);
2694
2695 tf->dma_lo = map;
2696 tf->dma_hi = (u64) map >> 32;
2697 pci_unmap_addr_set(e, mapaddr, map);
2698 pci_unmap_len_set(e, maplen, frag->size);
2699
2700 tf->control = BMU_OWN | BMU_SW | control | frag->size;
2701 }
2702 tf->control |= BMU_EOF | BMU_IRQ_EOF;
2703 }
2704 /* Make sure all the descriptors written */
2705 wmb();
2706 td->control = BMU_OWN | BMU_SW | BMU_STF | control | len;
2707 wmb();
2708
2709 skge_write8(hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_START);
2710
2711 if (unlikely(netif_msg_tx_queued(skge)))
2712 printk(KERN_DEBUG "%s: tx queued, slot %td, len %d\n",
2713 dev->name, e - skge->tx_ring.start, skb->len);
2714
2715 skge->tx_ring.to_use = e->next;
2716 smp_wmb();
2717
2718 if (skge_avail(&skge->tx_ring) <= TX_LOW_WATER) {
2719 pr_debug("%s: transmit queue full\n", dev->name);
2720 netif_stop_queue(dev);
2721 }
2722
2723 dev->trans_start = jiffies;
2724
2725 return NETDEV_TX_OK;
2726 }
2727
2728
2729 /* Free resources associated with this reing element */
2730 static void skge_tx_free(struct skge_port *skge, struct skge_element *e,
2731 u32 control)
2732 {
2733 struct pci_dev *pdev = skge->hw->pdev;
2734
2735 /* skb header vs. fragment */
2736 if (control & BMU_STF)
2737 pci_unmap_single(pdev, pci_unmap_addr(e, mapaddr),
2738 pci_unmap_len(e, maplen),
2739 PCI_DMA_TODEVICE);
2740 else
2741 pci_unmap_page(pdev, pci_unmap_addr(e, mapaddr),
2742 pci_unmap_len(e, maplen),
2743 PCI_DMA_TODEVICE);
2744
2745 if (control & BMU_EOF) {
2746 if (unlikely(netif_msg_tx_done(skge)))
2747 printk(KERN_DEBUG PFX "%s: tx done slot %td\n",
2748 skge->netdev->name, e - skge->tx_ring.start);
2749
2750 dev_kfree_skb(e->skb);
2751 }
2752 }
2753
2754 /* Free all buffers in transmit ring */
2755 static void skge_tx_clean(struct net_device *dev)
2756 {
2757 struct skge_port *skge = netdev_priv(dev);
2758 struct skge_element *e;
2759
2760 for (e = skge->tx_ring.to_clean; e != skge->tx_ring.to_use; e = e->next) {
2761 struct skge_tx_desc *td = e->desc;
2762 skge_tx_free(skge, e, td->control);
2763 td->control = 0;
2764 }
2765
2766 skge->tx_ring.to_clean = e;
2767 netif_wake_queue(dev);
2768 }
2769
2770 static void skge_tx_timeout(struct net_device *dev)
2771 {
2772 struct skge_port *skge = netdev_priv(dev);
2773
2774 if (netif_msg_timer(skge))
2775 printk(KERN_DEBUG PFX "%s: tx timeout\n", dev->name);
2776
2777 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_STOP);
2778 skge_tx_clean(dev);
2779 }
2780
2781 static int skge_change_mtu(struct net_device *dev, int new_mtu)
2782 {
2783 int err;
2784
2785 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
2786 return -EINVAL;
2787
2788 if (!netif_running(dev)) {
2789 dev->mtu = new_mtu;
2790 return 0;
2791 }
2792
2793 skge_down(dev);
2794
2795 dev->mtu = new_mtu;
2796
2797 err = skge_up(dev);
2798 if (err)
2799 dev_close(dev);
2800
2801 return err;
2802 }
2803
2804 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
2805
2806 static void genesis_add_filter(u8 filter[8], const u8 *addr)
2807 {
2808 u32 crc, bit;
2809
2810 crc = ether_crc_le(ETH_ALEN, addr);
2811 bit = ~crc & 0x3f;
2812 filter[bit/8] |= 1 << (bit%8);
2813 }
2814
2815 static void genesis_set_multicast(struct net_device *dev)
2816 {
2817 struct skge_port *skge = netdev_priv(dev);
2818 struct skge_hw *hw = skge->hw;
2819 int port = skge->port;
2820 int i, count = dev->mc_count;
2821 struct dev_mc_list *list = dev->mc_list;
2822 u32 mode;
2823 u8 filter[8];
2824
2825 mode = xm_read32(hw, port, XM_MODE);
2826 mode |= XM_MD_ENA_HASH;
2827 if (dev->flags & IFF_PROMISC)
2828 mode |= XM_MD_ENA_PROM;
2829 else
2830 mode &= ~XM_MD_ENA_PROM;
2831
2832 if (dev->flags & IFF_ALLMULTI)
2833 memset(filter, 0xff, sizeof(filter));
2834 else {
2835 memset(filter, 0, sizeof(filter));
2836
2837 if (skge->flow_status == FLOW_STAT_REM_SEND
2838 || skge->flow_status == FLOW_STAT_SYMMETRIC)
2839 genesis_add_filter(filter, pause_mc_addr);
2840
2841 for (i = 0; list && i < count; i++, list = list->next)
2842 genesis_add_filter(filter, list->dmi_addr);
2843 }
2844
2845 xm_write32(hw, port, XM_MODE, mode);
2846 xm_outhash(hw, port, XM_HSM, filter);
2847 }
2848
2849 static void yukon_add_filter(u8 filter[8], const u8 *addr)
2850 {
2851 u32 bit = ether_crc(ETH_ALEN, addr) & 0x3f;
2852 filter[bit/8] |= 1 << (bit%8);
2853 }
2854
2855 static void yukon_set_multicast(struct net_device *dev)
2856 {
2857 struct skge_port *skge = netdev_priv(dev);
2858 struct skge_hw *hw = skge->hw;
2859 int port = skge->port;
2860 struct dev_mc_list *list = dev->mc_list;
2861 int rx_pause = (skge->flow_status == FLOW_STAT_REM_SEND
2862 || skge->flow_status == FLOW_STAT_SYMMETRIC);
2863 u16 reg;
2864 u8 filter[8];
2865
2866 memset(filter, 0, sizeof(filter));
2867
2868 reg = gma_read16(hw, port, GM_RX_CTRL);
2869 reg |= GM_RXCR_UCF_ENA;
2870
2871 if (dev->flags & IFF_PROMISC) /* promiscuous */
2872 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
2873 else if (dev->flags & IFF_ALLMULTI) /* all multicast */
2874 memset(filter, 0xff, sizeof(filter));
2875 else if (dev->mc_count == 0 && !rx_pause)/* no multicast */
2876 reg &= ~GM_RXCR_MCF_ENA;
2877 else {
2878 int i;
2879 reg |= GM_RXCR_MCF_ENA;
2880
2881 if (rx_pause)
2882 yukon_add_filter(filter, pause_mc_addr);
2883
2884 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
2885 yukon_add_filter(filter, list->dmi_addr);
2886 }
2887
2888
2889 gma_write16(hw, port, GM_MC_ADDR_H1,
2890 (u16)filter[0] | ((u16)filter[1] << 8));
2891 gma_write16(hw, port, GM_MC_ADDR_H2,
2892 (u16)filter[2] | ((u16)filter[3] << 8));
2893 gma_write16(hw, port, GM_MC_ADDR_H3,
2894 (u16)filter[4] | ((u16)filter[5] << 8));
2895 gma_write16(hw, port, GM_MC_ADDR_H4,
2896 (u16)filter[6] | ((u16)filter[7] << 8));
2897
2898 gma_write16(hw, port, GM_RX_CTRL, reg);
2899 }
2900
2901 static inline u16 phy_length(const struct skge_hw *hw, u32 status)
2902 {
2903 if (hw->chip_id == CHIP_ID_GENESIS)
2904 return status >> XMR_FS_LEN_SHIFT;
2905 else
2906 return status >> GMR_FS_LEN_SHIFT;
2907 }
2908
2909 static inline int bad_phy_status(const struct skge_hw *hw, u32 status)
2910 {
2911 if (hw->chip_id == CHIP_ID_GENESIS)
2912 return (status & (XMR_FS_ERR | XMR_FS_2L_VLAN)) != 0;
2913 else
2914 return (status & GMR_FS_ANY_ERR) ||
2915 (status & GMR_FS_RX_OK) == 0;
2916 }
2917
2918
2919 /* Get receive buffer from descriptor.
2920 * Handles copy of small buffers and reallocation failures
2921 */
2922 static struct sk_buff *skge_rx_get(struct net_device *dev,
2923 struct skge_element *e,
2924 u32 control, u32 status, u16 csum)
2925 {
2926 struct skge_port *skge = netdev_priv(dev);
2927 struct sk_buff *skb;
2928 u16 len = control & BMU_BBC;
2929
2930 if (unlikely(netif_msg_rx_status(skge)))
2931 printk(KERN_DEBUG PFX "%s: rx slot %td status 0x%x len %d\n",
2932 dev->name, e - skge->rx_ring.start,
2933 status, len);
2934
2935 if (len > skge->rx_buf_size)
2936 goto error;
2937
2938 if ((control & (BMU_EOF|BMU_STF)) != (BMU_STF|BMU_EOF))
2939 goto error;
2940
2941 if (bad_phy_status(skge->hw, status))
2942 goto error;
2943
2944 if (phy_length(skge->hw, status) != len)
2945 goto error;
2946
2947 if (len < RX_COPY_THRESHOLD) {
2948 skb = netdev_alloc_skb(dev, len + 2);
2949 if (!skb)
2950 goto resubmit;
2951
2952 skb_reserve(skb, 2);
2953 pci_dma_sync_single_for_cpu(skge->hw->pdev,
2954 pci_unmap_addr(e, mapaddr),
2955 len, PCI_DMA_FROMDEVICE);
2956 skb_copy_from_linear_data(e->skb, skb->data, len);
2957 pci_dma_sync_single_for_device(skge->hw->pdev,
2958 pci_unmap_addr(e, mapaddr),
2959 len, PCI_DMA_FROMDEVICE);
2960 skge_rx_reuse(e, skge->rx_buf_size);
2961 } else {
2962 struct sk_buff *nskb;
2963 nskb = netdev_alloc_skb(dev, skge->rx_buf_size + NET_IP_ALIGN);
2964 if (!nskb)
2965 goto resubmit;
2966
2967 skb_reserve(nskb, NET_IP_ALIGN);
2968 pci_unmap_single(skge->hw->pdev,
2969 pci_unmap_addr(e, mapaddr),
2970 pci_unmap_len(e, maplen),
2971 PCI_DMA_FROMDEVICE);
2972 skb = e->skb;
2973 prefetch(skb->data);
2974 skge_rx_setup(skge, e, nskb, skge->rx_buf_size);
2975 }
2976
2977 skb_put(skb, len);
2978 if (skge->rx_csum) {
2979 skb->csum = csum;
2980 skb->ip_summed = CHECKSUM_COMPLETE;
2981 }
2982
2983 skb->protocol = eth_type_trans(skb, dev);
2984
2985 return skb;
2986 error:
2987
2988 if (netif_msg_rx_err(skge))
2989 printk(KERN_DEBUG PFX "%s: rx err, slot %td control 0x%x status 0x%x\n",
2990 dev->name, e - skge->rx_ring.start,
2991 control, status);
2992
2993 if (skge->hw->chip_id == CHIP_ID_GENESIS) {
2994 if (status & (XMR_FS_RUNT|XMR_FS_LNG_ERR))
2995 skge->net_stats.rx_length_errors++;
2996 if (status & XMR_FS_FRA_ERR)
2997 skge->net_stats.rx_frame_errors++;
2998 if (status & XMR_FS_FCS_ERR)
2999 skge->net_stats.rx_crc_errors++;
3000 } else {
3001 if (status & (GMR_FS_LONG_ERR|GMR_FS_UN_SIZE))
3002 skge->net_stats.rx_length_errors++;
3003 if (status & GMR_FS_FRAGMENT)
3004 skge->net_stats.rx_frame_errors++;
3005 if (status & GMR_FS_CRC_ERR)
3006 skge->net_stats.rx_crc_errors++;
3007 }
3008
3009 resubmit:
3010 skge_rx_reuse(e, skge->rx_buf_size);
3011 return NULL;
3012 }
3013
3014 /* Free all buffers in Tx ring which are no longer owned by device */
3015 static void skge_tx_done(struct net_device *dev)
3016 {
3017 struct skge_port *skge = netdev_priv(dev);
3018 struct skge_ring *ring = &skge->tx_ring;
3019 struct skge_element *e;
3020
3021 skge_write8(skge->hw, Q_ADDR(txqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3022
3023 for (e = ring->to_clean; e != ring->to_use; e = e->next) {
3024 u32 control = ((const struct skge_tx_desc *) e->desc)->control;
3025
3026 if (control & BMU_OWN)
3027 break;
3028
3029 skge_tx_free(skge, e, control);
3030 }
3031 skge->tx_ring.to_clean = e;
3032
3033 /* Can run lockless until we need to synchronize to restart queue. */
3034 smp_mb();
3035
3036 if (unlikely(netif_queue_stopped(dev) &&
3037 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3038 netif_tx_lock(dev);
3039 if (unlikely(netif_queue_stopped(dev) &&
3040 skge_avail(&skge->tx_ring) > TX_LOW_WATER)) {
3041 netif_wake_queue(dev);
3042
3043 }
3044 netif_tx_unlock(dev);
3045 }
3046 }
3047
3048 static int skge_poll(struct net_device *dev, int *budget)
3049 {
3050 struct skge_port *skge = netdev_priv(dev);
3051 struct skge_hw *hw = skge->hw;
3052 struct skge_ring *ring = &skge->rx_ring;
3053 struct skge_element *e;
3054 unsigned long flags;
3055 int to_do = min(dev->quota, *budget);
3056 int work_done = 0;
3057
3058 skge_tx_done(dev);
3059
3060 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_IRQ_CL_F);
3061
3062 for (e = ring->to_clean; prefetch(e->next), work_done < to_do; e = e->next) {
3063 struct skge_rx_desc *rd = e->desc;
3064 struct sk_buff *skb;
3065 u32 control;
3066
3067 rmb();
3068 control = rd->control;
3069 if (control & BMU_OWN)
3070 break;
3071
3072 skb = skge_rx_get(dev, e, control, rd->status, rd->csum2);
3073 if (likely(skb)) {
3074 dev->last_rx = jiffies;
3075 netif_receive_skb(skb);
3076
3077 ++work_done;
3078 }
3079 }
3080 ring->to_clean = e;
3081
3082 /* restart receiver */
3083 wmb();
3084 skge_write8(hw, Q_ADDR(rxqaddr[skge->port], Q_CSR), CSR_START);
3085
3086 *budget -= work_done;
3087 dev->quota -= work_done;
3088
3089 if (work_done >= to_do)
3090 return 1; /* not done */
3091
3092 spin_lock_irqsave(&hw->hw_lock, flags);
3093 __netif_rx_complete(dev);
3094 hw->intr_mask |= napimask[skge->port];
3095 skge_write32(hw, B0_IMSK, hw->intr_mask);
3096 skge_read32(hw, B0_IMSK);
3097 spin_unlock_irqrestore(&hw->hw_lock, flags);
3098
3099 return 0;
3100 }
3101
3102 /* Parity errors seem to happen when Genesis is connected to a switch
3103 * with no other ports present. Heartbeat error??
3104 */
3105 static void skge_mac_parity(struct skge_hw *hw, int port)
3106 {
3107 struct net_device *dev = hw->dev[port];
3108
3109 if (dev) {
3110 struct skge_port *skge = netdev_priv(dev);
3111 ++skge->net_stats.tx_heartbeat_errors;
3112 }
3113
3114 if (hw->chip_id == CHIP_ID_GENESIS)
3115 skge_write16(hw, SK_REG(port, TX_MFF_CTRL1),
3116 MFF_CLR_PERR);
3117 else
3118 /* HW-Bug #8: cleared by GMF_CLI_TX_FC instead of GMF_CLI_TX_PE */
3119 skge_write8(hw, SK_REG(port, TX_GMF_CTRL_T),
3120 (hw->chip_id == CHIP_ID_YUKON && hw->chip_rev == 0)
3121 ? GMF_CLI_TX_FC : GMF_CLI_TX_PE);
3122 }
3123
3124 static void skge_mac_intr(struct skge_hw *hw, int port)
3125 {
3126 if (hw->chip_id == CHIP_ID_GENESIS)
3127 genesis_mac_intr(hw, port);
3128 else
3129 yukon_mac_intr(hw, port);
3130 }
3131
3132 /* Handle device specific framing and timeout interrupts */
3133 static void skge_error_irq(struct skge_hw *hw)
3134 {
3135 struct pci_dev *pdev = hw->pdev;
3136 u32 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3137
3138 if (hw->chip_id == CHIP_ID_GENESIS) {
3139 /* clear xmac errors */
3140 if (hwstatus & (IS_NO_STAT_M1|IS_NO_TIST_M1))
3141 skge_write16(hw, RX_MFF_CTRL1, MFF_CLR_INSTAT);
3142 if (hwstatus & (IS_NO_STAT_M2|IS_NO_TIST_M2))
3143 skge_write16(hw, RX_MFF_CTRL2, MFF_CLR_INSTAT);
3144 } else {
3145 /* Timestamp (unused) overflow */
3146 if (hwstatus & IS_IRQ_TIST_OV)
3147 skge_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
3148 }
3149
3150 if (hwstatus & IS_RAM_RD_PAR) {
3151 dev_err(&pdev->dev, "Ram read data parity error\n");
3152 skge_write16(hw, B3_RI_CTRL, RI_CLR_RD_PERR);
3153 }
3154
3155 if (hwstatus & IS_RAM_WR_PAR) {
3156 dev_err(&pdev->dev, "Ram write data parity error\n");
3157 skge_write16(hw, B3_RI_CTRL, RI_CLR_WR_PERR);
3158 }
3159
3160 if (hwstatus & IS_M1_PAR_ERR)
3161 skge_mac_parity(hw, 0);
3162
3163 if (hwstatus & IS_M2_PAR_ERR)
3164 skge_mac_parity(hw, 1);
3165
3166 if (hwstatus & IS_R1_PAR_ERR) {
3167 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3168 hw->dev[0]->name);
3169 skge_write32(hw, B0_R1_CSR, CSR_IRQ_CL_P);
3170 }
3171
3172 if (hwstatus & IS_R2_PAR_ERR) {
3173 dev_err(&pdev->dev, "%s: receive queue parity error\n",
3174 hw->dev[1]->name);
3175 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P);
3176 }
3177
3178 if (hwstatus & (IS_IRQ_MST_ERR|IS_IRQ_STAT)) {
3179 u16 pci_status, pci_cmd;
3180
3181 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd);
3182 pci_read_config_word(pdev, PCI_STATUS, &pci_status);
3183
3184 dev_err(&pdev->dev, "PCI error cmd=%#x status=%#x\n",
3185 pci_cmd, pci_status);
3186
3187 /* Write the error bits back to clear them. */
3188 pci_status &= PCI_STATUS_ERROR_BITS;
3189 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3190 pci_write_config_word(pdev, PCI_COMMAND,
3191 pci_cmd | PCI_COMMAND_SERR | PCI_COMMAND_PARITY);
3192 pci_write_config_word(pdev, PCI_STATUS, pci_status);
3193 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3194
3195 /* if error still set then just ignore it */
3196 hwstatus = skge_read32(hw, B0_HWE_ISRC);
3197 if (hwstatus & IS_IRQ_STAT) {
3198 dev_warn(&hw->pdev->dev, "unable to clear error (so ignoring them)\n");
3199 hw->intr_mask &= ~IS_HW_ERR;
3200 }
3201 }
3202 }
3203
3204 /*
3205 * Interrupt from PHY are handled in tasklet (softirq)
3206 * because accessing phy registers requires spin wait which might
3207 * cause excess interrupt latency.
3208 */
3209 static void skge_extirq(unsigned long arg)
3210 {
3211 struct skge_hw *hw = (struct skge_hw *) arg;
3212 int port;
3213
3214 for (port = 0; port < hw->ports; port++) {
3215 struct net_device *dev = hw->dev[port];
3216
3217 if (netif_running(dev)) {
3218 struct skge_port *skge = netdev_priv(dev);
3219
3220 spin_lock(&hw->phy_lock);
3221 if (hw->chip_id != CHIP_ID_GENESIS)
3222 yukon_phy_intr(skge);
3223 else if (hw->phy_type == SK_PHY_BCOM)
3224 bcom_phy_intr(skge);
3225 spin_unlock(&hw->phy_lock);
3226 }
3227 }
3228
3229 spin_lock_irq(&hw->hw_lock);
3230 hw->intr_mask |= IS_EXT_REG;
3231 skge_write32(hw, B0_IMSK, hw->intr_mask);
3232 skge_read32(hw, B0_IMSK);
3233 spin_unlock_irq(&hw->hw_lock);
3234 }
3235
3236 static irqreturn_t skge_intr(int irq, void *dev_id)
3237 {
3238 struct skge_hw *hw = dev_id;
3239 u32 status;
3240 int handled = 0;
3241
3242 spin_lock(&hw->hw_lock);
3243 /* Reading this register masks IRQ */
3244 status = skge_read32(hw, B0_SP_ISRC);
3245 if (status == 0 || status == ~0)
3246 goto out;
3247
3248 handled = 1;
3249 status &= hw->intr_mask;
3250 if (status & IS_EXT_REG) {
3251 hw->intr_mask &= ~IS_EXT_REG;
3252 tasklet_schedule(&hw->phy_task);
3253 }
3254
3255 if (status & (IS_XA1_F|IS_R1_F)) {
3256 hw->intr_mask &= ~(IS_XA1_F|IS_R1_F);
3257 netif_rx_schedule(hw->dev[0]);
3258 }
3259
3260 if (status & IS_PA_TO_TX1)
3261 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX1);
3262
3263 if (status & IS_PA_TO_RX1) {
3264 struct skge_port *skge = netdev_priv(hw->dev[0]);
3265
3266 ++skge->net_stats.rx_over_errors;
3267 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX1);
3268 }
3269
3270
3271 if (status & IS_MAC1)
3272 skge_mac_intr(hw, 0);
3273
3274 if (hw->dev[1]) {
3275 if (status & (IS_XA2_F|IS_R2_F)) {
3276 hw->intr_mask &= ~(IS_XA2_F|IS_R2_F);
3277 netif_rx_schedule(hw->dev[1]);
3278 }
3279
3280 if (status & IS_PA_TO_RX2) {
3281 struct skge_port *skge = netdev_priv(hw->dev[1]);
3282 ++skge->net_stats.rx_over_errors;
3283 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_RX2);
3284 }
3285
3286 if (status & IS_PA_TO_TX2)
3287 skge_write16(hw, B3_PA_CTRL, PA_CLR_TO_TX2);
3288
3289 if (status & IS_MAC2)
3290 skge_mac_intr(hw, 1);
3291 }
3292
3293 if (status & IS_HW_ERR)
3294 skge_error_irq(hw);
3295
3296 skge_write32(hw, B0_IMSK, hw->intr_mask);
3297 skge_read32(hw, B0_IMSK);
3298 out:
3299 spin_unlock(&hw->hw_lock);
3300
3301 return IRQ_RETVAL(handled);
3302 }
3303
3304 #ifdef CONFIG_NET_POLL_CONTROLLER
3305 static void skge_netpoll(struct net_device *dev)
3306 {
3307 struct skge_port *skge = netdev_priv(dev);
3308
3309 disable_irq(dev->irq);
3310 skge_intr(dev->irq, skge->hw);
3311 enable_irq(dev->irq);
3312 }
3313 #endif
3314
3315 static int skge_set_mac_address(struct net_device *dev, void *p)
3316 {
3317 struct skge_port *skge = netdev_priv(dev);
3318 struct skge_hw *hw = skge->hw;
3319 unsigned port = skge->port;
3320 const struct sockaddr *addr = p;
3321 u16 ctrl;
3322
3323 if (!is_valid_ether_addr(addr->sa_data))
3324 return -EADDRNOTAVAIL;
3325
3326 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3327
3328 if (!netif_running(dev)) {
3329 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3330 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3331 } else {
3332 /* disable Rx */
3333 spin_lock_bh(&hw->phy_lock);
3334 ctrl = gma_read16(hw, port, GM_GP_CTRL);
3335 gma_write16(hw, port, GM_GP_CTRL, ctrl & ~GM_GPCR_RX_ENA);
3336
3337 memcpy_toio(hw->regs + B2_MAC_1 + port*8, dev->dev_addr, ETH_ALEN);
3338 memcpy_toio(hw->regs + B2_MAC_2 + port*8, dev->dev_addr, ETH_ALEN);
3339
3340 if (hw->chip_id == CHIP_ID_GENESIS)
3341 xm_outaddr(hw, port, XM_SA, dev->dev_addr);
3342 else {
3343 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3344 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3345 }
3346
3347 gma_write16(hw, port, GM_GP_CTRL, ctrl);
3348 spin_unlock_bh(&hw->phy_lock);
3349 }
3350
3351 return 0;
3352 }
3353
3354 static const struct {
3355 u8 id;
3356 const char *name;
3357 } skge_chips[] = {
3358 { CHIP_ID_GENESIS, "Genesis" },
3359 { CHIP_ID_YUKON, "Yukon" },
3360 { CHIP_ID_YUKON_LITE, "Yukon-Lite"},
3361 { CHIP_ID_YUKON_LP, "Yukon-LP"},
3362 };
3363
3364 static const char *skge_board_name(const struct skge_hw *hw)
3365 {
3366 int i;
3367 static char buf[16];
3368
3369 for (i = 0; i < ARRAY_SIZE(skge_chips); i++)
3370 if (skge_chips[i].id == hw->chip_id)
3371 return skge_chips[i].name;
3372
3373 snprintf(buf, sizeof buf, "chipid 0x%x", hw->chip_id);
3374 return buf;
3375 }
3376
3377
3378 /*
3379 * Setup the board data structure, but don't bring up
3380 * the port(s)
3381 */
3382 static int skge_reset(struct skge_hw *hw)
3383 {
3384 u32 reg;
3385 u16 ctst, pci_status;
3386 u8 t8, mac_cfg, pmd_type;
3387 int i;
3388
3389 ctst = skge_read16(hw, B0_CTST);
3390
3391 /* do a SW reset */
3392 skge_write8(hw, B0_CTST, CS_RST_SET);
3393 skge_write8(hw, B0_CTST, CS_RST_CLR);
3394
3395 /* clear PCI errors, if any */
3396 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3397 skge_write8(hw, B2_TST_CTRL2, 0);
3398
3399 pci_read_config_word(hw->pdev, PCI_STATUS, &pci_status);
3400 pci_write_config_word(hw->pdev, PCI_STATUS,
3401 pci_status | PCI_STATUS_ERROR_BITS);
3402 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3403 skge_write8(hw, B0_CTST, CS_MRST_CLR);
3404
3405 /* restore CLK_RUN bits (for Yukon-Lite) */
3406 skge_write16(hw, B0_CTST,
3407 ctst & (CS_CLK_RUN_HOT|CS_CLK_RUN_RST|CS_CLK_RUN_ENA));
3408
3409 hw->chip_id = skge_read8(hw, B2_CHIP_ID);
3410 hw->phy_type = skge_read8(hw, B2_E_1) & 0xf;
3411 pmd_type = skge_read8(hw, B2_PMD_TYP);
3412 hw->copper = (pmd_type == 'T' || pmd_type == '1');
3413
3414 switch (hw->chip_id) {
3415 case CHIP_ID_GENESIS:
3416 switch (hw->phy_type) {
3417 case SK_PHY_XMAC:
3418 hw->phy_addr = PHY_ADDR_XMAC;
3419 break;
3420 case SK_PHY_BCOM:
3421 hw->phy_addr = PHY_ADDR_BCOM;
3422 break;
3423 default:
3424 dev_err(&hw->pdev->dev, "unsupported phy type 0x%x\n",
3425 hw->phy_type);
3426 return -EOPNOTSUPP;
3427 }
3428 break;
3429
3430 case CHIP_ID_YUKON:
3431 case CHIP_ID_YUKON_LITE:
3432 case CHIP_ID_YUKON_LP:
3433 if (hw->phy_type < SK_PHY_MARV_COPPER && pmd_type != 'S')
3434 hw->copper = 1;
3435
3436 hw->phy_addr = PHY_ADDR_MARV;
3437 break;
3438
3439 default:
3440 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
3441 hw->chip_id);
3442 return -EOPNOTSUPP;
3443 }
3444
3445 mac_cfg = skge_read8(hw, B2_MAC_CFG);
3446 hw->ports = (mac_cfg & CFG_SNG_MAC) ? 1 : 2;
3447 hw->chip_rev = (mac_cfg & CFG_CHIP_R_MSK) >> 4;
3448
3449 /* read the adapters RAM size */
3450 t8 = skge_read8(hw, B2_E_0);
3451 if (hw->chip_id == CHIP_ID_GENESIS) {
3452 if (t8 == 3) {
3453 /* special case: 4 x 64k x 36, offset = 0x80000 */
3454 hw->ram_size = 0x100000;
3455 hw->ram_offset = 0x80000;
3456 } else
3457 hw->ram_size = t8 * 512;
3458 }
3459 else if (t8 == 0)
3460 hw->ram_size = 0x20000;
3461 else
3462 hw->ram_size = t8 * 4096;
3463
3464 hw->intr_mask = IS_HW_ERR;
3465
3466 /* Use PHY IRQ for all but fiber based Genesis board */
3467 if (!(hw->chip_id == CHIP_ID_GENESIS && hw->phy_type == SK_PHY_XMAC))
3468 hw->intr_mask |= IS_EXT_REG;
3469
3470 if (hw->chip_id == CHIP_ID_GENESIS)
3471 genesis_init(hw);
3472 else {
3473 /* switch power to VCC (WA for VAUX problem) */
3474 skge_write8(hw, B0_POWER_CTRL,
3475 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
3476
3477 /* avoid boards with stuck Hardware error bits */
3478 if ((skge_read32(hw, B0_ISRC) & IS_HW_ERR) &&
3479 (skge_read32(hw, B0_HWE_ISRC) & IS_IRQ_SENSOR)) {
3480 dev_warn(&hw->pdev->dev, "stuck hardware sensor bit\n");
3481 hw->intr_mask &= ~IS_HW_ERR;
3482 }
3483
3484 /* Clear PHY COMA */
3485 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
3486 pci_read_config_dword(hw->pdev, PCI_DEV_REG1, &reg);
3487 reg &= ~PCI_PHY_COMA;
3488 pci_write_config_dword(hw->pdev, PCI_DEV_REG1, reg);
3489 skge_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
3490
3491
3492 for (i = 0; i < hw->ports; i++) {
3493 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
3494 skge_write16(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
3495 }
3496 }
3497
3498 /* turn off hardware timer (unused) */
3499 skge_write8(hw, B2_TI_CTRL, TIM_STOP);
3500 skge_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
3501 skge_write8(hw, B0_LED, LED_STAT_ON);
3502
3503 /* enable the Tx Arbiters */
3504 for (i = 0; i < hw->ports; i++)
3505 skge_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
3506
3507 /* Initialize ram interface */
3508 skge_write16(hw, B3_RI_CTRL, RI_RST_CLR);
3509
3510 skge_write8(hw, B3_RI_WTO_R1, SK_RI_TO_53);
3511 skge_write8(hw, B3_RI_WTO_XA1, SK_RI_TO_53);
3512 skge_write8(hw, B3_RI_WTO_XS1, SK_RI_TO_53);
3513 skge_write8(hw, B3_RI_RTO_R1, SK_RI_TO_53);
3514 skge_write8(hw, B3_RI_RTO_XA1, SK_RI_TO_53);
3515 skge_write8(hw, B3_RI_RTO_XS1, SK_RI_TO_53);
3516 skge_write8(hw, B3_RI_WTO_R2, SK_RI_TO_53);
3517 skge_write8(hw, B3_RI_WTO_XA2, SK_RI_TO_53);
3518 skge_write8(hw, B3_RI_WTO_XS2, SK_RI_TO_53);
3519 skge_write8(hw, B3_RI_RTO_R2, SK_RI_TO_53);
3520 skge_write8(hw, B3_RI_RTO_XA2, SK_RI_TO_53);
3521 skge_write8(hw, B3_RI_RTO_XS2, SK_RI_TO_53);
3522
3523 skge_write32(hw, B0_HWE_IMSK, IS_ERR_MSK);
3524
3525 /* Set interrupt moderation for Transmit only
3526 * Receive interrupts avoided by NAPI
3527 */
3528 skge_write32(hw, B2_IRQM_MSK, IS_XA1_F|IS_XA2_F);
3529 skge_write32(hw, B2_IRQM_INI, skge_usecs2clk(hw, 100));
3530 skge_write32(hw, B2_IRQM_CTRL, TIM_START);
3531
3532 skge_write32(hw, B0_IMSK, hw->intr_mask);
3533
3534 for (i = 0; i < hw->ports; i++) {
3535 if (hw->chip_id == CHIP_ID_GENESIS)
3536 genesis_reset(hw, i);
3537 else
3538 yukon_reset(hw, i);
3539 }
3540
3541 return 0;
3542 }
3543
3544 /* Initialize network device */
3545 static struct net_device *skge_devinit(struct skge_hw *hw, int port,
3546 int highmem)
3547 {
3548 struct skge_port *skge;
3549 struct net_device *dev = alloc_etherdev(sizeof(*skge));
3550
3551 if (!dev) {
3552 dev_err(&hw->pdev->dev, "etherdev alloc failed\n");
3553 return NULL;
3554 }
3555
3556 SET_MODULE_OWNER(dev);
3557 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3558 dev->open = skge_up;
3559 dev->stop = skge_down;
3560 dev->do_ioctl = skge_ioctl;
3561 dev->hard_start_xmit = skge_xmit_frame;
3562 dev->get_stats = skge_get_stats;
3563 if (hw->chip_id == CHIP_ID_GENESIS)
3564 dev->set_multicast_list = genesis_set_multicast;
3565 else
3566 dev->set_multicast_list = yukon_set_multicast;
3567
3568 dev->set_mac_address = skge_set_mac_address;
3569 dev->change_mtu = skge_change_mtu;
3570 SET_ETHTOOL_OPS(dev, &skge_ethtool_ops);
3571 dev->tx_timeout = skge_tx_timeout;
3572 dev->watchdog_timeo = TX_WATCHDOG;
3573 dev->poll = skge_poll;
3574 dev->weight = NAPI_WEIGHT;
3575 #ifdef CONFIG_NET_POLL_CONTROLLER
3576 dev->poll_controller = skge_netpoll;
3577 #endif
3578 dev->irq = hw->pdev->irq;
3579
3580 if (highmem)
3581 dev->features |= NETIF_F_HIGHDMA;
3582
3583 skge = netdev_priv(dev);
3584 skge->netdev = dev;
3585 skge->hw = hw;
3586 skge->msg_enable = netif_msg_init(debug, default_msg);
3587
3588 skge->tx_ring.count = DEFAULT_TX_RING_SIZE;
3589 skge->rx_ring.count = DEFAULT_RX_RING_SIZE;
3590
3591 /* Auto speed and flow control */
3592 skge->autoneg = AUTONEG_ENABLE;
3593 skge->flow_control = FLOW_MODE_SYM_OR_REM;
3594 skge->duplex = -1;
3595 skge->speed = -1;
3596 skge->advertising = skge_supported_modes(hw);
3597
3598 if (pci_wake_enabled(hw->pdev))
3599 skge->wol = wol_supported(hw) & WAKE_MAGIC;
3600
3601 hw->dev[port] = dev;
3602
3603 skge->port = port;
3604
3605 /* Only used for Genesis XMAC */
3606 setup_timer(&skge->link_timer, xm_link_timer, (unsigned long) skge);
3607
3608 if (hw->chip_id != CHIP_ID_GENESIS) {
3609 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
3610 skge->rx_csum = 1;
3611 }
3612
3613 /* read the mac address */
3614 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port*8, ETH_ALEN);
3615 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3616
3617 /* device is off until link detection */
3618 netif_carrier_off(dev);
3619 netif_stop_queue(dev);
3620
3621 return dev;
3622 }
3623
3624 static void __devinit skge_show_addr(struct net_device *dev)
3625 {
3626 const struct skge_port *skge = netdev_priv(dev);
3627
3628 if (netif_msg_probe(skge))
3629 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3630 dev->name,
3631 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3632 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3633 }
3634
3635 static int __devinit skge_probe(struct pci_dev *pdev,
3636 const struct pci_device_id *ent)
3637 {
3638 struct net_device *dev, *dev1;
3639 struct skge_hw *hw;
3640 int err, using_dac = 0;
3641
3642 err = pci_enable_device(pdev);
3643 if (err) {
3644 dev_err(&pdev->dev, "cannot enable PCI device\n");
3645 goto err_out;
3646 }
3647
3648 err = pci_request_regions(pdev, DRV_NAME);
3649 if (err) {
3650 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
3651 goto err_out_disable_pdev;
3652 }
3653
3654 pci_set_master(pdev);
3655
3656 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3657 using_dac = 1;
3658 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3659 } else if (!(err = pci_set_dma_mask(pdev, DMA_32BIT_MASK))) {
3660 using_dac = 0;
3661 err = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3662 }
3663
3664 if (err) {
3665 dev_err(&pdev->dev, "no usable DMA configuration\n");
3666 goto err_out_free_regions;
3667 }
3668
3669 #ifdef __BIG_ENDIAN
3670 /* byte swap descriptors in hardware */
3671 {
3672 u32 reg;
3673
3674 pci_read_config_dword(pdev, PCI_DEV_REG2, &reg);
3675 reg |= PCI_REV_DESC;
3676 pci_write_config_dword(pdev, PCI_DEV_REG2, reg);
3677 }
3678 #endif
3679
3680 err = -ENOMEM;
3681 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3682 if (!hw) {
3683 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
3684 goto err_out_free_regions;
3685 }
3686
3687 hw->pdev = pdev;
3688 spin_lock_init(&hw->hw_lock);
3689 spin_lock_init(&hw->phy_lock);
3690 tasklet_init(&hw->phy_task, &skge_extirq, (unsigned long) hw);
3691
3692 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3693 if (!hw->regs) {
3694 dev_err(&pdev->dev, "cannot map device registers\n");
3695 goto err_out_free_hw;
3696 }
3697
3698 err = skge_reset(hw);
3699 if (err)
3700 goto err_out_iounmap;
3701
3702 printk(KERN_INFO PFX DRV_VERSION " addr 0x%llx irq %d chip %s rev %d\n",
3703 (unsigned long long)pci_resource_start(pdev, 0), pdev->irq,
3704 skge_board_name(hw), hw->chip_rev);
3705
3706 dev = skge_devinit(hw, 0, using_dac);
3707 if (!dev)
3708 goto err_out_led_off;
3709
3710 /* Some motherboards are broken and has zero in ROM. */
3711 if (!is_valid_ether_addr(dev->dev_addr))
3712 dev_warn(&pdev->dev, "bad (zero?) ethernet address in rom\n");
3713
3714 err = register_netdev(dev);
3715 if (err) {
3716 dev_err(&pdev->dev, "cannot register net device\n");
3717 goto err_out_free_netdev;
3718 }
3719
3720 err = request_irq(pdev->irq, skge_intr, IRQF_SHARED, dev->name, hw);
3721 if (err) {
3722 dev_err(&pdev->dev, "%s: cannot assign irq %d\n",
3723 dev->name, pdev->irq);
3724 goto err_out_unregister;
3725 }
3726 skge_show_addr(dev);
3727
3728 if (hw->ports > 1 && (dev1 = skge_devinit(hw, 1, using_dac))) {
3729 if (register_netdev(dev1) == 0)
3730 skge_show_addr(dev1);
3731 else {
3732 /* Failure to register second port need not be fatal */
3733 dev_warn(&pdev->dev, "register of second port failed\n");
3734 hw->dev[1] = NULL;
3735 free_netdev(dev1);
3736 }
3737 }
3738 pci_set_drvdata(pdev, hw);
3739
3740 return 0;
3741
3742 err_out_unregister:
3743 unregister_netdev(dev);
3744 err_out_free_netdev:
3745 free_netdev(dev);
3746 err_out_led_off:
3747 skge_write16(hw, B0_LED, LED_STAT_OFF);
3748 err_out_iounmap:
3749 iounmap(hw->regs);
3750 err_out_free_hw:
3751 kfree(hw);
3752 err_out_free_regions:
3753 pci_release_regions(pdev);
3754 err_out_disable_pdev:
3755 pci_disable_device(pdev);
3756 pci_set_drvdata(pdev, NULL);
3757 err_out:
3758 return err;
3759 }
3760
3761 static void __devexit skge_remove(struct pci_dev *pdev)
3762 {
3763 struct skge_hw *hw = pci_get_drvdata(pdev);
3764 struct net_device *dev0, *dev1;
3765
3766 if (!hw)
3767 return;
3768
3769 flush_scheduled_work();
3770
3771 if ((dev1 = hw->dev[1]))
3772 unregister_netdev(dev1);
3773 dev0 = hw->dev[0];
3774 unregister_netdev(dev0);
3775
3776 tasklet_disable(&hw->phy_task);
3777
3778 spin_lock_irq(&hw->hw_lock);
3779 hw->intr_mask = 0;
3780 skge_write32(hw, B0_IMSK, 0);
3781 skge_read32(hw, B0_IMSK);
3782 spin_unlock_irq(&hw->hw_lock);
3783
3784 skge_write16(hw, B0_LED, LED_STAT_OFF);
3785 skge_write8(hw, B0_CTST, CS_RST_SET);
3786
3787 free_irq(pdev->irq, hw);
3788 pci_release_regions(pdev);
3789 pci_disable_device(pdev);
3790 if (dev1)
3791 free_netdev(dev1);
3792 free_netdev(dev0);
3793
3794 iounmap(hw->regs);
3795 kfree(hw);
3796 pci_set_drvdata(pdev, NULL);
3797 }
3798
3799 #ifdef CONFIG_PM
3800 static int skge_suspend(struct pci_dev *pdev, pm_message_t state)
3801 {
3802 struct skge_hw *hw = pci_get_drvdata(pdev);
3803 int i, err, wol = 0;
3804
3805 if (!hw)
3806 return 0;
3807
3808 err = pci_save_state(pdev);
3809 if (err)
3810 return err;
3811
3812 for (i = 0; i < hw->ports; i++) {
3813 struct net_device *dev = hw->dev[i];
3814 struct skge_port *skge = netdev_priv(dev);
3815
3816 if (netif_running(dev))
3817 skge_down(dev);
3818 if (skge->wol)
3819 skge_wol_init(skge);
3820
3821 wol |= skge->wol;
3822 }
3823
3824 skge_write32(hw, B0_IMSK, 0);
3825 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
3826 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3827
3828 return 0;
3829 }
3830
3831 static int skge_resume(struct pci_dev *pdev)
3832 {
3833 struct skge_hw *hw = pci_get_drvdata(pdev);
3834 int i, err;
3835
3836 if (!hw)
3837 return 0;
3838
3839 err = pci_set_power_state(pdev, PCI_D0);
3840 if (err)
3841 goto out;
3842
3843 err = pci_restore_state(pdev);
3844 if (err)
3845 goto out;
3846
3847 pci_enable_wake(pdev, PCI_D0, 0);
3848
3849 err = skge_reset(hw);
3850 if (err)
3851 goto out;
3852
3853 for (i = 0; i < hw->ports; i++) {
3854 struct net_device *dev = hw->dev[i];
3855
3856 if (netif_running(dev)) {
3857 err = skge_up(dev);
3858
3859 if (err) {
3860 printk(KERN_ERR PFX "%s: could not up: %d\n",
3861 dev->name, err);
3862 dev_close(dev);
3863 goto out;
3864 }
3865 }
3866 }
3867 out:
3868 return err;
3869 }
3870 #endif
3871
3872 static void skge_shutdown(struct pci_dev *pdev)
3873 {
3874 struct skge_hw *hw = pci_get_drvdata(pdev);
3875 int i, wol = 0;
3876
3877 if (!hw)
3878 return;
3879
3880 for (i = 0; i < hw->ports; i++) {
3881 struct net_device *dev = hw->dev[i];
3882 struct skge_port *skge = netdev_priv(dev);
3883
3884 if (skge->wol)
3885 skge_wol_init(skge);
3886 wol |= skge->wol;
3887 }
3888
3889 pci_enable_wake(pdev, PCI_D3hot, wol);
3890 pci_enable_wake(pdev, PCI_D3cold, wol);
3891
3892 pci_disable_device(pdev);
3893 pci_set_power_state(pdev, PCI_D3hot);
3894
3895 }
3896
3897 static struct pci_driver skge_driver = {
3898 .name = DRV_NAME,
3899 .id_table = skge_id_table,
3900 .probe = skge_probe,
3901 .remove = __devexit_p(skge_remove),
3902 #ifdef CONFIG_PM
3903 .suspend = skge_suspend,
3904 .resume = skge_resume,
3905 #endif
3906 .shutdown = skge_shutdown,
3907 };
3908
3909 static int __init skge_init_module(void)
3910 {
3911 return pci_register_driver(&skge_driver);
3912 }
3913
3914 static void __exit skge_cleanup_module(void)
3915 {
3916 pci_unregister_driver(&skge_driver);
3917 }
3918
3919 module_init(skge_init_module);
3920 module_exit(skge_cleanup_module);
Verdex Pro support