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[TCP]: TCP_CONG_YEAH requires TCP_CONG_VEGAS
[linux-2.6/verdex.git] / drivers / net / sky2.c
blob104e20456e6f4bc64a076380a40aae460f9333e2
1 /*
2 * New driver for Marvell Yukon 2 chipset.
3 * Based on earlier sk98lin, and skge driver.
4 *
5 * This driver intentionally does not support all the features
6 * of the original driver such as link fail-over and link management because
7 * those should be done at higher levels.
8 *
9 * Copyright (C) 2005 Stephen Hemminger <shemminger@osdl.org>
10 *
11 * This program is free software; you can redistribute it and/or modify
12 * it under the terms of the GNU General Public License as published by
13 * the Free Software Foundation; either version 2 of the License.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 */
24
25 #include <linux/crc32.h>
26 #include <linux/kernel.h>
27 #include <linux/version.h>
28 #include <linux/module.h>
29 #include <linux/netdevice.h>
30 #include <linux/dma-mapping.h>
31 #include <linux/etherdevice.h>
32 #include <linux/ethtool.h>
33 #include <linux/pci.h>
34 #include <linux/ip.h>
35 #include <net/ip.h>
36 #include <linux/tcp.h>
37 #include <linux/in.h>
38 #include <linux/delay.h>
39 #include <linux/workqueue.h>
40 #include <linux/if_vlan.h>
41 #include <linux/prefetch.h>
42 #include <linux/mii.h>
43 #include <linux/dmi.h>
44
45 #include <asm/irq.h>
46
47 #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
48 #define SKY2_VLAN_TAG_USED 1
49 #endif
50
51 #include "sky2.h"
52
53 #define DRV_NAME "sky2"
54 #define DRV_VERSION "1.14"
55 #define PFX DRV_NAME " "
56
57 /*
58 * The Yukon II chipset takes 64 bit command blocks (called list elements)
59 * that are organized into three (receive, transmit, status) different rings
60 * similar to Tigon3.
61 */
62
63 #define RX_LE_SIZE 1024
64 #define RX_LE_BYTES (RX_LE_SIZE*sizeof(struct sky2_rx_le))
65 #define RX_MAX_PENDING (RX_LE_SIZE/6 - 2)
66 #define RX_DEF_PENDING RX_MAX_PENDING
67 #define RX_SKB_ALIGN 8
68 #define RX_BUF_WRITE 16
69
70 #define TX_RING_SIZE 512
71 #define TX_DEF_PENDING (TX_RING_SIZE - 1)
72 #define TX_MIN_PENDING 64
73 #define MAX_SKB_TX_LE (4 + (sizeof(dma_addr_t)/sizeof(u32))*MAX_SKB_FRAGS)
74
75 #define STATUS_RING_SIZE 2048 /* 2 ports * (TX + 2*RX) */
76 #define STATUS_LE_BYTES (STATUS_RING_SIZE*sizeof(struct sky2_status_le))
77 #define TX_WATCHDOG (5 * HZ)
78 #define NAPI_WEIGHT 64
79 #define PHY_RETRIES 1000
80
81 #define RING_NEXT(x,s) (((x)+1) & ((s)-1))
82
83 static const u32 default_msg =
84 NETIF_MSG_DRV | NETIF_MSG_PROBE | NETIF_MSG_LINK
85 | NETIF_MSG_TIMER | NETIF_MSG_TX_ERR | NETIF_MSG_RX_ERR
86 | NETIF_MSG_IFUP | NETIF_MSG_IFDOWN;
87
88 static int debug = -1; /* defaults above */
89 module_param(debug, int, 0);
90 MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all)");
91
92 static int copybreak __read_mostly = 128;
93 module_param(copybreak, int, 0);
94 MODULE_PARM_DESC(copybreak, "Receive copy threshold");
95
96 static int disable_msi = 0;
97 module_param(disable_msi, int, 0);
98 MODULE_PARM_DESC(disable_msi, "Disable Message Signaled Interrupt (MSI)");
99
100 static int idle_timeout = 0;
101 module_param(idle_timeout, int, 0);
102 MODULE_PARM_DESC(idle_timeout, "Watchdog timer for lost interrupts (ms)");
103
104 static const struct pci_device_id sky2_id_table[] = {
105 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9000) }, /* SK-9Sxx */
106 { PCI_DEVICE(PCI_VENDOR_ID_SYSKONNECT, 0x9E00) }, /* SK-9Exx */
107 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4b00) }, /* DGE-560T */
108 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4001) }, /* DGE-550SX */
109 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B02) }, /* DGE-560SX */
110 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x4B03) }, /* DGE-550T */
111 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4340) }, /* 88E8021 */
112 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4341) }, /* 88E8022 */
113 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4342) }, /* 88E8061 */
114 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4343) }, /* 88E8062 */
115 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4344) }, /* 88E8021 */
116 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4345) }, /* 88E8022 */
117 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4346) }, /* 88E8061 */
118 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4347) }, /* 88E8062 */
119 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4350) }, /* 88E8035 */
120 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4351) }, /* 88E8036 */
121 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4352) }, /* 88E8038 */
122 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4353) }, /* 88E8039 */
123 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4356) }, /* 88EC033 */
124 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4360) }, /* 88E8052 */
125 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4361) }, /* 88E8050 */
126 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4362) }, /* 88E8053 */
127 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4363) }, /* 88E8055 */
128 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4364) }, /* 88E8056 */
129 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4366) }, /* 88EC036 */
130 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4367) }, /* 88EC032 */
131 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4368) }, /* 88EC034 */
132 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x4369) }, /* 88EC042 */
133 { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436A) }, /* 88E8058 */
134 // { PCI_DEVICE(PCI_VENDOR_ID_MARVELL, 0x436B) }, /* 88E8071 */
135 { 0 }
136 };
137
138 MODULE_DEVICE_TABLE(pci, sky2_id_table);
139
140 /* Avoid conditionals by using array */
141 static const unsigned txqaddr[] = { Q_XA1, Q_XA2 };
142 static const unsigned rxqaddr[] = { Q_R1, Q_R2 };
143 static const u32 portirq_msk[] = { Y2_IS_PORT_1, Y2_IS_PORT_2 };
144
145 /* This driver supports yukon2 chipset only */
146 static const char *yukon2_name[] = {
147 "XL", /* 0xb3 */
148 "EC Ultra", /* 0xb4 */
149 "Extreme", /* 0xb5 */
150 "EC", /* 0xb6 */
151 "FE", /* 0xb7 */
152 };
153
154 static int dmi_blacklisted;
155
156 /* Access to external PHY */
157 static int gm_phy_write(struct sky2_hw *hw, unsigned port, u16 reg, u16 val)
158 {
159 int i;
160
161 gma_write16(hw, port, GM_SMI_DATA, val);
162 gma_write16(hw, port, GM_SMI_CTRL,
163 GM_SMI_CT_PHY_AD(PHY_ADDR_MARV) | GM_SMI_CT_REG_AD(reg));
164
165 for (i = 0; i < PHY_RETRIES; i++) {
166 if (!(gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_BUSY))
167 return 0;
168 udelay(1);
169 }
170
171 printk(KERN_WARNING PFX "%s: phy write timeout\n", hw->dev[port]->name);
172 return -ETIMEDOUT;
173 }
174
175 static int __gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg, u16 *val)
176 {
177 int i;
178
179 gma_write16(hw, port, GM_SMI_CTRL, GM_SMI_CT_PHY_AD(PHY_ADDR_MARV)
180 | GM_SMI_CT_REG_AD(reg) | GM_SMI_CT_OP_RD);
181
182 for (i = 0; i < PHY_RETRIES; i++) {
183 if (gma_read16(hw, port, GM_SMI_CTRL) & GM_SMI_CT_RD_VAL) {
184 *val = gma_read16(hw, port, GM_SMI_DATA);
185 return 0;
186 }
187
188 udelay(1);
189 }
190
191 return -ETIMEDOUT;
192 }
193
194 static u16 gm_phy_read(struct sky2_hw *hw, unsigned port, u16 reg)
195 {
196 u16 v;
197
198 if (__gm_phy_read(hw, port, reg, &v) != 0)
199 printk(KERN_WARNING PFX "%s: phy read timeout\n", hw->dev[port]->name);
200 return v;
201 }
202
203
204 static void sky2_power_on(struct sky2_hw *hw)
205 {
206 /* switch power to VCC (WA for VAUX problem) */
207 sky2_write8(hw, B0_POWER_CTRL,
208 PC_VAUX_ENA | PC_VCC_ENA | PC_VAUX_OFF | PC_VCC_ON);
209
210 /* disable Core Clock Division, */
211 sky2_write32(hw, B2_Y2_CLK_CTRL, Y2_CLK_DIV_DIS);
212
213 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
214 /* enable bits are inverted */
215 sky2_write8(hw, B2_Y2_CLK_GATE,
216 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
217 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
218 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
219 else
220 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
221
222 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
223 u32 reg1;
224
225 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
226 reg1 = sky2_pci_read32(hw, PCI_DEV_REG4);
227 reg1 &= P_ASPM_CONTROL_MSK;
228 sky2_pci_write32(hw, PCI_DEV_REG4, reg1);
229 sky2_pci_write32(hw, PCI_DEV_REG5, 0);
230 }
231 }
232
233 static void sky2_power_aux(struct sky2_hw *hw)
234 {
235 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
236 sky2_write8(hw, B2_Y2_CLK_GATE, 0);
237 else
238 /* enable bits are inverted */
239 sky2_write8(hw, B2_Y2_CLK_GATE,
240 Y2_PCI_CLK_LNK1_DIS | Y2_COR_CLK_LNK1_DIS |
241 Y2_CLK_GAT_LNK1_DIS | Y2_PCI_CLK_LNK2_DIS |
242 Y2_COR_CLK_LNK2_DIS | Y2_CLK_GAT_LNK2_DIS);
243
244 /* switch power to VAUX */
245 if (sky2_read16(hw, B0_CTST) & Y2_VAUX_AVAIL)
246 sky2_write8(hw, B0_POWER_CTRL,
247 (PC_VAUX_ENA | PC_VCC_ENA |
248 PC_VAUX_ON | PC_VCC_OFF));
249 }
250
251 static void sky2_gmac_reset(struct sky2_hw *hw, unsigned port)
252 {
253 u16 reg;
254
255 /* disable all GMAC IRQ's */
256 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), 0);
257 /* disable PHY IRQs */
258 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
259
260 gma_write16(hw, port, GM_MC_ADDR_H1, 0); /* clear MC hash */
261 gma_write16(hw, port, GM_MC_ADDR_H2, 0);
262 gma_write16(hw, port, GM_MC_ADDR_H3, 0);
263 gma_write16(hw, port, GM_MC_ADDR_H4, 0);
264
265 reg = gma_read16(hw, port, GM_RX_CTRL);
266 reg |= GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA;
267 gma_write16(hw, port, GM_RX_CTRL, reg);
268 }
269
270 /* flow control to advertise bits */
271 static const u16 copper_fc_adv[] = {
272 [FC_NONE] = 0,
273 [FC_TX] = PHY_M_AN_ASP,
274 [FC_RX] = PHY_M_AN_PC,
275 [FC_BOTH] = PHY_M_AN_PC | PHY_M_AN_ASP,
276 };
277
278 /* flow control to advertise bits when using 1000BaseX */
279 static const u16 fiber_fc_adv[] = {
280 [FC_BOTH] = PHY_M_P_BOTH_MD_X,
281 [FC_TX] = PHY_M_P_ASYM_MD_X,
282 [FC_RX] = PHY_M_P_SYM_MD_X,
283 [FC_NONE] = PHY_M_P_NO_PAUSE_X,
284 };
285
286 /* flow control to GMA disable bits */
287 static const u16 gm_fc_disable[] = {
288 [FC_NONE] = GM_GPCR_FC_RX_DIS | GM_GPCR_FC_TX_DIS,
289 [FC_TX] = GM_GPCR_FC_RX_DIS,
290 [FC_RX] = GM_GPCR_FC_TX_DIS,
291 [FC_BOTH] = 0,
292 };
293
294
295 static void sky2_phy_init(struct sky2_hw *hw, unsigned port)
296 {
297 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
298 u16 ctrl, ct1000, adv, pg, ledctrl, ledover, reg;
299
300 if (sky2->autoneg == AUTONEG_ENABLE
301 && !(hw->chip_id == CHIP_ID_YUKON_XL
302 || hw->chip_id == CHIP_ID_YUKON_EC_U
303 || hw->chip_id == CHIP_ID_YUKON_EX)) {
304 u16 ectrl = gm_phy_read(hw, port, PHY_MARV_EXT_CTRL);
305
306 ectrl &= ~(PHY_M_EC_M_DSC_MSK | PHY_M_EC_S_DSC_MSK |
307 PHY_M_EC_MAC_S_MSK);
308 ectrl |= PHY_M_EC_MAC_S(MAC_TX_CLK_25_MHZ);
309
310 if (hw->chip_id == CHIP_ID_YUKON_EC)
311 ectrl |= PHY_M_EC_DSC_2(2) | PHY_M_EC_DOWN_S_ENA;
312 else
313 ectrl |= PHY_M_EC_M_DSC(2) | PHY_M_EC_S_DSC(3);
314
315 gm_phy_write(hw, port, PHY_MARV_EXT_CTRL, ectrl);
316 }
317
318 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
319 if (sky2_is_copper(hw)) {
320 if (hw->chip_id == CHIP_ID_YUKON_FE) {
321 /* enable automatic crossover */
322 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO) >> 1;
323 } else {
324 /* disable energy detect */
325 ctrl &= ~PHY_M_PC_EN_DET_MSK;
326
327 /* enable automatic crossover */
328 ctrl |= PHY_M_PC_MDI_XMODE(PHY_M_PC_ENA_AUTO);
329
330 if (sky2->autoneg == AUTONEG_ENABLE
331 && (hw->chip_id == CHIP_ID_YUKON_XL
332 || hw->chip_id == CHIP_ID_YUKON_EC_U
333 || hw->chip_id == CHIP_ID_YUKON_EX)) {
334 ctrl &= ~PHY_M_PC_DSC_MSK;
335 ctrl |= PHY_M_PC_DSC(2) | PHY_M_PC_DOWN_S_ENA;
336 }
337 }
338 } else {
339 /* workaround for deviation #4.88 (CRC errors) */
340 /* disable Automatic Crossover */
341
342 ctrl &= ~PHY_M_PC_MDIX_MSK;
343 }
344
345 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
346
347 /* special setup for PHY 88E1112 Fiber */
348 if (hw->chip_id == CHIP_ID_YUKON_XL && !sky2_is_copper(hw)) {
349 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
350
351 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */
352 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 2);
353 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
354 ctrl &= ~PHY_M_MAC_MD_MSK;
355 ctrl |= PHY_M_MAC_MODE_SEL(PHY_M_MAC_MD_1000BX);
356 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ctrl);
357
358 if (hw->pmd_type == 'P') {
359 /* select page 1 to access Fiber registers */
360 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 1);
361
362 /* for SFP-module set SIGDET polarity to low */
363 ctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
364 ctrl |= PHY_M_FIB_SIGD_POL;
365 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
366 }
367
368 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
369 }
370
371 ctrl = PHY_CT_RESET;
372 ct1000 = 0;
373 adv = PHY_AN_CSMA;
374 reg = 0;
375
376 if (sky2->autoneg == AUTONEG_ENABLE) {
377 if (sky2_is_copper(hw)) {
378 if (sky2->advertising & ADVERTISED_1000baseT_Full)
379 ct1000 |= PHY_M_1000C_AFD;
380 if (sky2->advertising & ADVERTISED_1000baseT_Half)
381 ct1000 |= PHY_M_1000C_AHD;
382 if (sky2->advertising & ADVERTISED_100baseT_Full)
383 adv |= PHY_M_AN_100_FD;
384 if (sky2->advertising & ADVERTISED_100baseT_Half)
385 adv |= PHY_M_AN_100_HD;
386 if (sky2->advertising & ADVERTISED_10baseT_Full)
387 adv |= PHY_M_AN_10_FD;
388 if (sky2->advertising & ADVERTISED_10baseT_Half)
389 adv |= PHY_M_AN_10_HD;
390
391 adv |= copper_fc_adv[sky2->flow_mode];
392 } else { /* special defines for FIBER (88E1040S only) */
393 if (sky2->advertising & ADVERTISED_1000baseT_Full)
394 adv |= PHY_M_AN_1000X_AFD;
395 if (sky2->advertising & ADVERTISED_1000baseT_Half)
396 adv |= PHY_M_AN_1000X_AHD;
397
398 adv |= fiber_fc_adv[sky2->flow_mode];
399 }
400
401 /* Restart Auto-negotiation */
402 ctrl |= PHY_CT_ANE | PHY_CT_RE_CFG;
403 } else {
404 /* forced speed/duplex settings */
405 ct1000 = PHY_M_1000C_MSE;
406
407 /* Disable auto update for duplex flow control and speed */
408 reg |= GM_GPCR_AU_ALL_DIS;
409
410 switch (sky2->speed) {
411 case SPEED_1000:
412 ctrl |= PHY_CT_SP1000;
413 reg |= GM_GPCR_SPEED_1000;
414 break;
415 case SPEED_100:
416 ctrl |= PHY_CT_SP100;
417 reg |= GM_GPCR_SPEED_100;
418 break;
419 }
420
421 if (sky2->duplex == DUPLEX_FULL) {
422 reg |= GM_GPCR_DUP_FULL;
423 ctrl |= PHY_CT_DUP_MD;
424 } else if (sky2->speed < SPEED_1000)
425 sky2->flow_mode = FC_NONE;
426
427
428 reg |= gm_fc_disable[sky2->flow_mode];
429
430 /* Forward pause packets to GMAC? */
431 if (sky2->flow_mode & FC_RX)
432 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
433 else
434 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
435 }
436
437 gma_write16(hw, port, GM_GP_CTRL, reg);
438
439 if (hw->chip_id != CHIP_ID_YUKON_FE)
440 gm_phy_write(hw, port, PHY_MARV_1000T_CTRL, ct1000);
441
442 gm_phy_write(hw, port, PHY_MARV_AUNE_ADV, adv);
443 gm_phy_write(hw, port, PHY_MARV_CTRL, ctrl);
444
445 /* Setup Phy LED's */
446 ledctrl = PHY_M_LED_PULS_DUR(PULS_170MS);
447 ledover = 0;
448
449 switch (hw->chip_id) {
450 case CHIP_ID_YUKON_FE:
451 /* on 88E3082 these bits are at 11..9 (shifted left) */
452 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) << 1;
453
454 ctrl = gm_phy_read(hw, port, PHY_MARV_FE_LED_PAR);
455
456 /* delete ACT LED control bits */
457 ctrl &= ~PHY_M_FELP_LED1_MSK;
458 /* change ACT LED control to blink mode */
459 ctrl |= PHY_M_FELP_LED1_CTRL(LED_PAR_CTRL_ACT_BL);
460 gm_phy_write(hw, port, PHY_MARV_FE_LED_PAR, ctrl);
461 break;
462
463 case CHIP_ID_YUKON_XL:
464 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
465
466 /* select page 3 to access LED control register */
467 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
468
469 /* set LED Function Control register */
470 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
471 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
472 PHY_M_LEDC_INIT_CTRL(7) | /* 10 Mbps */
473 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
474 PHY_M_LEDC_STA0_CTRL(7))); /* 1000 Mbps */
475
476 /* set Polarity Control register */
477 gm_phy_write(hw, port, PHY_MARV_PHY_STAT,
478 (PHY_M_POLC_LS1_P_MIX(4) |
479 PHY_M_POLC_IS0_P_MIX(4) |
480 PHY_M_POLC_LOS_CTRL(2) |
481 PHY_M_POLC_INIT_CTRL(2) |
482 PHY_M_POLC_STA1_CTRL(2) |
483 PHY_M_POLC_STA0_CTRL(2)));
484
485 /* restore page register */
486 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
487 break;
488
489 case CHIP_ID_YUKON_EC_U:
490 case CHIP_ID_YUKON_EX:
491 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
492
493 /* select page 3 to access LED control register */
494 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
495
496 /* set LED Function Control register */
497 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
498 (PHY_M_LEDC_LOS_CTRL(1) | /* LINK/ACT */
499 PHY_M_LEDC_INIT_CTRL(8) | /* 10 Mbps */
500 PHY_M_LEDC_STA1_CTRL(7) | /* 100 Mbps */
501 PHY_M_LEDC_STA0_CTRL(7)));/* 1000 Mbps */
502
503 /* set Blink Rate in LED Timer Control Register */
504 gm_phy_write(hw, port, PHY_MARV_INT_MASK,
505 ledctrl | PHY_M_LED_BLINK_RT(BLINK_84MS));
506 /* restore page register */
507 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
508 break;
509
510 default:
511 /* set Tx LED (LED_TX) to blink mode on Rx OR Tx activity */
512 ledctrl |= PHY_M_LED_BLINK_RT(BLINK_84MS) | PHY_M_LEDC_TX_CTRL;
513 /* turn off the Rx LED (LED_RX) */
514 ledover &= ~PHY_M_LED_MO_RX;
515 }
516
517 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
518 hw->chip_rev == CHIP_REV_YU_EC_U_A1) {
519 /* apply fixes in PHY AFE */
520 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 255);
521
522 /* increase differential signal amplitude in 10BASE-T */
523 gm_phy_write(hw, port, 0x18, 0xaa99);
524 gm_phy_write(hw, port, 0x17, 0x2011);
525
526 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */
527 gm_phy_write(hw, port, 0x18, 0xa204);
528 gm_phy_write(hw, port, 0x17, 0x2002);
529
530 /* set page register to 0 */
531 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 0);
532 } else if (hw->chip_id != CHIP_ID_YUKON_EX) {
533 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
534
535 if (sky2->autoneg == AUTONEG_DISABLE || sky2->speed == SPEED_100) {
536 /* turn on 100 Mbps LED (LED_LINK100) */
537 ledover |= PHY_M_LED_MO_100;
538 }
539
540 if (ledover)
541 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
542
543 }
544
545 /* Enable phy interrupt on auto-negotiation complete (or link up) */
546 if (sky2->autoneg == AUTONEG_ENABLE)
547 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_IS_AN_COMPL);
548 else
549 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
550 }
551
552 static void sky2_phy_power(struct sky2_hw *hw, unsigned port, int onoff)
553 {
554 u32 reg1;
555 static const u32 phy_power[]
556 = { PCI_Y2_PHY1_POWD, PCI_Y2_PHY2_POWD };
557
558 /* looks like this XL is back asswards .. */
559 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev > 1)
560 onoff = !onoff;
561
562 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
563 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
564 if (onoff)
565 /* Turn off phy power saving */
566 reg1 &= ~phy_power[port];
567 else
568 reg1 |= phy_power[port];
569
570 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
571 sky2_pci_read32(hw, PCI_DEV_REG1);
572 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
573 udelay(100);
574 }
575
576 /* Force a renegotiation */
577 static void sky2_phy_reinit(struct sky2_port *sky2)
578 {
579 spin_lock_bh(&sky2->phy_lock);
580 sky2_phy_init(sky2->hw, sky2->port);
581 spin_unlock_bh(&sky2->phy_lock);
582 }
583
584 /* Put device in state to listen for Wake On Lan */
585 static void sky2_wol_init(struct sky2_port *sky2)
586 {
587 struct sky2_hw *hw = sky2->hw;
588 unsigned port = sky2->port;
589 enum flow_control save_mode;
590 u16 ctrl;
591 u32 reg1;
592
593 /* Bring hardware out of reset */
594 sky2_write16(hw, B0_CTST, CS_RST_CLR);
595 sky2_write16(hw, SK_REG(port, GMAC_LINK_CTRL), GMLC_RST_CLR);
596
597 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR);
598 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
599
600 /* Force to 10/100
601 * sky2_reset will re-enable on resume
602 */
603 save_mode = sky2->flow_mode;
604 ctrl = sky2->advertising;
605
606 sky2->advertising &= ~(ADVERTISED_1000baseT_Half|ADVERTISED_1000baseT_Full);
607 sky2->flow_mode = FC_NONE;
608 sky2_phy_power(hw, port, 1);
609 sky2_phy_reinit(sky2);
610
611 sky2->flow_mode = save_mode;
612 sky2->advertising = ctrl;
613
614 /* Set GMAC to no flow control and auto update for speed/duplex */
615 gma_write16(hw, port, GM_GP_CTRL,
616 GM_GPCR_FC_TX_DIS|GM_GPCR_TX_ENA|GM_GPCR_RX_ENA|
617 GM_GPCR_DUP_FULL|GM_GPCR_FC_RX_DIS|GM_GPCR_AU_FCT_DIS);
618
619 /* Set WOL address */
620 memcpy_toio(hw->regs + WOL_REGS(port, WOL_MAC_ADDR),
621 sky2->netdev->dev_addr, ETH_ALEN);
622
623 /* Turn on appropriate WOL control bits */
624 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), WOL_CTL_CLEAR_RESULT);
625 ctrl = 0;
626 if (sky2->wol & WAKE_PHY)
627 ctrl |= WOL_CTL_ENA_PME_ON_LINK_CHG|WOL_CTL_ENA_LINK_CHG_UNIT;
628 else
629 ctrl |= WOL_CTL_DIS_PME_ON_LINK_CHG|WOL_CTL_DIS_LINK_CHG_UNIT;
630
631 if (sky2->wol & WAKE_MAGIC)
632 ctrl |= WOL_CTL_ENA_PME_ON_MAGIC_PKT|WOL_CTL_ENA_MAGIC_PKT_UNIT;
633 else
634 ctrl |= WOL_CTL_DIS_PME_ON_MAGIC_PKT|WOL_CTL_DIS_MAGIC_PKT_UNIT;;
635
636 ctrl |= WOL_CTL_DIS_PME_ON_PATTERN|WOL_CTL_DIS_PATTERN_UNIT;
637 sky2_write16(hw, WOL_REGS(port, WOL_CTRL_STAT), ctrl);
638
639 /* Turn on legacy PCI-Express PME mode */
640 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
641 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1);
642 reg1 |= PCI_Y2_PME_LEGACY;
643 sky2_pci_write32(hw, PCI_DEV_REG1, reg1);
644 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
645
646 /* block receiver */
647 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
648
649 }
650
651 static void sky2_mac_init(struct sky2_hw *hw, unsigned port)
652 {
653 struct sky2_port *sky2 = netdev_priv(hw->dev[port]);
654 u16 reg;
655 int i;
656 const u8 *addr = hw->dev[port]->dev_addr;
657
658 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
659 sky2_write32(hw, SK_REG(port, GPHY_CTRL), GPC_RST_CLR|GPC_ENA_PAUSE);
660
661 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_CLR);
662
663 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0 && port == 1) {
664 /* WA DEV_472 -- looks like crossed wires on port 2 */
665 /* clear GMAC 1 Control reset */
666 sky2_write8(hw, SK_REG(0, GMAC_CTRL), GMC_RST_CLR);
667 do {
668 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_SET);
669 sky2_write8(hw, SK_REG(1, GMAC_CTRL), GMC_RST_CLR);
670 } while (gm_phy_read(hw, 1, PHY_MARV_ID0) != PHY_MARV_ID0_VAL ||
671 gm_phy_read(hw, 1, PHY_MARV_ID1) != PHY_MARV_ID1_Y2 ||
672 gm_phy_read(hw, 1, PHY_MARV_INT_MASK) != 0);
673 }
674
675 sky2_read16(hw, SK_REG(port, GMAC_IRQ_SRC));
676
677 /* Enable Transmit FIFO Underrun */
678 sky2_write8(hw, SK_REG(port, GMAC_IRQ_MSK), GMAC_DEF_MSK);
679
680 spin_lock_bh(&sky2->phy_lock);
681 sky2_phy_init(hw, port);
682 spin_unlock_bh(&sky2->phy_lock);
683
684 /* MIB clear */
685 reg = gma_read16(hw, port, GM_PHY_ADDR);
686 gma_write16(hw, port, GM_PHY_ADDR, reg | GM_PAR_MIB_CLR);
687
688 for (i = GM_MIB_CNT_BASE; i <= GM_MIB_CNT_END; i += 4)
689 gma_read16(hw, port, i);
690 gma_write16(hw, port, GM_PHY_ADDR, reg);
691
692 /* transmit control */
693 gma_write16(hw, port, GM_TX_CTRL, TX_COL_THR(TX_COL_DEF));
694
695 /* receive control reg: unicast + multicast + no FCS */
696 gma_write16(hw, port, GM_RX_CTRL,
697 GM_RXCR_UCF_ENA | GM_RXCR_CRC_DIS | GM_RXCR_MCF_ENA);
698
699 /* transmit flow control */
700 gma_write16(hw, port, GM_TX_FLOW_CTRL, 0xffff);
701
702 /* transmit parameter */
703 gma_write16(hw, port, GM_TX_PARAM,
704 TX_JAM_LEN_VAL(TX_JAM_LEN_DEF) |
705 TX_JAM_IPG_VAL(TX_JAM_IPG_DEF) |
706 TX_IPG_JAM_DATA(TX_IPG_JAM_DEF) |
707 TX_BACK_OFF_LIM(TX_BOF_LIM_DEF));
708
709 /* serial mode register */
710 reg = DATA_BLIND_VAL(DATA_BLIND_DEF) |
711 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
712
713 if (hw->dev[port]->mtu > ETH_DATA_LEN)
714 reg |= GM_SMOD_JUMBO_ENA;
715
716 gma_write16(hw, port, GM_SERIAL_MODE, reg);
717
718 /* virtual address for data */
719 gma_set_addr(hw, port, GM_SRC_ADDR_2L, addr);
720
721 /* physical address: used for pause frames */
722 gma_set_addr(hw, port, GM_SRC_ADDR_1L, addr);
723
724 /* ignore counter overflows */
725 gma_write16(hw, port, GM_TX_IRQ_MSK, 0);
726 gma_write16(hw, port, GM_RX_IRQ_MSK, 0);
727 gma_write16(hw, port, GM_TR_IRQ_MSK, 0);
728
729 /* Configure Rx MAC FIFO */
730 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_CLR);
731 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T),
732 GMF_OPER_ON | GMF_RX_F_FL_ON);
733
734 /* Flush Rx MAC FIFO on any flow control or error */
735 sky2_write16(hw, SK_REG(port, RX_GMF_FL_MSK), GMR_FS_ANY_ERR);
736
737 /* Set threshold to 0xa (64 bytes) + 1 to workaround pause bug */
738 sky2_write16(hw, SK_REG(port, RX_GMF_FL_THR), RX_GMF_FL_THR_DEF+1);
739
740 /* Configure Tx MAC FIFO */
741 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_CLR);
742 sky2_write16(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_OPER_ON);
743
744 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
745 sky2_write8(hw, SK_REG(port, RX_GMF_LP_THR), 768/8);
746 sky2_write8(hw, SK_REG(port, RX_GMF_UP_THR), 1024/8);
747
748 /* set Tx GMAC FIFO Almost Empty Threshold */
749 sky2_write32(hw, SK_REG(port, TX_GMF_AE_THR),
750 (ECU_JUMBO_WM << 16) | ECU_AE_THR);
751
752 if (hw->dev[port]->mtu > ETH_DATA_LEN)
753 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
754 TX_JUMBO_ENA | TX_STFW_DIS);
755 else
756 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
757 TX_JUMBO_DIS | TX_STFW_ENA);
758 }
759
760 }
761
762 /* Assign Ram Buffer allocation to queue */
763 static void sky2_ramset(struct sky2_hw *hw, u16 q, u32 start, u32 space)
764 {
765 u32 end;
766
767 /* convert from K bytes to qwords used for hw register */
768 start *= 1024/8;
769 space *= 1024/8;
770 end = start + space - 1;
771
772 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_RST_CLR);
773 sky2_write32(hw, RB_ADDR(q, RB_START), start);
774 sky2_write32(hw, RB_ADDR(q, RB_END), end);
775 sky2_write32(hw, RB_ADDR(q, RB_WP), start);
776 sky2_write32(hw, RB_ADDR(q, RB_RP), start);
777
778 if (q == Q_R1 || q == Q_R2) {
779 u32 tp = space - space/4;
780
781 /* On receive queue's set the thresholds
782 * give receiver priority when > 3/4 full
783 * send pause when down to 2K
784 */
785 sky2_write32(hw, RB_ADDR(q, RB_RX_UTHP), tp);
786 sky2_write32(hw, RB_ADDR(q, RB_RX_LTHP), space/2);
787
788 tp = space - 2048/8;
789 sky2_write32(hw, RB_ADDR(q, RB_RX_UTPP), tp);
790 sky2_write32(hw, RB_ADDR(q, RB_RX_LTPP), space/4);
791 } else {
792 /* Enable store & forward on Tx queue's because
793 * Tx FIFO is only 1K on Yukon
794 */
795 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_STFWD);
796 }
797
798 sky2_write8(hw, RB_ADDR(q, RB_CTRL), RB_ENA_OP_MD);
799 sky2_read8(hw, RB_ADDR(q, RB_CTRL));
800 }
801
802 /* Setup Bus Memory Interface */
803 static void sky2_qset(struct sky2_hw *hw, u16 q)
804 {
805 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_RESET);
806 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_OPER_INIT);
807 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_FIFO_OP_ON);
808 sky2_write32(hw, Q_ADDR(q, Q_WM), BMU_WM_DEFAULT);
809 }
810
811 /* Setup prefetch unit registers. This is the interface between
812 * hardware and driver list elements
813 */
814 static void sky2_prefetch_init(struct sky2_hw *hw, u32 qaddr,
815 u64 addr, u32 last)
816 {
817 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
818 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_RST_CLR);
819 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_HI), addr >> 32);
820 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_ADDR_LO), (u32) addr);
821 sky2_write16(hw, Y2_QADDR(qaddr, PREF_UNIT_LAST_IDX), last);
822 sky2_write32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL), PREF_UNIT_OP_ON);
823
824 sky2_read32(hw, Y2_QADDR(qaddr, PREF_UNIT_CTRL));
825 }
826
827 static inline struct sky2_tx_le *get_tx_le(struct sky2_port *sky2)
828 {
829 struct sky2_tx_le *le = sky2->tx_le + sky2->tx_prod;
830
831 sky2->tx_prod = RING_NEXT(sky2->tx_prod, TX_RING_SIZE);
832 le->ctrl = 0;
833 return le;
834 }
835
836 static inline struct tx_ring_info *tx_le_re(struct sky2_port *sky2,
837 struct sky2_tx_le *le)
838 {
839 return sky2->tx_ring + (le - sky2->tx_le);
840 }
841
842 /* Update chip's next pointer */
843 static inline void sky2_put_idx(struct sky2_hw *hw, unsigned q, u16 idx)
844 {
845 q = Y2_QADDR(q, PREF_UNIT_PUT_IDX);
846 wmb();
847 sky2_write16(hw, q, idx);
848 sky2_read16(hw, q);
849 }
850
851
852 static inline struct sky2_rx_le *sky2_next_rx(struct sky2_port *sky2)
853 {
854 struct sky2_rx_le *le = sky2->rx_le + sky2->rx_put;
855 sky2->rx_put = RING_NEXT(sky2->rx_put, RX_LE_SIZE);
856 le->ctrl = 0;
857 return le;
858 }
859
860 /* Return high part of DMA address (could be 32 or 64 bit) */
861 static inline u32 high32(dma_addr_t a)
862 {
863 return sizeof(a) > sizeof(u32) ? (a >> 16) >> 16 : 0;
864 }
865
866 /* Build description to hardware for one receive segment */
867 static void sky2_rx_add(struct sky2_port *sky2, u8 op,
868 dma_addr_t map, unsigned len)
869 {
870 struct sky2_rx_le *le;
871 u32 hi = high32(map);
872
873 if (sky2->rx_addr64 != hi) {
874 le = sky2_next_rx(sky2);
875 le->addr = cpu_to_le32(hi);
876 le->opcode = OP_ADDR64 | HW_OWNER;
877 sky2->rx_addr64 = high32(map + len);
878 }
879
880 le = sky2_next_rx(sky2);
881 le->addr = cpu_to_le32((u32) map);
882 le->length = cpu_to_le16(len);
883 le->opcode = op | HW_OWNER;
884 }
885
886 /* Build description to hardware for one possibly fragmented skb */
887 static void sky2_rx_submit(struct sky2_port *sky2,
888 const struct rx_ring_info *re)
889 {
890 int i;
891
892 sky2_rx_add(sky2, OP_PACKET, re->data_addr, sky2->rx_data_size);
893
894 for (i = 0; i < skb_shinfo(re->skb)->nr_frags; i++)
895 sky2_rx_add(sky2, OP_BUFFER, re->frag_addr[i], PAGE_SIZE);
896 }
897
898
899 static void sky2_rx_map_skb(struct pci_dev *pdev, struct rx_ring_info *re,
900 unsigned size)
901 {
902 struct sk_buff *skb = re->skb;
903 int i;
904
905 re->data_addr = pci_map_single(pdev, skb->data, size, PCI_DMA_FROMDEVICE);
906 pci_unmap_len_set(re, data_size, size);
907
908 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
909 re->frag_addr[i] = pci_map_page(pdev,
910 skb_shinfo(skb)->frags[i].page,
911 skb_shinfo(skb)->frags[i].page_offset,
912 skb_shinfo(skb)->frags[i].size,
913 PCI_DMA_FROMDEVICE);
914 }
915
916 static void sky2_rx_unmap_skb(struct pci_dev *pdev, struct rx_ring_info *re)
917 {
918 struct sk_buff *skb = re->skb;
919 int i;
920
921 pci_unmap_single(pdev, re->data_addr, pci_unmap_len(re, data_size),
922 PCI_DMA_FROMDEVICE);
923
924 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++)
925 pci_unmap_page(pdev, re->frag_addr[i],
926 skb_shinfo(skb)->frags[i].size,
927 PCI_DMA_FROMDEVICE);
928 }
929
930 /* Tell chip where to start receive checksum.
931 * Actually has two checksums, but set both same to avoid possible byte
932 * order problems.
933 */
934 static void rx_set_checksum(struct sky2_port *sky2)
935 {
936 struct sky2_rx_le *le;
937
938 le = sky2_next_rx(sky2);
939 le->addr = cpu_to_le32((ETH_HLEN << 16) | ETH_HLEN);
940 le->ctrl = 0;
941 le->opcode = OP_TCPSTART | HW_OWNER;
942
943 sky2_write32(sky2->hw,
944 Q_ADDR(rxqaddr[sky2->port], Q_CSR),
945 sky2->rx_csum ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
946
947 }
948
949 /*
950 * The RX Stop command will not work for Yukon-2 if the BMU does not
951 * reach the end of packet and since we can't make sure that we have
952 * incoming data, we must reset the BMU while it is not doing a DMA
953 * transfer. Since it is possible that the RX path is still active,
954 * the RX RAM buffer will be stopped first, so any possible incoming
955 * data will not trigger a DMA. After the RAM buffer is stopped, the
956 * BMU is polled until any DMA in progress is ended and only then it
957 * will be reset.
958 */
959 static void sky2_rx_stop(struct sky2_port *sky2)
960 {
961 struct sky2_hw *hw = sky2->hw;
962 unsigned rxq = rxqaddr[sky2->port];
963 int i;
964
965 /* disable the RAM Buffer receive queue */
966 sky2_write8(hw, RB_ADDR(rxq, RB_CTRL), RB_DIS_OP_MD);
967
968 for (i = 0; i < 0xffff; i++)
969 if (sky2_read8(hw, RB_ADDR(rxq, Q_RSL))
970 == sky2_read8(hw, RB_ADDR(rxq, Q_RL)))
971 goto stopped;
972
973 printk(KERN_WARNING PFX "%s: receiver stop failed\n",
974 sky2->netdev->name);
975 stopped:
976 sky2_write32(hw, Q_ADDR(rxq, Q_CSR), BMU_RST_SET | BMU_FIFO_RST);
977
978 /* reset the Rx prefetch unit */
979 sky2_write32(hw, Y2_QADDR(rxq, PREF_UNIT_CTRL), PREF_UNIT_RST_SET);
980 }
981
982 /* Clean out receive buffer area, assumes receiver hardware stopped */
983 static void sky2_rx_clean(struct sky2_port *sky2)
984 {
985 unsigned i;
986
987 memset(sky2->rx_le, 0, RX_LE_BYTES);
988 for (i = 0; i < sky2->rx_pending; i++) {
989 struct rx_ring_info *re = sky2->rx_ring + i;
990
991 if (re->skb) {
992 sky2_rx_unmap_skb(sky2->hw->pdev, re);
993 kfree_skb(re->skb);
994 re->skb = NULL;
995 }
996 }
997 }
998
999 /* Basic MII support */
1000 static int sky2_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
1001 {
1002 struct mii_ioctl_data *data = if_mii(ifr);
1003 struct sky2_port *sky2 = netdev_priv(dev);
1004 struct sky2_hw *hw = sky2->hw;
1005 int err = -EOPNOTSUPP;
1006
1007 if (!netif_running(dev))
1008 return -ENODEV; /* Phy still in reset */
1009
1010 switch (cmd) {
1011 case SIOCGMIIPHY:
1012 data->phy_id = PHY_ADDR_MARV;
1013
1014 /* fallthru */
1015 case SIOCGMIIREG: {
1016 u16 val = 0;
1017
1018 spin_lock_bh(&sky2->phy_lock);
1019 err = __gm_phy_read(hw, sky2->port, data->reg_num & 0x1f, &val);
1020 spin_unlock_bh(&sky2->phy_lock);
1021
1022 data->val_out = val;
1023 break;
1024 }
1025
1026 case SIOCSMIIREG:
1027 if (!capable(CAP_NET_ADMIN))
1028 return -EPERM;
1029
1030 spin_lock_bh(&sky2->phy_lock);
1031 err = gm_phy_write(hw, sky2->port, data->reg_num & 0x1f,
1032 data->val_in);
1033 spin_unlock_bh(&sky2->phy_lock);
1034 break;
1035 }
1036 return err;
1037 }
1038
1039 #ifdef SKY2_VLAN_TAG_USED
1040 static void sky2_vlan_rx_register(struct net_device *dev, struct vlan_group *grp)
1041 {
1042 struct sky2_port *sky2 = netdev_priv(dev);
1043 struct sky2_hw *hw = sky2->hw;
1044 u16 port = sky2->port;
1045
1046 netif_tx_lock_bh(dev);
1047
1048 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_ON);
1049 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_ON);
1050 sky2->vlgrp = grp;
1051
1052 netif_tx_unlock_bh(dev);
1053 }
1054
1055 static void sky2_vlan_rx_kill_vid(struct net_device *dev, unsigned short vid)
1056 {
1057 struct sky2_port *sky2 = netdev_priv(dev);
1058 struct sky2_hw *hw = sky2->hw;
1059 u16 port = sky2->port;
1060
1061 netif_tx_lock_bh(dev);
1062
1063 sky2_write32(hw, SK_REG(port, RX_GMF_CTRL_T), RX_VLAN_STRIP_OFF);
1064 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T), TX_VLAN_TAG_OFF);
1065 vlan_group_set_device(sky2->vlgrp, vid, NULL);
1066
1067 netif_tx_unlock_bh(dev);
1068 }
1069 #endif
1070
1071 /*
1072 * Allocate an skb for receiving. If the MTU is large enough
1073 * make the skb non-linear with a fragment list of pages.
1074 *
1075 * It appears the hardware has a bug in the FIFO logic that
1076 * cause it to hang if the FIFO gets overrun and the receive buffer
1077 * is not 64 byte aligned. The buffer returned from netdev_alloc_skb is
1078 * aligned except if slab debugging is enabled.
1079 */
1080 static struct sk_buff *sky2_rx_alloc(struct sky2_port *sky2)
1081 {
1082 struct sk_buff *skb;
1083 unsigned long p;
1084 int i;
1085
1086 skb = netdev_alloc_skb(sky2->netdev, sky2->rx_data_size + RX_SKB_ALIGN);
1087 if (!skb)
1088 goto nomem;
1089
1090 p = (unsigned long) skb->data;
1091 skb_reserve(skb, ALIGN(p, RX_SKB_ALIGN) - p);
1092
1093 for (i = 0; i < sky2->rx_nfrags; i++) {
1094 struct page *page = alloc_page(GFP_ATOMIC);
1095
1096 if (!page)
1097 goto free_partial;
1098 skb_fill_page_desc(skb, i, page, 0, PAGE_SIZE);
1099 }
1100
1101 return skb;
1102 free_partial:
1103 kfree_skb(skb);
1104 nomem:
1105 return NULL;
1106 }
1107
1108 /*
1109 * Allocate and setup receiver buffer pool.
1110 * Normal case this ends up creating one list element for skb
1111 * in the receive ring. Worst case if using large MTU and each
1112 * allocation falls on a different 64 bit region, that results
1113 * in 6 list elements per ring entry.
1114 * One element is used for checksum enable/disable, and one
1115 * extra to avoid wrap.
1116 */
1117 static int sky2_rx_start(struct sky2_port *sky2)
1118 {
1119 struct sky2_hw *hw = sky2->hw;
1120 struct rx_ring_info *re;
1121 unsigned rxq = rxqaddr[sky2->port];
1122 unsigned i, size, space, thresh;
1123
1124 sky2->rx_put = sky2->rx_next = 0;
1125 sky2_qset(hw, rxq);
1126
1127 /* On PCI express lowering the watermark gives better performance */
1128 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
1129 sky2_write32(hw, Q_ADDR(rxq, Q_WM), BMU_WM_PEX);
1130
1131 /* These chips have no ram buffer?
1132 * MAC Rx RAM Read is controlled by hardware */
1133 if (hw->chip_id == CHIP_ID_YUKON_EC_U &&
1134 (hw->chip_rev == CHIP_REV_YU_EC_U_A1
1135 || hw->chip_rev == CHIP_REV_YU_EC_U_B0))
1136 sky2_write32(hw, Q_ADDR(rxq, Q_F), F_M_RX_RAM_DIS);
1137
1138 sky2_prefetch_init(hw, rxq, sky2->rx_le_map, RX_LE_SIZE - 1);
1139
1140 rx_set_checksum(sky2);
1141
1142 /* Space needed for frame data + headers rounded up */
1143 size = ALIGN(sky2->netdev->mtu + ETH_HLEN + VLAN_HLEN, 8)
1144 + 8;
1145
1146 /* Stopping point for hardware truncation */
1147 thresh = (size - 8) / sizeof(u32);
1148
1149 /* Account for overhead of skb - to avoid order > 0 allocation */
1150 space = SKB_DATA_ALIGN(size) + NET_SKB_PAD
1151 + sizeof(struct skb_shared_info);
1152
1153 sky2->rx_nfrags = space >> PAGE_SHIFT;
1154 BUG_ON(sky2->rx_nfrags > ARRAY_SIZE(re->frag_addr));
1155
1156 if (sky2->rx_nfrags != 0) {
1157 /* Compute residue after pages */
1158 space = sky2->rx_nfrags << PAGE_SHIFT;
1159
1160 if (space < size)
1161 size -= space;
1162 else
1163 size = 0;
1164
1165 /* Optimize to handle small packets and headers */
1166 if (size < copybreak)
1167 size = copybreak;
1168 if (size < ETH_HLEN)
1169 size = ETH_HLEN;
1170 }
1171 sky2->rx_data_size = size;
1172
1173 /* Fill Rx ring */
1174 for (i = 0; i < sky2->rx_pending; i++) {
1175 re = sky2->rx_ring + i;
1176
1177 re->skb = sky2_rx_alloc(sky2);
1178 if (!re->skb)
1179 goto nomem;
1180
1181 sky2_rx_map_skb(hw->pdev, re, sky2->rx_data_size);
1182 sky2_rx_submit(sky2, re);
1183 }
1184
1185 /*
1186 * The receiver hangs if it receives frames larger than the
1187 * packet buffer. As a workaround, truncate oversize frames, but
1188 * the register is limited to 9 bits, so if you do frames > 2052
1189 * you better get the MTU right!
1190 */
1191 if (thresh > 0x1ff)
1192 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_OFF);
1193 else {
1194 sky2_write16(hw, SK_REG(sky2->port, RX_GMF_TR_THR), thresh);
1195 sky2_write32(hw, SK_REG(sky2->port, RX_GMF_CTRL_T), RX_TRUNC_ON);
1196 }
1197
1198 /* Tell chip about available buffers */
1199 sky2_write16(hw, Y2_QADDR(rxq, PREF_UNIT_PUT_IDX), sky2->rx_put);
1200 return 0;
1201 nomem:
1202 sky2_rx_clean(sky2);
1203 return -ENOMEM;
1204 }
1205
1206 /* Bring up network interface. */
1207 static int sky2_up(struct net_device *dev)
1208 {
1209 struct sky2_port *sky2 = netdev_priv(dev);
1210 struct sky2_hw *hw = sky2->hw;
1211 unsigned port = sky2->port;
1212 u32 ramsize, imask;
1213 int cap, err = -ENOMEM;
1214 struct net_device *otherdev = hw->dev[sky2->port^1];
1215
1216 /*
1217 * On dual port PCI-X card, there is an problem where status
1218 * can be received out of order due to split transactions
1219 */
1220 if (otherdev && netif_running(otherdev) &&
1221 (cap = pci_find_capability(hw->pdev, PCI_CAP_ID_PCIX))) {
1222 struct sky2_port *osky2 = netdev_priv(otherdev);
1223 u16 cmd;
1224
1225 cmd = sky2_pci_read16(hw, cap + PCI_X_CMD);
1226 cmd &= ~PCI_X_CMD_MAX_SPLIT;
1227 sky2_pci_write16(hw, cap + PCI_X_CMD, cmd);
1228
1229 sky2->rx_csum = 0;
1230 osky2->rx_csum = 0;
1231 }
1232
1233 if (netif_msg_ifup(sky2))
1234 printk(KERN_INFO PFX "%s: enabling interface\n", dev->name);
1235
1236 /* must be power of 2 */
1237 sky2->tx_le = pci_alloc_consistent(hw->pdev,
1238 TX_RING_SIZE *
1239 sizeof(struct sky2_tx_le),
1240 &sky2->tx_le_map);
1241 if (!sky2->tx_le)
1242 goto err_out;
1243
1244 sky2->tx_ring = kcalloc(TX_RING_SIZE, sizeof(struct tx_ring_info),
1245 GFP_KERNEL);
1246 if (!sky2->tx_ring)
1247 goto err_out;
1248 sky2->tx_prod = sky2->tx_cons = 0;
1249
1250 sky2->rx_le = pci_alloc_consistent(hw->pdev, RX_LE_BYTES,
1251 &sky2->rx_le_map);
1252 if (!sky2->rx_le)
1253 goto err_out;
1254 memset(sky2->rx_le, 0, RX_LE_BYTES);
1255
1256 sky2->rx_ring = kcalloc(sky2->rx_pending, sizeof(struct rx_ring_info),
1257 GFP_KERNEL);
1258 if (!sky2->rx_ring)
1259 goto err_out;
1260
1261 sky2_phy_power(hw, port, 1);
1262
1263 sky2_mac_init(hw, port);
1264
1265 /* Register is number of 4K blocks on internal RAM buffer. */
1266 ramsize = sky2_read8(hw, B2_E_0) * 4;
1267 printk(KERN_INFO PFX "%s: ram buffer %dK\n", dev->name, ramsize);
1268
1269 if (ramsize > 0) {
1270 u32 rxspace;
1271
1272 if (ramsize < 16)
1273 rxspace = ramsize / 2;
1274 else
1275 rxspace = 8 + (2*(ramsize - 16))/3;
1276
1277 sky2_ramset(hw, rxqaddr[port], 0, rxspace);
1278 sky2_ramset(hw, txqaddr[port], rxspace, ramsize - rxspace);
1279
1280 /* Make sure SyncQ is disabled */
1281 sky2_write8(hw, RB_ADDR(port == 0 ? Q_XS1 : Q_XS2, RB_CTRL),
1282 RB_RST_SET);
1283 }
1284
1285 sky2_qset(hw, txqaddr[port]);
1286
1287 /* Set almost empty threshold */
1288 if (hw->chip_id == CHIP_ID_YUKON_EC_U
1289 && hw->chip_rev == CHIP_REV_YU_EC_U_A0)
1290 sky2_write16(hw, Q_ADDR(txqaddr[port], Q_AL), ECU_TXFF_LEV);
1291
1292 sky2_prefetch_init(hw, txqaddr[port], sky2->tx_le_map,
1293 TX_RING_SIZE - 1);
1294
1295 err = sky2_rx_start(sky2);
1296 if (err)
1297 goto err_out;
1298
1299 /* Enable interrupts from phy/mac for port */
1300 imask = sky2_read32(hw, B0_IMSK);
1301 imask |= portirq_msk[port];
1302 sky2_write32(hw, B0_IMSK, imask);
1303
1304 return 0;
1305
1306 err_out:
1307 if (sky2->rx_le) {
1308 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1309 sky2->rx_le, sky2->rx_le_map);
1310 sky2->rx_le = NULL;
1311 }
1312 if (sky2->tx_le) {
1313 pci_free_consistent(hw->pdev,
1314 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1315 sky2->tx_le, sky2->tx_le_map);
1316 sky2->tx_le = NULL;
1317 }
1318 kfree(sky2->tx_ring);
1319 kfree(sky2->rx_ring);
1320
1321 sky2->tx_ring = NULL;
1322 sky2->rx_ring = NULL;
1323 return err;
1324 }
1325
1326 /* Modular subtraction in ring */
1327 static inline int tx_dist(unsigned tail, unsigned head)
1328 {
1329 return (head - tail) & (TX_RING_SIZE - 1);
1330 }
1331
1332 /* Number of list elements available for next tx */
1333 static inline int tx_avail(const struct sky2_port *sky2)
1334 {
1335 return sky2->tx_pending - tx_dist(sky2->tx_cons, sky2->tx_prod);
1336 }
1337
1338 /* Estimate of number of transmit list elements required */
1339 static unsigned tx_le_req(const struct sk_buff *skb)
1340 {
1341 unsigned count;
1342
1343 count = sizeof(dma_addr_t) / sizeof(u32);
1344 count += skb_shinfo(skb)->nr_frags * count;
1345
1346 if (skb_is_gso(skb))
1347 ++count;
1348
1349 if (skb->ip_summed == CHECKSUM_PARTIAL)
1350 ++count;
1351
1352 return count;
1353 }
1354
1355 /*
1356 * Put one packet in ring for transmit.
1357 * A single packet can generate multiple list elements, and
1358 * the number of ring elements will probably be less than the number
1359 * of list elements used.
1360 */
1361 static int sky2_xmit_frame(struct sk_buff *skb, struct net_device *dev)
1362 {
1363 struct sky2_port *sky2 = netdev_priv(dev);
1364 struct sky2_hw *hw = sky2->hw;
1365 struct sky2_tx_le *le = NULL;
1366 struct tx_ring_info *re;
1367 unsigned i, len;
1368 dma_addr_t mapping;
1369 u32 addr64;
1370 u16 mss;
1371 u8 ctrl;
1372
1373 if (unlikely(tx_avail(sky2) < tx_le_req(skb)))
1374 return NETDEV_TX_BUSY;
1375
1376 if (unlikely(netif_msg_tx_queued(sky2)))
1377 printk(KERN_DEBUG "%s: tx queued, slot %u, len %d\n",
1378 dev->name, sky2->tx_prod, skb->len);
1379
1380 len = skb_headlen(skb);
1381 mapping = pci_map_single(hw->pdev, skb->data, len, PCI_DMA_TODEVICE);
1382 addr64 = high32(mapping);
1383
1384 /* Send high bits if changed or crosses boundary */
1385 if (addr64 != sky2->tx_addr64 || high32(mapping + len) != sky2->tx_addr64) {
1386 le = get_tx_le(sky2);
1387 le->addr = cpu_to_le32(addr64);
1388 le->opcode = OP_ADDR64 | HW_OWNER;
1389 sky2->tx_addr64 = high32(mapping + len);
1390 }
1391
1392 /* Check for TCP Segmentation Offload */
1393 mss = skb_shinfo(skb)->gso_size;
1394 if (mss != 0) {
1395 mss += tcp_optlen(skb); /* TCP options */
1396 mss += ip_hdrlen(skb) + sizeof(struct tcphdr);
1397 mss += ETH_HLEN;
1398
1399 if (mss != sky2->tx_last_mss) {
1400 le = get_tx_le(sky2);
1401 le->addr = cpu_to_le32(mss);
1402 le->opcode = OP_LRGLEN | HW_OWNER;
1403 sky2->tx_last_mss = mss;
1404 }
1405 }
1406
1407 ctrl = 0;
1408 #ifdef SKY2_VLAN_TAG_USED
1409 /* Add VLAN tag, can piggyback on LRGLEN or ADDR64 */
1410 if (sky2->vlgrp && vlan_tx_tag_present(skb)) {
1411 if (!le) {
1412 le = get_tx_le(sky2);
1413 le->addr = 0;
1414 le->opcode = OP_VLAN|HW_OWNER;
1415 } else
1416 le->opcode |= OP_VLAN;
1417 le->length = cpu_to_be16(vlan_tx_tag_get(skb));
1418 ctrl |= INS_VLAN;
1419 }
1420 #endif
1421
1422 /* Handle TCP checksum offload */
1423 if (skb->ip_summed == CHECKSUM_PARTIAL) {
1424 const unsigned offset = skb_transport_offset(skb);
1425 u32 tcpsum;
1426
1427 tcpsum = offset << 16; /* sum start */
1428 tcpsum |= offset + skb->csum_offset; /* sum write */
1429
1430 ctrl = CALSUM | WR_SUM | INIT_SUM | LOCK_SUM;
1431 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1432 ctrl |= UDPTCP;
1433
1434 if (tcpsum != sky2->tx_tcpsum) {
1435 sky2->tx_tcpsum = tcpsum;
1436
1437 le = get_tx_le(sky2);
1438 le->addr = cpu_to_le32(tcpsum);
1439 le->length = 0; /* initial checksum value */
1440 le->ctrl = 1; /* one packet */
1441 le->opcode = OP_TCPLISW | HW_OWNER;
1442 }
1443 }
1444
1445 le = get_tx_le(sky2);
1446 le->addr = cpu_to_le32((u32) mapping);
1447 le->length = cpu_to_le16(len);
1448 le->ctrl = ctrl;
1449 le->opcode = mss ? (OP_LARGESEND | HW_OWNER) : (OP_PACKET | HW_OWNER);
1450
1451 re = tx_le_re(sky2, le);
1452 re->skb = skb;
1453 pci_unmap_addr_set(re, mapaddr, mapping);
1454 pci_unmap_len_set(re, maplen, len);
1455
1456 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
1457 const skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
1458
1459 mapping = pci_map_page(hw->pdev, frag->page, frag->page_offset,
1460 frag->size, PCI_DMA_TODEVICE);
1461 addr64 = high32(mapping);
1462 if (addr64 != sky2->tx_addr64) {
1463 le = get_tx_le(sky2);
1464 le->addr = cpu_to_le32(addr64);
1465 le->ctrl = 0;
1466 le->opcode = OP_ADDR64 | HW_OWNER;
1467 sky2->tx_addr64 = addr64;
1468 }
1469
1470 le = get_tx_le(sky2);
1471 le->addr = cpu_to_le32((u32) mapping);
1472 le->length = cpu_to_le16(frag->size);
1473 le->ctrl = ctrl;
1474 le->opcode = OP_BUFFER | HW_OWNER;
1475
1476 re = tx_le_re(sky2, le);
1477 re->skb = skb;
1478 pci_unmap_addr_set(re, mapaddr, mapping);
1479 pci_unmap_len_set(re, maplen, frag->size);
1480 }
1481
1482 le->ctrl |= EOP;
1483
1484 if (tx_avail(sky2) <= MAX_SKB_TX_LE)
1485 netif_stop_queue(dev);
1486
1487 sky2_put_idx(hw, txqaddr[sky2->port], sky2->tx_prod);
1488
1489 dev->trans_start = jiffies;
1490 return NETDEV_TX_OK;
1491 }
1492
1493 /*
1494 * Free ring elements from starting at tx_cons until "done"
1495 *
1496 * NB: the hardware will tell us about partial completion of multi-part
1497 * buffers so make sure not to free skb to early.
1498 */
1499 static void sky2_tx_complete(struct sky2_port *sky2, u16 done)
1500 {
1501 struct net_device *dev = sky2->netdev;
1502 struct pci_dev *pdev = sky2->hw->pdev;
1503 unsigned idx;
1504
1505 BUG_ON(done >= TX_RING_SIZE);
1506
1507 for (idx = sky2->tx_cons; idx != done;
1508 idx = RING_NEXT(idx, TX_RING_SIZE)) {
1509 struct sky2_tx_le *le = sky2->tx_le + idx;
1510 struct tx_ring_info *re = sky2->tx_ring + idx;
1511
1512 switch(le->opcode & ~HW_OWNER) {
1513 case OP_LARGESEND:
1514 case OP_PACKET:
1515 pci_unmap_single(pdev,
1516 pci_unmap_addr(re, mapaddr),
1517 pci_unmap_len(re, maplen),
1518 PCI_DMA_TODEVICE);
1519 break;
1520 case OP_BUFFER:
1521 pci_unmap_page(pdev, pci_unmap_addr(re, mapaddr),
1522 pci_unmap_len(re, maplen),
1523 PCI_DMA_TODEVICE);
1524 break;
1525 }
1526
1527 if (le->ctrl & EOP) {
1528 if (unlikely(netif_msg_tx_done(sky2)))
1529 printk(KERN_DEBUG "%s: tx done %u\n",
1530 dev->name, idx);
1531 sky2->net_stats.tx_packets++;
1532 sky2->net_stats.tx_bytes += re->skb->len;
1533
1534 dev_kfree_skb_any(re->skb);
1535 }
1536
1537 le->opcode = 0; /* paranoia */
1538 }
1539
1540 sky2->tx_cons = idx;
1541 if (tx_avail(sky2) > MAX_SKB_TX_LE + 4)
1542 netif_wake_queue(dev);
1543 }
1544
1545 /* Cleanup all untransmitted buffers, assume transmitter not running */
1546 static void sky2_tx_clean(struct net_device *dev)
1547 {
1548 struct sky2_port *sky2 = netdev_priv(dev);
1549
1550 netif_tx_lock_bh(dev);
1551 sky2_tx_complete(sky2, sky2->tx_prod);
1552 netif_tx_unlock_bh(dev);
1553 }
1554
1555 /* Network shutdown */
1556 static int sky2_down(struct net_device *dev)
1557 {
1558 struct sky2_port *sky2 = netdev_priv(dev);
1559 struct sky2_hw *hw = sky2->hw;
1560 unsigned port = sky2->port;
1561 u16 ctrl;
1562 u32 imask;
1563
1564 /* Never really got started! */
1565 if (!sky2->tx_le)
1566 return 0;
1567
1568 if (netif_msg_ifdown(sky2))
1569 printk(KERN_INFO PFX "%s: disabling interface\n", dev->name);
1570
1571 /* Stop more packets from being queued */
1572 netif_stop_queue(dev);
1573 netif_carrier_off(dev);
1574
1575 /* Disable port IRQ */
1576 imask = sky2_read32(hw, B0_IMSK);
1577 imask &= ~portirq_msk[port];
1578 sky2_write32(hw, B0_IMSK, imask);
1579
1580 /*
1581 * Both ports share the NAPI poll on port 0, so if necessary undo the
1582 * the disable that is done in dev_close.
1583 */
1584 if (sky2->port == 0 && hw->ports > 1)
1585 netif_poll_enable(dev);
1586
1587 sky2_gmac_reset(hw, port);
1588
1589 /* Stop transmitter */
1590 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_STOP);
1591 sky2_read32(hw, Q_ADDR(txqaddr[port], Q_CSR));
1592
1593 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL),
1594 RB_RST_SET | RB_DIS_OP_MD);
1595
1596 ctrl = gma_read16(hw, port, GM_GP_CTRL);
1597 ctrl &= ~(GM_GPCR_TX_ENA | GM_GPCR_RX_ENA);
1598 gma_write16(hw, port, GM_GP_CTRL, ctrl);
1599
1600 sky2_write8(hw, SK_REG(port, GPHY_CTRL), GPC_RST_SET);
1601
1602 /* Workaround shared GMAC reset */
1603 if (!(hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0
1604 && port == 0 && hw->dev[1] && netif_running(hw->dev[1])))
1605 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_RST_SET);
1606
1607 /* Disable Force Sync bit and Enable Alloc bit */
1608 sky2_write8(hw, SK_REG(port, TXA_CTRL),
1609 TXA_DIS_FSYNC | TXA_DIS_ALLOC | TXA_STOP_RC);
1610
1611 /* Stop Interval Timer and Limit Counter of Tx Arbiter */
1612 sky2_write32(hw, SK_REG(port, TXA_ITI_INI), 0L);
1613 sky2_write32(hw, SK_REG(port, TXA_LIM_INI), 0L);
1614
1615 /* Reset the PCI FIFO of the async Tx queue */
1616 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR),
1617 BMU_RST_SET | BMU_FIFO_RST);
1618
1619 /* Reset the Tx prefetch units */
1620 sky2_write32(hw, Y2_QADDR(txqaddr[port], PREF_UNIT_CTRL),
1621 PREF_UNIT_RST_SET);
1622
1623 sky2_write32(hw, RB_ADDR(txqaddr[port], RB_CTRL), RB_RST_SET);
1624
1625 sky2_rx_stop(sky2);
1626
1627 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_RST_SET);
1628 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_RST_SET);
1629
1630 sky2_phy_power(hw, port, 0);
1631
1632 /* turn off LED's */
1633 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
1634
1635 synchronize_irq(hw->pdev->irq);
1636
1637 sky2_tx_clean(dev);
1638 sky2_rx_clean(sky2);
1639
1640 pci_free_consistent(hw->pdev, RX_LE_BYTES,
1641 sky2->rx_le, sky2->rx_le_map);
1642 kfree(sky2->rx_ring);
1643
1644 pci_free_consistent(hw->pdev,
1645 TX_RING_SIZE * sizeof(struct sky2_tx_le),
1646 sky2->tx_le, sky2->tx_le_map);
1647 kfree(sky2->tx_ring);
1648
1649 sky2->tx_le = NULL;
1650 sky2->rx_le = NULL;
1651
1652 sky2->rx_ring = NULL;
1653 sky2->tx_ring = NULL;
1654
1655 return 0;
1656 }
1657
1658 static u16 sky2_phy_speed(const struct sky2_hw *hw, u16 aux)
1659 {
1660 if (!sky2_is_copper(hw))
1661 return SPEED_1000;
1662
1663 if (hw->chip_id == CHIP_ID_YUKON_FE)
1664 return (aux & PHY_M_PS_SPEED_100) ? SPEED_100 : SPEED_10;
1665
1666 switch (aux & PHY_M_PS_SPEED_MSK) {
1667 case PHY_M_PS_SPEED_1000:
1668 return SPEED_1000;
1669 case PHY_M_PS_SPEED_100:
1670 return SPEED_100;
1671 default:
1672 return SPEED_10;
1673 }
1674 }
1675
1676 static void sky2_link_up(struct sky2_port *sky2)
1677 {
1678 struct sky2_hw *hw = sky2->hw;
1679 unsigned port = sky2->port;
1680 u16 reg;
1681 static const char *fc_name[] = {
1682 [FC_NONE] = "none",
1683 [FC_TX] = "tx",
1684 [FC_RX] = "rx",
1685 [FC_BOTH] = "both",
1686 };
1687
1688 /* enable Rx/Tx */
1689 reg = gma_read16(hw, port, GM_GP_CTRL);
1690 reg |= GM_GPCR_RX_ENA | GM_GPCR_TX_ENA;
1691 gma_write16(hw, port, GM_GP_CTRL, reg);
1692
1693 gm_phy_write(hw, port, PHY_MARV_INT_MASK, PHY_M_DEF_MSK);
1694
1695 netif_carrier_on(sky2->netdev);
1696 netif_wake_queue(sky2->netdev);
1697
1698 /* Turn on link LED */
1699 sky2_write8(hw, SK_REG(port, LNK_LED_REG),
1700 LINKLED_ON | LINKLED_BLINK_OFF | LINKLED_LINKSYNC_OFF);
1701
1702 if (hw->chip_id == CHIP_ID_YUKON_XL
1703 || hw->chip_id == CHIP_ID_YUKON_EC_U
1704 || hw->chip_id == CHIP_ID_YUKON_EX) {
1705 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
1706 u16 led = PHY_M_LEDC_LOS_CTRL(1); /* link active */
1707
1708 switch(sky2->speed) {
1709 case SPEED_10:
1710 led |= PHY_M_LEDC_INIT_CTRL(7);
1711 break;
1712
1713 case SPEED_100:
1714 led |= PHY_M_LEDC_STA1_CTRL(7);
1715 break;
1716
1717 case SPEED_1000:
1718 led |= PHY_M_LEDC_STA0_CTRL(7);
1719 break;
1720 }
1721
1722 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
1723 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, led);
1724 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
1725 }
1726
1727 if (netif_msg_link(sky2))
1728 printk(KERN_INFO PFX
1729 "%s: Link is up at %d Mbps, %s duplex, flow control %s\n",
1730 sky2->netdev->name, sky2->speed,
1731 sky2->duplex == DUPLEX_FULL ? "full" : "half",
1732 fc_name[sky2->flow_status]);
1733 }
1734
1735 static void sky2_link_down(struct sky2_port *sky2)
1736 {
1737 struct sky2_hw *hw = sky2->hw;
1738 unsigned port = sky2->port;
1739 u16 reg;
1740
1741 gm_phy_write(hw, port, PHY_MARV_INT_MASK, 0);
1742
1743 reg = gma_read16(hw, port, GM_GP_CTRL);
1744 reg &= ~(GM_GPCR_RX_ENA | GM_GPCR_TX_ENA);
1745 gma_write16(hw, port, GM_GP_CTRL, reg);
1746
1747 netif_carrier_off(sky2->netdev);
1748 netif_stop_queue(sky2->netdev);
1749
1750 /* Turn on link LED */
1751 sky2_write8(hw, SK_REG(port, LNK_LED_REG), LINKLED_OFF);
1752
1753 if (netif_msg_link(sky2))
1754 printk(KERN_INFO PFX "%s: Link is down.\n", sky2->netdev->name);
1755
1756 sky2_phy_init(hw, port);
1757 }
1758
1759 static enum flow_control sky2_flow(int rx, int tx)
1760 {
1761 if (rx)
1762 return tx ? FC_BOTH : FC_RX;
1763 else
1764 return tx ? FC_TX : FC_NONE;
1765 }
1766
1767 static int sky2_autoneg_done(struct sky2_port *sky2, u16 aux)
1768 {
1769 struct sky2_hw *hw = sky2->hw;
1770 unsigned port = sky2->port;
1771 u16 advert, lpa;
1772
1773 advert = gm_phy_read(hw, port, PHY_MARV_AUNE_ADV);
1774 lpa = gm_phy_read(hw, port, PHY_MARV_AUNE_LP);
1775 if (lpa & PHY_M_AN_RF) {
1776 printk(KERN_ERR PFX "%s: remote fault", sky2->netdev->name);
1777 return -1;
1778 }
1779
1780 if (!(aux & PHY_M_PS_SPDUP_RES)) {
1781 printk(KERN_ERR PFX "%s: speed/duplex mismatch",
1782 sky2->netdev->name);
1783 return -1;
1784 }
1785
1786 sky2->speed = sky2_phy_speed(hw, aux);
1787 sky2->duplex = (aux & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1788
1789 /* Since the pause result bits seem to in different positions on
1790 * different chips. look at registers.
1791 */
1792 if (!sky2_is_copper(hw)) {
1793 /* Shift for bits in fiber PHY */
1794 advert &= ~(ADVERTISE_PAUSE_CAP|ADVERTISE_PAUSE_ASYM);
1795 lpa &= ~(LPA_PAUSE_CAP|LPA_PAUSE_ASYM);
1796
1797 if (advert & ADVERTISE_1000XPAUSE)
1798 advert |= ADVERTISE_PAUSE_CAP;
1799 if (advert & ADVERTISE_1000XPSE_ASYM)
1800 advert |= ADVERTISE_PAUSE_ASYM;
1801 if (lpa & LPA_1000XPAUSE)
1802 lpa |= LPA_PAUSE_CAP;
1803 if (lpa & LPA_1000XPAUSE_ASYM)
1804 lpa |= LPA_PAUSE_ASYM;
1805 }
1806
1807 sky2->flow_status = FC_NONE;
1808 if (advert & ADVERTISE_PAUSE_CAP) {
1809 if (lpa & LPA_PAUSE_CAP)
1810 sky2->flow_status = FC_BOTH;
1811 else if (advert & ADVERTISE_PAUSE_ASYM)
1812 sky2->flow_status = FC_RX;
1813 } else if (advert & ADVERTISE_PAUSE_ASYM) {
1814 if ((lpa & LPA_PAUSE_CAP) && (lpa & LPA_PAUSE_ASYM))
1815 sky2->flow_status = FC_TX;
1816 }
1817
1818 if (sky2->duplex == DUPLEX_HALF && sky2->speed < SPEED_1000
1819 && !(hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX))
1820 sky2->flow_status = FC_NONE;
1821
1822 if (sky2->flow_status & FC_TX)
1823 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_ON);
1824 else
1825 sky2_write8(hw, SK_REG(port, GMAC_CTRL), GMC_PAUSE_OFF);
1826
1827 return 0;
1828 }
1829
1830 /* Interrupt from PHY */
1831 static void sky2_phy_intr(struct sky2_hw *hw, unsigned port)
1832 {
1833 struct net_device *dev = hw->dev[port];
1834 struct sky2_port *sky2 = netdev_priv(dev);
1835 u16 istatus, phystat;
1836
1837 if (!netif_running(dev))
1838 return;
1839
1840 spin_lock(&sky2->phy_lock);
1841 istatus = gm_phy_read(hw, port, PHY_MARV_INT_STAT);
1842 phystat = gm_phy_read(hw, port, PHY_MARV_PHY_STAT);
1843
1844 if (netif_msg_intr(sky2))
1845 printk(KERN_INFO PFX "%s: phy interrupt status 0x%x 0x%x\n",
1846 sky2->netdev->name, istatus, phystat);
1847
1848 if (sky2->autoneg == AUTONEG_ENABLE && (istatus & PHY_M_IS_AN_COMPL)) {
1849 if (sky2_autoneg_done(sky2, phystat) == 0)
1850 sky2_link_up(sky2);
1851 goto out;
1852 }
1853
1854 if (istatus & PHY_M_IS_LSP_CHANGE)
1855 sky2->speed = sky2_phy_speed(hw, phystat);
1856
1857 if (istatus & PHY_M_IS_DUP_CHANGE)
1858 sky2->duplex =
1859 (phystat & PHY_M_PS_FULL_DUP) ? DUPLEX_FULL : DUPLEX_HALF;
1860
1861 if (istatus & PHY_M_IS_LST_CHANGE) {
1862 if (phystat & PHY_M_PS_LINK_UP)
1863 sky2_link_up(sky2);
1864 else
1865 sky2_link_down(sky2);
1866 }
1867 out:
1868 spin_unlock(&sky2->phy_lock);
1869 }
1870
1871 /* Transmit timeout is only called if we are running, carrier is up
1872 * and tx queue is full (stopped).
1873 */
1874 static void sky2_tx_timeout(struct net_device *dev)
1875 {
1876 struct sky2_port *sky2 = netdev_priv(dev);
1877 struct sky2_hw *hw = sky2->hw;
1878
1879 if (netif_msg_timer(sky2))
1880 printk(KERN_ERR PFX "%s: tx timeout\n", dev->name);
1881
1882 printk(KERN_DEBUG PFX "%s: transmit ring %u .. %u report=%u done=%u\n",
1883 dev->name, sky2->tx_cons, sky2->tx_prod,
1884 sky2_read16(hw, sky2->port == 0 ? STAT_TXA1_RIDX : STAT_TXA2_RIDX),
1885 sky2_read16(hw, Q_ADDR(txqaddr[sky2->port], Q_DONE)));
1886
1887 /* can't restart safely under softirq */
1888 schedule_work(&hw->restart_work);
1889 }
1890
1891 static int sky2_change_mtu(struct net_device *dev, int new_mtu)
1892 {
1893 struct sky2_port *sky2 = netdev_priv(dev);
1894 struct sky2_hw *hw = sky2->hw;
1895 unsigned port = sky2->port;
1896 int err;
1897 u16 ctl, mode;
1898 u32 imask;
1899
1900 if (new_mtu < ETH_ZLEN || new_mtu > ETH_JUMBO_MTU)
1901 return -EINVAL;
1902
1903 if (new_mtu > ETH_DATA_LEN && hw->chip_id == CHIP_ID_YUKON_FE)
1904 return -EINVAL;
1905
1906 if (!netif_running(dev)) {
1907 dev->mtu = new_mtu;
1908 return 0;
1909 }
1910
1911 imask = sky2_read32(hw, B0_IMSK);
1912 sky2_write32(hw, B0_IMSK, 0);
1913
1914 dev->trans_start = jiffies; /* prevent tx timeout */
1915 netif_stop_queue(dev);
1916 netif_poll_disable(hw->dev[0]);
1917
1918 synchronize_irq(hw->pdev->irq);
1919
1920 if (hw->chip_id == CHIP_ID_YUKON_EC_U || hw->chip_id == CHIP_ID_YUKON_EX) {
1921 if (new_mtu > ETH_DATA_LEN) {
1922 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1923 TX_JUMBO_ENA | TX_STFW_DIS);
1924 dev->features &= NETIF_F_TSO | NETIF_F_SG | NETIF_F_IP_CSUM;
1925 } else
1926 sky2_write32(hw, SK_REG(port, TX_GMF_CTRL_T),
1927 TX_JUMBO_DIS | TX_STFW_ENA);
1928 }
1929
1930 ctl = gma_read16(hw, port, GM_GP_CTRL);
1931 gma_write16(hw, port, GM_GP_CTRL, ctl & ~GM_GPCR_RX_ENA);
1932 sky2_rx_stop(sky2);
1933 sky2_rx_clean(sky2);
1934
1935 dev->mtu = new_mtu;
1936
1937 mode = DATA_BLIND_VAL(DATA_BLIND_DEF) |
1938 GM_SMOD_VLAN_ENA | IPG_DATA_VAL(IPG_DATA_DEF);
1939
1940 if (dev->mtu > ETH_DATA_LEN)
1941 mode |= GM_SMOD_JUMBO_ENA;
1942
1943 gma_write16(hw, port, GM_SERIAL_MODE, mode);
1944
1945 sky2_write8(hw, RB_ADDR(rxqaddr[port], RB_CTRL), RB_ENA_OP_MD);
1946
1947 err = sky2_rx_start(sky2);
1948 sky2_write32(hw, B0_IMSK, imask);
1949
1950 if (err)
1951 dev_close(dev);
1952 else {
1953 gma_write16(hw, port, GM_GP_CTRL, ctl);
1954
1955 netif_poll_enable(hw->dev[0]);
1956 netif_wake_queue(dev);
1957 }
1958
1959 return err;
1960 }
1961
1962 /* For small just reuse existing skb for next receive */
1963 static struct sk_buff *receive_copy(struct sky2_port *sky2,
1964 const struct rx_ring_info *re,
1965 unsigned length)
1966 {
1967 struct sk_buff *skb;
1968
1969 skb = netdev_alloc_skb(sky2->netdev, length + 2);
1970 if (likely(skb)) {
1971 skb_reserve(skb, 2);
1972 pci_dma_sync_single_for_cpu(sky2->hw->pdev, re->data_addr,
1973 length, PCI_DMA_FROMDEVICE);
1974 skb_copy_from_linear_data(re->skb, skb->data, length);
1975 skb->ip_summed = re->skb->ip_summed;
1976 skb->csum = re->skb->csum;
1977 pci_dma_sync_single_for_device(sky2->hw->pdev, re->data_addr,
1978 length, PCI_DMA_FROMDEVICE);
1979 re->skb->ip_summed = CHECKSUM_NONE;
1980 skb_put(skb, length);
1981 }
1982 return skb;
1983 }
1984
1985 /* Adjust length of skb with fragments to match received data */
1986 static void skb_put_frags(struct sk_buff *skb, unsigned int hdr_space,
1987 unsigned int length)
1988 {
1989 int i, num_frags;
1990 unsigned int size;
1991
1992 /* put header into skb */
1993 size = min(length, hdr_space);
1994 skb->tail += size;
1995 skb->len += size;
1996 length -= size;
1997
1998 num_frags = skb_shinfo(skb)->nr_frags;
1999 for (i = 0; i < num_frags; i++) {
2000 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2001
2002 if (length == 0) {
2003 /* don't need this page */
2004 __free_page(frag->page);
2005 --skb_shinfo(skb)->nr_frags;
2006 } else {
2007 size = min(length, (unsigned) PAGE_SIZE);
2008
2009 frag->size = size;
2010 skb->data_len += size;
2011 skb->truesize += size;
2012 skb->len += size;
2013 length -= size;
2014 }
2015 }
2016 }
2017
2018 /* Normal packet - take skb from ring element and put in a new one */
2019 static struct sk_buff *receive_new(struct sky2_port *sky2,
2020 struct rx_ring_info *re,
2021 unsigned int length)
2022 {
2023 struct sk_buff *skb, *nskb;
2024 unsigned hdr_space = sky2->rx_data_size;
2025
2026 pr_debug(PFX "receive new length=%d\n", length);
2027
2028 /* Don't be tricky about reusing pages (yet) */
2029 nskb = sky2_rx_alloc(sky2);
2030 if (unlikely(!nskb))
2031 return NULL;
2032
2033 skb = re->skb;
2034 sky2_rx_unmap_skb(sky2->hw->pdev, re);
2035
2036 prefetch(skb->data);
2037 re->skb = nskb;
2038 sky2_rx_map_skb(sky2->hw->pdev, re, hdr_space);
2039
2040 if (skb_shinfo(skb)->nr_frags)
2041 skb_put_frags(skb, hdr_space, length);
2042 else
2043 skb_put(skb, length);
2044 return skb;
2045 }
2046
2047 /*
2048 * Receive one packet.
2049 * For larger packets, get new buffer.
2050 */
2051 static struct sk_buff *sky2_receive(struct net_device *dev,
2052 u16 length, u32 status)
2053 {
2054 struct sky2_port *sky2 = netdev_priv(dev);
2055 struct rx_ring_info *re = sky2->rx_ring + sky2->rx_next;
2056 struct sk_buff *skb = NULL;
2057
2058 if (unlikely(netif_msg_rx_status(sky2)))
2059 printk(KERN_DEBUG PFX "%s: rx slot %u status 0x%x len %d\n",
2060 dev->name, sky2->rx_next, status, length);
2061
2062 sky2->rx_next = (sky2->rx_next + 1) % sky2->rx_pending;
2063 prefetch(sky2->rx_ring + sky2->rx_next);
2064
2065 if (status & GMR_FS_ANY_ERR)
2066 goto error;
2067
2068 if (!(status & GMR_FS_RX_OK))
2069 goto resubmit;
2070
2071 if (length < copybreak)
2072 skb = receive_copy(sky2, re, length);
2073 else
2074 skb = receive_new(sky2, re, length);
2075 resubmit:
2076 sky2_rx_submit(sky2, re);
2077
2078 return skb;
2079
2080 error:
2081 ++sky2->net_stats.rx_errors;
2082 if (status & GMR_FS_RX_FF_OV) {
2083 sky2->net_stats.rx_over_errors++;
2084 goto resubmit;
2085 }
2086
2087 if (netif_msg_rx_err(sky2) && net_ratelimit())
2088 printk(KERN_INFO PFX "%s: rx error, status 0x%x length %d\n",
2089 dev->name, status, length);
2090
2091 if (status & (GMR_FS_LONG_ERR | GMR_FS_UN_SIZE))
2092 sky2->net_stats.rx_length_errors++;
2093 if (status & GMR_FS_FRAGMENT)
2094 sky2->net_stats.rx_frame_errors++;
2095 if (status & GMR_FS_CRC_ERR)
2096 sky2->net_stats.rx_crc_errors++;
2097
2098 goto resubmit;
2099 }
2100
2101 /* Transmit complete */
2102 static inline void sky2_tx_done(struct net_device *dev, u16 last)
2103 {
2104 struct sky2_port *sky2 = netdev_priv(dev);
2105
2106 if (netif_running(dev)) {
2107 netif_tx_lock(dev);
2108 sky2_tx_complete(sky2, last);
2109 netif_tx_unlock(dev);
2110 }
2111 }
2112
2113 /* Process status response ring */
2114 static int sky2_status_intr(struct sky2_hw *hw, int to_do)
2115 {
2116 struct sky2_port *sky2;
2117 int work_done = 0;
2118 unsigned buf_write[2] = { 0, 0 };
2119 u16 hwidx = sky2_read16(hw, STAT_PUT_IDX);
2120
2121 rmb();
2122
2123 while (hw->st_idx != hwidx) {
2124 struct sky2_status_le *le = hw->st_le + hw->st_idx;
2125 struct net_device *dev;
2126 struct sk_buff *skb;
2127 u32 status;
2128 u16 length;
2129
2130 hw->st_idx = RING_NEXT(hw->st_idx, STATUS_RING_SIZE);
2131
2132 BUG_ON(le->link >= 2);
2133 dev = hw->dev[le->link];
2134
2135 sky2 = netdev_priv(dev);
2136 length = le16_to_cpu(le->length);
2137 status = le32_to_cpu(le->status);
2138
2139 switch (le->opcode & ~HW_OWNER) {
2140 case OP_RXSTAT:
2141 skb = sky2_receive(dev, length, status);
2142 if (!skb)
2143 goto force_update;
2144
2145 skb->protocol = eth_type_trans(skb, dev);
2146 sky2->net_stats.rx_packets++;
2147 sky2->net_stats.rx_bytes += skb->len;
2148 dev->last_rx = jiffies;
2149
2150 #ifdef SKY2_VLAN_TAG_USED
2151 if (sky2->vlgrp && (status & GMR_FS_VLAN)) {
2152 vlan_hwaccel_receive_skb(skb,
2153 sky2->vlgrp,
2154 be16_to_cpu(sky2->rx_tag));
2155 } else
2156 #endif
2157 netif_receive_skb(skb);
2158
2159 /* Update receiver after 16 frames */
2160 if (++buf_write[le->link] == RX_BUF_WRITE) {
2161 force_update:
2162 sky2_put_idx(hw, rxqaddr[le->link], sky2->rx_put);
2163 buf_write[le->link] = 0;
2164 }
2165
2166 /* Stop after net poll weight */
2167 if (++work_done >= to_do)
2168 goto exit_loop;
2169 break;
2170
2171 #ifdef SKY2_VLAN_TAG_USED
2172 case OP_RXVLAN:
2173 sky2->rx_tag = length;
2174 break;
2175
2176 case OP_RXCHKSVLAN:
2177 sky2->rx_tag = length;
2178 /* fall through */
2179 #endif
2180 case OP_RXCHKS:
2181 if (!sky2->rx_csum)
2182 break;
2183
2184 /* Both checksum counters are programmed to start at
2185 * the same offset, so unless there is a problem they
2186 * should match. This failure is an early indication that
2187 * hardware receive checksumming won't work.
2188 */
2189 if (likely(status >> 16 == (status & 0xffff))) {
2190 skb = sky2->rx_ring[sky2->rx_next].skb;
2191 skb->ip_summed = CHECKSUM_COMPLETE;
2192 skb->csum = status & 0xffff;
2193 } else {
2194 printk(KERN_NOTICE PFX "%s: hardware receive "
2195 "checksum problem (status = %#x)\n",
2196 dev->name, status);
2197 sky2->rx_csum = 0;
2198 sky2_write32(sky2->hw,
2199 Q_ADDR(rxqaddr[le->link], Q_CSR),
2200 BMU_DIS_RX_CHKSUM);
2201 }
2202 break;
2203
2204 case OP_TXINDEXLE:
2205 /* TX index reports status for both ports */
2206 BUILD_BUG_ON(TX_RING_SIZE > 0x1000);
2207 sky2_tx_done(hw->dev[0], status & 0xfff);
2208 if (hw->dev[1])
2209 sky2_tx_done(hw->dev[1],
2210 ((status >> 24) & 0xff)
2211 | (u16)(length & 0xf) << 8);
2212 break;
2213
2214 default:
2215 if (net_ratelimit())
2216 printk(KERN_WARNING PFX
2217 "unknown status opcode 0x%x\n", le->opcode);
2218 goto exit_loop;
2219 }
2220 }
2221
2222 /* Fully processed status ring so clear irq */
2223 sky2_write32(hw, STAT_CTRL, SC_STAT_CLR_IRQ);
2224
2225 exit_loop:
2226 if (buf_write[0]) {
2227 sky2 = netdev_priv(hw->dev[0]);
2228 sky2_put_idx(hw, Q_R1, sky2->rx_put);
2229 }
2230
2231 if (buf_write[1]) {
2232 sky2 = netdev_priv(hw->dev[1]);
2233 sky2_put_idx(hw, Q_R2, sky2->rx_put);
2234 }
2235
2236 return work_done;
2237 }
2238
2239 static void sky2_hw_error(struct sky2_hw *hw, unsigned port, u32 status)
2240 {
2241 struct net_device *dev = hw->dev[port];
2242
2243 if (net_ratelimit())
2244 printk(KERN_INFO PFX "%s: hw error interrupt status 0x%x\n",
2245 dev->name, status);
2246
2247 if (status & Y2_IS_PAR_RD1) {
2248 if (net_ratelimit())
2249 printk(KERN_ERR PFX "%s: ram data read parity error\n",
2250 dev->name);
2251 /* Clear IRQ */
2252 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_RD_PERR);
2253 }
2254
2255 if (status & Y2_IS_PAR_WR1) {
2256 if (net_ratelimit())
2257 printk(KERN_ERR PFX "%s: ram data write parity error\n",
2258 dev->name);
2259
2260 sky2_write16(hw, RAM_BUFFER(port, B3_RI_CTRL), RI_CLR_WR_PERR);
2261 }
2262
2263 if (status & Y2_IS_PAR_MAC1) {
2264 if (net_ratelimit())
2265 printk(KERN_ERR PFX "%s: MAC parity error\n", dev->name);
2266 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_PE);
2267 }
2268
2269 if (status & Y2_IS_PAR_RX1) {
2270 if (net_ratelimit())
2271 printk(KERN_ERR PFX "%s: RX parity error\n", dev->name);
2272 sky2_write32(hw, Q_ADDR(rxqaddr[port], Q_CSR), BMU_CLR_IRQ_PAR);
2273 }
2274
2275 if (status & Y2_IS_TCP_TXA1) {
2276 if (net_ratelimit())
2277 printk(KERN_ERR PFX "%s: TCP segmentation error\n",
2278 dev->name);
2279 sky2_write32(hw, Q_ADDR(txqaddr[port], Q_CSR), BMU_CLR_IRQ_TCP);
2280 }
2281 }
2282
2283 static void sky2_hw_intr(struct sky2_hw *hw)
2284 {
2285 u32 status = sky2_read32(hw, B0_HWE_ISRC);
2286
2287 if (status & Y2_IS_TIST_OV)
2288 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2289
2290 if (status & (Y2_IS_MST_ERR | Y2_IS_IRQ_STAT)) {
2291 u16 pci_err;
2292
2293 pci_err = sky2_pci_read16(hw, PCI_STATUS);
2294 if (net_ratelimit())
2295 dev_err(&hw->pdev->dev, "PCI hardware error (0x%x)\n",
2296 pci_err);
2297
2298 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2299 sky2_pci_write16(hw, PCI_STATUS,
2300 pci_err | PCI_STATUS_ERROR_BITS);
2301 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2302 }
2303
2304 if (status & Y2_IS_PCI_EXP) {
2305 /* PCI-Express uncorrectable Error occurred */
2306 u32 pex_err;
2307
2308 pex_err = sky2_pci_read32(hw, PEX_UNC_ERR_STAT);
2309
2310 if (net_ratelimit())
2311 dev_err(&hw->pdev->dev, "PCI Express error (0x%x)\n",
2312 pex_err);
2313
2314 /* clear the interrupt */
2315 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2316 sky2_pci_write32(hw, PEX_UNC_ERR_STAT,
2317 0xffffffffUL);
2318 sky2_write32(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2319
2320 if (pex_err & PEX_FATAL_ERRORS) {
2321 u32 hwmsk = sky2_read32(hw, B0_HWE_IMSK);
2322 hwmsk &= ~Y2_IS_PCI_EXP;
2323 sky2_write32(hw, B0_HWE_IMSK, hwmsk);
2324 }
2325 }
2326
2327 if (status & Y2_HWE_L1_MASK)
2328 sky2_hw_error(hw, 0, status);
2329 status >>= 8;
2330 if (status & Y2_HWE_L1_MASK)
2331 sky2_hw_error(hw, 1, status);
2332 }
2333
2334 static void sky2_mac_intr(struct sky2_hw *hw, unsigned port)
2335 {
2336 struct net_device *dev = hw->dev[port];
2337 struct sky2_port *sky2 = netdev_priv(dev);
2338 u8 status = sky2_read8(hw, SK_REG(port, GMAC_IRQ_SRC));
2339
2340 if (netif_msg_intr(sky2))
2341 printk(KERN_INFO PFX "%s: mac interrupt status 0x%x\n",
2342 dev->name, status);
2343
2344 if (status & GM_IS_RX_FF_OR) {
2345 ++sky2->net_stats.rx_fifo_errors;
2346 sky2_write8(hw, SK_REG(port, RX_GMF_CTRL_T), GMF_CLI_RX_FO);
2347 }
2348
2349 if (status & GM_IS_TX_FF_UR) {
2350 ++sky2->net_stats.tx_fifo_errors;
2351 sky2_write8(hw, SK_REG(port, TX_GMF_CTRL_T), GMF_CLI_TX_FU);
2352 }
2353 }
2354
2355 /* This should never happen it is a bug. */
2356 static void sky2_le_error(struct sky2_hw *hw, unsigned port,
2357 u16 q, unsigned ring_size)
2358 {
2359 struct net_device *dev = hw->dev[port];
2360 struct sky2_port *sky2 = netdev_priv(dev);
2361 unsigned idx;
2362 const u64 *le = (q == Q_R1 || q == Q_R2)
2363 ? (u64 *) sky2->rx_le : (u64 *) sky2->tx_le;
2364
2365 idx = sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_GET_IDX));
2366 printk(KERN_ERR PFX "%s: descriptor error q=%#x get=%u [%llx] put=%u\n",
2367 dev->name, (unsigned) q, idx, (unsigned long long) le[idx],
2368 (unsigned) sky2_read16(hw, Y2_QADDR(q, PREF_UNIT_PUT_IDX)));
2369
2370 sky2_write32(hw, Q_ADDR(q, Q_CSR), BMU_CLR_IRQ_CHK);
2371 }
2372
2373 /* If idle then force a fake soft NAPI poll once a second
2374 * to work around cases where sharing an edge triggered interrupt.
2375 */
2376 static inline void sky2_idle_start(struct sky2_hw *hw)
2377 {
2378 if (idle_timeout > 0)
2379 mod_timer(&hw->idle_timer,
2380 jiffies + msecs_to_jiffies(idle_timeout));
2381 }
2382
2383 static void sky2_idle(unsigned long arg)
2384 {
2385 struct sky2_hw *hw = (struct sky2_hw *) arg;
2386 struct net_device *dev = hw->dev[0];
2387
2388 if (__netif_rx_schedule_prep(dev))
2389 __netif_rx_schedule(dev);
2390
2391 mod_timer(&hw->idle_timer, jiffies + msecs_to_jiffies(idle_timeout));
2392 }
2393
2394 /* Hardware/software error handling */
2395 static void sky2_err_intr(struct sky2_hw *hw, u32 status)
2396 {
2397 if (net_ratelimit())
2398 dev_warn(&hw->pdev->dev, "error interrupt status=%#x\n", status);
2399
2400 if (status & Y2_IS_HW_ERR)
2401 sky2_hw_intr(hw);
2402
2403 if (status & Y2_IS_IRQ_MAC1)
2404 sky2_mac_intr(hw, 0);
2405
2406 if (status & Y2_IS_IRQ_MAC2)
2407 sky2_mac_intr(hw, 1);
2408
2409 if (status & Y2_IS_CHK_RX1)
2410 sky2_le_error(hw, 0, Q_R1, RX_LE_SIZE);
2411
2412 if (status & Y2_IS_CHK_RX2)
2413 sky2_le_error(hw, 1, Q_R2, RX_LE_SIZE);
2414
2415 if (status & Y2_IS_CHK_TXA1)
2416 sky2_le_error(hw, 0, Q_XA1, TX_RING_SIZE);
2417
2418 if (status & Y2_IS_CHK_TXA2)
2419 sky2_le_error(hw, 1, Q_XA2, TX_RING_SIZE);
2420 }
2421
2422 static int sky2_poll(struct net_device *dev0, int *budget)
2423 {
2424 struct sky2_hw *hw = ((struct sky2_port *) netdev_priv(dev0))->hw;
2425 int work_limit = min(dev0->quota, *budget);
2426 int work_done = 0;
2427 u32 status = sky2_read32(hw, B0_Y2_SP_EISR);
2428
2429 if (unlikely(status & Y2_IS_ERROR))
2430 sky2_err_intr(hw, status);
2431
2432 if (status & Y2_IS_IRQ_PHY1)
2433 sky2_phy_intr(hw, 0);
2434
2435 if (status & Y2_IS_IRQ_PHY2)
2436 sky2_phy_intr(hw, 1);
2437
2438 work_done = sky2_status_intr(hw, work_limit);
2439 if (work_done < work_limit) {
2440 netif_rx_complete(dev0);
2441
2442 sky2_read32(hw, B0_Y2_SP_LISR);
2443 return 0;
2444 } else {
2445 *budget -= work_done;
2446 dev0->quota -= work_done;
2447 return 1;
2448 }
2449 }
2450
2451 static irqreturn_t sky2_intr(int irq, void *dev_id)
2452 {
2453 struct sky2_hw *hw = dev_id;
2454 struct net_device *dev0 = hw->dev[0];
2455 u32 status;
2456
2457 /* Reading this mask interrupts as side effect */
2458 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
2459 if (status == 0 || status == ~0)
2460 return IRQ_NONE;
2461
2462 prefetch(&hw->st_le[hw->st_idx]);
2463 if (likely(__netif_rx_schedule_prep(dev0)))
2464 __netif_rx_schedule(dev0);
2465
2466 return IRQ_HANDLED;
2467 }
2468
2469 #ifdef CONFIG_NET_POLL_CONTROLLER
2470 static void sky2_netpoll(struct net_device *dev)
2471 {
2472 struct sky2_port *sky2 = netdev_priv(dev);
2473 struct net_device *dev0 = sky2->hw->dev[0];
2474
2475 if (netif_running(dev) && __netif_rx_schedule_prep(dev0))
2476 __netif_rx_schedule(dev0);
2477 }
2478 #endif
2479
2480 /* Chip internal frequency for clock calculations */
2481 static inline u32 sky2_mhz(const struct sky2_hw *hw)
2482 {
2483 switch (hw->chip_id) {
2484 case CHIP_ID_YUKON_EC:
2485 case CHIP_ID_YUKON_EC_U:
2486 case CHIP_ID_YUKON_EX:
2487 return 125; /* 125 Mhz */
2488 case CHIP_ID_YUKON_FE:
2489 return 100; /* 100 Mhz */
2490 default: /* YUKON_XL */
2491 return 156; /* 156 Mhz */
2492 }
2493 }
2494
2495 static inline u32 sky2_us2clk(const struct sky2_hw *hw, u32 us)
2496 {
2497 return sky2_mhz(hw) * us;
2498 }
2499
2500 static inline u32 sky2_clk2us(const struct sky2_hw *hw, u32 clk)
2501 {
2502 return clk / sky2_mhz(hw);
2503 }
2504
2505
2506 static int __devinit sky2_init(struct sky2_hw *hw)
2507 {
2508 u8 t8;
2509
2510 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2511
2512 hw->chip_id = sky2_read8(hw, B2_CHIP_ID);
2513 if (hw->chip_id < CHIP_ID_YUKON_XL || hw->chip_id > CHIP_ID_YUKON_FE) {
2514 dev_err(&hw->pdev->dev, "unsupported chip type 0x%x\n",
2515 hw->chip_id);
2516 return -EOPNOTSUPP;
2517 }
2518
2519 if (hw->chip_id == CHIP_ID_YUKON_EX)
2520 dev_warn(&hw->pdev->dev, "this driver not yet tested on this chip type\n"
2521 "Please report success or failure to <netdev@vger.kernel.org>\n");
2522
2523 /* Make sure and enable all clocks */
2524 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
2525 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
2526
2527 hw->chip_rev = (sky2_read8(hw, B2_MAC_CFG) & CFG_CHIP_R_MSK) >> 4;
2528
2529 /* This rev is really old, and requires untested workarounds */
2530 if (hw->chip_id == CHIP_ID_YUKON_EC && hw->chip_rev == CHIP_REV_YU_EC_A1) {
2531 dev_err(&hw->pdev->dev, "unsupported revision Yukon-%s (0x%x) rev %d\n",
2532 yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
2533 hw->chip_id, hw->chip_rev);
2534 return -EOPNOTSUPP;
2535 }
2536
2537
2538 /* Some Gigabyte motherboards have 88e8056 but cause problems
2539 * There is some unresolved hardware related problem that causes
2540 * descriptor errors and receive data corruption.
2541 */
2542 if (hw->chip_id == CHIP_ID_YUKON_EC_U && dmi_blacklisted) {
2543 dev_err(&hw->pdev->dev,
2544 "88E8056 on this motherboard not supported\n");
2545 return -EOPNOTSUPP;
2546 }
2547
2548 hw->pmd_type = sky2_read8(hw, B2_PMD_TYP);
2549 hw->ports = 1;
2550 t8 = sky2_read8(hw, B2_Y2_HW_RES);
2551 if ((t8 & CFG_DUAL_MAC_MSK) == CFG_DUAL_MAC_MSK) {
2552 if (!(sky2_read8(hw, B2_Y2_CLK_GATE) & Y2_STATUS_LNK2_INAC))
2553 ++hw->ports;
2554 }
2555
2556 return 0;
2557 }
2558
2559 static void sky2_reset(struct sky2_hw *hw)
2560 {
2561 u16 status;
2562 int i;
2563
2564 /* disable ASF */
2565 if (hw->chip_id == CHIP_ID_YUKON_EX) {
2566 status = sky2_read16(hw, HCU_CCSR);
2567 status &= ~(HCU_CCSR_AHB_RST | HCU_CCSR_CPU_RST_MODE |
2568 HCU_CCSR_UC_STATE_MSK);
2569 sky2_write16(hw, HCU_CCSR, status);
2570 } else
2571 sky2_write8(hw, B28_Y2_ASF_STAT_CMD, Y2_ASF_RESET);
2572 sky2_write16(hw, B0_CTST, Y2_ASF_DISABLE);
2573
2574 /* do a SW reset */
2575 sky2_write8(hw, B0_CTST, CS_RST_SET);
2576 sky2_write8(hw, B0_CTST, CS_RST_CLR);
2577
2578 /* clear PCI errors, if any */
2579 status = sky2_pci_read16(hw, PCI_STATUS);
2580
2581 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_ON);
2582 sky2_pci_write16(hw, PCI_STATUS, status | PCI_STATUS_ERROR_BITS);
2583
2584
2585 sky2_write8(hw, B0_CTST, CS_MRST_CLR);
2586
2587 /* clear any PEX errors */
2588 if (pci_find_capability(hw->pdev, PCI_CAP_ID_EXP))
2589 sky2_pci_write32(hw, PEX_UNC_ERR_STAT, 0xffffffffUL);
2590
2591
2592 sky2_power_on(hw);
2593
2594 for (i = 0; i < hw->ports; i++) {
2595 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_SET);
2596 sky2_write8(hw, SK_REG(i, GMAC_LINK_CTRL), GMLC_RST_CLR);
2597 }
2598
2599 sky2_write8(hw, B2_TST_CTRL1, TST_CFG_WRITE_OFF);
2600
2601 /* Clear I2C IRQ noise */
2602 sky2_write32(hw, B2_I2C_IRQ, 1);
2603
2604 /* turn off hardware timer (unused) */
2605 sky2_write8(hw, B2_TI_CTRL, TIM_STOP);
2606 sky2_write8(hw, B2_TI_CTRL, TIM_CLR_IRQ);
2607
2608 sky2_write8(hw, B0_Y2LED, LED_STAT_ON);
2609
2610 /* Turn off descriptor polling */
2611 sky2_write32(hw, B28_DPT_CTRL, DPT_STOP);
2612
2613 /* Turn off receive timestamp */
2614 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_STOP);
2615 sky2_write8(hw, GMAC_TI_ST_CTRL, GMT_ST_CLR_IRQ);
2616
2617 /* enable the Tx Arbiters */
2618 for (i = 0; i < hw->ports; i++)
2619 sky2_write8(hw, SK_REG(i, TXA_CTRL), TXA_ENA_ARB);
2620
2621 /* Initialize ram interface */
2622 for (i = 0; i < hw->ports; i++) {
2623 sky2_write8(hw, RAM_BUFFER(i, B3_RI_CTRL), RI_RST_CLR);
2624
2625 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R1), SK_RI_TO_53);
2626 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA1), SK_RI_TO_53);
2627 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS1), SK_RI_TO_53);
2628 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R1), SK_RI_TO_53);
2629 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA1), SK_RI_TO_53);
2630 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS1), SK_RI_TO_53);
2631 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_R2), SK_RI_TO_53);
2632 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XA2), SK_RI_TO_53);
2633 sky2_write8(hw, RAM_BUFFER(i, B3_RI_WTO_XS2), SK_RI_TO_53);
2634 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_R2), SK_RI_TO_53);
2635 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XA2), SK_RI_TO_53);
2636 sky2_write8(hw, RAM_BUFFER(i, B3_RI_RTO_XS2), SK_RI_TO_53);
2637 }
2638
2639 sky2_write32(hw, B0_HWE_IMSK, Y2_HWE_ALL_MASK);
2640
2641 for (i = 0; i < hw->ports; i++)
2642 sky2_gmac_reset(hw, i);
2643
2644 memset(hw->st_le, 0, STATUS_LE_BYTES);
2645 hw->st_idx = 0;
2646
2647 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_SET);
2648 sky2_write32(hw, STAT_CTRL, SC_STAT_RST_CLR);
2649
2650 sky2_write32(hw, STAT_LIST_ADDR_LO, hw->st_dma);
2651 sky2_write32(hw, STAT_LIST_ADDR_HI, (u64) hw->st_dma >> 32);
2652
2653 /* Set the list last index */
2654 sky2_write16(hw, STAT_LAST_IDX, STATUS_RING_SIZE - 1);
2655
2656 sky2_write16(hw, STAT_TX_IDX_TH, 10);
2657 sky2_write8(hw, STAT_FIFO_WM, 16);
2658
2659 /* set Status-FIFO ISR watermark */
2660 if (hw->chip_id == CHIP_ID_YUKON_XL && hw->chip_rev == 0)
2661 sky2_write8(hw, STAT_FIFO_ISR_WM, 4);
2662 else
2663 sky2_write8(hw, STAT_FIFO_ISR_WM, 16);
2664
2665 sky2_write32(hw, STAT_TX_TIMER_INI, sky2_us2clk(hw, 1000));
2666 sky2_write32(hw, STAT_ISR_TIMER_INI, sky2_us2clk(hw, 20));
2667 sky2_write32(hw, STAT_LEV_TIMER_INI, sky2_us2clk(hw, 100));
2668
2669 /* enable status unit */
2670 sky2_write32(hw, STAT_CTRL, SC_STAT_OP_ON);
2671
2672 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
2673 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
2674 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
2675 }
2676
2677 static void sky2_restart(struct work_struct *work)
2678 {
2679 struct sky2_hw *hw = container_of(work, struct sky2_hw, restart_work);
2680 struct net_device *dev;
2681 int i, err;
2682
2683 dev_dbg(&hw->pdev->dev, "restarting\n");
2684
2685 del_timer_sync(&hw->idle_timer);
2686
2687 rtnl_lock();
2688 sky2_write32(hw, B0_IMSK, 0);
2689 sky2_read32(hw, B0_IMSK);
2690
2691 netif_poll_disable(hw->dev[0]);
2692
2693 for (i = 0; i < hw->ports; i++) {
2694 dev = hw->dev[i];
2695 if (netif_running(dev))
2696 sky2_down(dev);
2697 }
2698
2699 sky2_reset(hw);
2700 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
2701 netif_poll_enable(hw->dev[0]);
2702
2703 for (i = 0; i < hw->ports; i++) {
2704 dev = hw->dev[i];
2705 if (netif_running(dev)) {
2706 err = sky2_up(dev);
2707 if (err) {
2708 printk(KERN_INFO PFX "%s: could not restart %d\n",
2709 dev->name, err);
2710 dev_close(dev);
2711 }
2712 }
2713 }
2714
2715 sky2_idle_start(hw);
2716
2717 rtnl_unlock();
2718 }
2719
2720 static inline u8 sky2_wol_supported(const struct sky2_hw *hw)
2721 {
2722 return sky2_is_copper(hw) ? (WAKE_PHY | WAKE_MAGIC) : 0;
2723 }
2724
2725 static void sky2_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2726 {
2727 const struct sky2_port *sky2 = netdev_priv(dev);
2728
2729 wol->supported = sky2_wol_supported(sky2->hw);
2730 wol->wolopts = sky2->wol;
2731 }
2732
2733 static int sky2_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2734 {
2735 struct sky2_port *sky2 = netdev_priv(dev);
2736 struct sky2_hw *hw = sky2->hw;
2737
2738 if (wol->wolopts & ~sky2_wol_supported(sky2->hw))
2739 return -EOPNOTSUPP;
2740
2741 sky2->wol = wol->wolopts;
2742
2743 if (hw->chip_id == CHIP_ID_YUKON_EC_U)
2744 sky2_write32(hw, B0_CTST, sky2->wol
2745 ? Y2_HW_WOL_ON : Y2_HW_WOL_OFF);
2746
2747 if (!netif_running(dev))
2748 sky2_wol_init(sky2);
2749 return 0;
2750 }
2751
2752 static u32 sky2_supported_modes(const struct sky2_hw *hw)
2753 {
2754 if (sky2_is_copper(hw)) {
2755 u32 modes = SUPPORTED_10baseT_Half
2756 | SUPPORTED_10baseT_Full
2757 | SUPPORTED_100baseT_Half
2758 | SUPPORTED_100baseT_Full
2759 | SUPPORTED_Autoneg | SUPPORTED_TP;
2760
2761 if (hw->chip_id != CHIP_ID_YUKON_FE)
2762 modes |= SUPPORTED_1000baseT_Half
2763 | SUPPORTED_1000baseT_Full;
2764 return modes;
2765 } else
2766 return SUPPORTED_1000baseT_Half
2767 | SUPPORTED_1000baseT_Full
2768 | SUPPORTED_Autoneg
2769 | SUPPORTED_FIBRE;
2770 }
2771
2772 static int sky2_get_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2773 {
2774 struct sky2_port *sky2 = netdev_priv(dev);
2775 struct sky2_hw *hw = sky2->hw;
2776
2777 ecmd->transceiver = XCVR_INTERNAL;
2778 ecmd->supported = sky2_supported_modes(hw);
2779 ecmd->phy_address = PHY_ADDR_MARV;
2780 if (sky2_is_copper(hw)) {
2781 ecmd->supported = SUPPORTED_10baseT_Half
2782 | SUPPORTED_10baseT_Full
2783 | SUPPORTED_100baseT_Half
2784 | SUPPORTED_100baseT_Full
2785 | SUPPORTED_1000baseT_Half
2786 | SUPPORTED_1000baseT_Full
2787 | SUPPORTED_Autoneg | SUPPORTED_TP;
2788 ecmd->port = PORT_TP;
2789 ecmd->speed = sky2->speed;
2790 } else {
2791 ecmd->speed = SPEED_1000;
2792 ecmd->port = PORT_FIBRE;
2793 }
2794
2795 ecmd->advertising = sky2->advertising;
2796 ecmd->autoneg = sky2->autoneg;
2797 ecmd->duplex = sky2->duplex;
2798 return 0;
2799 }
2800
2801 static int sky2_set_settings(struct net_device *dev, struct ethtool_cmd *ecmd)
2802 {
2803 struct sky2_port *sky2 = netdev_priv(dev);
2804 const struct sky2_hw *hw = sky2->hw;
2805 u32 supported = sky2_supported_modes(hw);
2806
2807 if (ecmd->autoneg == AUTONEG_ENABLE) {
2808 ecmd->advertising = supported;
2809 sky2->duplex = -1;
2810 sky2->speed = -1;
2811 } else {
2812 u32 setting;
2813
2814 switch (ecmd->speed) {
2815 case SPEED_1000:
2816 if (ecmd->duplex == DUPLEX_FULL)
2817 setting = SUPPORTED_1000baseT_Full;
2818 else if (ecmd->duplex == DUPLEX_HALF)
2819 setting = SUPPORTED_1000baseT_Half;
2820 else
2821 return -EINVAL;
2822 break;
2823 case SPEED_100:
2824 if (ecmd->duplex == DUPLEX_FULL)
2825 setting = SUPPORTED_100baseT_Full;
2826 else if (ecmd->duplex == DUPLEX_HALF)
2827 setting = SUPPORTED_100baseT_Half;
2828 else
2829 return -EINVAL;
2830 break;
2831
2832 case SPEED_10:
2833 if (ecmd->duplex == DUPLEX_FULL)
2834 setting = SUPPORTED_10baseT_Full;
2835 else if (ecmd->duplex == DUPLEX_HALF)
2836 setting = SUPPORTED_10baseT_Half;
2837 else
2838 return -EINVAL;
2839 break;
2840 default:
2841 return -EINVAL;
2842 }
2843
2844 if ((setting & supported) == 0)
2845 return -EINVAL;
2846
2847 sky2->speed = ecmd->speed;
2848 sky2->duplex = ecmd->duplex;
2849 }
2850
2851 sky2->autoneg = ecmd->autoneg;
2852 sky2->advertising = ecmd->advertising;
2853
2854 if (netif_running(dev))
2855 sky2_phy_reinit(sky2);
2856
2857 return 0;
2858 }
2859
2860 static void sky2_get_drvinfo(struct net_device *dev,
2861 struct ethtool_drvinfo *info)
2862 {
2863 struct sky2_port *sky2 = netdev_priv(dev);
2864
2865 strcpy(info->driver, DRV_NAME);
2866 strcpy(info->version, DRV_VERSION);
2867 strcpy(info->fw_version, "N/A");
2868 strcpy(info->bus_info, pci_name(sky2->hw->pdev));
2869 }
2870
2871 static const struct sky2_stat {
2872 char name[ETH_GSTRING_LEN];
2873 u16 offset;
2874 } sky2_stats[] = {
2875 { "tx_bytes", GM_TXO_OK_HI },
2876 { "rx_bytes", GM_RXO_OK_HI },
2877 { "tx_broadcast", GM_TXF_BC_OK },
2878 { "rx_broadcast", GM_RXF_BC_OK },
2879 { "tx_multicast", GM_TXF_MC_OK },
2880 { "rx_multicast", GM_RXF_MC_OK },
2881 { "tx_unicast", GM_TXF_UC_OK },
2882 { "rx_unicast", GM_RXF_UC_OK },
2883 { "tx_mac_pause", GM_TXF_MPAUSE },
2884 { "rx_mac_pause", GM_RXF_MPAUSE },
2885 { "collisions", GM_TXF_COL },
2886 { "late_collision",GM_TXF_LAT_COL },
2887 { "aborted", GM_TXF_ABO_COL },
2888 { "single_collisions", GM_TXF_SNG_COL },
2889 { "multi_collisions", GM_TXF_MUL_COL },
2890
2891 { "rx_short", GM_RXF_SHT },
2892 { "rx_runt", GM_RXE_FRAG },
2893 { "rx_64_byte_packets", GM_RXF_64B },
2894 { "rx_65_to_127_byte_packets", GM_RXF_127B },
2895 { "rx_128_to_255_byte_packets", GM_RXF_255B },
2896 { "rx_256_to_511_byte_packets", GM_RXF_511B },
2897 { "rx_512_to_1023_byte_packets", GM_RXF_1023B },
2898 { "rx_1024_to_1518_byte_packets", GM_RXF_1518B },
2899 { "rx_1518_to_max_byte_packets", GM_RXF_MAX_SZ },
2900 { "rx_too_long", GM_RXF_LNG_ERR },
2901 { "rx_fifo_overflow", GM_RXE_FIFO_OV },
2902 { "rx_jabber", GM_RXF_JAB_PKT },
2903 { "rx_fcs_error", GM_RXF_FCS_ERR },
2904
2905 { "tx_64_byte_packets", GM_TXF_64B },
2906 { "tx_65_to_127_byte_packets", GM_TXF_127B },
2907 { "tx_128_to_255_byte_packets", GM_TXF_255B },
2908 { "tx_256_to_511_byte_packets", GM_TXF_511B },
2909 { "tx_512_to_1023_byte_packets", GM_TXF_1023B },
2910 { "tx_1024_to_1518_byte_packets", GM_TXF_1518B },
2911 { "tx_1519_to_max_byte_packets", GM_TXF_MAX_SZ },
2912 { "tx_fifo_underrun", GM_TXE_FIFO_UR },
2913 };
2914
2915 static u32 sky2_get_rx_csum(struct net_device *dev)
2916 {
2917 struct sky2_port *sky2 = netdev_priv(dev);
2918
2919 return sky2->rx_csum;
2920 }
2921
2922 static int sky2_set_rx_csum(struct net_device *dev, u32 data)
2923 {
2924 struct sky2_port *sky2 = netdev_priv(dev);
2925
2926 sky2->rx_csum = data;
2927
2928 sky2_write32(sky2->hw, Q_ADDR(rxqaddr[sky2->port], Q_CSR),
2929 data ? BMU_ENA_RX_CHKSUM : BMU_DIS_RX_CHKSUM);
2930
2931 return 0;
2932 }
2933
2934 static u32 sky2_get_msglevel(struct net_device *netdev)
2935 {
2936 struct sky2_port *sky2 = netdev_priv(netdev);
2937 return sky2->msg_enable;
2938 }
2939
2940 static int sky2_nway_reset(struct net_device *dev)
2941 {
2942 struct sky2_port *sky2 = netdev_priv(dev);
2943
2944 if (!netif_running(dev) || sky2->autoneg != AUTONEG_ENABLE)
2945 return -EINVAL;
2946
2947 sky2_phy_reinit(sky2);
2948
2949 return 0;
2950 }
2951
2952 static void sky2_phy_stats(struct sky2_port *sky2, u64 * data, unsigned count)
2953 {
2954 struct sky2_hw *hw = sky2->hw;
2955 unsigned port = sky2->port;
2956 int i;
2957
2958 data[0] = (u64) gma_read32(hw, port, GM_TXO_OK_HI) << 32
2959 | (u64) gma_read32(hw, port, GM_TXO_OK_LO);
2960 data[1] = (u64) gma_read32(hw, port, GM_RXO_OK_HI) << 32
2961 | (u64) gma_read32(hw, port, GM_RXO_OK_LO);
2962
2963 for (i = 2; i < count; i++)
2964 data[i] = (u64) gma_read32(hw, port, sky2_stats[i].offset);
2965 }
2966
2967 static void sky2_set_msglevel(struct net_device *netdev, u32 value)
2968 {
2969 struct sky2_port *sky2 = netdev_priv(netdev);
2970 sky2->msg_enable = value;
2971 }
2972
2973 static int sky2_get_stats_count(struct net_device *dev)
2974 {
2975 return ARRAY_SIZE(sky2_stats);
2976 }
2977
2978 static void sky2_get_ethtool_stats(struct net_device *dev,
2979 struct ethtool_stats *stats, u64 * data)
2980 {
2981 struct sky2_port *sky2 = netdev_priv(dev);
2982
2983 sky2_phy_stats(sky2, data, ARRAY_SIZE(sky2_stats));
2984 }
2985
2986 static void sky2_get_strings(struct net_device *dev, u32 stringset, u8 * data)
2987 {
2988 int i;
2989
2990 switch (stringset) {
2991 case ETH_SS_STATS:
2992 for (i = 0; i < ARRAY_SIZE(sky2_stats); i++)
2993 memcpy(data + i * ETH_GSTRING_LEN,
2994 sky2_stats[i].name, ETH_GSTRING_LEN);
2995 break;
2996 }
2997 }
2998
2999 static struct net_device_stats *sky2_get_stats(struct net_device *dev)
3000 {
3001 struct sky2_port *sky2 = netdev_priv(dev);
3002 return &sky2->net_stats;
3003 }
3004
3005 static int sky2_set_mac_address(struct net_device *dev, void *p)
3006 {
3007 struct sky2_port *sky2 = netdev_priv(dev);
3008 struct sky2_hw *hw = sky2->hw;
3009 unsigned port = sky2->port;
3010 const struct sockaddr *addr = p;
3011
3012 if (!is_valid_ether_addr(addr->sa_data))
3013 return -EADDRNOTAVAIL;
3014
3015 memcpy(dev->dev_addr, addr->sa_data, ETH_ALEN);
3016 memcpy_toio(hw->regs + B2_MAC_1 + port * 8,
3017 dev->dev_addr, ETH_ALEN);
3018 memcpy_toio(hw->regs + B2_MAC_2 + port * 8,
3019 dev->dev_addr, ETH_ALEN);
3020
3021 /* virtual address for data */
3022 gma_set_addr(hw, port, GM_SRC_ADDR_2L, dev->dev_addr);
3023
3024 /* physical address: used for pause frames */
3025 gma_set_addr(hw, port, GM_SRC_ADDR_1L, dev->dev_addr);
3026
3027 return 0;
3028 }
3029
3030 static void inline sky2_add_filter(u8 filter[8], const u8 *addr)
3031 {
3032 u32 bit;
3033
3034 bit = ether_crc(ETH_ALEN, addr) & 63;
3035 filter[bit >> 3] |= 1 << (bit & 7);
3036 }
3037
3038 static void sky2_set_multicast(struct net_device *dev)
3039 {
3040 struct sky2_port *sky2 = netdev_priv(dev);
3041 struct sky2_hw *hw = sky2->hw;
3042 unsigned port = sky2->port;
3043 struct dev_mc_list *list = dev->mc_list;
3044 u16 reg;
3045 u8 filter[8];
3046 int rx_pause;
3047 static const u8 pause_mc_addr[ETH_ALEN] = { 0x1, 0x80, 0xc2, 0x0, 0x0, 0x1 };
3048
3049 rx_pause = (sky2->flow_status == FC_RX || sky2->flow_status == FC_BOTH);
3050 memset(filter, 0, sizeof(filter));
3051
3052 reg = gma_read16(hw, port, GM_RX_CTRL);
3053 reg |= GM_RXCR_UCF_ENA;
3054
3055 if (dev->flags & IFF_PROMISC) /* promiscuous */
3056 reg &= ~(GM_RXCR_UCF_ENA | GM_RXCR_MCF_ENA);
3057 else if (dev->flags & IFF_ALLMULTI)
3058 memset(filter, 0xff, sizeof(filter));
3059 else if (dev->mc_count == 0 && !rx_pause)
3060 reg &= ~GM_RXCR_MCF_ENA;
3061 else {
3062 int i;
3063 reg |= GM_RXCR_MCF_ENA;
3064
3065 if (rx_pause)
3066 sky2_add_filter(filter, pause_mc_addr);
3067
3068 for (i = 0; list && i < dev->mc_count; i++, list = list->next)
3069 sky2_add_filter(filter, list->dmi_addr);
3070 }
3071
3072 gma_write16(hw, port, GM_MC_ADDR_H1,
3073 (u16) filter[0] | ((u16) filter[1] << 8));
3074 gma_write16(hw, port, GM_MC_ADDR_H2,
3075 (u16) filter[2] | ((u16) filter[3] << 8));
3076 gma_write16(hw, port, GM_MC_ADDR_H3,
3077 (u16) filter[4] | ((u16) filter[5] << 8));
3078 gma_write16(hw, port, GM_MC_ADDR_H4,
3079 (u16) filter[6] | ((u16) filter[7] << 8));
3080
3081 gma_write16(hw, port, GM_RX_CTRL, reg);
3082 }
3083
3084 /* Can have one global because blinking is controlled by
3085 * ethtool and that is always under RTNL mutex
3086 */
3087 static void sky2_led(struct sky2_hw *hw, unsigned port, int on)
3088 {
3089 u16 pg;
3090
3091 switch (hw->chip_id) {
3092 case CHIP_ID_YUKON_XL:
3093 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3094 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3095 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL,
3096 on ? (PHY_M_LEDC_LOS_CTRL(1) |
3097 PHY_M_LEDC_INIT_CTRL(7) |
3098 PHY_M_LEDC_STA1_CTRL(7) |
3099 PHY_M_LEDC_STA0_CTRL(7))
3100 : 0);
3101
3102 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3103 break;
3104
3105 default:
3106 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, 0);
3107 gm_phy_write(hw, port, PHY_MARV_LED_OVER,
3108 on ? PHY_M_LED_ALL : 0);
3109 }
3110 }
3111
3112 /* blink LED's for finding board */
3113 static int sky2_phys_id(struct net_device *dev, u32 data)
3114 {
3115 struct sky2_port *sky2 = netdev_priv(dev);
3116 struct sky2_hw *hw = sky2->hw;
3117 unsigned port = sky2->port;
3118 u16 ledctrl, ledover = 0;
3119 long ms;
3120 int interrupted;
3121 int onoff = 1;
3122
3123 if (!data || data > (u32) (MAX_SCHEDULE_TIMEOUT / HZ))
3124 ms = jiffies_to_msecs(MAX_SCHEDULE_TIMEOUT);
3125 else
3126 ms = data * 1000;
3127
3128 /* save initial values */
3129 spin_lock_bh(&sky2->phy_lock);
3130 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3131 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3132 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3133 ledctrl = gm_phy_read(hw, port, PHY_MARV_PHY_CTRL);
3134 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3135 } else {
3136 ledctrl = gm_phy_read(hw, port, PHY_MARV_LED_CTRL);
3137 ledover = gm_phy_read(hw, port, PHY_MARV_LED_OVER);
3138 }
3139
3140 interrupted = 0;
3141 while (!interrupted && ms > 0) {
3142 sky2_led(hw, port, onoff);
3143 onoff = !onoff;
3144
3145 spin_unlock_bh(&sky2->phy_lock);
3146 interrupted = msleep_interruptible(250);
3147 spin_lock_bh(&sky2->phy_lock);
3148
3149 ms -= 250;
3150 }
3151
3152 /* resume regularly scheduled programming */
3153 if (hw->chip_id == CHIP_ID_YUKON_XL) {
3154 u16 pg = gm_phy_read(hw, port, PHY_MARV_EXT_ADR);
3155 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, 3);
3156 gm_phy_write(hw, port, PHY_MARV_PHY_CTRL, ledctrl);
3157 gm_phy_write(hw, port, PHY_MARV_EXT_ADR, pg);
3158 } else {
3159 gm_phy_write(hw, port, PHY_MARV_LED_CTRL, ledctrl);
3160 gm_phy_write(hw, port, PHY_MARV_LED_OVER, ledover);
3161 }
3162 spin_unlock_bh(&sky2->phy_lock);
3163
3164 return 0;
3165 }
3166
3167 static void sky2_get_pauseparam(struct net_device *dev,
3168 struct ethtool_pauseparam *ecmd)
3169 {
3170 struct sky2_port *sky2 = netdev_priv(dev);
3171
3172 switch (sky2->flow_mode) {
3173 case FC_NONE:
3174 ecmd->tx_pause = ecmd->rx_pause = 0;
3175 break;
3176 case FC_TX:
3177 ecmd->tx_pause = 1, ecmd->rx_pause = 0;
3178 break;
3179 case FC_RX:
3180 ecmd->tx_pause = 0, ecmd->rx_pause = 1;
3181 break;
3182 case FC_BOTH:
3183 ecmd->tx_pause = ecmd->rx_pause = 1;
3184 }
3185
3186 ecmd->autoneg = sky2->autoneg;
3187 }
3188
3189 static int sky2_set_pauseparam(struct net_device *dev,
3190 struct ethtool_pauseparam *ecmd)
3191 {
3192 struct sky2_port *sky2 = netdev_priv(dev);
3193
3194 sky2->autoneg = ecmd->autoneg;
3195 sky2->flow_mode = sky2_flow(ecmd->rx_pause, ecmd->tx_pause);
3196
3197 if (netif_running(dev))
3198 sky2_phy_reinit(sky2);
3199
3200 return 0;
3201 }
3202
3203 static int sky2_get_coalesce(struct net_device *dev,
3204 struct ethtool_coalesce *ecmd)
3205 {
3206 struct sky2_port *sky2 = netdev_priv(dev);
3207 struct sky2_hw *hw = sky2->hw;
3208
3209 if (sky2_read8(hw, STAT_TX_TIMER_CTRL) == TIM_STOP)
3210 ecmd->tx_coalesce_usecs = 0;
3211 else {
3212 u32 clks = sky2_read32(hw, STAT_TX_TIMER_INI);
3213 ecmd->tx_coalesce_usecs = sky2_clk2us(hw, clks);
3214 }
3215 ecmd->tx_max_coalesced_frames = sky2_read16(hw, STAT_TX_IDX_TH);
3216
3217 if (sky2_read8(hw, STAT_LEV_TIMER_CTRL) == TIM_STOP)
3218 ecmd->rx_coalesce_usecs = 0;
3219 else {
3220 u32 clks = sky2_read32(hw, STAT_LEV_TIMER_INI);
3221 ecmd->rx_coalesce_usecs = sky2_clk2us(hw, clks);
3222 }
3223 ecmd->rx_max_coalesced_frames = sky2_read8(hw, STAT_FIFO_WM);
3224
3225 if (sky2_read8(hw, STAT_ISR_TIMER_CTRL) == TIM_STOP)
3226 ecmd->rx_coalesce_usecs_irq = 0;
3227 else {
3228 u32 clks = sky2_read32(hw, STAT_ISR_TIMER_INI);
3229 ecmd->rx_coalesce_usecs_irq = sky2_clk2us(hw, clks);
3230 }
3231
3232 ecmd->rx_max_coalesced_frames_irq = sky2_read8(hw, STAT_FIFO_ISR_WM);
3233
3234 return 0;
3235 }
3236
3237 /* Note: this affect both ports */
3238 static int sky2_set_coalesce(struct net_device *dev,
3239 struct ethtool_coalesce *ecmd)
3240 {
3241 struct sky2_port *sky2 = netdev_priv(dev);
3242 struct sky2_hw *hw = sky2->hw;
3243 const u32 tmax = sky2_clk2us(hw, 0x0ffffff);
3244
3245 if (ecmd->tx_coalesce_usecs > tmax ||
3246 ecmd->rx_coalesce_usecs > tmax ||
3247 ecmd->rx_coalesce_usecs_irq > tmax)
3248 return -EINVAL;
3249
3250 if (ecmd->tx_max_coalesced_frames >= TX_RING_SIZE-1)
3251 return -EINVAL;
3252 if (ecmd->rx_max_coalesced_frames > RX_MAX_PENDING)
3253 return -EINVAL;
3254 if (ecmd->rx_max_coalesced_frames_irq >RX_MAX_PENDING)
3255 return -EINVAL;
3256
3257 if (ecmd->tx_coalesce_usecs == 0)
3258 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_STOP);
3259 else {
3260 sky2_write32(hw, STAT_TX_TIMER_INI,
3261 sky2_us2clk(hw, ecmd->tx_coalesce_usecs));
3262 sky2_write8(hw, STAT_TX_TIMER_CTRL, TIM_START);
3263 }
3264 sky2_write16(hw, STAT_TX_IDX_TH, ecmd->tx_max_coalesced_frames);
3265
3266 if (ecmd->rx_coalesce_usecs == 0)
3267 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_STOP);
3268 else {
3269 sky2_write32(hw, STAT_LEV_TIMER_INI,
3270 sky2_us2clk(hw, ecmd->rx_coalesce_usecs));
3271 sky2_write8(hw, STAT_LEV_TIMER_CTRL, TIM_START);
3272 }
3273 sky2_write8(hw, STAT_FIFO_WM, ecmd->rx_max_coalesced_frames);
3274
3275 if (ecmd->rx_coalesce_usecs_irq == 0)
3276 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_STOP);
3277 else {
3278 sky2_write32(hw, STAT_ISR_TIMER_INI,
3279 sky2_us2clk(hw, ecmd->rx_coalesce_usecs_irq));
3280 sky2_write8(hw, STAT_ISR_TIMER_CTRL, TIM_START);
3281 }
3282 sky2_write8(hw, STAT_FIFO_ISR_WM, ecmd->rx_max_coalesced_frames_irq);
3283 return 0;
3284 }
3285
3286 static void sky2_get_ringparam(struct net_device *dev,
3287 struct ethtool_ringparam *ering)
3288 {
3289 struct sky2_port *sky2 = netdev_priv(dev);
3290
3291 ering->rx_max_pending = RX_MAX_PENDING;
3292 ering->rx_mini_max_pending = 0;
3293 ering->rx_jumbo_max_pending = 0;
3294 ering->tx_max_pending = TX_RING_SIZE - 1;
3295
3296 ering->rx_pending = sky2->rx_pending;
3297 ering->rx_mini_pending = 0;
3298 ering->rx_jumbo_pending = 0;
3299 ering->tx_pending = sky2->tx_pending;
3300 }
3301
3302 static int sky2_set_ringparam(struct net_device *dev,
3303 struct ethtool_ringparam *ering)
3304 {
3305 struct sky2_port *sky2 = netdev_priv(dev);
3306 int err = 0;
3307
3308 if (ering->rx_pending > RX_MAX_PENDING ||
3309 ering->rx_pending < 8 ||
3310 ering->tx_pending < MAX_SKB_TX_LE ||
3311 ering->tx_pending > TX_RING_SIZE - 1)
3312 return -EINVAL;
3313
3314 if (netif_running(dev))
3315 sky2_down(dev);
3316
3317 sky2->rx_pending = ering->rx_pending;
3318 sky2->tx_pending = ering->tx_pending;
3319
3320 if (netif_running(dev)) {
3321 err = sky2_up(dev);
3322 if (err)
3323 dev_close(dev);
3324 else
3325 sky2_set_multicast(dev);
3326 }
3327
3328 return err;
3329 }
3330
3331 static int sky2_get_regs_len(struct net_device *dev)
3332 {
3333 return 0x4000;
3334 }
3335
3336 /*
3337 * Returns copy of control register region
3338 * Note: access to the RAM address register set will cause timeouts.
3339 */
3340 static void sky2_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3341 void *p)
3342 {
3343 const struct sky2_port *sky2 = netdev_priv(dev);
3344 const void __iomem *io = sky2->hw->regs;
3345
3346 BUG_ON(regs->len < B3_RI_WTO_R1);
3347 regs->version = 1;
3348 memset(p, 0, regs->len);
3349
3350 memcpy_fromio(p, io, B3_RAM_ADDR);
3351
3352 memcpy_fromio(p + B3_RI_WTO_R1,
3353 io + B3_RI_WTO_R1,
3354 regs->len - B3_RI_WTO_R1);
3355 }
3356
3357 /* In order to do Jumbo packets on these chips, need to turn off the
3358 * transmit store/forward. Therefore checksum offload won't work.
3359 */
3360 static int no_tx_offload(struct net_device *dev)
3361 {
3362 const struct sky2_port *sky2 = netdev_priv(dev);
3363 const struct sky2_hw *hw = sky2->hw;
3364
3365 return dev->mtu > ETH_DATA_LEN &&
3366 (hw->chip_id == CHIP_ID_YUKON_EX
3367 || hw->chip_id == CHIP_ID_YUKON_EC_U);
3368 }
3369
3370 static int sky2_set_tx_csum(struct net_device *dev, u32 data)
3371 {
3372 if (data && no_tx_offload(dev))
3373 return -EINVAL;
3374
3375 return ethtool_op_set_tx_csum(dev, data);
3376 }
3377
3378
3379 static int sky2_set_tso(struct net_device *dev, u32 data)
3380 {
3381 if (data && no_tx_offload(dev))
3382 return -EINVAL;
3383
3384 return ethtool_op_set_tso(dev, data);
3385 }
3386
3387 static const struct ethtool_ops sky2_ethtool_ops = {
3388 .get_settings = sky2_get_settings,
3389 .set_settings = sky2_set_settings,
3390 .get_drvinfo = sky2_get_drvinfo,
3391 .get_wol = sky2_get_wol,
3392 .set_wol = sky2_set_wol,
3393 .get_msglevel = sky2_get_msglevel,
3394 .set_msglevel = sky2_set_msglevel,
3395 .nway_reset = sky2_nway_reset,
3396 .get_regs_len = sky2_get_regs_len,
3397 .get_regs = sky2_get_regs,
3398 .get_link = ethtool_op_get_link,
3399 .get_sg = ethtool_op_get_sg,
3400 .set_sg = ethtool_op_set_sg,
3401 .get_tx_csum = ethtool_op_get_tx_csum,
3402 .set_tx_csum = sky2_set_tx_csum,
3403 .get_tso = ethtool_op_get_tso,
3404 .set_tso = sky2_set_tso,
3405 .get_rx_csum = sky2_get_rx_csum,
3406 .set_rx_csum = sky2_set_rx_csum,
3407 .get_strings = sky2_get_strings,
3408 .get_coalesce = sky2_get_coalesce,
3409 .set_coalesce = sky2_set_coalesce,
3410 .get_ringparam = sky2_get_ringparam,
3411 .set_ringparam = sky2_set_ringparam,
3412 .get_pauseparam = sky2_get_pauseparam,
3413 .set_pauseparam = sky2_set_pauseparam,
3414 .phys_id = sky2_phys_id,
3415 .get_stats_count = sky2_get_stats_count,
3416 .get_ethtool_stats = sky2_get_ethtool_stats,
3417 .get_perm_addr = ethtool_op_get_perm_addr,
3418 };
3419
3420 /* Initialize network device */
3421 static __devinit struct net_device *sky2_init_netdev(struct sky2_hw *hw,
3422 unsigned port,
3423 int highmem, int wol)
3424 {
3425 struct sky2_port *sky2;
3426 struct net_device *dev = alloc_etherdev(sizeof(*sky2));
3427
3428 if (!dev) {
3429 dev_err(&hw->pdev->dev, "etherdev alloc failed");
3430 return NULL;
3431 }
3432
3433 SET_MODULE_OWNER(dev);
3434 SET_NETDEV_DEV(dev, &hw->pdev->dev);
3435 dev->irq = hw->pdev->irq;
3436 dev->open = sky2_up;
3437 dev->stop = sky2_down;
3438 dev->do_ioctl = sky2_ioctl;
3439 dev->hard_start_xmit = sky2_xmit_frame;
3440 dev->get_stats = sky2_get_stats;
3441 dev->set_multicast_list = sky2_set_multicast;
3442 dev->set_mac_address = sky2_set_mac_address;
3443 dev->change_mtu = sky2_change_mtu;
3444 SET_ETHTOOL_OPS(dev, &sky2_ethtool_ops);
3445 dev->tx_timeout = sky2_tx_timeout;
3446 dev->watchdog_timeo = TX_WATCHDOG;
3447 if (port == 0)
3448 dev->poll = sky2_poll;
3449 dev->weight = NAPI_WEIGHT;
3450 #ifdef CONFIG_NET_POLL_CONTROLLER
3451 /* Network console (only works on port 0)
3452 * because netpoll makes assumptions about NAPI
3453 */
3454 if (port == 0)
3455 dev->poll_controller = sky2_netpoll;
3456 #endif
3457
3458 sky2 = netdev_priv(dev);
3459 sky2->netdev = dev;
3460 sky2->hw = hw;
3461 sky2->msg_enable = netif_msg_init(debug, default_msg);
3462
3463 /* Auto speed and flow control */
3464 sky2->autoneg = AUTONEG_ENABLE;
3465 sky2->flow_mode = FC_BOTH;
3466
3467 sky2->duplex = -1;
3468 sky2->speed = -1;
3469 sky2->advertising = sky2_supported_modes(hw);
3470 sky2->rx_csum = 1;
3471 sky2->wol = wol;
3472
3473 spin_lock_init(&sky2->phy_lock);
3474 sky2->tx_pending = TX_DEF_PENDING;
3475 sky2->rx_pending = RX_DEF_PENDING;
3476
3477 hw->dev[port] = dev;
3478
3479 sky2->port = port;
3480
3481 dev->features |= NETIF_F_TSO | NETIF_F_IP_CSUM | NETIF_F_SG;
3482 if (highmem)
3483 dev->features |= NETIF_F_HIGHDMA;
3484
3485 #ifdef SKY2_VLAN_TAG_USED
3486 dev->features |= NETIF_F_HW_VLAN_TX | NETIF_F_HW_VLAN_RX;
3487 dev->vlan_rx_register = sky2_vlan_rx_register;
3488 dev->vlan_rx_kill_vid = sky2_vlan_rx_kill_vid;
3489 #endif
3490
3491 /* read the mac address */
3492 memcpy_fromio(dev->dev_addr, hw->regs + B2_MAC_1 + port * 8, ETH_ALEN);
3493 memcpy(dev->perm_addr, dev->dev_addr, dev->addr_len);
3494
3495 /* device is off until link detection */
3496 netif_carrier_off(dev);
3497 netif_stop_queue(dev);
3498
3499 return dev;
3500 }
3501
3502 static void __devinit sky2_show_addr(struct net_device *dev)
3503 {
3504 const struct sky2_port *sky2 = netdev_priv(dev);
3505
3506 if (netif_msg_probe(sky2))
3507 printk(KERN_INFO PFX "%s: addr %02x:%02x:%02x:%02x:%02x:%02x\n",
3508 dev->name,
3509 dev->dev_addr[0], dev->dev_addr[1], dev->dev_addr[2],
3510 dev->dev_addr[3], dev->dev_addr[4], dev->dev_addr[5]);
3511 }
3512
3513 /* Handle software interrupt used during MSI test */
3514 static irqreturn_t __devinit sky2_test_intr(int irq, void *dev_id)
3515 {
3516 struct sky2_hw *hw = dev_id;
3517 u32 status = sky2_read32(hw, B0_Y2_SP_ISRC2);
3518
3519 if (status == 0)
3520 return IRQ_NONE;
3521
3522 if (status & Y2_IS_IRQ_SW) {
3523 hw->msi = 1;
3524 wake_up(&hw->msi_wait);
3525 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3526 }
3527 sky2_write32(hw, B0_Y2_SP_ICR, 2);
3528
3529 return IRQ_HANDLED;
3530 }
3531
3532 /* Test interrupt path by forcing a a software IRQ */
3533 static int __devinit sky2_test_msi(struct sky2_hw *hw)
3534 {
3535 struct pci_dev *pdev = hw->pdev;
3536 int err;
3537
3538 init_waitqueue_head (&hw->msi_wait);
3539
3540 sky2_write32(hw, B0_IMSK, Y2_IS_IRQ_SW);
3541
3542 err = request_irq(pdev->irq, sky2_test_intr, 0, DRV_NAME, hw);
3543 if (err) {
3544 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
3545 return err;
3546 }
3547
3548 sky2_write8(hw, B0_CTST, CS_ST_SW_IRQ);
3549 sky2_read8(hw, B0_CTST);
3550
3551 wait_event_timeout(hw->msi_wait, hw->msi, HZ/10);
3552
3553 if (!hw->msi) {
3554 /* MSI test failed, go back to INTx mode */
3555 dev_info(&pdev->dev, "No interrupt generated using MSI, "
3556 "switching to INTx mode.\n");
3557
3558 err = -EOPNOTSUPP;
3559 sky2_write8(hw, B0_CTST, CS_CL_SW_IRQ);
3560 }
3561
3562 sky2_write32(hw, B0_IMSK, 0);
3563 sky2_read32(hw, B0_IMSK);
3564
3565 free_irq(pdev->irq, hw);
3566
3567 return err;
3568 }
3569
3570 static int __devinit pci_wake_enabled(struct pci_dev *dev)
3571 {
3572 int pm = pci_find_capability(dev, PCI_CAP_ID_PM);
3573 u16 value;
3574
3575 if (!pm)
3576 return 0;
3577 if (pci_read_config_word(dev, pm + PCI_PM_CTRL, &value))
3578 return 0;
3579 return value & PCI_PM_CTRL_PME_ENABLE;
3580 }
3581
3582 static int __devinit sky2_probe(struct pci_dev *pdev,
3583 const struct pci_device_id *ent)
3584 {
3585 struct net_device *dev;
3586 struct sky2_hw *hw;
3587 int err, using_dac = 0, wol_default;
3588
3589 err = pci_enable_device(pdev);
3590 if (err) {
3591 dev_err(&pdev->dev, "cannot enable PCI device\n");
3592 goto err_out;
3593 }
3594
3595 err = pci_request_regions(pdev, DRV_NAME);
3596 if (err) {
3597 dev_err(&pdev->dev, "cannot obtain PCI resources\n");
3598 goto err_out_disable;
3599 }
3600
3601 pci_set_master(pdev);
3602
3603 if (sizeof(dma_addr_t) > sizeof(u32) &&
3604 !(err = pci_set_dma_mask(pdev, DMA_64BIT_MASK))) {
3605 using_dac = 1;
3606 err = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3607 if (err < 0) {
3608 dev_err(&pdev->dev, "unable to obtain 64 bit DMA "
3609 "for consistent allocations\n");
3610 goto err_out_free_regions;
3611 }
3612 } else {
3613 err = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3614 if (err) {
3615 dev_err(&pdev->dev, "no usable DMA configuration\n");
3616 goto err_out_free_regions;
3617 }
3618 }
3619
3620 wol_default = pci_wake_enabled(pdev) ? WAKE_MAGIC : 0;
3621
3622 err = -ENOMEM;
3623 hw = kzalloc(sizeof(*hw), GFP_KERNEL);
3624 if (!hw) {
3625 dev_err(&pdev->dev, "cannot allocate hardware struct\n");
3626 goto err_out_free_regions;
3627 }
3628
3629 hw->pdev = pdev;
3630
3631 hw->regs = ioremap_nocache(pci_resource_start(pdev, 0), 0x4000);
3632 if (!hw->regs) {
3633 dev_err(&pdev->dev, "cannot map device registers\n");
3634 goto err_out_free_hw;
3635 }
3636
3637 #ifdef __BIG_ENDIAN
3638 /* The sk98lin vendor driver uses hardware byte swapping but
3639 * this driver uses software swapping.
3640 */
3641 {
3642 u32 reg;
3643 reg = sky2_pci_read32(hw, PCI_DEV_REG2);
3644 reg &= ~PCI_REV_DESC;
3645 sky2_pci_write32(hw, PCI_DEV_REG2, reg);
3646 }
3647 #endif
3648
3649 /* ring for status responses */
3650 hw->st_le = pci_alloc_consistent(hw->pdev, STATUS_LE_BYTES,
3651 &hw->st_dma);
3652 if (!hw->st_le)
3653 goto err_out_iounmap;
3654
3655 err = sky2_init(hw);
3656 if (err)
3657 goto err_out_iounmap;
3658
3659 dev_info(&pdev->dev, "v%s addr 0x%llx irq %d Yukon-%s (0x%x) rev %d\n",
3660 DRV_VERSION, (unsigned long long)pci_resource_start(pdev, 0),
3661 pdev->irq, yukon2_name[hw->chip_id - CHIP_ID_YUKON_XL],
3662 hw->chip_id, hw->chip_rev);
3663
3664 sky2_reset(hw);
3665
3666 dev = sky2_init_netdev(hw, 0, using_dac, wol_default);
3667 if (!dev) {
3668 err = -ENOMEM;
3669 goto err_out_free_pci;
3670 }
3671
3672 if (!disable_msi && pci_enable_msi(pdev) == 0) {
3673 err = sky2_test_msi(hw);
3674 if (err == -EOPNOTSUPP)
3675 pci_disable_msi(pdev);
3676 else if (err)
3677 goto err_out_free_netdev;
3678 }
3679
3680 err = register_netdev(dev);
3681 if (err) {
3682 dev_err(&pdev->dev, "cannot register net device\n");
3683 goto err_out_free_netdev;
3684 }
3685
3686 err = request_irq(pdev->irq, sky2_intr, hw->msi ? 0 : IRQF_SHARED,
3687 dev->name, hw);
3688 if (err) {
3689 dev_err(&pdev->dev, "cannot assign irq %d\n", pdev->irq);
3690 goto err_out_unregister;
3691 }
3692 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3693
3694 sky2_show_addr(dev);
3695
3696 if (hw->ports > 1) {
3697 struct net_device *dev1;
3698
3699 dev1 = sky2_init_netdev(hw, 1, using_dac, wol_default);
3700 if (!dev1)
3701 dev_warn(&pdev->dev, "allocation for second device failed\n");
3702 else if ((err = register_netdev(dev1))) {
3703 dev_warn(&pdev->dev,
3704 "register of second port failed (%d)\n", err);
3705 hw->dev[1] = NULL;
3706 free_netdev(dev1);
3707 } else
3708 sky2_show_addr(dev1);
3709 }
3710
3711 setup_timer(&hw->idle_timer, sky2_idle, (unsigned long) hw);
3712 INIT_WORK(&hw->restart_work, sky2_restart);
3713
3714 sky2_idle_start(hw);
3715
3716 pci_set_drvdata(pdev, hw);
3717
3718 return 0;
3719
3720 err_out_unregister:
3721 if (hw->msi)
3722 pci_disable_msi(pdev);
3723 unregister_netdev(dev);
3724 err_out_free_netdev:
3725 free_netdev(dev);
3726 err_out_free_pci:
3727 sky2_write8(hw, B0_CTST, CS_RST_SET);
3728 pci_free_consistent(hw->pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3729 err_out_iounmap:
3730 iounmap(hw->regs);
3731 err_out_free_hw:
3732 kfree(hw);
3733 err_out_free_regions:
3734 pci_release_regions(pdev);
3735 err_out_disable:
3736 pci_disable_device(pdev);
3737 err_out:
3738 pci_set_drvdata(pdev, NULL);
3739 return err;
3740 }
3741
3742 static void __devexit sky2_remove(struct pci_dev *pdev)
3743 {
3744 struct sky2_hw *hw = pci_get_drvdata(pdev);
3745 struct net_device *dev0, *dev1;
3746
3747 if (!hw)
3748 return;
3749
3750 del_timer_sync(&hw->idle_timer);
3751
3752 flush_scheduled_work();
3753
3754 sky2_write32(hw, B0_IMSK, 0);
3755 synchronize_irq(hw->pdev->irq);
3756
3757 dev0 = hw->dev[0];
3758 dev1 = hw->dev[1];
3759 if (dev1)
3760 unregister_netdev(dev1);
3761 unregister_netdev(dev0);
3762
3763 sky2_power_aux(hw);
3764
3765 sky2_write16(hw, B0_Y2LED, LED_STAT_OFF);
3766 sky2_write8(hw, B0_CTST, CS_RST_SET);
3767 sky2_read8(hw, B0_CTST);
3768
3769 free_irq(pdev->irq, hw);
3770 if (hw->msi)
3771 pci_disable_msi(pdev);
3772 pci_free_consistent(pdev, STATUS_LE_BYTES, hw->st_le, hw->st_dma);
3773 pci_release_regions(pdev);
3774 pci_disable_device(pdev);
3775
3776 if (dev1)
3777 free_netdev(dev1);
3778 free_netdev(dev0);
3779 iounmap(hw->regs);
3780 kfree(hw);
3781
3782 pci_set_drvdata(pdev, NULL);
3783 }
3784
3785 #ifdef CONFIG_PM
3786 static int sky2_suspend(struct pci_dev *pdev, pm_message_t state)
3787 {
3788 struct sky2_hw *hw = pci_get_drvdata(pdev);
3789 int i, wol = 0;
3790
3791 if (!hw)
3792 return 0;
3793
3794 del_timer_sync(&hw->idle_timer);
3795 netif_poll_disable(hw->dev[0]);
3796
3797 for (i = 0; i < hw->ports; i++) {
3798 struct net_device *dev = hw->dev[i];
3799 struct sky2_port *sky2 = netdev_priv(dev);
3800
3801 if (netif_running(dev))
3802 sky2_down(dev);
3803
3804 if (sky2->wol)
3805 sky2_wol_init(sky2);
3806
3807 wol |= sky2->wol;
3808 }
3809
3810 sky2_write32(hw, B0_IMSK, 0);
3811 sky2_power_aux(hw);
3812
3813 pci_save_state(pdev);
3814 pci_enable_wake(pdev, pci_choose_state(pdev, state), wol);
3815 pci_set_power_state(pdev, pci_choose_state(pdev, state));
3816
3817 return 0;
3818 }
3819
3820 static int sky2_resume(struct pci_dev *pdev)
3821 {
3822 struct sky2_hw *hw = pci_get_drvdata(pdev);
3823 int i, err;
3824
3825 if (!hw)
3826 return 0;
3827
3828 err = pci_set_power_state(pdev, PCI_D0);
3829 if (err)
3830 goto out;
3831
3832 err = pci_restore_state(pdev);
3833 if (err)
3834 goto out;
3835
3836 pci_enable_wake(pdev, PCI_D0, 0);
3837
3838 /* Re-enable all clocks */
3839 if (hw->chip_id == CHIP_ID_YUKON_EX || hw->chip_id == CHIP_ID_YUKON_EC_U)
3840 sky2_pci_write32(hw, PCI_DEV_REG3, 0);
3841
3842 sky2_reset(hw);
3843
3844 sky2_write32(hw, B0_IMSK, Y2_IS_BASE);
3845
3846 for (i = 0; i < hw->ports; i++) {
3847 struct net_device *dev = hw->dev[i];
3848 if (netif_running(dev)) {
3849 err = sky2_up(dev);
3850 if (err) {
3851 printk(KERN_ERR PFX "%s: could not up: %d\n",
3852 dev->name, err);
3853 dev_close(dev);
3854 goto out;
3855 }
3856 }
3857 }
3858
3859 netif_poll_enable(hw->dev[0]);
3860 sky2_idle_start(hw);
3861 return 0;
3862 out:
3863 dev_err(&pdev->dev, "resume failed (%d)\n", err);
3864 pci_disable_device(pdev);
3865 return err;
3866 }
3867 #endif
3868
3869 static void sky2_shutdown(struct pci_dev *pdev)
3870 {
3871 struct sky2_hw *hw = pci_get_drvdata(pdev);
3872 int i, wol = 0;
3873
3874 if (!hw)
3875 return;
3876
3877 del_timer_sync(&hw->idle_timer);
3878 netif_poll_disable(hw->dev[0]);
3879
3880 for (i = 0; i < hw->ports; i++) {
3881 struct net_device *dev = hw->dev[i];
3882 struct sky2_port *sky2 = netdev_priv(dev);
3883
3884 if (sky2->wol) {
3885 wol = 1;
3886 sky2_wol_init(sky2);
3887 }
3888 }
3889
3890 if (wol)
3891 sky2_power_aux(hw);
3892
3893 pci_enable_wake(pdev, PCI_D3hot, wol);
3894 pci_enable_wake(pdev, PCI_D3cold, wol);
3895
3896 pci_disable_device(pdev);
3897 pci_set_power_state(pdev, PCI_D3hot);
3898
3899 }
3900
3901 static struct pci_driver sky2_driver = {
3902 .name = DRV_NAME,
3903 .id_table = sky2_id_table,
3904 .probe = sky2_probe,
3905 .remove = __devexit_p(sky2_remove),
3906 #ifdef CONFIG_PM
3907 .suspend = sky2_suspend,
3908 .resume = sky2_resume,
3909 #endif
3910 .shutdown = sky2_shutdown,
3911 };
3912
3913 static struct dmi_system_id __initdata broken_dmi_table[] = {
3914 {
3915 .ident = "Gigabyte 965P-S3",
3916 .matches = {
3917 DMI_MATCH(DMI_SYS_VENDOR, "Gigabyte Technology Co., Ltd."),
3918 DMI_MATCH(DMI_PRODUCT_NAME, "965P-S3"),
3919
3920 },
3921 },
3922 { }
3923 };
3924
3925 static int __init sky2_init_module(void)
3926 {
3927 /* Look for sick motherboards */
3928 if (dmi_check_system(broken_dmi_table))
3929 dmi_blacklisted = 1;
3930
3931 return pci_register_driver(&sky2_driver);
3932 }
3933
3934 static void __exit sky2_cleanup_module(void)
3935 {
3936 pci_unregister_driver(&sky2_driver);
3937 }
3938
3939 module_init(sky2_init_module);
3940 module_exit(sky2_cleanup_module);
3941
3942 MODULE_DESCRIPTION("Marvell Yukon 2 Gigabit Ethernet driver");
3943 MODULE_AUTHOR("Stephen Hemminger <shemminger@linux-foundation.org>");
3944 MODULE_LICENSE("GPL");
3945 MODULE_VERSION(DRV_VERSION);
Verdex Pro support