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[TCP]: TCP_CONG_YEAH requires TCP_CONG_VEGAS
[linux-2.6/verdex.git] / drivers / video / pm2fb.c
blobab5e66890e4e7f3f60a04e0cfda7acd841c828f8
1 /*
2 * Permedia2 framebuffer driver.
3 *
4 * 2.5/2.6 driver:
5 * Copyright (c) 2003 Jim Hague (jim.hague@acm.org)
6 *
7 * based on 2.4 driver:
8 * Copyright (c) 1998-2000 Ilario Nardinocchi (nardinoc@CS.UniBO.IT)
9 * Copyright (c) 1999 Jakub Jelinek (jakub@redhat.com)
10 *
11 * and additional input from James Simmon's port of Hannu Mallat's tdfx
12 * driver.
13 *
14 * I have a Creative Graphics Blaster Exxtreme card - pm2fb on x86. I
15 * have no access to other pm2fb implementations. Sparc (and thus
16 * hopefully other big-endian) devices now work, thanks to a lot of
17 * testing work by Ron Murray. I have no access to CVision hardware,
18 * and therefore for now I am omitting the CVision code.
19 *
20 * Multiple boards support has been on the TODO list for ages.
21 * Don't expect this to change.
22 *
23 * This file is subject to the terms and conditions of the GNU General Public
24 * License. See the file COPYING in the main directory of this archive for
25 * more details.
26 *
27 *
28 */
29
30 #include <linux/module.h>
31 #include <linux/moduleparam.h>
32 #include <linux/kernel.h>
33 #include <linux/errno.h>
34 #include <linux/string.h>
35 #include <linux/mm.h>
36 #include <linux/slab.h>
37 #include <linux/delay.h>
38 #include <linux/fb.h>
39 #include <linux/init.h>
40 #include <linux/pci.h>
41
42 #include <video/permedia2.h>
43 #include <video/cvisionppc.h>
44
45 #if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
46 #error "The endianness of the target host has not been defined."
47 #endif
48
49 #if !defined(CONFIG_PCI)
50 #error "Only generic PCI cards supported."
51 #endif
52
53 #undef PM2FB_MASTER_DEBUG
54 #ifdef PM2FB_MASTER_DEBUG
55 #define DPRINTK(a,b...) printk(KERN_DEBUG "pm2fb: %s: " a, __FUNCTION__ , ## b)
56 #else
57 #define DPRINTK(a,b...)
58 #endif
59
60 /*
61 * Driver data
62 */
63 static char *mode __devinitdata = NULL;
64
65 /*
66 * The XFree GLINT driver will (I think to implement hardware cursor
67 * support on TVP4010 and similar where there is no RAMDAC - see
68 * comment in set_video) always request +ve sync regardless of what
69 * the mode requires. This screws me because I have a Sun
70 * fixed-frequency monitor which absolutely has to have -ve sync. So
71 * these flags allow the user to specify that requests for +ve sync
72 * should be silently turned in -ve sync.
73 */
74 static int lowhsync;
75 static int lowvsync;
76
77 /*
78 * The hardware state of the graphics card that isn't part of the
79 * screeninfo.
80 */
81 struct pm2fb_par
82 {
83 pm2type_t type; /* Board type */
84 unsigned char __iomem *v_regs;/* virtual address of p_regs */
85 u32 memclock; /* memclock */
86 u32 video; /* video flags before blanking */
87 u32 mem_config; /* MemConfig reg at probe */
88 u32 mem_control; /* MemControl reg at probe */
89 u32 boot_address; /* BootAddress reg at probe */
90 u32 palette[16];
91 };
92
93 /*
94 * Here we define the default structs fb_fix_screeninfo and fb_var_screeninfo
95 * if we don't use modedb.
96 */
97 static struct fb_fix_screeninfo pm2fb_fix __devinitdata = {
98 .id = "",
99 .type = FB_TYPE_PACKED_PIXELS,
100 .visual = FB_VISUAL_PSEUDOCOLOR,
101 .xpanstep = 1,
102 .ypanstep = 1,
103 .ywrapstep = 0,
104 .accel = FB_ACCEL_3DLABS_PERMEDIA2,
105 };
106
107 /*
108 * Default video mode. In case the modedb doesn't work.
109 */
110 static struct fb_var_screeninfo pm2fb_var __devinitdata = {
111 /* "640x480, 8 bpp @ 60 Hz */
112 .xres = 640,
113 .yres = 480,
114 .xres_virtual = 640,
115 .yres_virtual = 480,
116 .bits_per_pixel =8,
117 .red = {0, 8, 0},
118 .blue = {0, 8, 0},
119 .green = {0, 8, 0},
120 .activate = FB_ACTIVATE_NOW,
121 .height = -1,
122 .width = -1,
123 .accel_flags = 0,
124 .pixclock = 39721,
125 .left_margin = 40,
126 .right_margin = 24,
127 .upper_margin = 32,
128 .lower_margin = 11,
129 .hsync_len = 96,
130 .vsync_len = 2,
131 .vmode = FB_VMODE_NONINTERLACED
132 };
133
134 /*
135 * Utility functions
136 */
137
138 static inline u32 RD32(unsigned char __iomem *base, s32 off)
139 {
140 return fb_readl(base + off);
141 }
142
143 static inline void WR32(unsigned char __iomem *base, s32 off, u32 v)
144 {
145 fb_writel(v, base + off);
146 }
147
148 static inline u32 pm2_RD(struct pm2fb_par* p, s32 off)
149 {
150 return RD32(p->v_regs, off);
151 }
152
153 static inline void pm2_WR(struct pm2fb_par* p, s32 off, u32 v)
154 {
155 WR32(p->v_regs, off, v);
156 }
157
158 static inline u32 pm2_RDAC_RD(struct pm2fb_par* p, s32 idx)
159 {
160 int index = PM2R_RD_INDEXED_DATA;
161 switch (p->type) {
162 case PM2_TYPE_PERMEDIA2:
163 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, idx);
164 break;
165 case PM2_TYPE_PERMEDIA2V:
166 pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);
167 index = PM2VR_RD_INDEXED_DATA;
168 break;
169 }
170 mb();
171 return pm2_RD(p, index);
172 }
173
174 static inline void pm2_RDAC_WR(struct pm2fb_par* p, s32 idx, u32 v)
175 {
176 int index = PM2R_RD_INDEXED_DATA;
177 switch (p->type) {
178 case PM2_TYPE_PERMEDIA2:
179 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, idx);
180 break;
181 case PM2_TYPE_PERMEDIA2V:
182 pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);
183 index = PM2VR_RD_INDEXED_DATA;
184 break;
185 }
186 mb();
187 pm2_WR(p, index, v);
188 }
189
190 static inline void pm2v_RDAC_WR(struct pm2fb_par* p, s32 idx, u32 v)
191 {
192 pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);
193 mb();
194 pm2_WR(p, PM2VR_RD_INDEXED_DATA, v);
195 }
196
197 #ifdef CONFIG_FB_PM2_FIFO_DISCONNECT
198 #define WAIT_FIFO(p,a)
199 #else
200 static inline void WAIT_FIFO(struct pm2fb_par* p, u32 a)
201 {
202 while( pm2_RD(p, PM2R_IN_FIFO_SPACE) < a );
203 mb();
204 }
205 #endif
206
207 /*
208 * partial products for the supported horizontal resolutions.
209 */
210 #define PACKPP(p0,p1,p2) (((p2) << 6) | ((p1) << 3) | (p0))
211 static const struct {
212 u16 width;
213 u16 pp;
214 } pp_table[] = {
215 { 32, PACKPP(1, 0, 0) }, { 64, PACKPP(1, 1, 0) },
216 { 96, PACKPP(1, 1, 1) }, { 128, PACKPP(2, 1, 1) },
217 { 160, PACKPP(2, 2, 1) }, { 192, PACKPP(2, 2, 2) },
218 { 224, PACKPP(3, 2, 1) }, { 256, PACKPP(3, 2, 2) },
219 { 288, PACKPP(3, 3, 1) }, { 320, PACKPP(3, 3, 2) },
220 { 384, PACKPP(3, 3, 3) }, { 416, PACKPP(4, 3, 1) },
221 { 448, PACKPP(4, 3, 2) }, { 512, PACKPP(4, 3, 3) },
222 { 544, PACKPP(4, 4, 1) }, { 576, PACKPP(4, 4, 2) },
223 { 640, PACKPP(4, 4, 3) }, { 768, PACKPP(4, 4, 4) },
224 { 800, PACKPP(5, 4, 1) }, { 832, PACKPP(5, 4, 2) },
225 { 896, PACKPP(5, 4, 3) }, { 1024, PACKPP(5, 4, 4) },
226 { 1056, PACKPP(5, 5, 1) }, { 1088, PACKPP(5, 5, 2) },
227 { 1152, PACKPP(5, 5, 3) }, { 1280, PACKPP(5, 5, 4) },
228 { 1536, PACKPP(5, 5, 5) }, { 1568, PACKPP(6, 5, 1) },
229 { 1600, PACKPP(6, 5, 2) }, { 1664, PACKPP(6, 5, 3) },
230 { 1792, PACKPP(6, 5, 4) }, { 2048, PACKPP(6, 5, 5) },
231 { 0, 0 } };
232
233 static u32 partprod(u32 xres)
234 {
235 int i;
236
237 for (i = 0; pp_table[i].width && pp_table[i].width != xres; i++)
238 ;
239 if ( pp_table[i].width == 0 )
240 DPRINTK("invalid width %u\n", xres);
241 return pp_table[i].pp;
242 }
243
244 static u32 to3264(u32 timing, int bpp, int is64)
245 {
246 switch (bpp) {
247 case 8:
248 timing >>= 2 + is64;
249 break;
250 case 16:
251 timing >>= 1 + is64;
252 break;
253 case 24:
254 timing = (timing * 3) >> (2 + is64);
255 break;
256 case 32:
257 if (is64)
258 timing >>= 1;
259 break;
260 }
261 return timing;
262 }
263
264 static void pm2_mnp(u32 clk, unsigned char* mm, unsigned char* nn,
265 unsigned char* pp)
266 {
267 unsigned char m;
268 unsigned char n;
269 unsigned char p;
270 u32 f;
271 s32 curr;
272 s32 delta = 100000;
273
274 *mm = *nn = *pp = 0;
275 for (n = 2; n < 15; n++) {
276 for (m = 2; m; m++) {
277 f = PM2_REFERENCE_CLOCK * m / n;
278 if (f >= 150000 && f <= 300000) {
279 for ( p = 0; p < 5; p++, f >>= 1) {
280 curr = ( clk > f ) ? clk - f : f - clk;
281 if ( curr < delta ) {
282 delta=curr;
283 *mm=m;
284 *nn=n;
285 *pp=p;
286 }
287 }
288 }
289 }
290 }
291 }
292
293 static void pm2v_mnp(u32 clk, unsigned char* mm, unsigned char* nn,
294 unsigned char* pp)
295 {
296 unsigned char m;
297 unsigned char n;
298 unsigned char p;
299 u32 f;
300 s32 delta = 1000;
301
302 *mm = *nn = *pp = 0;
303 for ( m = 1; m < 128; m++) {
304 for (n = 2 * m + 1; n; n++) {
305 for ( p = 0; p < 2; p++) {
306 f = ( PM2_REFERENCE_CLOCK >> ( p + 1 )) * n / m;
307 if ( clk > f - delta && clk < f + delta ) {
308 delta = ( clk > f ) ? clk - f : f - clk;
309 *mm=m;
310 *nn=n;
311 *pp=p;
312 }
313 }
314 }
315 }
316 }
317
318 static void clear_palette(struct pm2fb_par* p) {
319 int i=256;
320
321 WAIT_FIFO(p, 1);
322 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, 0);
323 wmb();
324 while (i--) {
325 WAIT_FIFO(p, 3);
326 pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
327 pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
328 pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
329 }
330 }
331
332 static void reset_card(struct pm2fb_par* p)
333 {
334 if (p->type == PM2_TYPE_PERMEDIA2V)
335 pm2_WR(p, PM2VR_RD_INDEX_HIGH, 0);
336 pm2_WR(p, PM2R_RESET_STATUS, 0);
337 mb();
338 while (pm2_RD(p, PM2R_RESET_STATUS) & PM2F_BEING_RESET)
339 ;
340 mb();
341 #ifdef CONFIG_FB_PM2_FIFO_DISCONNECT
342 DPRINTK("FIFO disconnect enabled\n");
343 pm2_WR(p, PM2R_FIFO_DISCON, 1);
344 mb();
345 #endif
346
347 /* Restore stashed memory config information from probe */
348 WAIT_FIFO(p, 3);
349 pm2_WR(p, PM2R_MEM_CONTROL, p->mem_control);
350 pm2_WR(p, PM2R_BOOT_ADDRESS, p->boot_address);
351 wmb();
352 pm2_WR(p, PM2R_MEM_CONFIG, p->mem_config);
353 }
354
355 static void reset_config(struct pm2fb_par* p)
356 {
357 WAIT_FIFO(p, 52);
358 pm2_WR(p, PM2R_CHIP_CONFIG, pm2_RD(p, PM2R_CHIP_CONFIG)&
359 ~(PM2F_VGA_ENABLE|PM2F_VGA_FIXED));
360 pm2_WR(p, PM2R_BYPASS_WRITE_MASK, ~(0L));
361 pm2_WR(p, PM2R_FRAMEBUFFER_WRITE_MASK, ~(0L));
362 pm2_WR(p, PM2R_FIFO_CONTROL, 0);
363 pm2_WR(p, PM2R_APERTURE_ONE, 0);
364 pm2_WR(p, PM2R_APERTURE_TWO, 0);
365 pm2_WR(p, PM2R_RASTERIZER_MODE, 0);
366 pm2_WR(p, PM2R_DELTA_MODE, PM2F_DELTA_ORDER_RGB);
367 pm2_WR(p, PM2R_LB_READ_FORMAT, 0);
368 pm2_WR(p, PM2R_LB_WRITE_FORMAT, 0);
369 pm2_WR(p, PM2R_LB_READ_MODE, 0);
370 pm2_WR(p, PM2R_LB_SOURCE_OFFSET, 0);
371 pm2_WR(p, PM2R_FB_SOURCE_OFFSET, 0);
372 pm2_WR(p, PM2R_FB_PIXEL_OFFSET, 0);
373 pm2_WR(p, PM2R_FB_WINDOW_BASE, 0);
374 pm2_WR(p, PM2R_LB_WINDOW_BASE, 0);
375 pm2_WR(p, PM2R_FB_SOFT_WRITE_MASK, ~(0L));
376 pm2_WR(p, PM2R_FB_HARD_WRITE_MASK, ~(0L));
377 pm2_WR(p, PM2R_FB_READ_PIXEL, 0);
378 pm2_WR(p, PM2R_DITHER_MODE, 0);
379 pm2_WR(p, PM2R_AREA_STIPPLE_MODE, 0);
380 pm2_WR(p, PM2R_DEPTH_MODE, 0);
381 pm2_WR(p, PM2R_STENCIL_MODE, 0);
382 pm2_WR(p, PM2R_TEXTURE_ADDRESS_MODE, 0);
383 pm2_WR(p, PM2R_TEXTURE_READ_MODE, 0);
384 pm2_WR(p, PM2R_TEXEL_LUT_MODE, 0);
385 pm2_WR(p, PM2R_YUV_MODE, 0);
386 pm2_WR(p, PM2R_COLOR_DDA_MODE, 0);
387 pm2_WR(p, PM2R_TEXTURE_COLOR_MODE, 0);
388 pm2_WR(p, PM2R_FOG_MODE, 0);
389 pm2_WR(p, PM2R_ALPHA_BLEND_MODE, 0);
390 pm2_WR(p, PM2R_LOGICAL_OP_MODE, 0);
391 pm2_WR(p, PM2R_STATISTICS_MODE, 0);
392 pm2_WR(p, PM2R_SCISSOR_MODE, 0);
393 pm2_WR(p, PM2R_FILTER_MODE, PM2F_SYNCHRONIZATION);
394 switch (p->type) {
395 case PM2_TYPE_PERMEDIA2:
396 pm2_RDAC_WR(p, PM2I_RD_MODE_CONTROL, 0); /* no overlay */
397 pm2_RDAC_WR(p, PM2I_RD_CURSOR_CONTROL, 0);
398 pm2_RDAC_WR(p, PM2I_RD_MISC_CONTROL, PM2F_RD_PALETTE_WIDTH_8);
399 break;
400 case PM2_TYPE_PERMEDIA2V:
401 pm2v_RDAC_WR(p, PM2VI_RD_MISC_CONTROL, 1); /* 8bit */
402 break;
403 }
404 pm2_RDAC_WR(p, PM2I_RD_COLOR_KEY_CONTROL, 0);
405 pm2_RDAC_WR(p, PM2I_RD_OVERLAY_KEY, 0);
406 pm2_RDAC_WR(p, PM2I_RD_RED_KEY, 0);
407 pm2_RDAC_WR(p, PM2I_RD_GREEN_KEY, 0);
408 pm2_RDAC_WR(p, PM2I_RD_BLUE_KEY, 0);
409 }
410
411 static void set_aperture(struct pm2fb_par* p, u32 depth)
412 {
413 /*
414 * The hardware is little-endian. When used in big-endian
415 * hosts, the on-chip aperture settings are used where
416 * possible to translate from host to card byte order.
417 */
418 WAIT_FIFO(p, 4);
419 #ifdef __LITTLE_ENDIAN
420 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_STANDARD);
421 #else
422 switch (depth) {
423 case 24: /* RGB->BGR */
424 /*
425 * We can't use the aperture to translate host to
426 * card byte order here, so we switch to BGR mode
427 * in pm2fb_set_par().
428 */
429 case 8: /* B->B */
430 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_STANDARD);
431 break;
432 case 16: /* HL->LH */
433 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_HALFWORDSWAP);
434 break;
435 case 32: /* RGBA->ABGR */
436 pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_BYTESWAP);
437 break;
438 }
439 #endif
440
441 // We don't use aperture two, so this may be superflous
442 pm2_WR(p, PM2R_APERTURE_TWO, PM2F_APERTURE_STANDARD);
443 }
444
445 static void set_color(struct pm2fb_par* p, unsigned char regno,
446 unsigned char r, unsigned char g, unsigned char b)
447 {
448 WAIT_FIFO(p, 4);
449 pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, regno);
450 wmb();
451 pm2_WR(p, PM2R_RD_PALETTE_DATA, r);
452 wmb();
453 pm2_WR(p, PM2R_RD_PALETTE_DATA, g);
454 wmb();
455 pm2_WR(p, PM2R_RD_PALETTE_DATA, b);
456 }
457
458 static void set_memclock(struct pm2fb_par* par, u32 clk)
459 {
460 int i;
461 unsigned char m, n, p;
462
463 switch (par->type) {
464 case PM2_TYPE_PERMEDIA2V:
465 pm2v_mnp(clk/2, &m, &n, &p);
466 WAIT_FIFO(par, 8);
467 pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_MCLK_CONTROL >> 8);
468 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_CONTROL, 0);
469 wmb();
470 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_PRESCALE, m);
471 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_FEEDBACK, n);
472 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_POSTSCALE, p);
473 wmb();
474 pm2v_RDAC_WR(par, PM2VI_RD_MCLK_CONTROL, 1);
475 rmb();
476 for (i = 256;
477 i && !(pm2_RDAC_RD(par, PM2VI_RD_MCLK_CONTROL) & 2);
478 i--)
479 ;
480 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
481 break;
482 case PM2_TYPE_PERMEDIA2:
483 pm2_mnp(clk, &m, &n, &p);
484 WAIT_FIFO(par, 10);
485 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 6);
486 wmb();
487 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_1, m);
488 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_2, n);
489 wmb();
490 pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 8|p);
491 wmb();
492 pm2_RDAC_RD(par, PM2I_RD_MEMORY_CLOCK_STATUS);
493 rmb();
494 for (i = 256;
495 i && !(pm2_RD(par, PM2R_RD_INDEXED_DATA) & PM2F_PLL_LOCKED);
496 i--)
497 ;
498 break;
499 }
500 }
501
502 static void set_pixclock(struct pm2fb_par* par, u32 clk)
503 {
504 int i;
505 unsigned char m, n, p;
506
507 switch (par->type) {
508 case PM2_TYPE_PERMEDIA2:
509 pm2_mnp(clk, &m, &n, &p);
510 WAIT_FIFO(par, 8);
511 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 0);
512 wmb();
513 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A1, m);
514 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A2, n);
515 wmb();
516 pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 8|p);
517 wmb();
518 pm2_RDAC_RD(par, PM2I_RD_PIXEL_CLOCK_STATUS);
519 rmb();
520 for (i = 256;
521 i && !(pm2_RD(par, PM2R_RD_INDEXED_DATA) & PM2F_PLL_LOCKED);
522 i--)
523 ;
524 break;
525 case PM2_TYPE_PERMEDIA2V:
526 pm2v_mnp(clk/2, &m, &n, &p);
527 WAIT_FIFO(par, 8);
528 pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_CLK0_PRESCALE >> 8);
529 pm2v_RDAC_WR(par, PM2VI_RD_CLK0_PRESCALE, m);
530 pm2v_RDAC_WR(par, PM2VI_RD_CLK0_FEEDBACK, n);
531 pm2v_RDAC_WR(par, PM2VI_RD_CLK0_POSTSCALE, p);
532 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
533 break;
534 }
535 }
536
537 static void set_video(struct pm2fb_par* p, u32 video) {
538 u32 tmp;
539 u32 vsync;
540
541 vsync = video;
542
543 DPRINTK("video = 0x%x\n", video);
544
545 /*
546 * The hardware cursor needs +vsync to recognise vert retrace.
547 * We may not be using the hardware cursor, but the X Glint
548 * driver may well. So always set +hsync/+vsync and then set
549 * the RAMDAC to invert the sync if necessary.
550 */
551 vsync &= ~(PM2F_HSYNC_MASK|PM2F_VSYNC_MASK);
552 vsync |= PM2F_HSYNC_ACT_HIGH|PM2F_VSYNC_ACT_HIGH;
553
554 WAIT_FIFO(p, 5);
555 pm2_WR(p, PM2R_VIDEO_CONTROL, vsync);
556
557 switch (p->type) {
558 case PM2_TYPE_PERMEDIA2:
559 tmp = PM2F_RD_PALETTE_WIDTH_8;
560 if ((video & PM2F_HSYNC_MASK) == PM2F_HSYNC_ACT_LOW)
561 tmp |= 4; /* invert hsync */
562 if ((video & PM2F_VSYNC_MASK) == PM2F_VSYNC_ACT_LOW)
563 tmp |= 8; /* invert vsync */
564 pm2_RDAC_WR(p, PM2I_RD_MISC_CONTROL, tmp);
565 break;
566 case PM2_TYPE_PERMEDIA2V:
567 tmp = 0;
568 if ((video & PM2F_HSYNC_MASK) == PM2F_HSYNC_ACT_LOW)
569 tmp |= 1; /* invert hsync */
570 if ((video & PM2F_VSYNC_MASK) == PM2F_VSYNC_ACT_LOW)
571 tmp |= 4; /* invert vsync */
572 pm2v_RDAC_WR(p, PM2VI_RD_SYNC_CONTROL, tmp);
573 pm2v_RDAC_WR(p, PM2VI_RD_MISC_CONTROL, 1);
574 break;
575 }
576 }
577
578 /*
579 *
580 */
581
582 /**
583 * pm2fb_check_var - Optional function. Validates a var passed in.
584 * @var: frame buffer variable screen structure
585 * @info: frame buffer structure that represents a single frame buffer
586 *
587 * Checks to see if the hardware supports the state requested by
588 * var passed in.
589 *
590 * Returns negative errno on error, or zero on success.
591 */
592 static int pm2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
593 {
594 u32 lpitch;
595
596 if (var->bits_per_pixel != 8 && var->bits_per_pixel != 16 &&
597 var->bits_per_pixel != 24 && var->bits_per_pixel != 32) {
598 DPRINTK("depth not supported: %u\n", var->bits_per_pixel);
599 return -EINVAL;
600 }
601
602 if (var->xres != var->xres_virtual) {
603 DPRINTK("virtual x resolution != physical x resolution not supported\n");
604 return -EINVAL;
605 }
606
607 if (var->yres > var->yres_virtual) {
608 DPRINTK("virtual y resolution < physical y resolution not possible\n");
609 return -EINVAL;
610 }
611
612 if (var->xoffset) {
613 DPRINTK("xoffset not supported\n");
614 return -EINVAL;
615 }
616
617 if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
618 DPRINTK("interlace not supported\n");
619 return -EINVAL;
620 }
621
622 var->xres = (var->xres + 15) & ~15; /* could sometimes be 8 */
623 lpitch = var->xres * ((var->bits_per_pixel + 7)>>3);
624
625 if (var->xres < 320 || var->xres > 1600) {
626 DPRINTK("width not supported: %u\n", var->xres);
627 return -EINVAL;
628 }
629
630 if (var->yres < 200 || var->yres > 1200) {
631 DPRINTK("height not supported: %u\n", var->yres);
632 return -EINVAL;
633 }
634
635 if (lpitch * var->yres_virtual > info->fix.smem_len) {
636 DPRINTK("no memory for screen (%ux%ux%u)\n",
637 var->xres, var->yres_virtual, var->bits_per_pixel);
638 return -EINVAL;
639 }
640
641 if (PICOS2KHZ(var->pixclock) > PM2_MAX_PIXCLOCK) {
642 DPRINTK("pixclock too high (%ldKHz)\n", PICOS2KHZ(var->pixclock));
643 return -EINVAL;
644 }
645
646 var->transp.offset = 0;
647 var->transp.length = 0;
648 switch(var->bits_per_pixel) {
649 case 8:
650 var->red.length = var->green.length = var->blue.length = 8;
651 break;
652 case 16:
653 var->red.offset = 11;
654 var->red.length = 5;
655 var->green.offset = 5;
656 var->green.length = 6;
657 var->blue.offset = 0;
658 var->blue.length = 5;
659 break;
660 case 32:
661 var->transp.offset = 24;
662 var->transp.length = 8;
663 var->red.offset = 16;
664 var->green.offset = 8;
665 var->blue.offset = 0;
666 var->red.length = var->green.length = var->blue.length = 8;
667 break;
668 case 24:
669 #ifdef __BIG_ENDIAN
670 var->red.offset = 0;
671 var->blue.offset = 16;
672 #else
673 var->red.offset = 16;
674 var->blue.offset = 0;
675 #endif
676 var->green.offset = 8;
677 var->red.length = var->green.length = var->blue.length = 8;
678 break;
679 }
680 var->height = var->width = -1;
681
682 var->accel_flags = 0; /* Can't mmap if this is on */
683
684 DPRINTK("Checking graphics mode at %dx%d depth %d\n",
685 var->xres, var->yres, var->bits_per_pixel);
686 return 0;
687 }
688
689 /**
690 * pm2fb_set_par - Alters the hardware state.
691 * @info: frame buffer structure that represents a single frame buffer
692 *
693 * Using the fb_var_screeninfo in fb_info we set the resolution of the
694 * this particular framebuffer.
695 */
696 static int pm2fb_set_par(struct fb_info *info)
697 {
698 struct pm2fb_par *par = info->par;
699 u32 pixclock;
700 u32 width, height, depth;
701 u32 hsstart, hsend, hbend, htotal;
702 u32 vsstart, vsend, vbend, vtotal;
703 u32 stride;
704 u32 base;
705 u32 video = 0;
706 u32 clrmode = PM2F_RD_COLOR_MODE_RGB | PM2F_RD_GUI_ACTIVE;
707 u32 txtmap = 0;
708 u32 pixsize = 0;
709 u32 clrformat = 0;
710 u32 xres;
711 int data64;
712
713 reset_card(par);
714 reset_config(par);
715 clear_palette(par);
716 if ( par->memclock )
717 set_memclock(par, par->memclock);
718
719 width = (info->var.xres_virtual + 7) & ~7;
720 height = info->var.yres_virtual;
721 depth = (info->var.bits_per_pixel + 7) & ~7;
722 depth = (depth > 32) ? 32 : depth;
723 data64 = depth > 8 || par->type == PM2_TYPE_PERMEDIA2V;
724
725 xres = (info->var.xres + 31) & ~31;
726 pixclock = PICOS2KHZ(info->var.pixclock);
727 if (pixclock > PM2_MAX_PIXCLOCK) {
728 DPRINTK("pixclock too high (%uKHz)\n", pixclock);
729 return -EINVAL;
730 }
731
732 hsstart = to3264(info->var.right_margin, depth, data64);
733 hsend = hsstart + to3264(info->var.hsync_len, depth, data64);
734 hbend = hsend + to3264(info->var.left_margin, depth, data64);
735 htotal = to3264(xres, depth, data64) + hbend - 1;
736 vsstart = (info->var.lower_margin)
737 ? info->var.lower_margin - 1
738 : 0; /* FIXME! */
739 vsend = info->var.lower_margin + info->var.vsync_len - 1;
740 vbend = info->var.lower_margin + info->var.vsync_len + info->var.upper_margin;
741 vtotal = info->var.yres + vbend - 1;
742 stride = to3264(width, depth, 1);
743 base = to3264(info->var.yoffset * xres + info->var.xoffset, depth, 1);
744 if (data64)
745 video |= PM2F_DATA_64_ENABLE;
746
747 if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) {
748 if (lowhsync) {
749 DPRINTK("ignoring +hsync, using -hsync.\n");
750 video |= PM2F_HSYNC_ACT_LOW;
751 } else
752 video |= PM2F_HSYNC_ACT_HIGH;
753 }
754 else
755 video |= PM2F_HSYNC_ACT_LOW;
756 if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) {
757 if (lowvsync) {
758 DPRINTK("ignoring +vsync, using -vsync.\n");
759 video |= PM2F_VSYNC_ACT_LOW;
760 } else
761 video |= PM2F_VSYNC_ACT_HIGH;
762 }
763 else
764 video |= PM2F_VSYNC_ACT_LOW;
765 if ((info->var.vmode & FB_VMODE_MASK)==FB_VMODE_INTERLACED) {
766 DPRINTK("interlaced not supported\n");
767 return -EINVAL;
768 }
769 if ((info->var.vmode & FB_VMODE_MASK)==FB_VMODE_DOUBLE)
770 video |= PM2F_LINE_DOUBLE;
771 if ((info->var.activate & FB_ACTIVATE_MASK)==FB_ACTIVATE_NOW)
772 video |= PM2F_VIDEO_ENABLE;
773 par->video = video;
774
775 info->fix.visual =
776 (depth == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
777 info->fix.line_length = info->var.xres * depth / 8;
778 info->cmap.len = 256;
779
780 /*
781 * Settings calculated. Now write them out.
782 */
783 if (par->type == PM2_TYPE_PERMEDIA2V) {
784 WAIT_FIFO(par, 1);
785 pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
786 }
787
788 set_aperture(par, depth);
789
790 mb();
791 WAIT_FIFO(par, 19);
792 pm2_RDAC_WR(par, PM2I_RD_COLOR_KEY_CONTROL,
793 ( depth == 8 ) ? 0 : PM2F_COLOR_KEY_TEST_OFF);
794 switch (depth) {
795 case 8:
796 pm2_WR(par, PM2R_FB_READ_PIXEL, 0);
797 clrformat = 0x0e;
798 break;
799 case 16:
800 pm2_WR(par, PM2R_FB_READ_PIXEL, 1);
801 clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGB565;
802 txtmap = PM2F_TEXTEL_SIZE_16;
803 pixsize = 1;
804 clrformat = 0x70;
805 break;
806 case 32:
807 pm2_WR(par, PM2R_FB_READ_PIXEL, 2);
808 clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGBA8888;
809 txtmap = PM2F_TEXTEL_SIZE_32;
810 pixsize = 2;
811 clrformat = 0x20;
812 break;
813 case 24:
814 pm2_WR(par, PM2R_FB_READ_PIXEL, 4);
815 clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGB888;
816 txtmap = PM2F_TEXTEL_SIZE_24;
817 pixsize = 4;
818 clrformat = 0x20;
819 break;
820 }
821 pm2_WR(par, PM2R_FB_WRITE_MODE, PM2F_FB_WRITE_ENABLE);
822 pm2_WR(par, PM2R_FB_READ_MODE, partprod(xres));
823 pm2_WR(par, PM2R_LB_READ_MODE, partprod(xres));
824 pm2_WR(par, PM2R_TEXTURE_MAP_FORMAT, txtmap | partprod(xres));
825 pm2_WR(par, PM2R_H_TOTAL, htotal);
826 pm2_WR(par, PM2R_HS_START, hsstart);
827 pm2_WR(par, PM2R_HS_END, hsend);
828 pm2_WR(par, PM2R_HG_END, hbend);
829 pm2_WR(par, PM2R_HB_END, hbend);
830 pm2_WR(par, PM2R_V_TOTAL, vtotal);
831 pm2_WR(par, PM2R_VS_START, vsstart);
832 pm2_WR(par, PM2R_VS_END, vsend);
833 pm2_WR(par, PM2R_VB_END, vbend);
834 pm2_WR(par, PM2R_SCREEN_STRIDE, stride);
835 wmb();
836 pm2_WR(par, PM2R_WINDOW_ORIGIN, 0);
837 pm2_WR(par, PM2R_SCREEN_SIZE, (height << 16) | width);
838 pm2_WR(par, PM2R_SCISSOR_MODE, PM2F_SCREEN_SCISSOR_ENABLE);
839 wmb();
840 pm2_WR(par, PM2R_SCREEN_BASE, base);
841 wmb();
842 set_video(par, video);
843 WAIT_FIFO(par, 4);
844 switch (par->type) {
845 case PM2_TYPE_PERMEDIA2:
846 pm2_RDAC_WR(par, PM2I_RD_COLOR_MODE, clrmode);
847 break;
848 case PM2_TYPE_PERMEDIA2V:
849 pm2v_RDAC_WR(par, PM2VI_RD_PIXEL_SIZE, pixsize);
850 pm2v_RDAC_WR(par, PM2VI_RD_COLOR_FORMAT, clrformat);
851 break;
852 }
853 set_pixclock(par, pixclock);
854 DPRINTK("Setting graphics mode at %dx%d depth %d\n",
855 info->var.xres, info->var.yres, info->var.bits_per_pixel);
856 return 0;
857 }
858
859 /**
860 * pm2fb_setcolreg - Sets a color register.
861 * @regno: boolean, 0 copy local, 1 get_user() function
862 * @red: frame buffer colormap structure
863 * @green: The green value which can be up to 16 bits wide
864 * @blue: The blue value which can be up to 16 bits wide.
865 * @transp: If supported the alpha value which can be up to 16 bits wide.
866 * @info: frame buffer info structure
867 *
868 * Set a single color register. The values supplied have a 16 bit
869 * magnitude which needs to be scaled in this function for the hardware.
870 * Pretty much a direct lift from tdfxfb.c.
871 *
872 * Returns negative errno on error, or zero on success.
873 */
874 static int pm2fb_setcolreg(unsigned regno, unsigned red, unsigned green,
875 unsigned blue, unsigned transp,
876 struct fb_info *info)
877 {
878 struct pm2fb_par *par = info->par;
879
880 if (regno >= info->cmap.len) /* no. of hw registers */
881 return 1;
882 /*
883 * Program hardware... do anything you want with transp
884 */
885
886 /* grayscale works only partially under directcolor */
887 if (info->var.grayscale) {
888 /* grayscale = 0.30*R + 0.59*G + 0.11*B */
889 red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
890 }
891
892 /* Directcolor:
893 * var->{color}.offset contains start of bitfield
894 * var->{color}.length contains length of bitfield
895 * {hardwarespecific} contains width of DAC
896 * cmap[X] is programmed to
897 * (X << red.offset) | (X << green.offset) | (X << blue.offset)
898 * RAMDAC[X] is programmed to (red, green, blue)
899 *
900 * Pseudocolor:
901 * uses offset = 0 && length = DAC register width.
902 * var->{color}.offset is 0
903 * var->{color}.length contains widht of DAC
904 * cmap is not used
905 * DAC[X] is programmed to (red, green, blue)
906 * Truecolor:
907 * does not use RAMDAC (usually has 3 of them).
908 * var->{color}.offset contains start of bitfield
909 * var->{color}.length contains length of bitfield
910 * cmap is programmed to
911 * (red << red.offset) | (green << green.offset) |
912 * (blue << blue.offset) | (transp << transp.offset)
913 * RAMDAC does not exist
914 */
915 #define CNVT_TOHW(val,width) ((((val)<<(width))+0x7FFF-(val))>>16)
916 switch (info->fix.visual) {
917 case FB_VISUAL_TRUECOLOR:
918 case FB_VISUAL_PSEUDOCOLOR:
919 red = CNVT_TOHW(red, info->var.red.length);
920 green = CNVT_TOHW(green, info->var.green.length);
921 blue = CNVT_TOHW(blue, info->var.blue.length);
922 transp = CNVT_TOHW(transp, info->var.transp.length);
923 break;
924 case FB_VISUAL_DIRECTCOLOR:
925 /* example here assumes 8 bit DAC. Might be different
926 * for your hardware */
927 red = CNVT_TOHW(red, 8);
928 green = CNVT_TOHW(green, 8);
929 blue = CNVT_TOHW(blue, 8);
930 /* hey, there is bug in transp handling... */
931 transp = CNVT_TOHW(transp, 8);
932 break;
933 }
934 #undef CNVT_TOHW
935 /* Truecolor has hardware independent palette */
936 if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
937 u32 v;
938
939 if (regno >= 16)
940 return 1;
941
942 v = (red << info->var.red.offset) |
943 (green << info->var.green.offset) |
944 (blue << info->var.blue.offset) |
945 (transp << info->var.transp.offset);
946
947 switch (info->var.bits_per_pixel) {
948 case 8:
949 break;
950 case 16:
951 case 24:
952 case 32:
953 par->palette[regno] = v;
954 break;
955 }
956 return 0;
957 }
958 else if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR)
959 set_color(par, regno, red, green, blue);
960
961 return 0;
962 }
963
964 /**
965 * pm2fb_pan_display - Pans the display.
966 * @var: frame buffer variable screen structure
967 * @info: frame buffer structure that represents a single frame buffer
968 *
969 * Pan (or wrap, depending on the `vmode' field) the display using the
970 * `xoffset' and `yoffset' fields of the `var' structure.
971 * If the values don't fit, return -EINVAL.
972 *
973 * Returns negative errno on error, or zero on success.
974 *
975 */
976 static int pm2fb_pan_display(struct fb_var_screeninfo *var,
977 struct fb_info *info)
978 {
979 struct pm2fb_par *p = info->par;
980 u32 base;
981 u32 depth;
982 u32 xres;
983
984 xres = (var->xres + 31) & ~31;
985 depth = (var->bits_per_pixel + 7) & ~7;
986 depth = (depth > 32) ? 32 : depth;
987 base = to3264(var->yoffset * xres + var->xoffset, depth, 1);
988 WAIT_FIFO(p, 1);
989 pm2_WR(p, PM2R_SCREEN_BASE, base);
990 return 0;
991 }
992
993 /**
994 * pm2fb_blank - Blanks the display.
995 * @blank_mode: the blank mode we want.
996 * @info: frame buffer structure that represents a single frame buffer
997 *
998 * Blank the screen if blank_mode != 0, else unblank. Return 0 if
999 * blanking succeeded, != 0 if un-/blanking failed due to e.g. a
1000 * video mode which doesn't support it. Implements VESA suspend
1001 * and powerdown modes on hardware that supports disabling hsync/vsync:
1002 * blank_mode == 2: suspend vsync
1003 * blank_mode == 3: suspend hsync
1004 * blank_mode == 4: powerdown
1005 *
1006 * Returns negative errno on error, or zero on success.
1007 *
1008 */
1009 static int pm2fb_blank(int blank_mode, struct fb_info *info)
1010 {
1011 struct pm2fb_par *par = info->par;
1012 u32 video = par->video;
1013
1014 DPRINTK("blank_mode %d\n", blank_mode);
1015
1016 switch (blank_mode) {
1017 case FB_BLANK_UNBLANK:
1018 /* Screen: On */
1019 video |= PM2F_VIDEO_ENABLE;
1020 break;
1021 case FB_BLANK_NORMAL:
1022 /* Screen: Off */
1023 video &= ~PM2F_VIDEO_ENABLE;
1024 break;
1025 case FB_BLANK_VSYNC_SUSPEND:
1026 /* VSync: Off */
1027 video &= ~(PM2F_VSYNC_MASK | PM2F_BLANK_LOW );
1028 break;
1029 case FB_BLANK_HSYNC_SUSPEND:
1030 /* HSync: Off */
1031 video &= ~(PM2F_HSYNC_MASK | PM2F_BLANK_LOW );
1032 break;
1033 case FB_BLANK_POWERDOWN:
1034 /* HSync: Off, VSync: Off */
1035 video &= ~(PM2F_VSYNC_MASK | PM2F_HSYNC_MASK| PM2F_BLANK_LOW);
1036 break;
1037 }
1038 set_video(par, video);
1039 return 0;
1040 }
1041
1042 static int pm2fb_sync(struct fb_info *info)
1043 {
1044 struct pm2fb_par *par = info->par;
1045
1046 WAIT_FIFO(par, 1);
1047 pm2_WR(par, PM2R_SYNC, 0);
1048 mb();
1049 do {
1050 while (pm2_RD(par, PM2R_OUT_FIFO_WORDS) == 0)
1051 udelay(10);
1052 rmb();
1053 } while (pm2_RD(par, PM2R_OUT_FIFO) != PM2TAG(PM2R_SYNC));
1054
1055 return 0;
1056 }
1057
1058 /*
1059 * block operation. copy=0: rectangle fill, copy=1: rectangle copy.
1060 */
1061 static void pm2fb_block_op(struct fb_info* info, int copy,
1062 s32 xsrc, s32 ysrc,
1063 s32 x, s32 y, s32 w, s32 h,
1064 u32 color) {
1065 struct pm2fb_par *par = info->par;
1066
1067 if (!w || !h)
1068 return;
1069 WAIT_FIFO(par, 6);
1070 pm2_WR(par, PM2R_CONFIG, PM2F_CONFIG_FB_WRITE_ENABLE |
1071 PM2F_CONFIG_FB_READ_SOURCE_ENABLE);
1072 pm2_WR(par, PM2R_FB_PIXEL_OFFSET, 0);
1073 if (copy)
1074 pm2_WR(par, PM2R_FB_SOURCE_DELTA,
1075 ((ysrc-y) & 0xfff) << 16 | ((xsrc-x) & 0xfff));
1076 else
1077 pm2_WR(par, PM2R_FB_BLOCK_COLOR, color);
1078 pm2_WR(par, PM2R_RECTANGLE_ORIGIN, (y << 16) | x);
1079 pm2_WR(par, PM2R_RECTANGLE_SIZE, (h << 16) | w);
1080 wmb();
1081 pm2_WR(par, PM2R_RENDER,PM2F_RENDER_RECTANGLE |
1082 (x<xsrc ? PM2F_INCREASE_X : 0) |
1083 (y<ysrc ? PM2F_INCREASE_Y : 0) |
1084 (copy ? 0 : PM2F_RENDER_FASTFILL));
1085 }
1086
1087 static void pm2fb_fillrect (struct fb_info *info,
1088 const struct fb_fillrect *region)
1089 {
1090 struct fb_fillrect modded;
1091 int vxres, vyres;
1092 u32 color = (info->fix.visual == FB_VISUAL_TRUECOLOR) ?
1093 ((u32*)info->pseudo_palette)[region->color] : region->color;
1094
1095 if (info->state != FBINFO_STATE_RUNNING)
1096 return;
1097 if ((info->flags & FBINFO_HWACCEL_DISABLED) ||
1098 region->rop != ROP_COPY ) {
1099 cfb_fillrect(info, region);
1100 return;
1101 }
1102
1103 vxres = info->var.xres_virtual;
1104 vyres = info->var.yres_virtual;
1105
1106 memcpy(&modded, region, sizeof(struct fb_fillrect));
1107
1108 if(!modded.width || !modded.height ||
1109 modded.dx >= vxres || modded.dy >= vyres)
1110 return;
1111
1112 if(modded.dx + modded.width > vxres)
1113 modded.width = vxres - modded.dx;
1114 if(modded.dy + modded.height > vyres)
1115 modded.height = vyres - modded.dy;
1116
1117 if(info->var.bits_per_pixel == 8)
1118 color |= color << 8;
1119 if(info->var.bits_per_pixel <= 16)
1120 color |= color << 16;
1121
1122 if(info->var.bits_per_pixel != 24)
1123 pm2fb_block_op(info, 0, 0, 0,
1124 modded.dx, modded.dy,
1125 modded.width, modded.height, color);
1126 else
1127 cfb_fillrect(info, region);
1128 }
1129
1130 static void pm2fb_copyarea(struct fb_info *info,
1131 const struct fb_copyarea *area)
1132 {
1133 struct fb_copyarea modded;
1134 u32 vxres, vyres;
1135
1136 if (info->state != FBINFO_STATE_RUNNING)
1137 return;
1138 if (info->flags & FBINFO_HWACCEL_DISABLED) {
1139 cfb_copyarea(info, area);
1140 return;
1141 }
1142
1143 memcpy(&modded, area, sizeof(struct fb_copyarea));
1144
1145 vxres = info->var.xres_virtual;
1146 vyres = info->var.yres_virtual;
1147
1148 if(!modded.width || !modded.height ||
1149 modded.sx >= vxres || modded.sy >= vyres ||
1150 modded.dx >= vxres || modded.dy >= vyres)
1151 return;
1152
1153 if(modded.sx + modded.width > vxres)
1154 modded.width = vxres - modded.sx;
1155 if(modded.dx + modded.width > vxres)
1156 modded.width = vxres - modded.dx;
1157 if(modded.sy + modded.height > vyres)
1158 modded.height = vyres - modded.sy;
1159 if(modded.dy + modded.height > vyres)
1160 modded.height = vyres - modded.dy;
1161
1162 pm2fb_block_op(info, 1, modded.sx, modded.sy,
1163 modded.dx, modded.dy,
1164 modded.width, modded.height, 0);
1165 }
1166
1167 /* ------------ Hardware Independent Functions ------------ */
1168
1169 /*
1170 * Frame buffer operations
1171 */
1172
1173 static struct fb_ops pm2fb_ops = {
1174 .owner = THIS_MODULE,
1175 .fb_check_var = pm2fb_check_var,
1176 .fb_set_par = pm2fb_set_par,
1177 .fb_setcolreg = pm2fb_setcolreg,
1178 .fb_blank = pm2fb_blank,
1179 .fb_pan_display = pm2fb_pan_display,
1180 .fb_fillrect = pm2fb_fillrect,
1181 .fb_copyarea = pm2fb_copyarea,
1182 .fb_imageblit = cfb_imageblit,
1183 .fb_sync = pm2fb_sync,
1184 };
1185
1186 /*
1187 * PCI stuff
1188 */
1189
1190
1191 /**
1192 * Device initialisation
1193 *
1194 * Initialise and allocate resource for PCI device.
1195 *
1196 * @param pdev PCI device.
1197 * @param id PCI device ID.
1198 */
1199 static int __devinit pm2fb_probe(struct pci_dev *pdev,
1200 const struct pci_device_id *id)
1201 {
1202 struct pm2fb_par *default_par;
1203 struct fb_info *info;
1204 int err, err_retval = -ENXIO;
1205
1206 err = pci_enable_device(pdev);
1207 if ( err ) {
1208 printk(KERN_WARNING "pm2fb: Can't enable pdev: %d\n", err);
1209 return err;
1210 }
1211
1212 info = framebuffer_alloc(sizeof(struct pm2fb_par), &pdev->dev);
1213 if ( !info )
1214 return -ENOMEM;
1215 default_par = info->par;
1216
1217 switch (pdev->device) {
1218 case PCI_DEVICE_ID_TI_TVP4020:
1219 strcpy(pm2fb_fix.id, "TVP4020");
1220 default_par->type = PM2_TYPE_PERMEDIA2;
1221 break;
1222 case PCI_DEVICE_ID_3DLABS_PERMEDIA2:
1223 strcpy(pm2fb_fix.id, "Permedia2");
1224 default_par->type = PM2_TYPE_PERMEDIA2;
1225 break;
1226 case PCI_DEVICE_ID_3DLABS_PERMEDIA2V:
1227 strcpy(pm2fb_fix.id, "Permedia2v");
1228 default_par->type = PM2_TYPE_PERMEDIA2V;
1229 break;
1230 }
1231
1232 pm2fb_fix.mmio_start = pci_resource_start(pdev, 0);
1233 pm2fb_fix.mmio_len = PM2_REGS_SIZE;
1234
1235 #if defined(__BIG_ENDIAN)
1236 /*
1237 * PM2 has a 64k register file, mapped twice in 128k. Lower
1238 * map is little-endian, upper map is big-endian.
1239 */
1240 pm2fb_fix.mmio_start += PM2_REGS_SIZE;
1241 DPRINTK("Adjusting register base for big-endian.\n");
1242 #endif
1243 DPRINTK("Register base at 0x%lx\n", pm2fb_fix.mmio_start);
1244
1245 /* Registers - request region and map it. */
1246 if ( !request_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len,
1247 "pm2fb regbase") ) {
1248 printk(KERN_WARNING "pm2fb: Can't reserve regbase.\n");
1249 goto err_exit_neither;
1250 }
1251 default_par->v_regs =
1252 ioremap_nocache(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
1253 if ( !default_par->v_regs ) {
1254 printk(KERN_WARNING "pm2fb: Can't remap %s register area.\n",
1255 pm2fb_fix.id);
1256 release_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
1257 goto err_exit_neither;
1258 }
1259
1260 /* Stash away memory register info for use when we reset the board */
1261 default_par->mem_control = pm2_RD(default_par, PM2R_MEM_CONTROL);
1262 default_par->boot_address = pm2_RD(default_par, PM2R_BOOT_ADDRESS);
1263 default_par->mem_config = pm2_RD(default_par, PM2R_MEM_CONFIG);
1264 DPRINTK("MemControl 0x%x BootAddress 0x%x MemConfig 0x%x\n",
1265 default_par->mem_control, default_par->boot_address,
1266 default_par->mem_config);
1267
1268 if(default_par->mem_control == 0 &&
1269 default_par->boot_address == 0x31 &&
1270 default_par->mem_config == 0x259fffff) {
1271 default_par->memclock = CVPPC_MEMCLOCK;
1272 default_par->mem_control=0;
1273 default_par->boot_address=0x20;
1274 default_par->mem_config=0xe6002021;
1275 if (pdev->subsystem_vendor == 0x1048 &&
1276 pdev->subsystem_device == 0x0a31) {
1277 DPRINTK("subsystem_vendor: %04x, subsystem_device: %04x\n",
1278 pdev->subsystem_vendor, pdev->subsystem_device);
1279 DPRINTK("We have not been initialized by VGA BIOS "
1280 "and are running on an Elsa Winner 2000 Office\n");
1281 DPRINTK("Initializing card timings manually...\n");
1282 default_par->memclock=70000;
1283 }
1284 if (pdev->subsystem_vendor == 0x3d3d &&
1285 pdev->subsystem_device == 0x0100) {
1286 DPRINTK("subsystem_vendor: %04x, subsystem_device: %04x\n",
1287 pdev->subsystem_vendor, pdev->subsystem_device);
1288 DPRINTK("We have not been initialized by VGA BIOS "
1289 "and are running on an 3dlabs reference board\n");
1290 DPRINTK("Initializing card timings manually...\n");
1291 default_par->memclock=74894;
1292 }
1293 }
1294
1295 /* Now work out how big lfb is going to be. */
1296 switch(default_par->mem_config & PM2F_MEM_CONFIG_RAM_MASK) {
1297 case PM2F_MEM_BANKS_1:
1298 pm2fb_fix.smem_len=0x200000;
1299 break;
1300 case PM2F_MEM_BANKS_2:
1301 pm2fb_fix.smem_len=0x400000;
1302 break;
1303 case PM2F_MEM_BANKS_3:
1304 pm2fb_fix.smem_len=0x600000;
1305 break;
1306 case PM2F_MEM_BANKS_4:
1307 pm2fb_fix.smem_len=0x800000;
1308 break;
1309 }
1310 pm2fb_fix.smem_start = pci_resource_start(pdev, 1);
1311
1312 /* Linear frame buffer - request region and map it. */
1313 if ( !request_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len,
1314 "pm2fb smem") ) {
1315 printk(KERN_WARNING "pm2fb: Can't reserve smem.\n");
1316 goto err_exit_mmio;
1317 }
1318 info->screen_base =
1319 ioremap_nocache(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
1320 if ( !info->screen_base ) {
1321 printk(KERN_WARNING "pm2fb: Can't ioremap smem area.\n");
1322 release_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
1323 goto err_exit_mmio;
1324 }
1325
1326 info->fbops = &pm2fb_ops;
1327 info->fix = pm2fb_fix;
1328 info->pseudo_palette = default_par->palette;
1329 info->flags = FBINFO_DEFAULT |
1330 FBINFO_HWACCEL_YPAN |
1331 FBINFO_HWACCEL_COPYAREA |
1332 FBINFO_HWACCEL_FILLRECT;
1333
1334 if (!mode)
1335 mode = "640x480@60";
1336
1337 err = fb_find_mode(&info->var, info, mode, NULL, 0, NULL, 8);
1338 if (!err || err == 4)
1339 info->var = pm2fb_var;
1340
1341 if (fb_alloc_cmap(&info->cmap, 256, 0) < 0)
1342 goto err_exit_both;
1343
1344 if (register_framebuffer(info) < 0)
1345 goto err_exit_all;
1346
1347 printk(KERN_INFO "fb%d: %s frame buffer device, memory = %dK.\n",
1348 info->node, info->fix.id, pm2fb_fix.smem_len / 1024);
1349
1350 /*
1351 * Our driver data
1352 */
1353 pci_set_drvdata(pdev, info);
1354
1355 return 0;
1356
1357 err_exit_all:
1358 fb_dealloc_cmap(&info->cmap);
1359 err_exit_both:
1360 iounmap(info->screen_base);
1361 release_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
1362 err_exit_mmio:
1363 iounmap(default_par->v_regs);
1364 release_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
1365 err_exit_neither:
1366 framebuffer_release(info);
1367 return err_retval;
1368 }
1369
1370 /**
1371 * Device removal.
1372 *
1373 * Release all device resources.
1374 *
1375 * @param pdev PCI device to clean up.
1376 */
1377 static void __devexit pm2fb_remove(struct pci_dev *pdev)
1378 {
1379 struct fb_info* info = pci_get_drvdata(pdev);
1380 struct fb_fix_screeninfo* fix = &info->fix;
1381 struct pm2fb_par *par = info->par;
1382
1383 unregister_framebuffer(info);
1384
1385 iounmap(info->screen_base);
1386 release_mem_region(fix->smem_start, fix->smem_len);
1387 iounmap(par->v_regs);
1388 release_mem_region(fix->mmio_start, fix->mmio_len);
1389
1390 pci_set_drvdata(pdev, NULL);
1391 kfree(info);
1392 }
1393
1394 static struct pci_device_id pm2fb_id_table[] = {
1395 { PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TVP4020,
1396 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
1397 0xff0000, 0 },
1398 { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2,
1399 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
1400 0xff0000, 0 },
1401 { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2V,
1402 PCI_ANY_ID, PCI_ANY_ID, PCI_BASE_CLASS_DISPLAY << 16,
1403 0xff0000, 0 },
1404 { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2V,
1405 PCI_ANY_ID, PCI_ANY_ID, PCI_CLASS_NOT_DEFINED_VGA << 8,
1406 0xff00, 0 },
1407 { 0, }
1408 };
1409
1410 static struct pci_driver pm2fb_driver = {
1411 .name = "pm2fb",
1412 .id_table = pm2fb_id_table,
1413 .probe = pm2fb_probe,
1414 .remove = __devexit_p(pm2fb_remove),
1415 };
1416
1417 MODULE_DEVICE_TABLE(pci, pm2fb_id_table);
1418
1419
1420 #ifndef MODULE
1421 /**
1422 * Parse user speficied options.
1423 *
1424 * This is, comma-separated options following `video=pm2fb:'.
1425 */
1426 static int __init pm2fb_setup(char *options)
1427 {
1428 char* this_opt;
1429
1430 if (!options || !*options)
1431 return 0;
1432
1433 while ((this_opt = strsep(&options, ",")) != NULL) {
1434 if (!*this_opt)
1435 continue;
1436 if(!strcmp(this_opt, "lowhsync")) {
1437 lowhsync = 1;
1438 } else if(!strcmp(this_opt, "lowvsync")) {
1439 lowvsync = 1;
1440 } else {
1441 mode = this_opt;
1442 }
1443 }
1444 return 0;
1445 }
1446 #endif
1447
1448
1449 static int __init pm2fb_init(void)
1450 {
1451 #ifndef MODULE
1452 char *option = NULL;
1453
1454 if (fb_get_options("pm2fb", &option))
1455 return -ENODEV;
1456 pm2fb_setup(option);
1457 #endif
1458
1459 return pci_register_driver(&pm2fb_driver);
1460 }
1461
1462 module_init(pm2fb_init);
1463
1464 #ifdef MODULE
1465 /*
1466 * Cleanup
1467 */
1468
1469 static void __exit pm2fb_exit(void)
1470 {
1471 pci_unregister_driver(&pm2fb_driver);
1472 }
1473 #endif
1474
1475 #ifdef MODULE
1476 module_exit(pm2fb_exit);
1477
1478 module_param(mode, charp, 0);
1479 MODULE_PARM_DESC(mode, "Preferred video mode e.g. '648x480-8@60'");
1480 module_param(lowhsync, bool, 0);
1481 MODULE_PARM_DESC(lowhsync, "Force horizontal sync low regardless of mode");
1482 module_param(lowvsync, bool, 0);
1483 MODULE_PARM_DESC(lowvsync, "Force vertical sync low regardless of mode");
1484
1485 MODULE_AUTHOR("Jim Hague <jim.hague@acm.org>");
1486 MODULE_DESCRIPTION("Permedia2 framebuffer device driver");
1487 MODULE_LICENSE("GPL");
1488 #endif
Verdex Pro support