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[PATCH] Avoid console spam with ext3 aborted journal.
[linux-2.6/verdex.git] / arch / i386 / kernel / cpu / common.c
blob11e6e6f23fa01636331c4fff676e10d13976a709
1 #include <linux/init.h>
2 #include <linux/string.h>
3 #include <linux/delay.h>
4 #include <linux/smp.h>
5 #include <linux/module.h>
6 #include <linux/percpu.h>
7 #include <asm/semaphore.h>
8 #include <asm/processor.h>
9 #include <asm/i387.h>
10 #include <asm/msr.h>
11 #include <asm/io.h>
12 #include <asm/mmu_context.h>
13 #ifdef CONFIG_X86_LOCAL_APIC
14 #include <asm/mpspec.h>
15 #include <asm/apic.h>
16 #include <mach_apic.h>
17 #endif
18
19 #include "cpu.h"
20
21 DEFINE_PER_CPU(struct desc_struct, cpu_gdt_table[GDT_ENTRIES]);
22 EXPORT_PER_CPU_SYMBOL(cpu_gdt_table);
23
24 DEFINE_PER_CPU(unsigned char, cpu_16bit_stack[CPU_16BIT_STACK_SIZE]);
25 EXPORT_PER_CPU_SYMBOL(cpu_16bit_stack);
26
27 static int cachesize_override __initdata = -1;
28 static int disable_x86_fxsr __initdata = 0;
29 static int disable_x86_serial_nr __initdata = 1;
30
31 struct cpu_dev * cpu_devs[X86_VENDOR_NUM] = {};
32
33 extern void mcheck_init(struct cpuinfo_x86 *c);
34
35 extern int disable_pse;
36
37 static void default_init(struct cpuinfo_x86 * c)
38 {
39 /* Not much we can do here... */
40 /* Check if at least it has cpuid */
41 if (c->cpuid_level == -1) {
42 /* No cpuid. It must be an ancient CPU */
43 if (c->x86 == 4)
44 strcpy(c->x86_model_id, "486");
45 else if (c->x86 == 3)
46 strcpy(c->x86_model_id, "386");
47 }
48 }
49
50 static struct cpu_dev default_cpu = {
51 .c_init = default_init,
52 };
53 static struct cpu_dev * this_cpu = &default_cpu;
54
55 static int __init cachesize_setup(char *str)
56 {
57 get_option (&str, &cachesize_override);
58 return 1;
59 }
60 __setup("cachesize=", cachesize_setup);
61
62 int __init get_model_name(struct cpuinfo_x86 *c)
63 {
64 unsigned int *v;
65 char *p, *q;
66
67 if (cpuid_eax(0x80000000) < 0x80000004)
68 return 0;
69
70 v = (unsigned int *) c->x86_model_id;
71 cpuid(0x80000002, &v[0], &v[1], &v[2], &v[3]);
72 cpuid(0x80000003, &v[4], &v[5], &v[6], &v[7]);
73 cpuid(0x80000004, &v[8], &v[9], &v[10], &v[11]);
74 c->x86_model_id[48] = 0;
75
76 /* Intel chips right-justify this string for some dumb reason;
77 undo that brain damage */
78 p = q = &c->x86_model_id[0];
79 while ( *p == ' ' )
80 p++;
81 if ( p != q ) {
82 while ( *p )
83 *q++ = *p++;
84 while ( q <= &c->x86_model_id[48] )
85 *q++ = '\0'; /* Zero-pad the rest */
86 }
87
88 return 1;
89 }
90
91
92 void __init display_cacheinfo(struct cpuinfo_x86 *c)
93 {
94 unsigned int n, dummy, ecx, edx, l2size;
95
96 n = cpuid_eax(0x80000000);
97
98 if (n >= 0x80000005) {
99 cpuid(0x80000005, &dummy, &dummy, &ecx, &edx);
100 printk(KERN_INFO "CPU: L1 I Cache: %dK (%d bytes/line), D cache %dK (%d bytes/line)\n",
101 edx>>24, edx&0xFF, ecx>>24, ecx&0xFF);
102 c->x86_cache_size=(ecx>>24)+(edx>>24);
103 }
104
105 if (n < 0x80000006) /* Some chips just has a large L1. */
106 return;
107
108 ecx = cpuid_ecx(0x80000006);
109 l2size = ecx >> 16;
110
111 /* do processor-specific cache resizing */
112 if (this_cpu->c_size_cache)
113 l2size = this_cpu->c_size_cache(c,l2size);
114
115 /* Allow user to override all this if necessary. */
116 if (cachesize_override != -1)
117 l2size = cachesize_override;
118
119 if ( l2size == 0 )
120 return; /* Again, no L2 cache is possible */
121
122 c->x86_cache_size = l2size;
123
124 printk(KERN_INFO "CPU: L2 Cache: %dK (%d bytes/line)\n",
125 l2size, ecx & 0xFF);
126 }
127
128 /* Naming convention should be: <Name> [(<Codename>)] */
129 /* This table only is used unless init_<vendor>() below doesn't set it; */
130 /* in particular, if CPUID levels 0x80000002..4 are supported, this isn't used */
131
132 /* Look up CPU names by table lookup. */
133 static char __init *table_lookup_model(struct cpuinfo_x86 *c)
134 {
135 struct cpu_model_info *info;
136
137 if ( c->x86_model >= 16 )
138 return NULL; /* Range check */
139
140 if (!this_cpu)
141 return NULL;
142
143 info = this_cpu->c_models;
144
145 while (info && info->family) {
146 if (info->family == c->x86)
147 return info->model_names[c->x86_model];
148 info++;
149 }
150 return NULL; /* Not found */
151 }
152
153
154 void __init get_cpu_vendor(struct cpuinfo_x86 *c, int early)
155 {
156 char *v = c->x86_vendor_id;
157 int i;
158
159 for (i = 0; i < X86_VENDOR_NUM; i++) {
160 if (cpu_devs[i]) {
161 if (!strcmp(v,cpu_devs[i]->c_ident[0]) ||
162 (cpu_devs[i]->c_ident[1] &&
163 !strcmp(v,cpu_devs[i]->c_ident[1]))) {
164 c->x86_vendor = i;
165 if (!early)
166 this_cpu = cpu_devs[i];
167 break;
168 }
169 }
170 }
171 }
172
173
174 static int __init x86_fxsr_setup(char * s)
175 {
176 disable_x86_fxsr = 1;
177 return 1;
178 }
179 __setup("nofxsr", x86_fxsr_setup);
180
181
182 /* Standard macro to see if a specific flag is changeable */
183 static inline int flag_is_changeable_p(u32 flag)
184 {
185 u32 f1, f2;
186
187 asm("pushfl\n\t"
188 "pushfl\n\t"
189 "popl %0\n\t"
190 "movl %0,%1\n\t"
191 "xorl %2,%0\n\t"
192 "pushl %0\n\t"
193 "popfl\n\t"
194 "pushfl\n\t"
195 "popl %0\n\t"
196 "popfl\n\t"
197 : "=&r" (f1), "=&r" (f2)
198 : "ir" (flag));
199
200 return ((f1^f2) & flag) != 0;
201 }
202
203
204 /* Probe for the CPUID instruction */
205 static int __init have_cpuid_p(void)
206 {
207 return flag_is_changeable_p(X86_EFLAGS_ID);
208 }
209
210 /* Do minimum CPU detection early.
211 Fields really needed: vendor, cpuid_level, family, model, mask, cache alignment.
212 The others are not touched to avoid unwanted side effects. */
213 static void __init early_cpu_detect(void)
214 {
215 struct cpuinfo_x86 *c = &boot_cpu_data;
216
217 c->x86_cache_alignment = 32;
218
219 if (!have_cpuid_p())
220 return;
221
222 /* Get vendor name */
223 cpuid(0x00000000, &c->cpuid_level,
224 (int *)&c->x86_vendor_id[0],
225 (int *)&c->x86_vendor_id[8],
226 (int *)&c->x86_vendor_id[4]);
227
228 get_cpu_vendor(c, 1);
229
230 c->x86 = 4;
231 if (c->cpuid_level >= 0x00000001) {
232 u32 junk, tfms, cap0, misc;
233 cpuid(0x00000001, &tfms, &misc, &junk, &cap0);
234 c->x86 = (tfms >> 8) & 15;
235 c->x86_model = (tfms >> 4) & 15;
236 if (c->x86 == 0xf) {
237 c->x86 += (tfms >> 20) & 0xff;
238 c->x86_model += ((tfms >> 16) & 0xF) << 4;
239 }
240 c->x86_mask = tfms & 15;
241 if (cap0 & (1<<19))
242 c->x86_cache_alignment = ((misc >> 8) & 0xff) * 8;
243 }
244
245 early_intel_workaround(c);
246
247 #ifdef CONFIG_SMP
248 #ifdef CONFIG_X86_HT
249 phys_proc_id[smp_processor_id()] =
250 #endif
251 cpu_core_id[smp_processor_id()] = (cpuid_ebx(1) >> 24) & 0xff;
252 #endif
253 }
254
255 void __init generic_identify(struct cpuinfo_x86 * c)
256 {
257 u32 tfms, xlvl;
258 int junk;
259
260 if (have_cpuid_p()) {
261 /* Get vendor name */
262 cpuid(0x00000000, &c->cpuid_level,
263 (int *)&c->x86_vendor_id[0],
264 (int *)&c->x86_vendor_id[8],
265 (int *)&c->x86_vendor_id[4]);
266
267 get_cpu_vendor(c, 0);
268 /* Initialize the standard set of capabilities */
269 /* Note that the vendor-specific code below might override */
270
271 /* Intel-defined flags: level 0x00000001 */
272 if ( c->cpuid_level >= 0x00000001 ) {
273 u32 capability, excap;
274 cpuid(0x00000001, &tfms, &junk, &excap, &capability);
275 c->x86_capability[0] = capability;
276 c->x86_capability[4] = excap;
277 c->x86 = (tfms >> 8) & 15;
278 c->x86_model = (tfms >> 4) & 15;
279 if (c->x86 == 0xf) {
280 c->x86 += (tfms >> 20) & 0xff;
281 c->x86_model += ((tfms >> 16) & 0xF) << 4;
282 }
283 c->x86_mask = tfms & 15;
284 } else {
285 /* Have CPUID level 0 only - unheard of */
286 c->x86 = 4;
287 }
288
289 /* AMD-defined flags: level 0x80000001 */
290 xlvl = cpuid_eax(0x80000000);
291 if ( (xlvl & 0xffff0000) == 0x80000000 ) {
292 if ( xlvl >= 0x80000001 ) {
293 c->x86_capability[1] = cpuid_edx(0x80000001);
294 c->x86_capability[6] = cpuid_ecx(0x80000001);
295 }
296 if ( xlvl >= 0x80000004 )
297 get_model_name(c); /* Default name */
298 }
299 }
300 }
301
302 static void __init squash_the_stupid_serial_number(struct cpuinfo_x86 *c)
303 {
304 if (cpu_has(c, X86_FEATURE_PN) && disable_x86_serial_nr ) {
305 /* Disable processor serial number */
306 unsigned long lo,hi;
307 rdmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
308 lo |= 0x200000;
309 wrmsr(MSR_IA32_BBL_CR_CTL,lo,hi);
310 printk(KERN_NOTICE "CPU serial number disabled.\n");
311 clear_bit(X86_FEATURE_PN, c->x86_capability);
312
313 /* Disabling the serial number may affect the cpuid level */
314 c->cpuid_level = cpuid_eax(0);
315 }
316 }
317
318 static int __init x86_serial_nr_setup(char *s)
319 {
320 disable_x86_serial_nr = 0;
321 return 1;
322 }
323 __setup("serialnumber", x86_serial_nr_setup);
324
325
326
327 /*
328 * This does the hard work of actually picking apart the CPU stuff...
329 */
330 void __init identify_cpu(struct cpuinfo_x86 *c)
331 {
332 int i;
333
334 c->loops_per_jiffy = loops_per_jiffy;
335 c->x86_cache_size = -1;
336 c->x86_vendor = X86_VENDOR_UNKNOWN;
337 c->cpuid_level = -1; /* CPUID not detected */
338 c->x86_model = c->x86_mask = 0; /* So far unknown... */
339 c->x86_vendor_id[0] = '\0'; /* Unset */
340 c->x86_model_id[0] = '\0'; /* Unset */
341 c->x86_num_cores = 1;
342 memset(&c->x86_capability, 0, sizeof c->x86_capability);
343
344 if (!have_cpuid_p()) {
345 /* First of all, decide if this is a 486 or higher */
346 /* It's a 486 if we can modify the AC flag */
347 if ( flag_is_changeable_p(X86_EFLAGS_AC) )
348 c->x86 = 4;
349 else
350 c->x86 = 3;
351 }
352
353 generic_identify(c);
354
355 printk(KERN_DEBUG "CPU: After generic identify, caps:");
356 for (i = 0; i < NCAPINTS; i++)
357 printk(" %08lx", c->x86_capability[i]);
358 printk("\n");
359
360 if (this_cpu->c_identify) {
361 this_cpu->c_identify(c);
362
363 printk(KERN_DEBUG "CPU: After vendor identify, caps:");
364 for (i = 0; i < NCAPINTS; i++)
365 printk(" %08lx", c->x86_capability[i]);
366 printk("\n");
367 }
368
369 /*
370 * Vendor-specific initialization. In this section we
371 * canonicalize the feature flags, meaning if there are
372 * features a certain CPU supports which CPUID doesn't
373 * tell us, CPUID claiming incorrect flags, or other bugs,
374 * we handle them here.
375 *
376 * At the end of this section, c->x86_capability better
377 * indicate the features this CPU genuinely supports!
378 */
379 if (this_cpu->c_init)
380 this_cpu->c_init(c);
381
382 /* Disable the PN if appropriate */
383 squash_the_stupid_serial_number(c);
384
385 /*
386 * The vendor-specific functions might have changed features. Now
387 * we do "generic changes."
388 */
389
390 /* TSC disabled? */
391 if ( tsc_disable )
392 clear_bit(X86_FEATURE_TSC, c->x86_capability);
393
394 /* FXSR disabled? */
395 if (disable_x86_fxsr) {
396 clear_bit(X86_FEATURE_FXSR, c->x86_capability);
397 clear_bit(X86_FEATURE_XMM, c->x86_capability);
398 }
399
400 if (disable_pse)
401 clear_bit(X86_FEATURE_PSE, c->x86_capability);
402
403 /* If the model name is still unset, do table lookup. */
404 if ( !c->x86_model_id[0] ) {
405 char *p;
406 p = table_lookup_model(c);
407 if ( p )
408 strcpy(c->x86_model_id, p);
409 else
410 /* Last resort... */
411 sprintf(c->x86_model_id, "%02x/%02x",
412 c->x86_vendor, c->x86_model);
413 }
414
415 /* Now the feature flags better reflect actual CPU features! */
416
417 printk(KERN_DEBUG "CPU: After all inits, caps:");
418 for (i = 0; i < NCAPINTS; i++)
419 printk(" %08lx", c->x86_capability[i]);
420 printk("\n");
421
422 /*
423 * On SMP, boot_cpu_data holds the common feature set between
424 * all CPUs; so make sure that we indicate which features are
425 * common between the CPUs. The first time this routine gets
426 * executed, c == &boot_cpu_data.
427 */
428 if ( c != &boot_cpu_data ) {
429 /* AND the already accumulated flags with these */
430 for ( i = 0 ; i < NCAPINTS ; i++ )
431 boot_cpu_data.x86_capability[i] &= c->x86_capability[i];
432 }
433
434 /* Init Machine Check Exception if available. */
435 #ifdef CONFIG_X86_MCE
436 mcheck_init(c);
437 #endif
438 }
439
440 #ifdef CONFIG_X86_HT
441 void __init detect_ht(struct cpuinfo_x86 *c)
442 {
443 u32 eax, ebx, ecx, edx;
444 int index_msb, tmp;
445 int cpu = smp_processor_id();
446
447 if (!cpu_has(c, X86_FEATURE_HT) || cpu_has(c, X86_FEATURE_CMP_LEGACY))
448 return;
449
450 cpuid(1, &eax, &ebx, &ecx, &edx);
451 smp_num_siblings = (ebx & 0xff0000) >> 16;
452
453 if (smp_num_siblings == 1) {
454 printk(KERN_INFO "CPU: Hyper-Threading is disabled\n");
455 } else if (smp_num_siblings > 1 ) {
456 index_msb = 31;
457
458 if (smp_num_siblings > NR_CPUS) {
459 printk(KERN_WARNING "CPU: Unsupported number of the siblings %d", smp_num_siblings);
460 smp_num_siblings = 1;
461 return;
462 }
463 tmp = smp_num_siblings;
464 while ((tmp & 0x80000000 ) == 0) {
465 tmp <<=1 ;
466 index_msb--;
467 }
468 if (smp_num_siblings & (smp_num_siblings - 1))
469 index_msb++;
470 phys_proc_id[cpu] = phys_pkg_id((ebx >> 24) & 0xFF, index_msb);
471
472 printk(KERN_INFO "CPU: Physical Processor ID: %d\n",
473 phys_proc_id[cpu]);
474
475 smp_num_siblings = smp_num_siblings / c->x86_num_cores;
476
477 tmp = smp_num_siblings;
478 index_msb = 31;
479 while ((tmp & 0x80000000) == 0) {
480 tmp <<=1 ;
481 index_msb--;
482 }
483
484 if (smp_num_siblings & (smp_num_siblings - 1))
485 index_msb++;
486
487 cpu_core_id[cpu] = phys_pkg_id((ebx >> 24) & 0xFF, index_msb);
488
489 if (c->x86_num_cores > 1)
490 printk(KERN_INFO "CPU: Processor Core ID: %d\n",
491 cpu_core_id[cpu]);
492 }
493 }
494 #endif
495
496 void __init print_cpu_info(struct cpuinfo_x86 *c)
497 {
498 char *vendor = NULL;
499
500 if (c->x86_vendor < X86_VENDOR_NUM)
501 vendor = this_cpu->c_vendor;
502 else if (c->cpuid_level >= 0)
503 vendor = c->x86_vendor_id;
504
505 if (vendor && strncmp(c->x86_model_id, vendor, strlen(vendor)))
506 printk("%s ", vendor);
507
508 if (!c->x86_model_id[0])
509 printk("%d86", c->x86);
510 else
511 printk("%s", c->x86_model_id);
512
513 if (c->x86_mask || c->cpuid_level >= 0)
514 printk(" stepping %02x\n", c->x86_mask);
515 else
516 printk("\n");
517 }
518
519 cpumask_t cpu_initialized __initdata = CPU_MASK_NONE;
520
521 /* This is hacky. :)
522 * We're emulating future behavior.
523 * In the future, the cpu-specific init functions will be called implicitly
524 * via the magic of initcalls.
525 * They will insert themselves into the cpu_devs structure.
526 * Then, when cpu_init() is called, we can just iterate over that array.
527 */
528
529 extern int intel_cpu_init(void);
530 extern int cyrix_init_cpu(void);
531 extern int nsc_init_cpu(void);
532 extern int amd_init_cpu(void);
533 extern int centaur_init_cpu(void);
534 extern int transmeta_init_cpu(void);
535 extern int rise_init_cpu(void);
536 extern int nexgen_init_cpu(void);
537 extern int umc_init_cpu(void);
538
539 void __init early_cpu_init(void)
540 {
541 intel_cpu_init();
542 cyrix_init_cpu();
543 nsc_init_cpu();
544 amd_init_cpu();
545 centaur_init_cpu();
546 transmeta_init_cpu();
547 rise_init_cpu();
548 nexgen_init_cpu();
549 umc_init_cpu();
550 early_cpu_detect();
551
552 #ifdef CONFIG_DEBUG_PAGEALLOC
553 /* pse is not compatible with on-the-fly unmapping,
554 * disable it even if the cpus claim to support it.
555 */
556 clear_bit(X86_FEATURE_PSE, boot_cpu_data.x86_capability);
557 disable_pse = 1;
558 #endif
559 }
560 /*
561 * cpu_init() initializes state that is per-CPU. Some data is already
562 * initialized (naturally) in the bootstrap process, such as the GDT
563 * and IDT. We reload them nevertheless, this function acts as a
564 * 'CPU state barrier', nothing should get across.
565 */
566 void __init cpu_init (void)
567 {
568 int cpu = smp_processor_id();
569 struct tss_struct * t = &per_cpu(init_tss, cpu);
570 struct thread_struct *thread = &current->thread;
571 __u32 stk16_off = (__u32)&per_cpu(cpu_16bit_stack, cpu);
572
573 if (cpu_test_and_set(cpu, cpu_initialized)) {
574 printk(KERN_WARNING "CPU#%d already initialized!\n", cpu);
575 for (;;) local_irq_enable();
576 }
577 printk(KERN_INFO "Initializing CPU#%d\n", cpu);
578
579 if (cpu_has_vme || cpu_has_tsc || cpu_has_de)
580 clear_in_cr4(X86_CR4_VME|X86_CR4_PVI|X86_CR4_TSD|X86_CR4_DE);
581 if (tsc_disable && cpu_has_tsc) {
582 printk(KERN_NOTICE "Disabling TSC...\n");
583 /**** FIX-HPA: DOES THIS REALLY BELONG HERE? ****/
584 clear_bit(X86_FEATURE_TSC, boot_cpu_data.x86_capability);
585 set_in_cr4(X86_CR4_TSD);
586 }
587
588 /*
589 * Initialize the per-CPU GDT with the boot GDT,
590 * and set up the GDT descriptor:
591 */
592 memcpy(&per_cpu(cpu_gdt_table, cpu), cpu_gdt_table,
593 GDT_SIZE);
594
595 /* Set up GDT entry for 16bit stack */
596 *(__u64 *)&(per_cpu(cpu_gdt_table, cpu)[GDT_ENTRY_ESPFIX_SS]) |=
597 ((((__u64)stk16_off) << 16) & 0x000000ffffff0000ULL) |
598 ((((__u64)stk16_off) << 32) & 0xff00000000000000ULL) |
599 (CPU_16BIT_STACK_SIZE - 1);
600
601 cpu_gdt_descr[cpu].size = GDT_SIZE - 1;
602 cpu_gdt_descr[cpu].address =
603 (unsigned long)&per_cpu(cpu_gdt_table, cpu);
604
605 /*
606 * Set up the per-thread TLS descriptor cache:
607 */
608 memcpy(thread->tls_array, &per_cpu(cpu_gdt_table, cpu),
609 GDT_ENTRY_TLS_ENTRIES * 8);
610
611 __asm__ __volatile__("lgdt %0" : : "m" (cpu_gdt_descr[cpu]));
612 __asm__ __volatile__("lidt %0" : : "m" (idt_descr));
613
614 /*
615 * Delete NT
616 */
617 __asm__("pushfl ; andl $0xffffbfff,(%esp) ; popfl");
618
619 /*
620 * Set up and load the per-CPU TSS and LDT
621 */
622 atomic_inc(&init_mm.mm_count);
623 current->active_mm = &init_mm;
624 if (current->mm)
625 BUG();
626 enter_lazy_tlb(&init_mm, current);
627
628 load_esp0(t, thread);
629 set_tss_desc(cpu,t);
630 load_TR_desc();
631 load_LDT(&init_mm.context);
632
633 /* Set up doublefault TSS pointer in the GDT */
634 __set_tss_desc(cpu, GDT_ENTRY_DOUBLEFAULT_TSS, &doublefault_tss);
635
636 /* Clear %fs and %gs. */
637 asm volatile ("xorl %eax, %eax; movl %eax, %fs; movl %eax, %gs");
638
639 /* Clear all 6 debug registers: */
640
641 #define CD(register) __asm__("movl %0,%%db" #register ::"r"(0) );
642
643 CD(0); CD(1); CD(2); CD(3); /* no db4 and db5 */; CD(6); CD(7);
644
645 #undef CD
646
647 /*
648 * Force FPU initialization:
649 */
650 current_thread_info()->status = 0;
651 clear_used_math();
652 mxcsr_feature_mask_init();
653 }
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