arch/i386/kernel/cpu/intel.c

   1 #include <linux/config.h>
   2 #include <linux/init.h>
   3 #include <linux/kernel.h>
   4
   5 #include <linux/string.h>
   6 #include <linux/bitops.h>
   7 #include <linux/smp.h>
   8 #include <linux/thread_info.h>
   9
  10 #include <asm/processor.h>
  11 #include <asm/msr.h>
  12 #include <asm/uaccess.h>
  13
  14 #include "cpu.h"
  15
  16 #ifdef CONFIG_X86_LOCAL_APIC
  17 #include <asm/mpspec.h>
  18 #include <asm/apic.h>
  19 #include <mach_apic.h>
  20 #endif
  21
  22 extern int trap_init_f00f_bug(void);
  23
  24 #ifdef CONFIG_X86_INTEL_USERCOPY
  25 /*
  26  * Alignment at which movsl is preferred for bulk memory copies.
  27  */
  28 struct movsl_mask movsl_mask;
  29 #endif
  30
  31 void __init early_intel_workaround(struct cpuinfo_x86 *c)
  32 {
  33         if (c->x86_vendor != X86_VENDOR_INTEL)
  34                 return;
  35         /* Netburst reports 64 bytes clflush size, but does IO in 128 bytes */
  36         if (c->x86 == 15 && c->x86_cache_alignment == 64)
  37                 c->x86_cache_alignment = 128;
  38 }
  39
  40 /*
  41  *      Early probe support logic for ppro memory erratum #50
  42  *
  43  *      This is called before we do cpu ident work
  44  */
  45
  46 int __init ppro_with_ram_bug(void)
  47 {
  48         /* Uses data from early_cpu_detect now */
  49         if (boot_cpu_data.x86_vendor == X86_VENDOR_INTEL &&
  50             boot_cpu_data.x86 == 6 &&
  51             boot_cpu_data.x86_model == 1 &&
  52             boot_cpu_data.x86_mask < 8) {
  53                 printk(KERN_INFO "Pentium Pro with Errata#50 detected. Taking evasive action.\n");
  54                 return 1;
  55         }
  56         return 0;
  57 }
  58
  59
  60 /*
  61  * P4 Xeon errata 037 workaround.
  62  * Hardware prefetcher may cause stale data to be loaded into the cache.
  63  */
  64 static void __init Intel_errata_workarounds(struct cpuinfo_x86 *c)
  65 {
  66         unsigned long lo, hi;
  67
  68         if ((c->x86 == 15) && (c->x86_model == 1) && (c->x86_mask == 1)) {
  69                 rdmsr (MSR_IA32_MISC_ENABLE, lo, hi);
  70                 if ((lo & (1<<9)) == 0) {
  71                         printk (KERN_INFO "CPU: C0 stepping P4 Xeon detected.\n");
  72                         printk (KERN_INFO "CPU: Disabling hardware prefetching (Errata 037)\n");
  73                         lo |= (1<<9);   /* Disable hw prefetching */
  74                         wrmsr (MSR_IA32_MISC_ENABLE, lo, hi);
  75                 }
  76         }
  77 }
  78
  79
  80 /*
  81  * find out the number of processor cores on the die
  82  */
  83 static int __init num_cpu_cores(struct cpuinfo_x86 *c)
  84 {
  85         unsigned int eax;
  86
  87         if (c->cpuid_level < 4)
  88                 return 1;
  89
  90         __asm__("cpuid"
  91                 : "=a" (eax)
  92                 : "0" (4), "c" (0)
  93                 : "bx", "dx");
  94
  95         if (eax & 0x1f)
  96                 return ((eax >> 26) + 1);
  97         else
  98                 return 1;
  99 }
 100
 101 static void __init init_intel(struct cpuinfo_x86 *c)
 102 {
 103         unsigned int l2 = 0;
 104         char *p = NULL;
 105
 106 #ifdef CONFIG_X86_F00F_BUG
 107         /*
 108          * All current models of Pentium and Pentium with MMX technology CPUs
 109          * have the F0 0F bug, which lets nonprivileged users lock up the system.
 110          * Note that the workaround only should be initialized once...
 111          */
 112         c->f00f_bug = 0;
 113         if ( c->x86 == 5 ) {
 114                 static int f00f_workaround_enabled = 0;
 115
 116                 c->f00f_bug = 1;
 117                 if ( !f00f_workaround_enabled ) {
 118                         trap_init_f00f_bug();
 119                         printk(KERN_NOTICE "Intel Pentium with F0 0F bug - workaround enabled.\n");
 120                         f00f_workaround_enabled = 1;
 121                 }
 122         }
 123 #endif
 124
 125         select_idle_routine(c);
 126         l2 = init_intel_cacheinfo(c);
 127
 128         /* SEP CPUID bug: Pentium Pro reports SEP but doesn't have it until model 3 mask 3 */
 129         if ((c->x86<<8 | c->x86_model<<4 | c->x86_mask) < 0x633)
 130                 clear_bit(X86_FEATURE_SEP, c->x86_capability);
 131
 132         /* Names for the Pentium II/Celeron processors
 133            detectable only by also checking the cache size.
 134            Dixon is NOT a Celeron. */
 135         if (c->x86 == 6) {
 136                 switch (c->x86_model) {
 137                 case 5:
 138                         if (c->x86_mask == 0) {
 139                                 if (l2 == 0)
 140                                         p = "Celeron (Covington)";
 141                                 else if (l2 == 256)
 142                                         p = "Mobile Pentium II (Dixon)";
 143                         }
 144                         break;
 145
 146                 case 6:
 147                         if (l2 == 128)
 148                                 p = "Celeron (Mendocino)";
 149                         else if (c->x86_mask == 0 || c->x86_mask == 5)
 150                                 p = "Celeron-A";
 151                         break;
 152
 153                 case 8:
 154                         if (l2 == 128)
 155                                 p = "Celeron (Coppermine)";
 156                         break;
 157                 }
 158         }
 159
 160         if ( p )
 161                 strcpy(c->x86_model_id, p);
 162
 163         c->x86_num_cores = num_cpu_cores(c);
 164
 165         detect_ht(c);
 166
 167         /* Work around errata */
 168         Intel_errata_workarounds(c);
 169
 170 #ifdef CONFIG_X86_INTEL_USERCOPY
 171         /*
 172          * Set up the preferred alignment for movsl bulk memory moves
 173          */
 174         switch (c->x86) {
 175         case 4:         /* 486: untested */
 176                 break;
 177         case 5:         /* Old Pentia: untested */
 178                 break;
 179         case 6:         /* PII/PIII only like movsl with 8-byte alignment */
 180                 movsl_mask.mask = 7;
 181                 break;
 182         case 15:        /* P4 is OK down to 8-byte alignment */
 183                 movsl_mask.mask = 7;
 184                 break;
 185         }
 186 #endif
 187
 188         if (c->x86 == 15)
 189                 set_bit(X86_FEATURE_P4, c->x86_capability);
 190         if (c->x86 == 6)
 191                 set_bit(X86_FEATURE_P3, c->x86_capability);
 192 }
 193
 194
 195 static unsigned int intel_size_cache(struct cpuinfo_x86 * c, unsigned int size)
 196 {
 197         /* Intel PIII Tualatin. This comes in two flavours.
 198          * One has 256kb of cache, the other 512. We have no way
 199          * to determine which, so we use a boottime override
 200          * for the 512kb model, and assume 256 otherwise.
 201          */
 202         if ((c->x86 == 6) && (c->x86_model == 11) && (size == 0))
 203                 size = 256;
 204         return size;
 205 }
 206
 207 static struct cpu_dev intel_cpu_dev __initdata = {
 208         .c_vendor       = "Intel",
 209         .c_ident        = { "GenuineIntel" },
 210         .c_models = {
 211                 { .vendor = X86_VENDOR_INTEL, .family = 4, .model_names =
 212                   {
 213                           [0] = "486 DX-25/33",
 214                           [1] = "486 DX-50",
 215                           [2] = "486 SX",
 216                           [3] = "486 DX/2",
 217                           [4] = "486 SL",
 218                           [5] = "486 SX/2",
 219                           [7] = "486 DX/2-WB",
 220                           [8] = "486 DX/4",
 221                           [9] = "486 DX/4-WB"
 222                   }
 223                 },
 224                 { .vendor = X86_VENDOR_INTEL, .family = 5, .model_names =
 225                   {
 226                           [0] = "Pentium 60/66 A-step",
 227                           [1] = "Pentium 60/66",
 228                           [2] = "Pentium 75 - 200",
 229                           [3] = "OverDrive PODP5V83",
 230                           [4] = "Pentium MMX",
 231                           [7] = "Mobile Pentium 75 - 200",
 232                           [8] = "Mobile Pentium MMX"
 233                   }
 234                 },
 235                 { .vendor = X86_VENDOR_INTEL, .family = 6, .model_names =
 236                   {
 237                           [0] = "Pentium Pro A-step",
 238                           [1] = "Pentium Pro",
 239                           [3] = "Pentium II (Klamath)",
 240                           [4] = "Pentium II (Deschutes)",
 241                           [5] = "Pentium II (Deschutes)",
 242                           [6] = "Mobile Pentium II",
 243                           [7] = "Pentium III (Katmai)",
 244                           [8] = "Pentium III (Coppermine)",
 245                           [10] = "Pentium III (Cascades)",
 246                           [11] = "Pentium III (Tualatin)",
 247                   }
 248                 },
 249                 { .vendor = X86_VENDOR_INTEL, .family = 15, .model_names =
 250                   {
 251                           [0] = "Pentium 4 (Unknown)",
 252                           [1] = "Pentium 4 (Willamette)",
 253                           [2] = "Pentium 4 (Northwood)",
 254                           [4] = "Pentium 4 (Foster)",
 255                           [5] = "Pentium 4 (Foster)",
 256                   }
 257                 },
 258         },
 259         .c_init         = init_intel,
 260         .c_identify     = generic_identify,
 261         .c_size_cache   = intel_size_cache,
 262 };
 263
 264 __init int intel_cpu_init(void)
 265 {
 266         cpu_devs[X86_VENDOR_INTEL] = &intel_cpu_dev;
 267         return 0;
 268 }
 269
 270 // arch_initcall(intel_cpu_init);
 271