arch/i386/kernel/cpu/mcheck/p6.c

   1 /*
   2  * P6 specific Machine Check Exception Reporting
   3  * (C) Copyright 2002 Alan Cox <alan@redhat.com>
   4  */
   5
   6 #include <linux/init.h>
   7 #include <linux/types.h>
   8 #include <linux/kernel.h>
   9 #include <linux/irq.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/smp.h>
  12
  13 #include <asm/processor.h>
  14 #include <asm/system.h>
  15 #include <asm/msr.h>
  16
  17 #include "mce.h"
  18
  19 /* Machine Check Handler For PII/PIII */
  20 static fastcall void intel_machine_check(struct pt_regs * regs, long error_code)
  21 {
  22         int recover=1;
  23         u32 alow, ahigh, high, low;
  24         u32 mcgstl, mcgsth;
  25         int i;
  26
  27         rdmsr (MSR_IA32_MCG_STATUS, mcgstl, mcgsth);
  28         if (mcgstl & (1<<0))    /* Recoverable ? */
  29                 recover=0;
  30
  31         printk (KERN_EMERG "CPU %d: Machine Check Exception: %08x%08x\n",
  32                 smp_processor_id(), mcgsth, mcgstl);
  33
  34         for (i=0; i<nr_mce_banks; i++) {
  35                 rdmsr (MSR_IA32_MC0_STATUS+i*4,low, high);
  36                 if (high & (1<<31)) {
  37                         if (high & (1<<29))
  38                                 recover |= 1;
  39                         if (high & (1<<25))
  40                                 recover |= 2;
  41                         printk (KERN_EMERG "Bank %d: %08x%08x", i, high, low);
  42                         high &= ~(1<<31);
  43                         if (high & (1<<27)) {
  44                                 rdmsr (MSR_IA32_MC0_MISC+i*4, alow, ahigh);
  45                                 printk ("[%08x%08x]", ahigh, alow);
  46                         }
  47                         if (high & (1<<26)) {
  48                                 rdmsr (MSR_IA32_MC0_ADDR+i*4, alow, ahigh);
  49                                 printk (" at %08x%08x", ahigh, alow);
  50                         }
  51                         printk ("\n");
  52                 }
  53         }
  54
  55         if (recover & 2)
  56                 panic ("CPU context corrupt");
  57         if (recover & 1)
  58                 panic ("Unable to continue");
  59
  60         printk (KERN_EMERG "Attempting to continue.\n");
  61         /*
  62          * Do not clear the MSR_IA32_MCi_STATUS if the error is not
  63          * recoverable/continuable.This will allow BIOS to look at the MSRs
  64          * for errors if the OS could not log the error.
  65          */
  66         for (i=0; i<nr_mce_banks; i++) {
  67                 unsigned int msr;
  68                 msr = MSR_IA32_MC0_STATUS+i*4;
  69                 rdmsr (msr,low, high);
  70                 if (high & (1<<31)) {
  71                         /* Clear it */
  72                         wrmsr (msr, 0UL, 0UL);
  73                         /* Serialize */
  74                         wmb();
  75                         add_taint(TAINT_MACHINE_CHECK);
  76                 }
  77         }
  78         mcgstl &= ~(1<<2);
  79         wrmsr (MSR_IA32_MCG_STATUS,mcgstl, mcgsth);
  80 }
  81
  82 /* Set up machine check reporting for processors with Intel style MCE */
  83 void __init intel_p6_mcheck_init(struct cpuinfo_x86 *c)
  84 {
  85         u32 l, h;
  86         int i;
  87
  88         /* Check for MCE support */
  89         if (!cpu_has(c, X86_FEATURE_MCE))
  90                 return;
  91
  92         /* Check for PPro style MCA */
  93         if (!cpu_has(c, X86_FEATURE_MCA))
  94                 return;
  95
  96         /* Ok machine check is available */
  97         machine_check_vector = intel_machine_check;
  98         wmb();
  99
 100         printk (KERN_INFO "Intel machine check architecture supported.\n");
 101         rdmsr (MSR_IA32_MCG_CAP, l, h);
 102         if (l & (1<<8)) /* Control register present ? */
 103                 wrmsr(MSR_IA32_MCG_CTL, 0xffffffff, 0xffffffff);
 104         nr_mce_banks = l & 0xff;
 105
 106         /* Don't enable bank 0 on intel P6 cores, it goes bang quickly. */
 107         for (i=1; i<nr_mce_banks; i++) {
 108                 wrmsr (MSR_IA32_MC0_CTL+4*i, 0xffffffff, 0xffffffff);
 109                 wrmsr (MSR_IA32_MC0_STATUS+4*i, 0x0, 0x0);
 110         }
 111
 112         set_in_cr4 (X86_CR4_MCE);
 113         printk (KERN_INFO "Intel machine check reporting enabled on CPU#%d.\n",
 114                 smp_processor_id());
 115 }