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[PATCH] Avoid console spam with ext3 aborted journal.
[linux-2.6/verdex.git] / arch / x86_64 / kernel / mpparse.c
blobf86d9db94bfcc437b378fc32024d603c449cfdf1
1 /*
2 * Intel Multiprocessor Specification 1.1 and 1.4
3 * compliant MP-table parsing routines.
4 *
5 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
6 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 *
8 * Fixes
9 * Erich Boleyn : MP v1.4 and additional changes.
10 * Alan Cox : Added EBDA scanning
11 * Ingo Molnar : various cleanups and rewrites
12 * Maciej W. Rozycki: Bits for default MP configurations
13 * Paul Diefenbaugh: Added full ACPI support
14 */
15
16 #include <linux/mm.h>
17 #include <linux/irq.h>
18 #include <linux/init.h>
19 #include <linux/delay.h>
20 #include <linux/config.h>
21 #include <linux/bootmem.h>
22 #include <linux/smp_lock.h>
23 #include <linux/kernel_stat.h>
24 #include <linux/mc146818rtc.h>
25 #include <linux/acpi.h>
26
27 #include <asm/smp.h>
28 #include <asm/mtrr.h>
29 #include <asm/mpspec.h>
30 #include <asm/pgalloc.h>
31 #include <asm/io_apic.h>
32 #include <asm/proto.h>
33
34 /* Have we found an MP table */
35 int smp_found_config;
36 unsigned int __initdata maxcpus = NR_CPUS;
37
38 int acpi_found_madt;
39
40 /*
41 * Various Linux-internal data structures created from the
42 * MP-table.
43 */
44 int apic_version [MAX_APICS];
45 unsigned char mp_bus_id_to_type [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
46 int mp_bus_id_to_pci_bus [MAX_MP_BUSSES] = { [0 ... MAX_MP_BUSSES-1] = -1 };
47 cpumask_t pci_bus_to_cpumask [256] = { [0 ... 255] = CPU_MASK_ALL };
48
49 static int mp_current_pci_id = 0;
50 /* I/O APIC entries */
51 struct mpc_config_ioapic mp_ioapics[MAX_IO_APICS];
52
53 /* # of MP IRQ source entries */
54 struct mpc_config_intsrc mp_irqs[MAX_IRQ_SOURCES];
55
56 /* MP IRQ source entries */
57 int mp_irq_entries;
58
59 int nr_ioapics;
60 int pic_mode;
61 unsigned long mp_lapic_addr = 0;
62
63
64
65 /* Processor that is doing the boot up */
66 unsigned int boot_cpu_id = -1U;
67 /* Internal processor count */
68 static unsigned int num_processors = 0;
69
70 /* Bitmask of physically existing CPUs */
71 physid_mask_t phys_cpu_present_map = PHYSID_MASK_NONE;
72
73 /* ACPI MADT entry parsing functions */
74 #ifdef CONFIG_ACPI_BOOT
75 extern struct acpi_boot_flags acpi_boot;
76 #ifdef CONFIG_X86_LOCAL_APIC
77 extern int acpi_parse_lapic (acpi_table_entry_header *header);
78 extern int acpi_parse_lapic_addr_ovr (acpi_table_entry_header *header);
79 extern int acpi_parse_lapic_nmi (acpi_table_entry_header *header);
80 #endif /*CONFIG_X86_LOCAL_APIC*/
81 #ifdef CONFIG_X86_IO_APIC
82 extern int acpi_parse_ioapic (acpi_table_entry_header *header);
83 #endif /*CONFIG_X86_IO_APIC*/
84 #endif /*CONFIG_ACPI_BOOT*/
85
86 u8 bios_cpu_apicid[NR_CPUS] = { [0 ... NR_CPUS-1] = BAD_APICID };
87
88
89 /*
90 * Intel MP BIOS table parsing routines:
91 */
92
93 /*
94 * Checksum an MP configuration block.
95 */
96
97 static int __init mpf_checksum(unsigned char *mp, int len)
98 {
99 int sum = 0;
100
101 while (len--)
102 sum += *mp++;
103
104 return sum & 0xFF;
105 }
106
107 static void __init MP_processor_info (struct mpc_config_processor *m)
108 {
109 int ver;
110 static int found_bsp=0;
111
112 if (!(m->mpc_cpuflag & CPU_ENABLED))
113 return;
114
115 printk(KERN_INFO "Processor #%d %d:%d APIC version %d\n",
116 m->mpc_apicid,
117 (m->mpc_cpufeature & CPU_FAMILY_MASK)>>8,
118 (m->mpc_cpufeature & CPU_MODEL_MASK)>>4,
119 m->mpc_apicver);
120
121 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
122 Dprintk(" Bootup CPU\n");
123 boot_cpu_id = m->mpc_apicid;
124 }
125 if (num_processors >= NR_CPUS) {
126 printk(KERN_WARNING "WARNING: NR_CPUS limit of %i reached."
127 " Processor ignored.\n", NR_CPUS);
128 return;
129 }
130
131 num_processors++;
132
133 if (m->mpc_apicid > MAX_APICS) {
134 printk(KERN_ERR "Processor #%d INVALID. (Max ID: %d).\n",
135 m->mpc_apicid, MAX_APICS);
136 return;
137 }
138 ver = m->mpc_apicver;
139
140 physid_set(m->mpc_apicid, phys_cpu_present_map);
141 /*
142 * Validate version
143 */
144 if (ver == 0x0) {
145 printk(KERN_ERR "BIOS bug, APIC version is 0 for CPU#%d! fixing up to 0x10. (tell your hw vendor)\n", m->mpc_apicid);
146 ver = 0x10;
147 }
148 apic_version[m->mpc_apicid] = ver;
149 if (m->mpc_cpuflag & CPU_BOOTPROCESSOR) {
150 /*
151 * bios_cpu_apicid is required to have processors listed
152 * in same order as logical cpu numbers. Hence the first
153 * entry is BSP, and so on.
154 */
155 bios_cpu_apicid[0] = m->mpc_apicid;
156 x86_cpu_to_apicid[0] = m->mpc_apicid;
157 found_bsp = 1;
158 } else {
159 bios_cpu_apicid[num_processors - found_bsp] = m->mpc_apicid;
160 x86_cpu_to_apicid[num_processors - found_bsp] = m->mpc_apicid;
161 }
162 }
163
164 static void __init MP_bus_info (struct mpc_config_bus *m)
165 {
166 char str[7];
167
168 memcpy(str, m->mpc_bustype, 6);
169 str[6] = 0;
170 Dprintk("Bus #%d is %s\n", m->mpc_busid, str);
171
172 if (strncmp(str, "ISA", 3) == 0) {
173 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_ISA;
174 } else if (strncmp(str, "EISA", 4) == 0) {
175 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_EISA;
176 } else if (strncmp(str, "PCI", 3) == 0) {
177 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_PCI;
178 mp_bus_id_to_pci_bus[m->mpc_busid] = mp_current_pci_id;
179 mp_current_pci_id++;
180 } else if (strncmp(str, "MCA", 3) == 0) {
181 mp_bus_id_to_type[m->mpc_busid] = MP_BUS_MCA;
182 } else {
183 printk(KERN_ERR "Unknown bustype %s\n", str);
184 }
185 }
186
187 static void __init MP_ioapic_info (struct mpc_config_ioapic *m)
188 {
189 if (!(m->mpc_flags & MPC_APIC_USABLE))
190 return;
191
192 printk("I/O APIC #%d Version %d at 0x%X.\n",
193 m->mpc_apicid, m->mpc_apicver, m->mpc_apicaddr);
194 if (nr_ioapics >= MAX_IO_APICS) {
195 printk(KERN_ERR "Max # of I/O APICs (%d) exceeded (found %d).\n",
196 MAX_IO_APICS, nr_ioapics);
197 panic("Recompile kernel with bigger MAX_IO_APICS!.\n");
198 }
199 if (!m->mpc_apicaddr) {
200 printk(KERN_ERR "WARNING: bogus zero I/O APIC address"
201 " found in MP table, skipping!\n");
202 return;
203 }
204 mp_ioapics[nr_ioapics] = *m;
205 nr_ioapics++;
206 }
207
208 static void __init MP_intsrc_info (struct mpc_config_intsrc *m)
209 {
210 mp_irqs [mp_irq_entries] = *m;
211 Dprintk("Int: type %d, pol %d, trig %d, bus %d,"
212 " IRQ %02x, APIC ID %x, APIC INT %02x\n",
213 m->mpc_irqtype, m->mpc_irqflag & 3,
214 (m->mpc_irqflag >> 2) & 3, m->mpc_srcbus,
215 m->mpc_srcbusirq, m->mpc_dstapic, m->mpc_dstirq);
216 if (++mp_irq_entries == MAX_IRQ_SOURCES)
217 panic("Max # of irq sources exceeded!!\n");
218 }
219
220 static void __init MP_lintsrc_info (struct mpc_config_lintsrc *m)
221 {
222 Dprintk("Lint: type %d, pol %d, trig %d, bus %d,"
223 " IRQ %02x, APIC ID %x, APIC LINT %02x\n",
224 m->mpc_irqtype, m->mpc_irqflag & 3,
225 (m->mpc_irqflag >> 2) &3, m->mpc_srcbusid,
226 m->mpc_srcbusirq, m->mpc_destapic, m->mpc_destapiclint);
227 /*
228 * Well it seems all SMP boards in existence
229 * use ExtINT/LVT1 == LINT0 and
230 * NMI/LVT2 == LINT1 - the following check
231 * will show us if this assumptions is false.
232 * Until then we do not have to add baggage.
233 */
234 if ((m->mpc_irqtype == mp_ExtINT) &&
235 (m->mpc_destapiclint != 0))
236 BUG();
237 if ((m->mpc_irqtype == mp_NMI) &&
238 (m->mpc_destapiclint != 1))
239 BUG();
240 }
241
242 /*
243 * Read/parse the MPC
244 */
245
246 static int __init smp_read_mpc(struct mp_config_table *mpc)
247 {
248 char str[16];
249 int count=sizeof(*mpc);
250 unsigned char *mpt=((unsigned char *)mpc)+count;
251
252 if (memcmp(mpc->mpc_signature,MPC_SIGNATURE,4)) {
253 printk("SMP mptable: bad signature [%c%c%c%c]!\n",
254 mpc->mpc_signature[0],
255 mpc->mpc_signature[1],
256 mpc->mpc_signature[2],
257 mpc->mpc_signature[3]);
258 return 0;
259 }
260 if (mpf_checksum((unsigned char *)mpc,mpc->mpc_length)) {
261 printk("SMP mptable: checksum error!\n");
262 return 0;
263 }
264 if (mpc->mpc_spec!=0x01 && mpc->mpc_spec!=0x04) {
265 printk(KERN_ERR "SMP mptable: bad table version (%d)!!\n",
266 mpc->mpc_spec);
267 return 0;
268 }
269 if (!mpc->mpc_lapic) {
270 printk(KERN_ERR "SMP mptable: null local APIC address!\n");
271 return 0;
272 }
273 memcpy(str,mpc->mpc_oem,8);
274 str[8]=0;
275 printk(KERN_INFO "OEM ID: %s ",str);
276
277 memcpy(str,mpc->mpc_productid,12);
278 str[12]=0;
279 printk(KERN_INFO "Product ID: %s ",str);
280
281 printk(KERN_INFO "APIC at: 0x%X\n",mpc->mpc_lapic);
282
283 /* save the local APIC address, it might be non-default */
284 if (!acpi_lapic)
285 mp_lapic_addr = mpc->mpc_lapic;
286
287 /*
288 * Now process the configuration blocks.
289 */
290 while (count < mpc->mpc_length) {
291 switch(*mpt) {
292 case MP_PROCESSOR:
293 {
294 struct mpc_config_processor *m=
295 (struct mpc_config_processor *)mpt;
296 if (!acpi_lapic)
297 MP_processor_info(m);
298 mpt += sizeof(*m);
299 count += sizeof(*m);
300 break;
301 }
302 case MP_BUS:
303 {
304 struct mpc_config_bus *m=
305 (struct mpc_config_bus *)mpt;
306 MP_bus_info(m);
307 mpt += sizeof(*m);
308 count += sizeof(*m);
309 break;
310 }
311 case MP_IOAPIC:
312 {
313 struct mpc_config_ioapic *m=
314 (struct mpc_config_ioapic *)mpt;
315 MP_ioapic_info(m);
316 mpt+=sizeof(*m);
317 count+=sizeof(*m);
318 break;
319 }
320 case MP_INTSRC:
321 {
322 struct mpc_config_intsrc *m=
323 (struct mpc_config_intsrc *)mpt;
324
325 MP_intsrc_info(m);
326 mpt+=sizeof(*m);
327 count+=sizeof(*m);
328 break;
329 }
330 case MP_LINTSRC:
331 {
332 struct mpc_config_lintsrc *m=
333 (struct mpc_config_lintsrc *)mpt;
334 MP_lintsrc_info(m);
335 mpt+=sizeof(*m);
336 count+=sizeof(*m);
337 break;
338 }
339 }
340 }
341 clustered_apic_check();
342 if (!num_processors)
343 printk(KERN_ERR "SMP mptable: no processors registered!\n");
344 return num_processors;
345 }
346
347 static int __init ELCR_trigger(unsigned int irq)
348 {
349 unsigned int port;
350
351 port = 0x4d0 + (irq >> 3);
352 return (inb(port) >> (irq & 7)) & 1;
353 }
354
355 static void __init construct_default_ioirq_mptable(int mpc_default_type)
356 {
357 struct mpc_config_intsrc intsrc;
358 int i;
359 int ELCR_fallback = 0;
360
361 intsrc.mpc_type = MP_INTSRC;
362 intsrc.mpc_irqflag = 0; /* conforming */
363 intsrc.mpc_srcbus = 0;
364 intsrc.mpc_dstapic = mp_ioapics[0].mpc_apicid;
365
366 intsrc.mpc_irqtype = mp_INT;
367
368 /*
369 * If true, we have an ISA/PCI system with no IRQ entries
370 * in the MP table. To prevent the PCI interrupts from being set up
371 * incorrectly, we try to use the ELCR. The sanity check to see if
372 * there is good ELCR data is very simple - IRQ0, 1, 2 and 13 can
373 * never be level sensitive, so we simply see if the ELCR agrees.
374 * If it does, we assume it's valid.
375 */
376 if (mpc_default_type == 5) {
377 printk(KERN_INFO "ISA/PCI bus type with no IRQ information... falling back to ELCR\n");
378
379 if (ELCR_trigger(0) || ELCR_trigger(1) || ELCR_trigger(2) || ELCR_trigger(13))
380 printk(KERN_ERR "ELCR contains invalid data... not using ELCR\n");
381 else {
382 printk(KERN_INFO "Using ELCR to identify PCI interrupts\n");
383 ELCR_fallback = 1;
384 }
385 }
386
387 for (i = 0; i < 16; i++) {
388 switch (mpc_default_type) {
389 case 2:
390 if (i == 0 || i == 13)
391 continue; /* IRQ0 & IRQ13 not connected */
392 /* fall through */
393 default:
394 if (i == 2)
395 continue; /* IRQ2 is never connected */
396 }
397
398 if (ELCR_fallback) {
399 /*
400 * If the ELCR indicates a level-sensitive interrupt, we
401 * copy that information over to the MP table in the
402 * irqflag field (level sensitive, active high polarity).
403 */
404 if (ELCR_trigger(i))
405 intsrc.mpc_irqflag = 13;
406 else
407 intsrc.mpc_irqflag = 0;
408 }
409
410 intsrc.mpc_srcbusirq = i;
411 intsrc.mpc_dstirq = i ? i : 2; /* IRQ0 to INTIN2 */
412 MP_intsrc_info(&intsrc);
413 }
414
415 intsrc.mpc_irqtype = mp_ExtINT;
416 intsrc.mpc_srcbusirq = 0;
417 intsrc.mpc_dstirq = 0; /* 8259A to INTIN0 */
418 MP_intsrc_info(&intsrc);
419 }
420
421 static inline void __init construct_default_ISA_mptable(int mpc_default_type)
422 {
423 struct mpc_config_processor processor;
424 struct mpc_config_bus bus;
425 struct mpc_config_ioapic ioapic;
426 struct mpc_config_lintsrc lintsrc;
427 int linttypes[2] = { mp_ExtINT, mp_NMI };
428 int i;
429
430 /*
431 * local APIC has default address
432 */
433 mp_lapic_addr = APIC_DEFAULT_PHYS_BASE;
434
435 /*
436 * 2 CPUs, numbered 0 & 1.
437 */
438 processor.mpc_type = MP_PROCESSOR;
439 /* Either an integrated APIC or a discrete 82489DX. */
440 processor.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
441 processor.mpc_cpuflag = CPU_ENABLED;
442 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
443 (boot_cpu_data.x86_model << 4) |
444 boot_cpu_data.x86_mask;
445 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
446 processor.mpc_reserved[0] = 0;
447 processor.mpc_reserved[1] = 0;
448 for (i = 0; i < 2; i++) {
449 processor.mpc_apicid = i;
450 MP_processor_info(&processor);
451 }
452
453 bus.mpc_type = MP_BUS;
454 bus.mpc_busid = 0;
455 switch (mpc_default_type) {
456 default:
457 printk(KERN_ERR "???\nUnknown standard configuration %d\n",
458 mpc_default_type);
459 /* fall through */
460 case 1:
461 case 5:
462 memcpy(bus.mpc_bustype, "ISA ", 6);
463 break;
464 case 2:
465 case 6:
466 case 3:
467 memcpy(bus.mpc_bustype, "EISA ", 6);
468 break;
469 case 4:
470 case 7:
471 memcpy(bus.mpc_bustype, "MCA ", 6);
472 }
473 MP_bus_info(&bus);
474 if (mpc_default_type > 4) {
475 bus.mpc_busid = 1;
476 memcpy(bus.mpc_bustype, "PCI ", 6);
477 MP_bus_info(&bus);
478 }
479
480 ioapic.mpc_type = MP_IOAPIC;
481 ioapic.mpc_apicid = 2;
482 ioapic.mpc_apicver = mpc_default_type > 4 ? 0x10 : 0x01;
483 ioapic.mpc_flags = MPC_APIC_USABLE;
484 ioapic.mpc_apicaddr = 0xFEC00000;
485 MP_ioapic_info(&ioapic);
486
487 /*
488 * We set up most of the low 16 IO-APIC pins according to MPS rules.
489 */
490 construct_default_ioirq_mptable(mpc_default_type);
491
492 lintsrc.mpc_type = MP_LINTSRC;
493 lintsrc.mpc_irqflag = 0; /* conforming */
494 lintsrc.mpc_srcbusid = 0;
495 lintsrc.mpc_srcbusirq = 0;
496 lintsrc.mpc_destapic = MP_APIC_ALL;
497 for (i = 0; i < 2; i++) {
498 lintsrc.mpc_irqtype = linttypes[i];
499 lintsrc.mpc_destapiclint = i;
500 MP_lintsrc_info(&lintsrc);
501 }
502 }
503
504 static struct intel_mp_floating *mpf_found;
505
506 /*
507 * Scan the memory blocks for an SMP configuration block.
508 */
509 void __init get_smp_config (void)
510 {
511 struct intel_mp_floating *mpf = mpf_found;
512
513 /*
514 * ACPI may be used to obtain the entire SMP configuration or just to
515 * enumerate/configure processors (CONFIG_ACPI_BOOT). Note that
516 * ACPI supports both logical (e.g. Hyper-Threading) and physical
517 * processors, where MPS only supports physical.
518 */
519 if (acpi_lapic && acpi_ioapic) {
520 printk(KERN_INFO "Using ACPI (MADT) for SMP configuration information\n");
521 return;
522 }
523 else if (acpi_lapic)
524 printk(KERN_INFO "Using ACPI for processor (LAPIC) configuration information\n");
525
526 printk("Intel MultiProcessor Specification v1.%d\n", mpf->mpf_specification);
527 if (mpf->mpf_feature2 & (1<<7)) {
528 printk(KERN_INFO " IMCR and PIC compatibility mode.\n");
529 pic_mode = 1;
530 } else {
531 printk(KERN_INFO " Virtual Wire compatibility mode.\n");
532 pic_mode = 0;
533 }
534
535 /*
536 * Now see if we need to read further.
537 */
538 if (mpf->mpf_feature1 != 0) {
539
540 printk(KERN_INFO "Default MP configuration #%d\n", mpf->mpf_feature1);
541 construct_default_ISA_mptable(mpf->mpf_feature1);
542
543 } else if (mpf->mpf_physptr) {
544
545 /*
546 * Read the physical hardware table. Anything here will
547 * override the defaults.
548 */
549 if (!smp_read_mpc((void *)(unsigned long)mpf->mpf_physptr)) {
550 smp_found_config = 0;
551 printk(KERN_ERR "BIOS bug, MP table errors detected!...\n");
552 printk(KERN_ERR "... disabling SMP support. (tell your hw vendor)\n");
553 return;
554 }
555 /*
556 * If there are no explicit MP IRQ entries, then we are
557 * broken. We set up most of the low 16 IO-APIC pins to
558 * ISA defaults and hope it will work.
559 */
560 if (!mp_irq_entries) {
561 struct mpc_config_bus bus;
562
563 printk(KERN_ERR "BIOS bug, no explicit IRQ entries, using default mptable. (tell your hw vendor)\n");
564
565 bus.mpc_type = MP_BUS;
566 bus.mpc_busid = 0;
567 memcpy(bus.mpc_bustype, "ISA ", 6);
568 MP_bus_info(&bus);
569
570 construct_default_ioirq_mptable(0);
571 }
572
573 } else
574 BUG();
575
576 printk(KERN_INFO "Processors: %d\n", num_processors);
577 /*
578 * Only use the first configuration found.
579 */
580 }
581
582 static int __init smp_scan_config (unsigned long base, unsigned long length)
583 {
584 extern void __bad_mpf_size(void);
585 unsigned int *bp = phys_to_virt(base);
586 struct intel_mp_floating *mpf;
587
588 Dprintk("Scan SMP from %p for %ld bytes.\n", bp,length);
589 if (sizeof(*mpf) != 16)
590 __bad_mpf_size();
591
592 while (length > 0) {
593 mpf = (struct intel_mp_floating *)bp;
594 if ((*bp == SMP_MAGIC_IDENT) &&
595 (mpf->mpf_length == 1) &&
596 !mpf_checksum((unsigned char *)bp, 16) &&
597 ((mpf->mpf_specification == 1)
598 || (mpf->mpf_specification == 4)) ) {
599
600 smp_found_config = 1;
601 reserve_bootmem_generic(virt_to_phys(mpf), PAGE_SIZE);
602 if (mpf->mpf_physptr)
603 reserve_bootmem_generic(mpf->mpf_physptr, PAGE_SIZE);
604 mpf_found = mpf;
605 return 1;
606 }
607 bp += 4;
608 length -= 16;
609 }
610 return 0;
611 }
612
613 void __init find_intel_smp (void)
614 {
615 unsigned int address;
616
617 /*
618 * FIXME: Linux assumes you have 640K of base ram..
619 * this continues the error...
620 *
621 * 1) Scan the bottom 1K for a signature
622 * 2) Scan the top 1K of base RAM
623 * 3) Scan the 64K of bios
624 */
625 if (smp_scan_config(0x0,0x400) ||
626 smp_scan_config(639*0x400,0x400) ||
627 smp_scan_config(0xF0000,0x10000))
628 return;
629 /*
630 * If it is an SMP machine we should know now, unless the
631 * configuration is in an EISA/MCA bus machine with an
632 * extended bios data area.
633 *
634 * there is a real-mode segmented pointer pointing to the
635 * 4K EBDA area at 0x40E, calculate and scan it here.
636 *
637 * NOTE! There are Linux loaders that will corrupt the EBDA
638 * area, and as such this kind of SMP config may be less
639 * trustworthy, simply because the SMP table may have been
640 * stomped on during early boot. These loaders are buggy and
641 * should be fixed.
642 */
643
644 address = *(unsigned short *)phys_to_virt(0x40E);
645 address <<= 4;
646 if (smp_scan_config(address, 0x1000))
647 return;
648
649 /* If we have come this far, we did not find an MP table */
650 printk(KERN_INFO "No mptable found.\n");
651 }
652
653 /*
654 * - Intel MP Configuration Table
655 */
656 void __init find_smp_config (void)
657 {
658 #ifdef CONFIG_X86_LOCAL_APIC
659 find_intel_smp();
660 #endif
661 }
662
663
664 /* --------------------------------------------------------------------------
665 ACPI-based MP Configuration
666 -------------------------------------------------------------------------- */
667
668 #ifdef CONFIG_ACPI_BOOT
669
670 void __init mp_register_lapic_address (
671 u64 address)
672 {
673 mp_lapic_addr = (unsigned long) address;
674
675 set_fixmap_nocache(FIX_APIC_BASE, mp_lapic_addr);
676
677 if (boot_cpu_id == -1U)
678 boot_cpu_id = GET_APIC_ID(apic_read(APIC_ID));
679
680 Dprintk("Boot CPU = %d\n", boot_cpu_physical_apicid);
681 }
682
683
684 void __init mp_register_lapic (
685 u8 id,
686 u8 enabled)
687 {
688 struct mpc_config_processor processor;
689 int boot_cpu = 0;
690
691 if (id >= MAX_APICS) {
692 printk(KERN_WARNING "Processor #%d invalid (max %d)\n",
693 id, MAX_APICS);
694 return;
695 }
696
697 if (id == boot_cpu_physical_apicid)
698 boot_cpu = 1;
699
700 processor.mpc_type = MP_PROCESSOR;
701 processor.mpc_apicid = id;
702 processor.mpc_apicver = 0x10; /* TBD: lapic version */
703 processor.mpc_cpuflag = (enabled ? CPU_ENABLED : 0);
704 processor.mpc_cpuflag |= (boot_cpu ? CPU_BOOTPROCESSOR : 0);
705 processor.mpc_cpufeature = (boot_cpu_data.x86 << 8) |
706 (boot_cpu_data.x86_model << 4) | boot_cpu_data.x86_mask;
707 processor.mpc_featureflag = boot_cpu_data.x86_capability[0];
708 processor.mpc_reserved[0] = 0;
709 processor.mpc_reserved[1] = 0;
710
711 MP_processor_info(&processor);
712 }
713
714 #ifdef CONFIG_X86_IO_APIC
715
716 #define MP_ISA_BUS 0
717 #define MP_MAX_IOAPIC_PIN 127
718
719 static struct mp_ioapic_routing {
720 int apic_id;
721 int gsi_start;
722 int gsi_end;
723 u32 pin_programmed[4];
724 } mp_ioapic_routing[MAX_IO_APICS];
725
726
727 static int mp_find_ioapic (
728 int gsi)
729 {
730 int i = 0;
731
732 /* Find the IOAPIC that manages this GSI. */
733 for (i = 0; i < nr_ioapics; i++) {
734 if ((gsi >= mp_ioapic_routing[i].gsi_start)
735 && (gsi <= mp_ioapic_routing[i].gsi_end))
736 return i;
737 }
738
739 printk(KERN_ERR "ERROR: Unable to locate IOAPIC for GSI %d\n", gsi);
740
741 return -1;
742 }
743
744
745 void __init mp_register_ioapic (
746 u8 id,
747 u32 address,
748 u32 gsi_base)
749 {
750 int idx = 0;
751
752 if (nr_ioapics >= MAX_IO_APICS) {
753 printk(KERN_ERR "ERROR: Max # of I/O APICs (%d) exceeded "
754 "(found %d)\n", MAX_IO_APICS, nr_ioapics);
755 panic("Recompile kernel with bigger MAX_IO_APICS!\n");
756 }
757 if (!address) {
758 printk(KERN_ERR "WARNING: Bogus (zero) I/O APIC address"
759 " found in MADT table, skipping!\n");
760 return;
761 }
762
763 idx = nr_ioapics++;
764
765 mp_ioapics[idx].mpc_type = MP_IOAPIC;
766 mp_ioapics[idx].mpc_flags = MPC_APIC_USABLE;
767 mp_ioapics[idx].mpc_apicaddr = address;
768
769 set_fixmap_nocache(FIX_IO_APIC_BASE_0 + idx, address);
770 mp_ioapics[idx].mpc_apicid = id;
771 mp_ioapics[idx].mpc_apicver = io_apic_get_version(idx);
772
773 /*
774 * Build basic IRQ lookup table to facilitate gsi->io_apic lookups
775 * and to prevent reprogramming of IOAPIC pins (PCI IRQs).
776 */
777 mp_ioapic_routing[idx].apic_id = mp_ioapics[idx].mpc_apicid;
778 mp_ioapic_routing[idx].gsi_start = gsi_base;
779 mp_ioapic_routing[idx].gsi_end = gsi_base +
780 io_apic_get_redir_entries(idx);
781
782 printk(KERN_INFO "IOAPIC[%d]: apic_id %d, version %d, address 0x%x, "
783 "GSI %d-%d\n", idx, mp_ioapics[idx].mpc_apicid,
784 mp_ioapics[idx].mpc_apicver, mp_ioapics[idx].mpc_apicaddr,
785 mp_ioapic_routing[idx].gsi_start,
786 mp_ioapic_routing[idx].gsi_end);
787
788 return;
789 }
790
791
792 void __init mp_override_legacy_irq (
793 u8 bus_irq,
794 u8 polarity,
795 u8 trigger,
796 u32 gsi)
797 {
798 struct mpc_config_intsrc intsrc;
799 int ioapic = -1;
800 int pin = -1;
801
802 /*
803 * Convert 'gsi' to 'ioapic.pin'.
804 */
805 ioapic = mp_find_ioapic(gsi);
806 if (ioapic < 0)
807 return;
808 pin = gsi - mp_ioapic_routing[ioapic].gsi_start;
809
810 /*
811 * TBD: This check is for faulty timer entries, where the override
812 * erroneously sets the trigger to level, resulting in a HUGE
813 * increase of timer interrupts!
814 */
815 if ((bus_irq == 0) && (trigger == 3))
816 trigger = 1;
817
818 intsrc.mpc_type = MP_INTSRC;
819 intsrc.mpc_irqtype = mp_INT;
820 intsrc.mpc_irqflag = (trigger << 2) | polarity;
821 intsrc.mpc_srcbus = MP_ISA_BUS;
822 intsrc.mpc_srcbusirq = bus_irq; /* IRQ */
823 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid; /* APIC ID */
824 intsrc.mpc_dstirq = pin; /* INTIN# */
825
826 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, %d-%d\n",
827 intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
828 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
829 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic, intsrc.mpc_dstirq);
830
831 mp_irqs[mp_irq_entries] = intsrc;
832 if (++mp_irq_entries == MAX_IRQ_SOURCES)
833 panic("Max # of irq sources exceeded!\n");
834
835 return;
836 }
837
838
839 void __init mp_config_acpi_legacy_irqs (void)
840 {
841 struct mpc_config_intsrc intsrc;
842 int i = 0;
843 int ioapic = -1;
844
845 /*
846 * Fabricate the legacy ISA bus (bus #31).
847 */
848 mp_bus_id_to_type[MP_ISA_BUS] = MP_BUS_ISA;
849 Dprintk("Bus #%d is ISA\n", MP_ISA_BUS);
850
851 /*
852 * Locate the IOAPIC that manages the ISA IRQs (0-15).
853 */
854 ioapic = mp_find_ioapic(0);
855 if (ioapic < 0)
856 return;
857
858 intsrc.mpc_type = MP_INTSRC;
859 intsrc.mpc_irqflag = 0; /* Conforming */
860 intsrc.mpc_srcbus = MP_ISA_BUS;
861 intsrc.mpc_dstapic = mp_ioapics[ioapic].mpc_apicid;
862
863 /*
864 * Use the default configuration for the IRQs 0-15. Unless
865 * overridden by (MADT) interrupt source override entries.
866 */
867 for (i = 0; i < 16; i++) {
868 int idx;
869
870 for (idx = 0; idx < mp_irq_entries; idx++) {
871 struct mpc_config_intsrc *irq = mp_irqs + idx;
872
873 /* Do we already have a mapping for this ISA IRQ? */
874 if (irq->mpc_srcbus == MP_ISA_BUS && irq->mpc_srcbusirq == i)
875 break;
876
877 /* Do we already have a mapping for this IOAPIC pin */
878 if ((irq->mpc_dstapic == intsrc.mpc_dstapic) &&
879 (irq->mpc_dstirq == i))
880 break;
881 }
882
883 if (idx != mp_irq_entries) {
884 printk(KERN_DEBUG "ACPI: IRQ%d used by override.\n", i);
885 continue; /* IRQ already used */
886 }
887
888 intsrc.mpc_irqtype = mp_INT;
889 intsrc.mpc_srcbusirq = i; /* Identity mapped */
890 intsrc.mpc_dstirq = i;
891
892 Dprintk("Int: type %d, pol %d, trig %d, bus %d, irq %d, "
893 "%d-%d\n", intsrc.mpc_irqtype, intsrc.mpc_irqflag & 3,
894 (intsrc.mpc_irqflag >> 2) & 3, intsrc.mpc_srcbus,
895 intsrc.mpc_srcbusirq, intsrc.mpc_dstapic,
896 intsrc.mpc_dstirq);
897
898 mp_irqs[mp_irq_entries] = intsrc;
899 if (++mp_irq_entries == MAX_IRQ_SOURCES)
900 panic("Max # of irq sources exceeded!\n");
901 }
902
903 return;
904 }
905
906 int mp_register_gsi(u32 gsi, int edge_level, int active_high_low)
907 {
908 int ioapic = -1;
909 int ioapic_pin = 0;
910 int idx, bit = 0;
911
912 if (acpi_irq_model != ACPI_IRQ_MODEL_IOAPIC)
913 return gsi;
914
915 #ifdef CONFIG_ACPI_BUS
916 /* Don't set up the ACPI SCI because it's already set up */
917 if (acpi_fadt.sci_int == gsi)
918 return gsi;
919 #endif
920
921 ioapic = mp_find_ioapic(gsi);
922 if (ioapic < 0) {
923 printk(KERN_WARNING "No IOAPIC for GSI %u\n", gsi);
924 return gsi;
925 }
926
927 ioapic_pin = gsi - mp_ioapic_routing[ioapic].gsi_start;
928
929 /*
930 * Avoid pin reprogramming. PRTs typically include entries
931 * with redundant pin->gsi mappings (but unique PCI devices);
932 * we only program the IOAPIC on the first.
933 */
934 bit = ioapic_pin % 32;
935 idx = (ioapic_pin < 32) ? 0 : (ioapic_pin / 32);
936 if (idx > 3) {
937 printk(KERN_ERR "Invalid reference to IOAPIC pin "
938 "%d-%d\n", mp_ioapic_routing[ioapic].apic_id,
939 ioapic_pin);
940 return gsi;
941 }
942 if ((1<<bit) & mp_ioapic_routing[ioapic].pin_programmed[idx]) {
943 Dprintk(KERN_DEBUG "Pin %d-%d already programmed\n",
944 mp_ioapic_routing[ioapic].apic_id, ioapic_pin);
945 return gsi;
946 }
947
948 mp_ioapic_routing[ioapic].pin_programmed[idx] |= (1<<bit);
949
950 io_apic_set_pci_routing(ioapic, ioapic_pin, gsi,
951 edge_level == ACPI_EDGE_SENSITIVE ? 0 : 1,
952 active_high_low == ACPI_ACTIVE_HIGH ? 0 : 1);
953 return gsi;
954 }
955
956 #endif /*CONFIG_X86_IO_APIC*/
957 #endif /*CONFIG_ACPI_BOOT*/
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