arch/ppc/platforms/pq2ads.h

   1 /*
   2  * A collection of structures, addresses, and values associated with
   3  * the Motorola MPC8260ADS/MPC8266ADS-PCI boards.
   4  * Copied from the RPX-Classic and SBS8260 stuff.
   5  *
   6  * Copyright (c) 2001 Dan Malek (dan@mvista.com)
   7  */
   8 #ifdef __KERNEL__
   9 #ifndef __MACH_ADS8260_DEFS
  10 #define __MACH_ADS8260_DEFS
  11
  12 #include <linux/config.h>
  13
  14 #include <asm/ppcboot.h>
  15
  16 #if defined(CONFIG_ADS8272)
  17 #define BOARD_CHIP_NAME "8272"
  18 #endif
  19
  20 /* Memory map is configured by the PROM startup.
  21  * We just map a few things we need.  The CSR is actually 4 byte-wide
  22  * registers that can be accessed as 8-, 16-, or 32-bit values.
  23  */
  24 #define CPM_MAP_ADDR            ((uint)0xf0000000)
  25 #define BCSR_ADDR               ((uint)0xf4500000)
  26 #define BCSR_SIZE               ((uint)(32 * 1024))
  27
  28 #define BOOTROM_RESTART_ADDR    ((uint)0xff000104)
  29
  30 /* For our show_cpuinfo hooks. */
  31 #define CPUINFO_VENDOR          "Motorola"
  32 #define CPUINFO_MACHINE         "PQ2 ADS PowerPC"
  33
  34 /* The ADS8260 has 16, 32-bit wide control/status registers, accessed
  35  * only on word boundaries.
  36  * Not all are used (yet), or are interesting to us (yet).
  37  */
  38
  39 /* Things of interest in the CSR.
  40 */
  41 #define BCSR0_LED0              ((uint)0x02000000)      /* 0 == on */
  42 #define BCSR0_LED1              ((uint)0x01000000)      /* 0 == on */
  43 #define BCSR1_FETHIEN           ((uint)0x08000000)      /* 0 == enable */
  44 #define BCSR1_FETH_RST          ((uint)0x04000000)      /* 0 == reset */
  45 #define BCSR1_RS232_EN1         ((uint)0x02000000)      /* 0 == enable */
  46 #define BCSR1_RS232_EN2         ((uint)0x01000000)      /* 0 == enable */
  47 #define BCSR3_FETHIEN2          ((uint)0x10000000)      /* 0 == enable */
  48 #define BCSR3_FETH2_RST         ((uint)0x80000000)      /* 0 == reset */
  49
  50 #define PHY_INTERRUPT   SIU_INT_IRQ7
  51
  52 #ifdef CONFIG_PCI
  53 /* PCI interrupt controller */
  54 #define PCI_INT_STAT_REG        0xF8200000
  55 #define PCI_INT_MASK_REG        0xF8200004
  56 #define PIRQA                   (NR_CPM_INTS + 0)
  57 #define PIRQB                   (NR_CPM_INTS + 1)
  58 #define PIRQC                   (NR_CPM_INTS + 2)
  59 #define PIRQD                   (NR_CPM_INTS + 3)
  60
  61 /*
  62  * PCI memory map definitions for MPC8266ADS-PCI.
  63  *
  64  * processor view
  65  *      local address           PCI address             target
  66  *      0x80000000-0x9FFFFFFF   0x80000000-0x9FFFFFFF   PCI mem with prefetch
  67  *      0xA0000000-0xBFFFFFFF   0xA0000000-0xBFFFFFFF   PCI mem w/o prefetch
  68  *      0xF4000000-0xF7FFFFFF   0x00000000-0x03FFFFFF   PCI IO
  69  *
  70  * PCI master view
  71  *      local address           PCI address             target
  72  *      0x00000000-0x1FFFFFFF   0x00000000-0x1FFFFFFF   MPC8266 local memory
  73  */
  74
  75 /* All the other PCI memory map definitions reside at syslib/m82xx_pci.h
  76    Here we should redefine what is unique for this board */
  77 #define M82xx_PCI_SLAVE_MEM_LOCAL       0x00000000      /* Local base */
  78 #define M82xx_PCI_SLAVE_MEM_BUS         0x00000000      /* PCI base */
  79 #define M82xx_PCI_SLAVE_MEM_SIZE        0x10000000      /* 256 Mb */
  80
  81 #define M82xx_PCI_SLAVE_SEC_WND_SIZE    ~(0x40000000 - 1U)      /* 2 x 512Mb  */
  82 #define M82xx_PCI_SLAVE_SEC_WND_BASE    0x80000000              /* PCI Memory base */
  83
  84 #if defined(CONFIG_ADS8272)
  85 #define PCI_INT_TO_SIU  SIU_INT_IRQ2
  86 #elif defined(CONFIG_PQ2FADS)
  87 #define PCI_INT_TO_SIU  SIU_INT_IRQ6
  88 #else
  89 #warning PCI Bridge will be without interrupts support
  90 #endif
  91
  92 #endif /* CONFIG_PCI */
  93
  94 #endif /* __MACH_ADS8260_DEFS */
  95 #endif /* __KERNEL__ */