1 #include <linux/kernel.h>
2 #include <linux/sched.h>
3 #include <linux/interrupt.h>
4 #include <linux/init.h>
5 #include <linux/clocksource.h>
6 #include <linux/time.h>
7 #include <linux/acpi.h>
8 #include <linux/cpufreq.h>
9 #include <linux/acpi_pmtmr.h>
12 #include <asm/timex.h>
14 static int notsc __initdata
= 0;
16 unsigned int cpu_khz
; /* TSC clocks / usec, not used here */
17 EXPORT_SYMBOL(cpu_khz
);
19 EXPORT_SYMBOL(tsc_khz
);
21 static unsigned int cyc2ns_scale __read_mostly
;
23 static inline void set_cyc2ns_scale(unsigned long khz
)
25 cyc2ns_scale
= (NSEC_PER_MSEC
<< NS_SCALE
) / khz
;
28 static unsigned long long cycles_2_ns(unsigned long long cyc
)
30 return (cyc
* cyc2ns_scale
) >> NS_SCALE
;
33 unsigned long long sched_clock(void)
37 /* Could do CPU core sync here. Opteron can execute rdtsc speculatively,
38 * which means it is not completely exact and may not be monotonous
39 * between CPUs. But the errors should be too small to matter for
40 * scheduling purposes.
44 return cycles_2_ns(a
);
47 static int tsc_unstable
;
49 inline int check_tsc_unstable(void)
53 #ifdef CONFIG_CPU_FREQ
55 /* Frequency scaling support. Adjust the TSC based timer when the cpu frequency
58 * RED-PEN: On SMP we assume all CPUs run with the same frequency. It's
59 * not that important because current Opteron setups do not support
60 * scaling on SMP anyroads.
62 * Should fix up last_tsc too. Currently gettimeofday in the
63 * first tick after the change will be slightly wrong.
66 static unsigned int ref_freq
;
67 static unsigned long loops_per_jiffy_ref
;
68 static unsigned long tsc_khz_ref
;
70 static int time_cpufreq_notifier(struct notifier_block
*nb
, unsigned long val
,
73 struct cpufreq_freqs
*freq
= data
;
74 unsigned long *lpj
, dummy
;
76 if (cpu_has(&cpu_data
[freq
->cpu
], X86_FEATURE_CONSTANT_TSC
))
80 if (!(freq
->flags
& CPUFREQ_CONST_LOOPS
))
82 lpj
= &cpu_data
[freq
->cpu
].loops_per_jiffy
;
84 lpj
= &boot_cpu_data
.loops_per_jiffy
;
89 loops_per_jiffy_ref
= *lpj
;
90 tsc_khz_ref
= tsc_khz
;
92 if ((val
== CPUFREQ_PRECHANGE
&& freq
->old
< freq
->new) ||
93 (val
== CPUFREQ_POSTCHANGE
&& freq
->old
> freq
->new) ||
94 (val
== CPUFREQ_RESUMECHANGE
)) {
96 cpufreq_scale(loops_per_jiffy_ref
, ref_freq
, freq
->new);
98 tsc_khz
= cpufreq_scale(tsc_khz_ref
, ref_freq
, freq
->new);
99 if (!(freq
->flags
& CPUFREQ_CONST_LOOPS
))
100 mark_tsc_unstable("cpufreq changes");
103 set_cyc2ns_scale(tsc_khz_ref
);
108 static struct notifier_block time_cpufreq_notifier_block
= {
109 .notifier_call
= time_cpufreq_notifier
112 static int __init
cpufreq_tsc(void)
114 cpufreq_register_notifier(&time_cpufreq_notifier_block
,
115 CPUFREQ_TRANSITION_NOTIFIER
);
119 core_initcall(cpufreq_tsc
);
123 #define MAX_RETRIES 5
124 #define SMI_TRESHOLD 50000
127 * Read TSC and the reference counters. Take care of SMI disturbance
129 static unsigned long __init
tsc_read_refs(unsigned long *pm
,
132 unsigned long t1
, t2
;
135 for (i
= 0; i
< MAX_RETRIES
; i
++) {
136 t1
= get_cycles_sync();
138 *hpet
= hpet_readl(HPET_COUNTER
) & 0xFFFFFFFF;
140 *pm
= acpi_pm_read_early();
141 t2
= get_cycles_sync();
142 if ((t2
- t1
) < SMI_TRESHOLD
)
149 * tsc_calibrate - calibrate the tsc on boot
151 void __init
tsc_calibrate(void)
153 unsigned long flags
, tsc1
, tsc2
, tr1
, tr2
, pm1
, pm2
, hpet1
, hpet2
;
154 int hpet
= is_hpet_enabled();
156 local_irq_save(flags
);
158 tsc1
= tsc_read_refs(&pm1
, hpet
? &hpet1
: NULL
);
160 outb((inb(0x61) & ~0x02) | 0x01, 0x61);
163 outb((CLOCK_TICK_RATE
/ (1000 / 50)) & 0xff, 0x42);
164 outb((CLOCK_TICK_RATE
/ (1000 / 50)) >> 8, 0x42);
165 tr1
= get_cycles_sync();
166 while ((inb(0x61) & 0x20) == 0);
167 tr2
= get_cycles_sync();
169 tsc2
= tsc_read_refs(&pm2
, hpet
? &hpet2
: NULL
);
171 local_irq_restore(flags
);
174 * Preset the result with the raw and inaccurate PIT
177 tsc_khz
= (tr2
- tr1
) / 50;
179 /* hpet or pmtimer available ? */
180 if (!hpet
&& !pm1
&& !pm2
) {
181 printk(KERN_INFO
"TSC calibrated against PIT\n");
185 /* Check, whether the sampling was disturbed by an SMI */
186 if (tsc1
== ULONG_MAX
|| tsc2
== ULONG_MAX
) {
187 printk(KERN_WARNING
"TSC calibration disturbed by SMI, "
188 "using PIT calibration result\n");
192 tsc2
= (tsc2
- tsc1
) * 1000000L;
195 printk(KERN_INFO
"TSC calibrated against HPET\n");
197 hpet2
+= 0x100000000;
199 tsc1
= (hpet2
* hpet_readl(HPET_PERIOD
)) / 1000000;
201 printk(KERN_INFO
"TSC calibrated against PM_TIMER\n");
203 pm2
+= ACPI_PM_OVRRUN
;
205 tsc1
= (pm2
* 1000000000) / PMTMR_TICKS_PER_SEC
;
208 tsc_khz
= tsc2
/ tsc1
;
209 set_cyc2ns_scale(tsc_khz
);
213 * Make an educated guess if the TSC is trustworthy and synchronized
216 __cpuinit
int unsynchronized_tsc(void)
222 if (apic_is_clustered_box())
225 /* Most intel systems have synchronized TSCs except for
226 multi node systems */
227 if (boot_cpu_data
.x86_vendor
== X86_VENDOR_INTEL
) {
229 /* But TSC doesn't tick in C3 so don't use it there */
230 if (acpi_gbl_FADT
.header
.length
> 0 &&
231 acpi_gbl_FADT
.C3latency
< 1000)
237 /* Assume multi socket systems are not synchronized */
238 return num_present_cpus() > 1;
241 int __init
notsc_setup(char *s
)
247 __setup("notsc", notsc_setup
);
250 /* clock source code: */
251 static cycle_t
read_tsc(void)
253 cycle_t ret
= (cycle_t
)get_cycles_sync();
257 static cycle_t __vsyscall_fn
vread_tsc(void)
259 cycle_t ret
= (cycle_t
)get_cycles_sync();
263 static struct clocksource clocksource_tsc
= {
267 .mask
= CLOCKSOURCE_MASK(64),
269 .flags
= CLOCK_SOURCE_IS_CONTINUOUS
|
270 CLOCK_SOURCE_MUST_VERIFY
,
274 void mark_tsc_unstable(char *reason
)
278 printk("Marking TSC unstable due to %s\n", reason
);
279 /* Change only the rating, when not registered */
280 if (clocksource_tsc
.mult
)
281 clocksource_change_rating(&clocksource_tsc
, 0);
283 clocksource_tsc
.rating
= 0;
286 EXPORT_SYMBOL_GPL(mark_tsc_unstable
);
288 void __init
init_tsc_clocksource(void)
291 clocksource_tsc
.mult
= clocksource_khz2mult(tsc_khz
,
292 clocksource_tsc
.shift
);
293 if (check_tsc_unstable())
294 clocksource_tsc
.rating
= 0;
296 clocksource_register(&clocksource_tsc
);