2 * x86 SMP booting functions
4 * (c) 1995 Alan Cox, Building #3 <alan@redhat.com>
5 * (c) 1998, 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Much of the core SMP work is based on previous work by Thomas Radke, to
8 * whom a great many thanks are extended.
10 * Thanks to Intel for making available several different Pentium,
11 * Pentium Pro and Pentium-II/Xeon MP machines.
12 * Original development of Linux SMP code supported by Caldera.
14 * This code is released under the GNU General Public License version 2 or
18 * Felix Koop : NR_CPUS used properly
19 * Jose Renau : Handle single CPU case.
20 * Alan Cox : By repeated request 8) - Total BogoMIPS report.
21 * Greg Wright : Fix for kernel stacks panic.
22 * Erich Boleyn : MP v1.4 and additional changes.
23 * Matthias Sattler : Changes for 2.1 kernel map.
24 * Michel Lespinasse : Changes for 2.1 kernel map.
25 * Michael Chastain : Change trampoline.S to gnu as.
26 * Alan Cox : Dumb bug: 'B' step PPro's are fine
27 * Ingo Molnar : Added APIC timers, based on code
29 * Ingo Molnar : various cleanups and rewrites
30 * Tigran Aivazian : fixed "0.00 in /proc/uptime on SMP" bug.
31 * Maciej W. Rozycki : Bits for genuine 82489DX APICs
32 * Martin J. Bligh : Added support for multi-quad systems
33 * Dave Jones : Report invalid combinations of Athlon CPUs.
34 * Rusty Russell : Hacked into shape for new "hotplug" boot process. */
36 #include <linux/module.h>
37 #include <linux/config.h>
38 #include <linux/init.h>
39 #include <linux/kernel.h>
42 #include <linux/sched.h>
43 #include <linux/kernel_stat.h>
44 #include <linux/smp_lock.h>
45 #include <linux/bootmem.h>
46 #include <linux/notifier.h>
47 #include <linux/cpu.h>
48 #include <linux/percpu.h>
50 #include <linux/delay.h>
51 #include <linux/mc146818rtc.h>
52 #include <asm/tlbflush.h>
54 #include <asm/arch_hooks.h>
56 #include <mach_apic.h>
57 #include <mach_wakecpu.h>
58 #include <smpboot_hooks.h>
60 /* Set if we find a B stepping CPU */
61 static int __devinitdata smp_b_stepping
;
63 /* Number of siblings per CPU package */
64 int smp_num_siblings
= 1;
66 EXPORT_SYMBOL(smp_num_siblings
);
69 /* Package ID of each logical CPU */
70 int phys_proc_id
[NR_CPUS
] __read_mostly
= {[0 ... NR_CPUS
-1] = BAD_APICID
};
72 /* Core ID of each logical CPU */
73 int cpu_core_id
[NR_CPUS
] __read_mostly
= {[0 ... NR_CPUS
-1] = BAD_APICID
};
75 /* representing HT siblings of each logical CPU */
76 cpumask_t cpu_sibling_map
[NR_CPUS
] __read_mostly
;
77 EXPORT_SYMBOL(cpu_sibling_map
);
79 /* representing HT and core siblings of each logical CPU */
80 cpumask_t cpu_core_map
[NR_CPUS
] __read_mostly
;
81 EXPORT_SYMBOL(cpu_core_map
);
83 /* bitmap of online cpus */
84 cpumask_t cpu_online_map __read_mostly
;
85 EXPORT_SYMBOL(cpu_online_map
);
87 cpumask_t cpu_callin_map
;
88 cpumask_t cpu_callout_map
;
89 EXPORT_SYMBOL(cpu_callout_map
);
90 cpumask_t cpu_possible_map
;
91 EXPORT_SYMBOL(cpu_possible_map
);
92 static cpumask_t smp_commenced_mask
;
94 /* TSC's upper 32 bits can't be written in eariler CPU (before prescott), there
95 * is no way to resync one AP against BP. TBD: for prescott and above, we
96 * should use IA64's algorithm
98 static int __devinitdata tsc_sync_disabled
;
100 /* Per CPU bogomips and other parameters */
101 struct cpuinfo_x86 cpu_data
[NR_CPUS
] __cacheline_aligned
;
102 EXPORT_SYMBOL(cpu_data
);
104 u8 x86_cpu_to_apicid
[NR_CPUS
] __read_mostly
=
105 { [0 ... NR_CPUS
-1] = 0xff };
106 EXPORT_SYMBOL(x86_cpu_to_apicid
);
109 * Trampoline 80x86 program as an array.
112 extern unsigned char trampoline_data
[];
113 extern unsigned char trampoline_end
[];
114 static unsigned char *trampoline_base
;
115 static int trampoline_exec
;
117 static void map_cpu_to_logical_apicid(void);
119 /* State of each CPU. */
120 DEFINE_PER_CPU(int, cpu_state
) = { 0 };
123 * Currently trivial. Write the real->protected mode
124 * bootstrap into the page concerned. The caller
125 * has made sure it's suitably aligned.
128 static unsigned long __devinit
setup_trampoline(void)
130 memcpy(trampoline_base
, trampoline_data
, trampoline_end
- trampoline_data
);
131 return virt_to_phys(trampoline_base
);
135 * We are called very early to get the low memory for the
136 * SMP bootup trampoline page.
138 void __init
smp_alloc_memory(void)
140 trampoline_base
= (void *) alloc_bootmem_low_pages(PAGE_SIZE
);
142 * Has to be in very low memory so we can execute
145 if (__pa(trampoline_base
) >= 0x9F000)
148 * Make the SMP trampoline executable:
150 trampoline_exec
= set_kernel_exec((unsigned long)trampoline_base
, 1);
154 * The bootstrap kernel entry code has set these up. Save them for
158 static void __devinit
smp_store_cpu_info(int id
)
160 struct cpuinfo_x86
*c
= cpu_data
+ id
;
166 * Mask B, Pentium, but not Pentium MMX
168 if (c
->x86_vendor
== X86_VENDOR_INTEL
&&
170 c
->x86_mask
>= 1 && c
->x86_mask
<= 4 &&
173 * Remember we have B step Pentia with bugs
178 * Certain Athlons might work (for various values of 'work') in SMP
179 * but they are not certified as MP capable.
181 if ((c
->x86_vendor
== X86_VENDOR_AMD
) && (c
->x86
== 6)) {
183 /* Athlon 660/661 is valid. */
184 if ((c
->x86_model
==6) && ((c
->x86_mask
==0) || (c
->x86_mask
==1)))
187 /* Duron 670 is valid */
188 if ((c
->x86_model
==7) && (c
->x86_mask
==0))
192 * Athlon 662, Duron 671, and Athlon >model 7 have capability bit.
193 * It's worth noting that the A5 stepping (662) of some Athlon XP's
194 * have the MP bit set.
195 * See http://www.heise.de/newsticker/data/jow-18.10.01-000 for more.
197 if (((c
->x86_model
==6) && (c
->x86_mask
>=2)) ||
198 ((c
->x86_model
==7) && (c
->x86_mask
>=1)) ||
203 /* If we get here, it's not a certified SMP capable AMD system. */
204 add_taint(TAINT_UNSAFE_SMP
);
212 * TSC synchronization.
214 * We first check whether all CPUs have their TSC's synchronized,
215 * then we print a warning if not, and always resync.
218 static atomic_t tsc_start_flag
= ATOMIC_INIT(0);
219 static atomic_t tsc_count_start
= ATOMIC_INIT(0);
220 static atomic_t tsc_count_stop
= ATOMIC_INIT(0);
221 static unsigned long long tsc_values
[NR_CPUS
];
225 static void __init
synchronize_tsc_bp (void)
228 unsigned long long t0
;
229 unsigned long long sum
, avg
;
231 unsigned int one_usec
;
234 printk(KERN_INFO
"checking TSC synchronization across %u CPUs: ", num_booting_cpus());
236 /* convert from kcyc/sec to cyc/usec */
237 one_usec
= cpu_khz
/ 1000;
239 atomic_set(&tsc_start_flag
, 1);
243 * We loop a few times to get a primed instruction cache,
244 * then the last pass is more or less synchronized and
245 * the BP and APs set their cycle counters to zero all at
246 * once. This reduces the chance of having random offsets
247 * between the processors, and guarantees that the maximum
248 * delay between the cycle counters is never bigger than
249 * the latency of information-passing (cachelines) between
252 for (i
= 0; i
< NR_LOOPS
; i
++) {
254 * all APs synchronize but they loop on '== num_cpus'
256 while (atomic_read(&tsc_count_start
) != num_booting_cpus()-1)
258 atomic_set(&tsc_count_stop
, 0);
261 * this lets the APs save their current TSC:
263 atomic_inc(&tsc_count_start
);
265 rdtscll(tsc_values
[smp_processor_id()]);
267 * We clear the TSC in the last loop:
273 * Wait for all APs to leave the synchronization point:
275 while (atomic_read(&tsc_count_stop
) != num_booting_cpus()-1)
277 atomic_set(&tsc_count_start
, 0);
279 atomic_inc(&tsc_count_stop
);
283 for (i
= 0; i
< NR_CPUS
; i
++) {
284 if (cpu_isset(i
, cpu_callout_map
)) {
290 do_div(avg
, num_booting_cpus());
293 for (i
= 0; i
< NR_CPUS
; i
++) {
294 if (!cpu_isset(i
, cpu_callout_map
))
296 delta
= tsc_values
[i
] - avg
;
300 * We report bigger than 2 microseconds clock differences.
302 if (delta
> 2*one_usec
) {
309 do_div(realdelta
, one_usec
);
310 if (tsc_values
[i
] < avg
)
311 realdelta
= -realdelta
;
313 printk(KERN_INFO
"CPU#%d had %ld usecs TSC skew, fixed it up.\n", i
, realdelta
);
322 static void __init
synchronize_tsc_ap (void)
327 * Not every cpu is online at the time
328 * this gets called, so we first wait for the BP to
329 * finish SMP initialization:
331 while (!atomic_read(&tsc_start_flag
)) mb();
333 for (i
= 0; i
< NR_LOOPS
; i
++) {
334 atomic_inc(&tsc_count_start
);
335 while (atomic_read(&tsc_count_start
) != num_booting_cpus())
338 rdtscll(tsc_values
[smp_processor_id()]);
342 atomic_inc(&tsc_count_stop
);
343 while (atomic_read(&tsc_count_stop
) != num_booting_cpus()) mb();
348 extern void calibrate_delay(void);
350 static atomic_t init_deasserted
;
352 static void __devinit
smp_callin(void)
355 unsigned long timeout
;
358 * If waken up by an INIT in an 82489DX configuration
359 * we may get here before an INIT-deassert IPI reaches
360 * our local APIC. We have to wait for the IPI or we'll
361 * lock up on an APIC access.
363 wait_for_init_deassert(&init_deasserted
);
366 * (This works even if the APIC is not enabled.)
368 phys_id
= GET_APIC_ID(apic_read(APIC_ID
));
369 cpuid
= smp_processor_id();
370 if (cpu_isset(cpuid
, cpu_callin_map
)) {
371 printk("huh, phys CPU#%d, CPU#%d already present??\n",
375 Dprintk("CPU#%d (phys ID: %d) waiting for CALLOUT\n", cpuid
, phys_id
);
378 * STARTUP IPIs are fragile beasts as they might sometimes
379 * trigger some glue motherboard logic. Complete APIC bus
380 * silence for 1 second, this overestimates the time the
381 * boot CPU is spending to send the up to 2 STARTUP IPIs
382 * by a factor of two. This should be enough.
386 * Waiting 2s total for startup (udelay is not yet working)
388 timeout
= jiffies
+ 2*HZ
;
389 while (time_before(jiffies
, timeout
)) {
391 * Has the boot CPU finished it's STARTUP sequence?
393 if (cpu_isset(cpuid
, cpu_callout_map
))
398 if (!time_before(jiffies
, timeout
)) {
399 printk("BUG: CPU%d started up but did not get a callout!\n",
405 * the boot CPU has finished the init stage and is spinning
406 * on callin_map until we finish. We are free to set up this
407 * CPU, first the APIC. (this is probably redundant on most
411 Dprintk("CALLIN, before setup_local_APIC().\n");
412 smp_callin_clear_local_apic();
414 map_cpu_to_logical_apicid();
420 Dprintk("Stack at about %p\n",&cpuid
);
423 * Save our processor parameters
425 smp_store_cpu_info(cpuid
);
427 disable_APIC_timer();
430 * Allow the master to continue.
432 cpu_set(cpuid
, cpu_callin_map
);
435 * Synchronize the TSC with the BP
437 if (cpu_has_tsc
&& cpu_khz
&& !tsc_sync_disabled
)
438 synchronize_tsc_ap();
443 /* representing cpus for which sibling maps can be computed */
444 static cpumask_t cpu_sibling_setup_map
;
447 set_cpu_sibling_map(int cpu
)
450 struct cpuinfo_x86
*c
= cpu_data
;
452 cpu_set(cpu
, cpu_sibling_setup_map
);
454 if (smp_num_siblings
> 1) {
455 for_each_cpu_mask(i
, cpu_sibling_setup_map
) {
456 if (phys_proc_id
[cpu
] == phys_proc_id
[i
] &&
457 cpu_core_id
[cpu
] == cpu_core_id
[i
]) {
458 cpu_set(i
, cpu_sibling_map
[cpu
]);
459 cpu_set(cpu
, cpu_sibling_map
[i
]);
460 cpu_set(i
, cpu_core_map
[cpu
]);
461 cpu_set(cpu
, cpu_core_map
[i
]);
465 cpu_set(cpu
, cpu_sibling_map
[cpu
]);
468 if (current_cpu_data
.x86_max_cores
== 1) {
469 cpu_core_map
[cpu
] = cpu_sibling_map
[cpu
];
470 c
[cpu
].booted_cores
= 1;
474 for_each_cpu_mask(i
, cpu_sibling_setup_map
) {
475 if (phys_proc_id
[cpu
] == phys_proc_id
[i
]) {
476 cpu_set(i
, cpu_core_map
[cpu
]);
477 cpu_set(cpu
, cpu_core_map
[i
]);
479 * Does this new cpu bringup a new core?
481 if (cpus_weight(cpu_sibling_map
[cpu
]) == 1) {
483 * for each core in package, increment
484 * the booted_cores for this new cpu
486 if (first_cpu(cpu_sibling_map
[i
]) == i
)
487 c
[cpu
].booted_cores
++;
489 * increment the core count for all
490 * the other cpus in this package
494 } else if (i
!= cpu
&& !c
[cpu
].booted_cores
)
495 c
[cpu
].booted_cores
= c
[i
].booted_cores
;
501 * Activate a secondary processor.
503 static void __devinit
start_secondary(void *unused
)
506 * Dont put anything before smp_callin(), SMP
507 * booting is too fragile that we want to limit the
508 * things done here to the most necessary things.
513 while (!cpu_isset(smp_processor_id(), smp_commenced_mask
))
515 setup_secondary_APIC_clock();
516 if (nmi_watchdog
== NMI_IO_APIC
) {
517 disable_8259A_irq(0);
518 enable_NMI_through_LVT0(NULL
);
523 * low-memory mappings have been cleared, flush them from
524 * the local TLBs too.
528 /* This must be done before setting cpu_online_map */
529 set_cpu_sibling_map(raw_smp_processor_id());
533 * We need to hold call_lock, so there is no inconsistency
534 * between the time smp_call_function() determines number of
535 * IPI receipients, and the time when the determination is made
536 * for which cpus receive the IPI. Holding this
537 * lock helps us to not include this cpu in a currently in progress
538 * smp_call_function().
540 lock_ipi_call_lock();
541 cpu_set(smp_processor_id(), cpu_online_map
);
542 unlock_ipi_call_lock();
543 per_cpu(cpu_state
, smp_processor_id()) = CPU_ONLINE
;
545 /* We can take interrupts now: we're officially "up". */
553 * Everything has been set up for the secondary
554 * CPUs - they just need to reload everything
555 * from the task structure
556 * This function must not return.
558 void __devinit
initialize_secondary(void)
561 * We don't actually need to load the full TSS,
562 * basically just the stack pointer and the eip.
569 :"r" (current
->thread
.esp
),"r" (current
->thread
.eip
));
579 /* which logical CPUs are on which nodes */
580 cpumask_t node_2_cpu_mask
[MAX_NUMNODES
] __read_mostly
=
581 { [0 ... MAX_NUMNODES
-1] = CPU_MASK_NONE
};
582 /* which node each logical CPU is on */
583 int cpu_2_node
[NR_CPUS
] __read_mostly
= { [0 ... NR_CPUS
-1] = 0 };
584 EXPORT_SYMBOL(cpu_2_node
);
586 /* set up a mapping between cpu and node. */
587 static inline void map_cpu_to_node(int cpu
, int node
)
589 printk("Mapping cpu %d to node %d\n", cpu
, node
);
590 cpu_set(cpu
, node_2_cpu_mask
[node
]);
591 cpu_2_node
[cpu
] = node
;
594 /* undo a mapping between cpu and node. */
595 static inline void unmap_cpu_to_node(int cpu
)
599 printk("Unmapping cpu %d from all nodes\n", cpu
);
600 for (node
= 0; node
< MAX_NUMNODES
; node
++)
601 cpu_clear(cpu
, node_2_cpu_mask
[node
]);
604 #else /* !CONFIG_NUMA */
606 #define map_cpu_to_node(cpu, node) ({})
607 #define unmap_cpu_to_node(cpu) ({})
609 #endif /* CONFIG_NUMA */
611 u8 cpu_2_logical_apicid
[NR_CPUS
] __read_mostly
= { [0 ... NR_CPUS
-1] = BAD_APICID
};
613 static void map_cpu_to_logical_apicid(void)
615 int cpu
= smp_processor_id();
616 int apicid
= logical_smp_processor_id();
618 cpu_2_logical_apicid
[cpu
] = apicid
;
619 map_cpu_to_node(cpu
, apicid_to_node(apicid
));
622 static void unmap_cpu_to_logical_apicid(int cpu
)
624 cpu_2_logical_apicid
[cpu
] = BAD_APICID
;
625 unmap_cpu_to_node(cpu
);
629 static inline void __inquire_remote_apic(int apicid
)
631 int i
, regs
[] = { APIC_ID
>> 4, APIC_LVR
>> 4, APIC_SPIV
>> 4 };
632 char *names
[] = { "ID", "VERSION", "SPIV" };
635 printk("Inquiring remote APIC #%d...\n", apicid
);
637 for (i
= 0; i
< ARRAY_SIZE(regs
); i
++) {
638 printk("... APIC #%d %s: ", apicid
, names
[i
]);
643 apic_wait_icr_idle();
645 apic_write_around(APIC_ICR2
, SET_APIC_DEST_FIELD(apicid
));
646 apic_write_around(APIC_ICR
, APIC_DM_REMRD
| regs
[i
]);
651 status
= apic_read(APIC_ICR
) & APIC_ICR_RR_MASK
;
652 } while (status
== APIC_ICR_RR_INPROG
&& timeout
++ < 1000);
655 case APIC_ICR_RR_VALID
:
656 status
= apic_read(APIC_RRR
);
657 printk("%08x\n", status
);
666 #ifdef WAKE_SECONDARY_VIA_NMI
668 * Poke the other CPU in the eye via NMI to wake it up. Remember that the normal
669 * INIT, INIT, STARTUP sequence will reset the chip hard for us, and this
670 * won't ... remember to clear down the APIC, etc later.
673 wakeup_secondary_cpu(int logical_apicid
, unsigned long start_eip
)
675 unsigned long send_status
= 0, accept_status
= 0;
679 apic_write_around(APIC_ICR2
, SET_APIC_DEST_FIELD(logical_apicid
));
681 /* Boot on the stack */
682 /* Kick the second */
683 apic_write_around(APIC_ICR
, APIC_DM_NMI
| APIC_DEST_LOGICAL
);
685 Dprintk("Waiting for send to finish...\n");
690 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
691 } while (send_status
&& (timeout
++ < 1000));
694 * Give the other CPU some time to accept the IPI.
698 * Due to the Pentium erratum 3AP.
700 maxlvt
= get_maxlvt();
702 apic_read_around(APIC_SPIV
);
703 apic_write(APIC_ESR
, 0);
705 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
706 Dprintk("NMI sent.\n");
709 printk("APIC never delivered???\n");
711 printk("APIC delivery error (%lx).\n", accept_status
);
713 return (send_status
| accept_status
);
715 #endif /* WAKE_SECONDARY_VIA_NMI */
717 #ifdef WAKE_SECONDARY_VIA_INIT
719 wakeup_secondary_cpu(int phys_apicid
, unsigned long start_eip
)
721 unsigned long send_status
= 0, accept_status
= 0;
722 int maxlvt
, timeout
, num_starts
, j
;
725 * Be paranoid about clearing APIC errors.
727 if (APIC_INTEGRATED(apic_version
[phys_apicid
])) {
728 apic_read_around(APIC_SPIV
);
729 apic_write(APIC_ESR
, 0);
733 Dprintk("Asserting INIT.\n");
736 * Turn INIT on target chip
738 apic_write_around(APIC_ICR2
, SET_APIC_DEST_FIELD(phys_apicid
));
743 apic_write_around(APIC_ICR
, APIC_INT_LEVELTRIG
| APIC_INT_ASSERT
746 Dprintk("Waiting for send to finish...\n");
751 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
752 } while (send_status
&& (timeout
++ < 1000));
756 Dprintk("Deasserting INIT.\n");
759 apic_write_around(APIC_ICR2
, SET_APIC_DEST_FIELD(phys_apicid
));
762 apic_write_around(APIC_ICR
, APIC_INT_LEVELTRIG
| APIC_DM_INIT
);
764 Dprintk("Waiting for send to finish...\n");
769 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
770 } while (send_status
&& (timeout
++ < 1000));
772 atomic_set(&init_deasserted
, 1);
775 * Should we send STARTUP IPIs ?
777 * Determine this based on the APIC version.
778 * If we don't have an integrated APIC, don't send the STARTUP IPIs.
780 if (APIC_INTEGRATED(apic_version
[phys_apicid
]))
786 * Run STARTUP IPI loop.
788 Dprintk("#startup loops: %d.\n", num_starts
);
790 maxlvt
= get_maxlvt();
792 for (j
= 1; j
<= num_starts
; j
++) {
793 Dprintk("Sending STARTUP #%d.\n",j
);
794 apic_read_around(APIC_SPIV
);
795 apic_write(APIC_ESR
, 0);
797 Dprintk("After apic_write.\n");
804 apic_write_around(APIC_ICR2
, SET_APIC_DEST_FIELD(phys_apicid
));
806 /* Boot on the stack */
807 /* Kick the second */
808 apic_write_around(APIC_ICR
, APIC_DM_STARTUP
809 | (start_eip
>> 12));
812 * Give the other CPU some time to accept the IPI.
816 Dprintk("Startup point 1.\n");
818 Dprintk("Waiting for send to finish...\n");
823 send_status
= apic_read(APIC_ICR
) & APIC_ICR_BUSY
;
824 } while (send_status
&& (timeout
++ < 1000));
827 * Give the other CPU some time to accept the IPI.
831 * Due to the Pentium erratum 3AP.
834 apic_read_around(APIC_SPIV
);
835 apic_write(APIC_ESR
, 0);
837 accept_status
= (apic_read(APIC_ESR
) & 0xEF);
838 if (send_status
|| accept_status
)
841 Dprintk("After Startup.\n");
844 printk("APIC never delivered???\n");
846 printk("APIC delivery error (%lx).\n", accept_status
);
848 return (send_status
| accept_status
);
850 #endif /* WAKE_SECONDARY_VIA_INIT */
852 extern cpumask_t cpu_initialized
;
853 static inline int alloc_cpu_id(void)
857 cpus_complement(tmp_map
, cpu_present_map
);
858 cpu
= first_cpu(tmp_map
);
864 #ifdef CONFIG_HOTPLUG_CPU
865 static struct task_struct
* __devinitdata cpu_idle_tasks
[NR_CPUS
];
866 static inline struct task_struct
* alloc_idle_task(int cpu
)
868 struct task_struct
*idle
;
870 if ((idle
= cpu_idle_tasks
[cpu
]) != NULL
) {
871 /* initialize thread_struct. we really want to avoid destroy
874 idle
->thread
.esp
= (unsigned long)task_pt_regs(idle
);
875 init_idle(idle
, cpu
);
878 idle
= fork_idle(cpu
);
881 cpu_idle_tasks
[cpu
] = idle
;
885 #define alloc_idle_task(cpu) fork_idle(cpu)
888 static int __devinit
do_boot_cpu(int apicid
, int cpu
)
890 * NOTE - on most systems this is a PHYSICAL apic ID, but on multiquad
891 * (ie clustered apic addressing mode), this is a LOGICAL apic ID.
892 * Returns zero if CPU booted OK, else error code from wakeup_secondary_cpu.
895 struct task_struct
*idle
;
896 unsigned long boot_error
;
898 unsigned long start_eip
;
899 unsigned short nmi_high
= 0, nmi_low
= 0;
904 * We can't use kernel_thread since we must avoid to
905 * reschedule the child.
907 idle
= alloc_idle_task(cpu
);
909 panic("failed fork for CPU %d", cpu
);
910 idle
->thread
.eip
= (unsigned long) start_secondary
;
911 /* start_eip had better be page-aligned! */
912 start_eip
= setup_trampoline();
914 /* So we see what's up */
915 printk("Booting processor %d/%d eip %lx\n", cpu
, apicid
, start_eip
);
916 /* Stack for startup_32 can be just as for start_secondary onwards */
917 stack_start
.esp
= (void *) idle
->thread
.esp
;
922 * This grunge runs the startup process for
923 * the targeted processor.
926 atomic_set(&init_deasserted
, 0);
928 Dprintk("Setting warm reset code and vector.\n");
930 store_NMI_vector(&nmi_high
, &nmi_low
);
932 smpboot_setup_warm_reset_vector(start_eip
);
935 * Starting actual IPI sequence...
937 boot_error
= wakeup_secondary_cpu(apicid
, start_eip
);
941 * allow APs to start initializing.
943 Dprintk("Before Callout %d.\n", cpu
);
944 cpu_set(cpu
, cpu_callout_map
);
945 Dprintk("After Callout %d.\n", cpu
);
948 * Wait 5s total for a response
950 for (timeout
= 0; timeout
< 50000; timeout
++) {
951 if (cpu_isset(cpu
, cpu_callin_map
))
952 break; /* It has booted */
956 if (cpu_isset(cpu
, cpu_callin_map
)) {
957 /* number CPUs logically, starting from 1 (BSP is 0) */
959 printk("CPU%d: ", cpu
);
960 print_cpu_info(&cpu_data
[cpu
]);
961 Dprintk("CPU has booted.\n");
964 if (*((volatile unsigned char *)trampoline_base
)
966 /* trampoline started but...? */
967 printk("Stuck ??\n");
969 /* trampoline code not run */
970 printk("Not responding.\n");
971 inquire_remote_apic(apicid
);
976 /* Try to put things back the way they were before ... */
977 unmap_cpu_to_logical_apicid(cpu
);
978 cpu_clear(cpu
, cpu_callout_map
); /* was set here (do_boot_cpu()) */
979 cpu_clear(cpu
, cpu_initialized
); /* was set by cpu_init() */
982 x86_cpu_to_apicid
[cpu
] = apicid
;
983 cpu_set(cpu
, cpu_present_map
);
986 /* mark "stuck" area as not stuck */
987 *((volatile unsigned long *)trampoline_base
) = 0;
992 #ifdef CONFIG_HOTPLUG_CPU
993 void cpu_exit_clear(void)
995 int cpu
= raw_smp_processor_id();
1003 cpu_clear(cpu
, cpu_callout_map
);
1004 cpu_clear(cpu
, cpu_callin_map
);
1005 cpu_clear(cpu
, cpu_present_map
);
1007 cpu_clear(cpu
, smp_commenced_mask
);
1008 unmap_cpu_to_logical_apicid(cpu
);
1011 struct warm_boot_cpu_info
{
1012 struct completion
*complete
;
1017 static void __devinit
do_warm_boot_cpu(void *p
)
1019 struct warm_boot_cpu_info
*info
= p
;
1020 do_boot_cpu(info
->apicid
, info
->cpu
);
1021 complete(info
->complete
);
1024 int __devinit
smp_prepare_cpu(int cpu
)
1026 DECLARE_COMPLETION(done
);
1027 struct warm_boot_cpu_info info
;
1028 struct work_struct task
;
1032 apicid
= x86_cpu_to_apicid
[cpu
];
1033 if (apicid
== BAD_APICID
) {
1038 info
.complete
= &done
;
1039 info
.apicid
= apicid
;
1041 INIT_WORK(&task
, do_warm_boot_cpu
, &info
);
1043 tsc_sync_disabled
= 1;
1045 /* init low mem mapping */
1046 clone_pgd_range(swapper_pg_dir
, swapper_pg_dir
+ USER_PGD_PTRS
,
1049 schedule_work(&task
);
1050 wait_for_completion(&done
);
1052 tsc_sync_disabled
= 0;
1056 unlock_cpu_hotplug();
1061 static void smp_tune_scheduling (void)
1063 unsigned long cachesize
; /* kB */
1064 unsigned long bandwidth
= 350; /* MB/s */
1066 * Rough estimation for SMP scheduling, this is the number of
1067 * cycles it takes for a fully memory-limited process to flush
1068 * the SMP-local cache.
1070 * (For a P5 this pretty much means we will choose another idle
1071 * CPU almost always at wakeup time (this is due to the small
1072 * L1 cache), on PIIs it's around 50-100 usecs, depending on
1078 * this basically disables processor-affinity
1079 * scheduling on SMP without a TSC.
1083 cachesize
= boot_cpu_data
.x86_cache_size
;
1084 if (cachesize
== -1) {
1085 cachesize
= 16; /* Pentiums, 2x8kB cache */
1088 max_cache_size
= cachesize
* 1024;
1093 * Cycle through the processors sending APIC IPIs to boot each.
1096 static int boot_cpu_logical_apicid
;
1097 /* Where the IO area was mapped on multiquad, always 0 otherwise */
1099 #ifdef CONFIG_X86_NUMAQ
1100 EXPORT_SYMBOL(xquad_portio
);
1103 static void __init
smp_boot_cpus(unsigned int max_cpus
)
1105 int apicid
, cpu
, bit
, kicked
;
1106 unsigned long bogosum
= 0;
1109 * Setup boot CPU information
1111 smp_store_cpu_info(0); /* Final full version of the data */
1112 printk("CPU%d: ", 0);
1113 print_cpu_info(&cpu_data
[0]);
1115 boot_cpu_physical_apicid
= GET_APIC_ID(apic_read(APIC_ID
));
1116 boot_cpu_logical_apicid
= logical_smp_processor_id();
1117 x86_cpu_to_apicid
[0] = boot_cpu_physical_apicid
;
1119 current_thread_info()->cpu
= 0;
1120 smp_tune_scheduling();
1122 set_cpu_sibling_map(0);
1125 * If we couldn't find an SMP configuration at boot time,
1126 * get out of here now!
1128 if (!smp_found_config
&& !acpi_lapic
) {
1129 printk(KERN_NOTICE
"SMP motherboard not detected.\n");
1130 smpboot_clear_io_apic_irqs();
1131 phys_cpu_present_map
= physid_mask_of_physid(0);
1132 if (APIC_init_uniprocessor())
1133 printk(KERN_NOTICE
"Local APIC not detected."
1134 " Using dummy APIC emulation.\n");
1135 map_cpu_to_logical_apicid();
1136 cpu_set(0, cpu_sibling_map
[0]);
1137 cpu_set(0, cpu_core_map
[0]);
1142 * Should not be necessary because the MP table should list the boot
1143 * CPU too, but we do it for the sake of robustness anyway.
1144 * Makes no sense to do this check in clustered apic mode, so skip it
1146 if (!check_phys_apicid_present(boot_cpu_physical_apicid
)) {
1147 printk("weird, boot CPU (#%d) not listed by the BIOS.\n",
1148 boot_cpu_physical_apicid
);
1149 physid_set(hard_smp_processor_id(), phys_cpu_present_map
);
1153 * If we couldn't find a local APIC, then get out of here now!
1155 if (APIC_INTEGRATED(apic_version
[boot_cpu_physical_apicid
]) && !cpu_has_apic
) {
1156 printk(KERN_ERR
"BIOS bug, local APIC #%d not detected!...\n",
1157 boot_cpu_physical_apicid
);
1158 printk(KERN_ERR
"... forcing use of dummy APIC emulation. (tell your hw vendor)\n");
1159 smpboot_clear_io_apic_irqs();
1160 phys_cpu_present_map
= physid_mask_of_physid(0);
1161 cpu_set(0, cpu_sibling_map
[0]);
1162 cpu_set(0, cpu_core_map
[0]);
1166 verify_local_APIC();
1169 * If SMP should be disabled, then really disable it!
1172 smp_found_config
= 0;
1173 printk(KERN_INFO
"SMP mode deactivated, forcing use of dummy APIC emulation.\n");
1174 smpboot_clear_io_apic_irqs();
1175 phys_cpu_present_map
= physid_mask_of_physid(0);
1176 cpu_set(0, cpu_sibling_map
[0]);
1177 cpu_set(0, cpu_core_map
[0]);
1183 map_cpu_to_logical_apicid();
1186 setup_portio_remap();
1189 * Scan the CPU present map and fire up the other CPUs via do_boot_cpu
1191 * In clustered apic mode, phys_cpu_present_map is a constructed thus:
1192 * bits 0-3 are quad0, 4-7 are quad1, etc. A perverse twist on the
1193 * clustered apic ID.
1195 Dprintk("CPU present map: %lx\n", physids_coerce(phys_cpu_present_map
));
1198 for (bit
= 0; kicked
< NR_CPUS
&& bit
< MAX_APICS
; bit
++) {
1199 apicid
= cpu_present_to_apicid(bit
);
1201 * Don't even attempt to start the boot CPU!
1203 if ((apicid
== boot_cpu_apicid
) || (apicid
== BAD_APICID
))
1206 if (!check_apicid_present(bit
))
1208 if (max_cpus
<= cpucount
+1)
1211 if (((cpu
= alloc_cpu_id()) <= 0) || do_boot_cpu(apicid
, cpu
))
1212 printk("CPU #%d not responding - cannot use it.\n",
1219 * Cleanup possible dangling ends...
1221 smpboot_restore_warm_reset_vector();
1224 * Allow the user to impress friends.
1226 Dprintk("Before bogomips.\n");
1227 for (cpu
= 0; cpu
< NR_CPUS
; cpu
++)
1228 if (cpu_isset(cpu
, cpu_callout_map
))
1229 bogosum
+= cpu_data
[cpu
].loops_per_jiffy
;
1231 "Total of %d processors activated (%lu.%02lu BogoMIPS).\n",
1233 bogosum
/(500000/HZ
),
1234 (bogosum
/(5000/HZ
))%100);
1236 Dprintk("Before bogocount - setting activated=1.\n");
1239 printk(KERN_WARNING
"WARNING: SMP operation may be unreliable with B stepping processors.\n");
1242 * Don't taint if we are running SMP kernel on a single non-MP
1245 if (tainted
& TAINT_UNSAFE_SMP
) {
1247 printk (KERN_INFO
"WARNING: This combination of AMD processors is not suitable for SMP.\n");
1249 tainted
&= ~TAINT_UNSAFE_SMP
;
1252 Dprintk("Boot done.\n");
1255 * construct cpu_sibling_map[], so that we can tell sibling CPUs
1258 for (cpu
= 0; cpu
< NR_CPUS
; cpu
++) {
1259 cpus_clear(cpu_sibling_map
[cpu
]);
1260 cpus_clear(cpu_core_map
[cpu
]);
1263 cpu_set(0, cpu_sibling_map
[0]);
1264 cpu_set(0, cpu_core_map
[0]);
1266 smpboot_setup_io_apic();
1268 setup_boot_APIC_clock();
1271 * Synchronize the TSC with the AP
1273 if (cpu_has_tsc
&& cpucount
&& cpu_khz
)
1274 synchronize_tsc_bp();
1277 /* These are wrappers to interface to the new boot process. Someone
1278 who understands all this stuff should rewrite it properly. --RR 15/Jul/02 */
1279 void __init
smp_prepare_cpus(unsigned int max_cpus
)
1281 smp_commenced_mask
= cpumask_of_cpu(0);
1282 cpu_callin_map
= cpumask_of_cpu(0);
1284 smp_boot_cpus(max_cpus
);
1287 void __devinit
smp_prepare_boot_cpu(void)
1289 cpu_set(smp_processor_id(), cpu_online_map
);
1290 cpu_set(smp_processor_id(), cpu_callout_map
);
1291 cpu_set(smp_processor_id(), cpu_present_map
);
1292 cpu_set(smp_processor_id(), cpu_possible_map
);
1293 per_cpu(cpu_state
, smp_processor_id()) = CPU_ONLINE
;
1296 #ifdef CONFIG_HOTPLUG_CPU
1298 remove_siblinginfo(int cpu
)
1301 struct cpuinfo_x86
*c
= cpu_data
;
1303 for_each_cpu_mask(sibling
, cpu_core_map
[cpu
]) {
1304 cpu_clear(cpu
, cpu_core_map
[sibling
]);
1306 * last thread sibling in this cpu core going down
1308 if (cpus_weight(cpu_sibling_map
[cpu
]) == 1)
1309 c
[sibling
].booted_cores
--;
1312 for_each_cpu_mask(sibling
, cpu_sibling_map
[cpu
])
1313 cpu_clear(cpu
, cpu_sibling_map
[sibling
]);
1314 cpus_clear(cpu_sibling_map
[cpu
]);
1315 cpus_clear(cpu_core_map
[cpu
]);
1316 phys_proc_id
[cpu
] = BAD_APICID
;
1317 cpu_core_id
[cpu
] = BAD_APICID
;
1318 cpu_clear(cpu
, cpu_sibling_setup_map
);
1321 int __cpu_disable(void)
1323 cpumask_t map
= cpu_online_map
;
1324 int cpu
= smp_processor_id();
1327 * Perhaps use cpufreq to drop frequency, but that could go
1328 * into generic code.
1330 * We won't take down the boot processor on i386 due to some
1331 * interrupts only being able to be serviced by the BSP.
1332 * Especially so if we're not using an IOAPIC -zwane
1338 /* Allow any queued timer interrupts to get serviced */
1341 local_irq_disable();
1343 remove_siblinginfo(cpu
);
1345 cpu_clear(cpu
, map
);
1347 /* It's now safe to remove this processor from the online map */
1348 cpu_clear(cpu
, cpu_online_map
);
1352 void __cpu_die(unsigned int cpu
)
1354 /* We don't do anything here: idle task is faking death itself. */
1357 for (i
= 0; i
< 10; i
++) {
1358 /* They ack this in play_dead by setting CPU_DEAD */
1359 if (per_cpu(cpu_state
, cpu
) == CPU_DEAD
) {
1360 printk ("CPU %d is now offline\n", cpu
);
1365 printk(KERN_ERR
"CPU %u didn't die...\n", cpu
);
1367 #else /* ... !CONFIG_HOTPLUG_CPU */
1368 int __cpu_disable(void)
1373 void __cpu_die(unsigned int cpu
)
1375 /* We said "no" in __cpu_disable */
1378 #endif /* CONFIG_HOTPLUG_CPU */
1380 int __devinit
__cpu_up(unsigned int cpu
)
1382 /* In case one didn't come up */
1383 if (!cpu_isset(cpu
, cpu_callin_map
)) {
1384 printk(KERN_DEBUG
"skipping cpu%d, didn't come online\n", cpu
);
1390 per_cpu(cpu_state
, cpu
) = CPU_UP_PREPARE
;
1391 /* Unleash the CPU! */
1392 cpu_set(cpu
, smp_commenced_mask
);
1393 while (!cpu_isset(cpu
, cpu_online_map
))
1398 void __init
smp_cpus_done(unsigned int max_cpus
)
1400 #ifdef CONFIG_X86_IO_APIC
1401 setup_ioapic_dest();
1404 #ifndef CONFIG_HOTPLUG_CPU
1406 * Disable executability of the SMP trampoline:
1408 set_kernel_exec((unsigned long)trampoline_base
, trampoline_exec
);
1412 void __init
smp_intr_init(void)
1415 * IRQ0 must be given a fixed assignment and initialized,
1416 * because it's used before the IO-APIC is set up.
1418 set_intr_gate(FIRST_DEVICE_VECTOR
, interrupt
[0]);
1421 * The reschedule interrupt is a CPU-to-CPU reschedule-helper
1422 * IPI, driven by wakeup.
1424 set_intr_gate(RESCHEDULE_VECTOR
, reschedule_interrupt
);
1426 /* IPI for invalidation */
1427 set_intr_gate(INVALIDATE_TLB_VECTOR
, invalidate_interrupt
);
1429 /* IPI for generic function call */
1430 set_intr_gate(CALL_FUNCTION_VECTOR
, call_function_interrupt
);