2 * Core routines and tables shareable across OS platforms.
4 * Copyright (c) 1994-2002 Justin T. Gibbs.
5 * Copyright (c) 2000-2003 Adaptec Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions, and the following disclaimer,
13 * without modification.
14 * 2. Redistributions in binary form must reproduce at minimum a disclaimer
15 * substantially similar to the "NO WARRANTY" disclaimer below
16 * ("Disclaimer") and any redistribution must be conditioned upon
17 * including a substantially similar Disclaimer requirement for further
18 * binary redistribution.
19 * 3. Neither the names of the above-listed copyright holders nor the names
20 * of any contributors may be used to endorse or promote products derived
21 * from this software without specific prior written permission.
23 * Alternatively, this software may be distributed under the terms of the
24 * GNU General Public License ("GPL") version 2 as published by the Free
25 * Software Foundation.
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
33 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
34 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
36 * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
37 * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
38 * POSSIBILITY OF SUCH DAMAGES.
40 * $Id: //depot/aic7xxx/aic7xxx/aic79xx.c#250 $
44 #include "aic79xx_osm.h"
45 #include "aic79xx_inline.h"
46 #include "aicasm/aicasm_insformat.h"
48 #include <dev/aic7xxx/aic79xx_osm.h>
49 #include <dev/aic7xxx/aic79xx_inline.h>
50 #include <dev/aic7xxx/aicasm/aicasm_insformat.h>
54 /***************************** Lookup Tables **********************************/
55 char *ahd_chip_names
[] =
62 static const u_int num_chip_names
= NUM_ELEMENTS(ahd_chip_names
);
65 * Hardware error codes.
67 struct ahd_hard_error_entry
{
72 static struct ahd_hard_error_entry ahd_hard_errors
[] = {
73 { DSCTMOUT
, "Discard Timer has timed out" },
74 { ILLOPCODE
, "Illegal Opcode in sequencer program" },
75 { SQPARERR
, "Sequencer Parity Error" },
76 { DPARERR
, "Data-path Parity Error" },
77 { MPARERR
, "Scratch or SCB Memory Parity Error" },
78 { CIOPARERR
, "CIOBUS Parity Error" },
80 static const u_int num_errors
= NUM_ELEMENTS(ahd_hard_errors
);
82 static struct ahd_phase_table_entry ahd_phase_table
[] =
84 { P_DATAOUT
, MSG_NOOP
, "in Data-out phase" },
85 { P_DATAIN
, MSG_INITIATOR_DET_ERR
, "in Data-in phase" },
86 { P_DATAOUT_DT
, MSG_NOOP
, "in DT Data-out phase" },
87 { P_DATAIN_DT
, MSG_INITIATOR_DET_ERR
, "in DT Data-in phase" },
88 { P_COMMAND
, MSG_NOOP
, "in Command phase" },
89 { P_MESGOUT
, MSG_NOOP
, "in Message-out phase" },
90 { P_STATUS
, MSG_INITIATOR_DET_ERR
, "in Status phase" },
91 { P_MESGIN
, MSG_PARITY_ERROR
, "in Message-in phase" },
92 { P_BUSFREE
, MSG_NOOP
, "while idle" },
93 { 0, MSG_NOOP
, "in unknown phase" }
97 * In most cases we only wish to itterate over real phases, so
98 * exclude the last element from the count.
100 static const u_int num_phases
= NUM_ELEMENTS(ahd_phase_table
) - 1;
102 /* Our Sequencer Program */
103 #include "aic79xx_seq.h"
105 /**************************** Function Declarations ***************************/
106 static void ahd_handle_transmission_error(struct ahd_softc
*ahd
);
107 static void ahd_handle_lqiphase_error(struct ahd_softc
*ahd
,
109 static int ahd_handle_pkt_busfree(struct ahd_softc
*ahd
,
111 static int ahd_handle_nonpkt_busfree(struct ahd_softc
*ahd
);
112 static void ahd_handle_proto_violation(struct ahd_softc
*ahd
);
113 static void ahd_force_renegotiation(struct ahd_softc
*ahd
,
114 struct ahd_devinfo
*devinfo
);
116 static struct ahd_tmode_tstate
*
117 ahd_alloc_tstate(struct ahd_softc
*ahd
,
118 u_int scsi_id
, char channel
);
119 #ifdef AHD_TARGET_MODE
120 static void ahd_free_tstate(struct ahd_softc
*ahd
,
121 u_int scsi_id
, char channel
, int force
);
123 static void ahd_devlimited_syncrate(struct ahd_softc
*ahd
,
124 struct ahd_initiator_tinfo
*,
128 static void ahd_update_neg_table(struct ahd_softc
*ahd
,
129 struct ahd_devinfo
*devinfo
,
130 struct ahd_transinfo
*tinfo
);
131 static void ahd_update_pending_scbs(struct ahd_softc
*ahd
);
132 static void ahd_fetch_devinfo(struct ahd_softc
*ahd
,
133 struct ahd_devinfo
*devinfo
);
134 static void ahd_scb_devinfo(struct ahd_softc
*ahd
,
135 struct ahd_devinfo
*devinfo
,
137 static void ahd_setup_initiator_msgout(struct ahd_softc
*ahd
,
138 struct ahd_devinfo
*devinfo
,
140 static void ahd_build_transfer_msg(struct ahd_softc
*ahd
,
141 struct ahd_devinfo
*devinfo
);
142 static void ahd_construct_sdtr(struct ahd_softc
*ahd
,
143 struct ahd_devinfo
*devinfo
,
144 u_int period
, u_int offset
);
145 static void ahd_construct_wdtr(struct ahd_softc
*ahd
,
146 struct ahd_devinfo
*devinfo
,
148 static void ahd_construct_ppr(struct ahd_softc
*ahd
,
149 struct ahd_devinfo
*devinfo
,
150 u_int period
, u_int offset
,
151 u_int bus_width
, u_int ppr_options
);
152 static void ahd_clear_msg_state(struct ahd_softc
*ahd
);
153 static void ahd_handle_message_phase(struct ahd_softc
*ahd
);
159 static int ahd_sent_msg(struct ahd_softc
*ahd
, ahd_msgtype type
,
160 u_int msgval
, int full
);
161 static int ahd_parse_msg(struct ahd_softc
*ahd
,
162 struct ahd_devinfo
*devinfo
);
163 static int ahd_handle_msg_reject(struct ahd_softc
*ahd
,
164 struct ahd_devinfo
*devinfo
);
165 static void ahd_handle_ign_wide_residue(struct ahd_softc
*ahd
,
166 struct ahd_devinfo
*devinfo
);
167 static void ahd_reinitialize_dataptrs(struct ahd_softc
*ahd
);
168 static void ahd_handle_devreset(struct ahd_softc
*ahd
,
169 struct ahd_devinfo
*devinfo
,
170 u_int lun
, cam_status status
,
171 char *message
, int verbose_level
);
172 #ifdef AHD_TARGET_MODE
173 static void ahd_setup_target_msgin(struct ahd_softc
*ahd
,
174 struct ahd_devinfo
*devinfo
,
178 static u_int
ahd_sglist_size(struct ahd_softc
*ahd
);
179 static u_int
ahd_sglist_allocsize(struct ahd_softc
*ahd
);
180 static bus_dmamap_callback_t
182 static void ahd_initialize_hscbs(struct ahd_softc
*ahd
);
183 static int ahd_init_scbdata(struct ahd_softc
*ahd
);
184 static void ahd_fini_scbdata(struct ahd_softc
*ahd
);
185 static void ahd_setup_iocell_workaround(struct ahd_softc
*ahd
);
186 static void ahd_iocell_first_selection(struct ahd_softc
*ahd
);
187 static void ahd_add_col_list(struct ahd_softc
*ahd
,
188 struct scb
*scb
, u_int col_idx
);
189 static void ahd_rem_col_list(struct ahd_softc
*ahd
,
191 static void ahd_chip_init(struct ahd_softc
*ahd
);
192 static void ahd_qinfifo_requeue(struct ahd_softc
*ahd
,
193 struct scb
*prev_scb
,
195 static int ahd_qinfifo_count(struct ahd_softc
*ahd
);
196 static int ahd_search_scb_list(struct ahd_softc
*ahd
, int target
,
197 char channel
, int lun
, u_int tag
,
198 role_t role
, uint32_t status
,
199 ahd_search_action action
,
200 u_int
*list_head
, u_int
*list_tail
,
202 static void ahd_stitch_tid_list(struct ahd_softc
*ahd
,
203 u_int tid_prev
, u_int tid_cur
,
205 static void ahd_add_scb_to_free_list(struct ahd_softc
*ahd
,
207 static u_int
ahd_rem_wscb(struct ahd_softc
*ahd
, u_int scbid
,
208 u_int prev
, u_int next
, u_int tid
);
209 static void ahd_reset_current_bus(struct ahd_softc
*ahd
);
210 static ahd_callback_t ahd_stat_timer
;
212 static void ahd_dumpseq(struct ahd_softc
*ahd
);
214 static void ahd_loadseq(struct ahd_softc
*ahd
);
215 static int ahd_check_patch(struct ahd_softc
*ahd
,
216 struct patch
**start_patch
,
217 u_int start_instr
, u_int
*skip_addr
);
218 static u_int
ahd_resolve_seqaddr(struct ahd_softc
*ahd
,
220 static void ahd_download_instr(struct ahd_softc
*ahd
,
221 u_int instrptr
, uint8_t *dconsts
);
222 static int ahd_probe_stack_size(struct ahd_softc
*ahd
);
223 static int ahd_scb_active_in_fifo(struct ahd_softc
*ahd
,
225 static void ahd_run_data_fifo(struct ahd_softc
*ahd
,
228 #ifdef AHD_TARGET_MODE
229 static void ahd_queue_lstate_event(struct ahd_softc
*ahd
,
230 struct ahd_tmode_lstate
*lstate
,
234 static void ahd_update_scsiid(struct ahd_softc
*ahd
,
236 static int ahd_handle_target_cmd(struct ahd_softc
*ahd
,
237 struct target_cmd
*cmd
);
240 /******************************** Private Inlines *****************************/
241 static __inline
void ahd_assert_atn(struct ahd_softc
*ahd
);
242 static __inline
int ahd_currently_packetized(struct ahd_softc
*ahd
);
243 static __inline
int ahd_set_active_fifo(struct ahd_softc
*ahd
);
246 ahd_assert_atn(struct ahd_softc
*ahd
)
248 ahd_outb(ahd
, SCSISIGO
, ATNO
);
252 * Determine if the current connection has a packetized
253 * agreement. This does not necessarily mean that we
254 * are currently in a packetized transfer. We could
255 * just as easily be sending or receiving a message.
258 ahd_currently_packetized(struct ahd_softc
*ahd
)
260 ahd_mode_state saved_modes
;
263 saved_modes
= ahd_save_modes(ahd
);
264 if ((ahd
->bugs
& AHD_PKTIZED_STATUS_BUG
) != 0) {
266 * The packetized bit refers to the last
267 * connection, not the current one. Check
268 * for non-zero LQISTATE instead.
270 ahd_set_modes(ahd
, AHD_MODE_CFG
, AHD_MODE_CFG
);
271 packetized
= ahd_inb(ahd
, LQISTATE
) != 0;
273 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
274 packetized
= ahd_inb(ahd
, LQISTAT2
) & PACKETIZED
;
276 ahd_restore_modes(ahd
, saved_modes
);
281 ahd_set_active_fifo(struct ahd_softc
*ahd
)
285 AHD_ASSERT_MODES(ahd
, AHD_MODE_SCSI_MSK
, AHD_MODE_SCSI_MSK
);
286 active_fifo
= ahd_inb(ahd
, DFFSTAT
) & CURRFIFO
;
287 switch (active_fifo
) {
290 ahd_set_modes(ahd
, active_fifo
, active_fifo
);
297 /************************* Sequencer Execution Control ************************/
299 * Restart the sequencer program from address zero
302 ahd_restart(struct ahd_softc
*ahd
)
307 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
309 /* No more pending messages */
310 ahd_clear_msg_state(ahd
);
311 ahd_outb(ahd
, SCSISIGO
, 0); /* De-assert BSY */
312 ahd_outb(ahd
, MSG_OUT
, MSG_NOOP
); /* No message to send */
313 ahd_outb(ahd
, SXFRCTL1
, ahd_inb(ahd
, SXFRCTL1
) & ~BITBUCKET
);
314 ahd_outb(ahd
, SEQINTCTL
, 0);
315 ahd_outb(ahd
, LASTPHASE
, P_BUSFREE
);
316 ahd_outb(ahd
, SEQ_FLAGS
, 0);
317 ahd_outb(ahd
, SAVED_SCSIID
, 0xFF);
318 ahd_outb(ahd
, SAVED_LUN
, 0xFF);
321 * Ensure that the sequencer's idea of TQINPOS
322 * matches our own. The sequencer increments TQINPOS
323 * only after it sees a DMA complete and a reset could
324 * occur before the increment leaving the kernel to believe
325 * the command arrived but the sequencer to not.
327 ahd_outb(ahd
, TQINPOS
, ahd
->tqinfifonext
);
329 /* Always allow reselection */
330 ahd_outb(ahd
, SCSISEQ1
,
331 ahd_inb(ahd
, SCSISEQ_TEMPLATE
) & (ENSELI
|ENRSELI
|ENAUTOATNP
));
332 ahd_set_modes(ahd
, AHD_MODE_CCHAN
, AHD_MODE_CCHAN
);
335 * Clear any pending sequencer interrupt. It is no
336 * longer relevant since we're resetting the Program
339 ahd_outb(ahd
, CLRINT
, CLRSEQINT
);
341 ahd_outb(ahd
, SEQCTL0
, FASTMODE
|SEQRESET
);
346 ahd_clear_fifo(struct ahd_softc
*ahd
, u_int fifo
)
348 ahd_mode_state saved_modes
;
351 if ((ahd_debug
& AHD_SHOW_FIFOS
) != 0)
352 printf("%s: Clearing FIFO %d\n", ahd_name(ahd
), fifo
);
354 saved_modes
= ahd_save_modes(ahd
);
355 ahd_set_modes(ahd
, fifo
, fifo
);
356 ahd_outb(ahd
, DFFSXFRCTL
, RSTCHN
|CLRSHCNT
);
357 if ((ahd_inb(ahd
, SG_STATE
) & FETCH_INPROG
) != 0)
358 ahd_outb(ahd
, CCSGCTL
, CCSGRESET
);
359 ahd_outb(ahd
, LONGJMP_ADDR
+ 1, INVALID_ADDR
);
360 ahd_outb(ahd
, SG_STATE
, 0);
361 ahd_restore_modes(ahd
, saved_modes
);
364 /************************* Input/Output Queues ********************************/
366 * Flush and completed commands that are sitting in the command
367 * complete queues down on the chip but have yet to be dma'ed back up.
370 ahd_flush_qoutfifo(struct ahd_softc
*ahd
)
373 ahd_mode_state saved_modes
;
379 saved_modes
= ahd_save_modes(ahd
);
382 * Flush the good status FIFO for completed packetized commands.
384 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
385 saved_scbptr
= ahd_get_scbptr(ahd
);
386 while ((ahd_inb(ahd
, LQISTAT2
) & LQIGSAVAIL
) != 0) {
390 scbid
= ahd_inw(ahd
, GSFIFO
);
391 scb
= ahd_lookup_scb(ahd
, scbid
);
393 printf("%s: Warning - GSFIFO SCB %d invalid\n",
394 ahd_name(ahd
), scbid
);
398 * Determine if this transaction is still active in
399 * any FIFO. If it is, we must flush that FIFO to
400 * the host before completing the command.
404 for (i
= 0; i
< 2; i
++) {
405 /* Toggle to the other mode. */
407 ahd_set_modes(ahd
, fifo_mode
, fifo_mode
);
409 if (ahd_scb_active_in_fifo(ahd
, scb
) == 0)
412 ahd_run_data_fifo(ahd
, scb
);
415 * Running this FIFO may cause a CFG4DATA for
416 * this same transaction to assert in the other
417 * FIFO or a new snapshot SAVEPTRS interrupt
418 * in this FIFO. Even running a FIFO may not
419 * clear the transaction if we are still waiting
420 * for data to drain to the host. We must loop
421 * until the transaction is not active in either
422 * FIFO just to be sure. Reset our loop counter
423 * so we will visit both FIFOs again before
424 * declaring this transaction finished. We
425 * also delay a bit so that status has a chance
426 * to change before we look at this FIFO again.
431 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
432 ahd_set_scbptr(ahd
, scbid
);
433 if ((ahd_inb_scbram(ahd
, SCB_SGPTR
) & SG_LIST_NULL
) == 0
434 && ((ahd_inb_scbram(ahd
, SCB_SGPTR
) & SG_FULL_RESID
) != 0
435 || (ahd_inb_scbram(ahd
, SCB_RESIDUAL_SGPTR
)
436 & SG_LIST_NULL
) != 0)) {
440 * The transfer completed with a residual.
441 * Place this SCB on the complete DMA list
442 * so that we update our in-core copy of the
443 * SCB before completing the command.
445 ahd_outb(ahd
, SCB_SCSI_STATUS
, 0);
446 ahd_outb(ahd
, SCB_SGPTR
,
447 ahd_inb_scbram(ahd
, SCB_SGPTR
)
449 ahd_outw(ahd
, SCB_TAG
, scbid
);
450 ahd_outw(ahd
, SCB_NEXT_COMPLETE
, SCB_LIST_NULL
);
451 comp_head
= ahd_inw(ahd
, COMPLETE_DMA_SCB_HEAD
);
452 if (SCBID_IS_NULL(comp_head
)) {
453 ahd_outw(ahd
, COMPLETE_DMA_SCB_HEAD
, scbid
);
454 ahd_outw(ahd
, COMPLETE_DMA_SCB_TAIL
, scbid
);
458 tail
= ahd_inw(ahd
, COMPLETE_DMA_SCB_TAIL
);
459 ahd_set_scbptr(ahd
, tail
);
460 ahd_outw(ahd
, SCB_NEXT_COMPLETE
, scbid
);
461 ahd_outw(ahd
, COMPLETE_DMA_SCB_TAIL
, scbid
);
462 ahd_set_scbptr(ahd
, scbid
);
465 ahd_complete_scb(ahd
, scb
);
467 ahd_set_scbptr(ahd
, saved_scbptr
);
470 * Setup for command channel portion of flush.
472 ahd_set_modes(ahd
, AHD_MODE_CCHAN
, AHD_MODE_CCHAN
);
475 * Wait for any inprogress DMA to complete and clear DMA state
476 * if this if for an SCB in the qinfifo.
478 while (((ccscbctl
= ahd_inb(ahd
, CCSCBCTL
)) & (CCARREN
|CCSCBEN
)) != 0) {
480 if ((ccscbctl
& (CCSCBDIR
|CCARREN
)) == (CCSCBDIR
|CCARREN
)) {
481 if ((ccscbctl
& ARRDONE
) != 0)
483 } else if ((ccscbctl
& CCSCBDONE
) != 0)
488 * We leave the sequencer to cleanup in the case of DMA's to
489 * update the qoutfifo. In all other cases (DMA's to the
490 * chip or a push of an SCB from the COMPLETE_DMA_SCB list),
491 * we disable the DMA engine so that the sequencer will not
492 * attempt to handle the DMA completion.
494 if ((ccscbctl
& CCSCBDIR
) != 0 || (ccscbctl
& ARRDONE
) != 0)
495 ahd_outb(ahd
, CCSCBCTL
, ccscbctl
& ~(CCARREN
|CCSCBEN
));
498 * Complete any SCBs that just finished
499 * being DMA'ed into the qoutfifo.
501 ahd_run_qoutfifo(ahd
);
503 saved_scbptr
= ahd_get_scbptr(ahd
);
505 * Manually update/complete any completed SCBs that are waiting to be
506 * DMA'ed back up to the host.
508 scbid
= ahd_inw(ahd
, COMPLETE_DMA_SCB_HEAD
);
509 while (!SCBID_IS_NULL(scbid
)) {
513 ahd_set_scbptr(ahd
, scbid
);
514 next_scbid
= ahd_inw_scbram(ahd
, SCB_NEXT_COMPLETE
);
515 scb
= ahd_lookup_scb(ahd
, scbid
);
517 printf("%s: Warning - DMA-up and complete "
518 "SCB %d invalid\n", ahd_name(ahd
), scbid
);
521 hscb_ptr
= (uint8_t *)scb
->hscb
;
522 for (i
= 0; i
< sizeof(struct hardware_scb
); i
++)
523 *hscb_ptr
++ = ahd_inb_scbram(ahd
, SCB_BASE
+ i
);
525 ahd_complete_scb(ahd
, scb
);
528 ahd_outw(ahd
, COMPLETE_DMA_SCB_HEAD
, SCB_LIST_NULL
);
529 ahd_outw(ahd
, COMPLETE_DMA_SCB_TAIL
, SCB_LIST_NULL
);
531 scbid
= ahd_inw(ahd
, COMPLETE_ON_QFREEZE_HEAD
);
532 while (!SCBID_IS_NULL(scbid
)) {
534 ahd_set_scbptr(ahd
, scbid
);
535 next_scbid
= ahd_inw_scbram(ahd
, SCB_NEXT_COMPLETE
);
536 scb
= ahd_lookup_scb(ahd
, scbid
);
538 printf("%s: Warning - Complete Qfrz SCB %d invalid\n",
539 ahd_name(ahd
), scbid
);
543 ahd_complete_scb(ahd
, scb
);
546 ahd_outw(ahd
, COMPLETE_ON_QFREEZE_HEAD
, SCB_LIST_NULL
);
548 scbid
= ahd_inw(ahd
, COMPLETE_SCB_HEAD
);
549 while (!SCBID_IS_NULL(scbid
)) {
551 ahd_set_scbptr(ahd
, scbid
);
552 next_scbid
= ahd_inw_scbram(ahd
, SCB_NEXT_COMPLETE
);
553 scb
= ahd_lookup_scb(ahd
, scbid
);
555 printf("%s: Warning - Complete SCB %d invalid\n",
556 ahd_name(ahd
), scbid
);
560 ahd_complete_scb(ahd
, scb
);
563 ahd_outw(ahd
, COMPLETE_SCB_HEAD
, SCB_LIST_NULL
);
568 ahd_set_scbptr(ahd
, saved_scbptr
);
569 ahd_restore_modes(ahd
, saved_modes
);
570 ahd
->flags
|= AHD_UPDATE_PEND_CMDS
;
574 * Determine if an SCB for a packetized transaction
575 * is active in a FIFO.
578 ahd_scb_active_in_fifo(struct ahd_softc
*ahd
, struct scb
*scb
)
582 * The FIFO is only active for our transaction if
583 * the SCBPTR matches the SCB's ID and the firmware
584 * has installed a handler for the FIFO or we have
585 * a pending SAVEPTRS or CFG4DATA interrupt.
587 if (ahd_get_scbptr(ahd
) != SCB_GET_TAG(scb
)
588 || ((ahd_inb(ahd
, LONGJMP_ADDR
+1) & INVALID_ADDR
) != 0
589 && (ahd_inb(ahd
, SEQINTSRC
) & (CFG4DATA
|SAVEPTRS
)) == 0))
596 * Run a data fifo to completion for a transaction we know
597 * has completed across the SCSI bus (good status has been
598 * received). We are already set to the correct FIFO mode
599 * on entry to this routine.
601 * This function attempts to operate exactly as the firmware
602 * would when running this FIFO. Care must be taken to update
603 * this routine any time the firmware's FIFO algorithm is
607 ahd_run_data_fifo(struct ahd_softc
*ahd
, struct scb
*scb
)
611 seqintsrc
= ahd_inb(ahd
, SEQINTSRC
);
612 if ((seqintsrc
& CFG4DATA
) != 0) {
617 * Clear full residual flag.
619 sgptr
= ahd_inl_scbram(ahd
, SCB_SGPTR
) & ~SG_FULL_RESID
;
620 ahd_outb(ahd
, SCB_SGPTR
, sgptr
);
623 * Load datacnt and address.
625 datacnt
= ahd_inl_scbram(ahd
, SCB_DATACNT
);
626 if ((datacnt
& AHD_DMA_LAST_SEG
) != 0) {
628 ahd_outb(ahd
, SG_STATE
, 0);
630 ahd_outb(ahd
, SG_STATE
, LOADING_NEEDED
);
631 ahd_outq(ahd
, HADDR
, ahd_inq_scbram(ahd
, SCB_DATAPTR
));
632 ahd_outl(ahd
, HCNT
, datacnt
& AHD_SG_LEN_MASK
);
633 ahd_outb(ahd
, SG_CACHE_PRE
, sgptr
);
634 ahd_outb(ahd
, DFCNTRL
, PRELOADEN
|SCSIEN
|HDMAEN
);
637 * Initialize Residual Fields.
639 ahd_outb(ahd
, SCB_RESIDUAL_DATACNT
+3, datacnt
>> 24);
640 ahd_outl(ahd
, SCB_RESIDUAL_SGPTR
, sgptr
& SG_PTR_MASK
);
643 * Mark the SCB as having a FIFO in use.
645 ahd_outb(ahd
, SCB_FIFO_USE_COUNT
,
646 ahd_inb_scbram(ahd
, SCB_FIFO_USE_COUNT
) + 1);
649 * Install a "fake" handler for this FIFO.
651 ahd_outw(ahd
, LONGJMP_ADDR
, 0);
654 * Notify the hardware that we have satisfied
655 * this sequencer interrupt.
657 ahd_outb(ahd
, CLRSEQINTSRC
, CLRCFG4DATA
);
658 } else if ((seqintsrc
& SAVEPTRS
) != 0) {
662 if ((ahd_inb(ahd
, LONGJMP_ADDR
+1)&INVALID_ADDR
) != 0) {
664 * Snapshot Save Pointers. All that
665 * is necessary to clear the snapshot
672 * Disable S/G fetch so the DMA engine
673 * is available to future users.
675 if ((ahd_inb(ahd
, SG_STATE
) & FETCH_INPROG
) != 0)
676 ahd_outb(ahd
, CCSGCTL
, 0);
677 ahd_outb(ahd
, SG_STATE
, 0);
680 * Flush the data FIFO. Strickly only
681 * necessary for Rev A parts.
683 ahd_outb(ahd
, DFCNTRL
, ahd_inb(ahd
, DFCNTRL
) | FIFOFLUSH
);
686 * Calculate residual.
688 sgptr
= ahd_inl_scbram(ahd
, SCB_RESIDUAL_SGPTR
);
689 resid
= ahd_inl(ahd
, SHCNT
);
690 resid
|= ahd_inb_scbram(ahd
, SCB_RESIDUAL_DATACNT
+3) << 24;
691 ahd_outl(ahd
, SCB_RESIDUAL_DATACNT
, resid
);
692 if ((ahd_inb(ahd
, SG_CACHE_SHADOW
) & LAST_SEG
) == 0) {
694 * Must back up to the correct S/G element.
695 * Typically this just means resetting our
696 * low byte to the offset in the SG_CACHE,
697 * but if we wrapped, we have to correct
698 * the other bytes of the sgptr too.
700 if ((ahd_inb(ahd
, SG_CACHE_SHADOW
) & 0x80) != 0
701 && (sgptr
& 0x80) == 0)
704 sgptr
|= ahd_inb(ahd
, SG_CACHE_SHADOW
)
706 ahd_outl(ahd
, SCB_RESIDUAL_SGPTR
, sgptr
);
707 ahd_outb(ahd
, SCB_RESIDUAL_DATACNT
+ 3, 0);
708 } else if ((resid
& AHD_SG_LEN_MASK
) == 0) {
709 ahd_outb(ahd
, SCB_RESIDUAL_SGPTR
,
710 sgptr
| SG_LIST_NULL
);
715 ahd_outq(ahd
, SCB_DATAPTR
, ahd_inq(ahd
, SHADDR
));
716 ahd_outl(ahd
, SCB_DATACNT
, resid
);
717 ahd_outl(ahd
, SCB_SGPTR
, sgptr
);
718 ahd_outb(ahd
, CLRSEQINTSRC
, CLRSAVEPTRS
);
719 ahd_outb(ahd
, SEQIMODE
,
720 ahd_inb(ahd
, SEQIMODE
) | ENSAVEPTRS
);
722 * If the data is to the SCSI bus, we are
723 * done, otherwise wait for FIFOEMP.
725 if ((ahd_inb(ahd
, DFCNTRL
) & DIRECTION
) != 0)
727 } else if ((ahd_inb(ahd
, SG_STATE
) & LOADING_NEEDED
) != 0) {
734 * Disable S/G fetch so the DMA engine
735 * is available to future users. We won't
736 * be using the DMA engine to load segments.
738 if ((ahd_inb(ahd
, SG_STATE
) & FETCH_INPROG
) != 0) {
739 ahd_outb(ahd
, CCSGCTL
, 0);
740 ahd_outb(ahd
, SG_STATE
, LOADING_NEEDED
);
744 * Wait for the DMA engine to notice that the
745 * host transfer is enabled and that there is
746 * space in the S/G FIFO for new segments before
747 * loading more segments.
749 if ((ahd_inb(ahd
, DFSTATUS
) & PRELOAD_AVAIL
) != 0
750 && (ahd_inb(ahd
, DFCNTRL
) & HDMAENACK
) != 0) {
753 * Determine the offset of the next S/G
756 sgptr
= ahd_inl_scbram(ahd
, SCB_RESIDUAL_SGPTR
);
757 sgptr
&= SG_PTR_MASK
;
758 if ((ahd
->flags
& AHD_64BIT_ADDRESSING
) != 0) {
759 struct ahd_dma64_seg
*sg
;
761 sg
= ahd_sg_bus_to_virt(ahd
, scb
, sgptr
);
762 data_addr
= sg
->addr
;
764 sgptr
+= sizeof(*sg
);
766 struct ahd_dma_seg
*sg
;
768 sg
= ahd_sg_bus_to_virt(ahd
, scb
, sgptr
);
769 data_addr
= sg
->len
& AHD_SG_HIGH_ADDR_MASK
;
771 data_addr
|= sg
->addr
;
773 sgptr
+= sizeof(*sg
);
777 * Update residual information.
779 ahd_outb(ahd
, SCB_RESIDUAL_DATACNT
+3, data_len
>> 24);
780 ahd_outl(ahd
, SCB_RESIDUAL_SGPTR
, sgptr
);
785 if (data_len
& AHD_DMA_LAST_SEG
) {
787 ahd_outb(ahd
, SG_STATE
, 0);
789 ahd_outq(ahd
, HADDR
, data_addr
);
790 ahd_outl(ahd
, HCNT
, data_len
& AHD_SG_LEN_MASK
);
791 ahd_outb(ahd
, SG_CACHE_PRE
, sgptr
& 0xFF);
794 * Advertise the segment to the hardware.
796 dfcntrl
= ahd_inb(ahd
, DFCNTRL
)|PRELOADEN
|HDMAEN
;
797 if ((ahd
->features
& AHD_NEW_DFCNTRL_OPTS
) != 0) {
799 * Use SCSIENWRDIS so that SCSIEN
800 * is never modified by this
803 dfcntrl
|= SCSIENWRDIS
;
805 ahd_outb(ahd
, DFCNTRL
, dfcntrl
);
807 } else if ((ahd_inb(ahd
, SG_CACHE_SHADOW
) & LAST_SEG_DONE
) != 0) {
810 * Transfer completed to the end of SG list
811 * and has flushed to the host.
813 ahd_outb(ahd
, SCB_SGPTR
,
814 ahd_inb_scbram(ahd
, SCB_SGPTR
) | SG_LIST_NULL
);
816 } else if ((ahd_inb(ahd
, DFSTATUS
) & FIFOEMP
) != 0) {
819 * Clear any handler for this FIFO, decrement
820 * the FIFO use count for the SCB, and release
823 ahd_outb(ahd
, LONGJMP_ADDR
+ 1, INVALID_ADDR
);
824 ahd_outb(ahd
, SCB_FIFO_USE_COUNT
,
825 ahd_inb_scbram(ahd
, SCB_FIFO_USE_COUNT
) - 1);
826 ahd_outb(ahd
, DFFSXFRCTL
, CLRCHN
);
831 * Look for entries in the QoutFIFO that have completed.
832 * The valid_tag completion field indicates the validity
833 * of the entry - the valid value toggles each time through
834 * the queue. We use the sg_status field in the completion
835 * entry to avoid referencing the hscb if the completion
836 * occurred with no errors and no residual. sg_status is
837 * a copy of the first byte (little endian) of the sgptr
841 ahd_run_qoutfifo(struct ahd_softc
*ahd
)
843 struct ahd_completion
*completion
;
847 if ((ahd
->flags
& AHD_RUNNING_QOUTFIFO
) != 0)
848 panic("ahd_run_qoutfifo recursion");
849 ahd
->flags
|= AHD_RUNNING_QOUTFIFO
;
850 ahd_sync_qoutfifo(ahd
, BUS_DMASYNC_POSTREAD
);
852 completion
= &ahd
->qoutfifo
[ahd
->qoutfifonext
];
854 if (completion
->valid_tag
!= ahd
->qoutfifonext_valid_tag
)
857 scb_index
= ahd_le16toh(completion
->tag
);
858 scb
= ahd_lookup_scb(ahd
, scb_index
);
860 printf("%s: WARNING no command for scb %d "
861 "(cmdcmplt)\nQOUTPOS = %d\n",
862 ahd_name(ahd
), scb_index
,
864 ahd_dump_card_state(ahd
);
865 } else if ((completion
->sg_status
& SG_STATUS_VALID
) != 0) {
866 ahd_handle_scb_status(ahd
, scb
);
871 ahd
->qoutfifonext
= (ahd
->qoutfifonext
+1) & (AHD_QOUT_SIZE
-1);
872 if (ahd
->qoutfifonext
== 0)
873 ahd
->qoutfifonext_valid_tag
^= QOUTFIFO_ENTRY_VALID
;
875 ahd
->flags
&= ~AHD_RUNNING_QOUTFIFO
;
878 /************************* Interrupt Handling *********************************/
880 ahd_handle_hwerrint(struct ahd_softc
*ahd
)
883 * Some catastrophic hardware error has occurred.
884 * Print it for the user and disable the controller.
889 error
= ahd_inb(ahd
, ERROR
);
890 for (i
= 0; i
< num_errors
; i
++) {
891 if ((error
& ahd_hard_errors
[i
].errno
) != 0)
892 printf("%s: hwerrint, %s\n",
893 ahd_name(ahd
), ahd_hard_errors
[i
].errmesg
);
896 ahd_dump_card_state(ahd
);
899 /* Tell everyone that this HBA is no longer available */
900 ahd_abort_scbs(ahd
, CAM_TARGET_WILDCARD
, ALL_CHANNELS
,
901 CAM_LUN_WILDCARD
, SCB_LIST_NULL
, ROLE_UNKNOWN
,
904 /* Tell the system that this controller has gone away. */
909 ahd_handle_seqint(struct ahd_softc
*ahd
, u_int intstat
)
914 * Save the sequencer interrupt code and clear the SEQINT
915 * bit. We will unpause the sequencer, if appropriate,
916 * after servicing the request.
918 seqintcode
= ahd_inb(ahd
, SEQINTCODE
);
919 ahd_outb(ahd
, CLRINT
, CLRSEQINT
);
920 if ((ahd
->bugs
& AHD_INTCOLLISION_BUG
) != 0) {
922 * Unpause the sequencer and let it clear
923 * SEQINT by writing NO_SEQINT to it. This
924 * will cause the sequencer to be paused again,
925 * which is the expected state of this routine.
928 while (!ahd_is_paused(ahd
))
930 ahd_outb(ahd
, CLRINT
, CLRSEQINT
);
932 ahd_update_modes(ahd
);
934 if ((ahd_debug
& AHD_SHOW_MISC
) != 0)
935 printf("%s: Handle Seqint Called for code %d\n",
936 ahd_name(ahd
), seqintcode
);
938 switch (seqintcode
) {
939 case ENTERING_NONPACK
:
944 AHD_ASSERT_MODES(ahd
, ~(AHD_MODE_UNKNOWN_MSK
|AHD_MODE_CFG_MSK
),
945 ~(AHD_MODE_UNKNOWN_MSK
|AHD_MODE_CFG_MSK
));
946 scbid
= ahd_get_scbptr(ahd
);
947 scb
= ahd_lookup_scb(ahd
, scbid
);
950 * Somehow need to know if this
951 * is from a selection or reselection.
952 * From that, we can determine target
953 * ID so we at least have an I_T nexus.
956 ahd_outb(ahd
, SAVED_SCSIID
, scb
->hscb
->scsiid
);
957 ahd_outb(ahd
, SAVED_LUN
, scb
->hscb
->lun
);
958 ahd_outb(ahd
, SEQ_FLAGS
, 0x0);
960 if ((ahd_inb(ahd
, LQISTAT2
) & LQIPHASE_OUTPKT
) != 0
961 && (ahd_inb(ahd
, SCSISIGO
) & ATNO
) != 0) {
963 * Phase change after read stream with
964 * CRC error with P0 asserted on last
968 if ((ahd_debug
& AHD_SHOW_RECOVERY
) != 0)
969 printf("%s: Assuming LQIPHASE_NLQ with "
970 "P0 assertion\n", ahd_name(ahd
));
974 if ((ahd_debug
& AHD_SHOW_RECOVERY
) != 0)
975 printf("%s: Entering NONPACK\n", ahd_name(ahd
));
980 printf("%s: Invalid Sequencer interrupt occurred, "
981 "resetting channel.\n",
984 if ((ahd_debug
& AHD_SHOW_RECOVERY
) != 0)
985 ahd_dump_card_state(ahd
);
987 ahd_reset_channel(ahd
, 'A', /*Initiate Reset*/TRUE
);
994 scbid
= ahd_get_scbptr(ahd
);
995 scb
= ahd_lookup_scb(ahd
, scbid
);
997 ahd_print_path(ahd
, scb
);
999 printf("%s: ", ahd_name(ahd
));
1000 printf("SCB %d Packetized Status Overrun", scbid
);
1001 ahd_dump_card_state(ahd
);
1002 ahd_reset_channel(ahd
, 'A', /*Initiate Reset*/TRUE
);
1005 case CFG4ISTAT_INTR
:
1010 scbid
= ahd_get_scbptr(ahd
);
1011 scb
= ahd_lookup_scb(ahd
, scbid
);
1013 ahd_dump_card_state(ahd
);
1014 printf("CFG4ISTAT: Free SCB %d referenced", scbid
);
1015 panic("For safety");
1017 ahd_outq(ahd
, HADDR
, scb
->sense_busaddr
);
1018 ahd_outw(ahd
, HCNT
, AHD_SENSE_BUFSIZE
);
1019 ahd_outb(ahd
, HCNT
+ 2, 0);
1020 ahd_outb(ahd
, SG_CACHE_PRE
, SG_LAST_SEG
);
1021 ahd_outb(ahd
, DFCNTRL
, PRELOADEN
|SCSIEN
|HDMAEN
);
1028 bus_phase
= ahd_inb(ahd
, SCSISIGI
) & PHASE_MASK
;
1029 printf("%s: ILLEGAL_PHASE 0x%x\n",
1030 ahd_name(ahd
), bus_phase
);
1032 switch (bus_phase
) {
1040 ahd_reset_channel(ahd
, 'A', /*Initiate Reset*/TRUE
);
1041 printf("%s: Issued Bus Reset.\n", ahd_name(ahd
));
1045 struct ahd_devinfo devinfo
;
1047 struct ahd_initiator_tinfo
*targ_info
;
1048 struct ahd_tmode_tstate
*tstate
;
1049 struct ahd_transinfo
*tinfo
;
1053 * If a target takes us into the command phase
1054 * assume that it has been externally reset and
1055 * has thus lost our previous packetized negotiation
1057 * Revert to async/narrow transfers until we
1058 * can renegotiate with the device and notify
1059 * the OSM about the reset.
1061 scbid
= ahd_get_scbptr(ahd
);
1062 scb
= ahd_lookup_scb(ahd
, scbid
);
1064 printf("Invalid phase with no valid SCB. "
1065 "Resetting bus.\n");
1066 ahd_reset_channel(ahd
, 'A',
1067 /*Initiate Reset*/TRUE
);
1070 ahd_compile_devinfo(&devinfo
, SCB_GET_OUR_ID(scb
),
1071 SCB_GET_TARGET(ahd
, scb
),
1073 SCB_GET_CHANNEL(ahd
, scb
),
1075 targ_info
= ahd_fetch_transinfo(ahd
,
1080 tinfo
= &targ_info
->curr
;
1081 ahd_set_width(ahd
, &devinfo
, MSG_EXT_WDTR_BUS_8_BIT
,
1082 AHD_TRANS_ACTIVE
, /*paused*/TRUE
);
1083 ahd_set_syncrate(ahd
, &devinfo
, /*period*/0,
1084 /*offset*/0, /*ppr_options*/0,
1085 AHD_TRANS_ACTIVE
, /*paused*/TRUE
);
1086 scb
->flags
|= SCB_EXTERNAL_RESET
;
1087 ahd_freeze_devq(ahd
, scb
);
1088 ahd_set_transaction_status(scb
, CAM_REQUEUE_REQ
);
1089 ahd_freeze_scb(scb
);
1092 ahd_send_async(ahd
, devinfo
.channel
, devinfo
.target
,
1093 CAM_LUN_WILDCARD
, AC_SENT_BDR
, NULL
);
1096 * Allow the sequencer to continue with
1097 * non-pack processing.
1099 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
1100 ahd_outb(ahd
, CLRLQOINT1
, CLRLQOPHACHGINPKT
);
1101 if ((ahd
->bugs
& AHD_CLRLQO_AUTOCLR_BUG
) != 0) {
1102 ahd_outb(ahd
, CLRLQOINT1
, 0);
1105 if ((ahd_debug
& AHD_SHOW_RECOVERY
) != 0) {
1106 ahd_print_path(ahd
, scb
);
1107 printf("Unexpected command phase from "
1108 "packetized target\n");
1122 if ((ahd_debug
& AHD_SHOW_RECOVERY
) != 0) {
1123 printf("%s: CFG4OVERRUN mode = %x\n", ahd_name(ahd
),
1124 ahd_inb(ahd
, MODE_PTR
));
1127 scb_index
= ahd_get_scbptr(ahd
);
1128 scb
= ahd_lookup_scb(ahd
, scb_index
);
1131 * Attempt to transfer to an SCB that is
1134 ahd_assert_atn(ahd
);
1135 ahd_outb(ahd
, MSG_OUT
, HOST_MSG
);
1136 ahd
->msgout_buf
[0] = MSG_ABORT_TASK
;
1137 ahd
->msgout_len
= 1;
1138 ahd
->msgout_index
= 0;
1139 ahd
->msg_type
= MSG_TYPE_INITIATOR_MSGOUT
;
1141 * Clear status received flag to prevent any
1142 * attempt to complete this bogus SCB.
1144 ahd_outb(ahd
, SCB_CONTROL
,
1145 ahd_inb_scbram(ahd
, SCB_CONTROL
)
1150 case DUMP_CARD_STATE
:
1152 ahd_dump_card_state(ahd
);
1158 if ((ahd_debug
& AHD_SHOW_RECOVERY
) != 0) {
1159 printf("%s: PDATA_REINIT - DFCNTRL = 0x%x "
1160 "SG_CACHE_SHADOW = 0x%x\n",
1161 ahd_name(ahd
), ahd_inb(ahd
, DFCNTRL
),
1162 ahd_inb(ahd
, SG_CACHE_SHADOW
));
1165 ahd_reinitialize_dataptrs(ahd
);
1170 struct ahd_devinfo devinfo
;
1173 * The sequencer has encountered a message phase
1174 * that requires host assistance for completion.
1175 * While handling the message phase(s), we will be
1176 * notified by the sequencer after each byte is
1177 * transfered so we can track bus phase changes.
1179 * If this is the first time we've seen a HOST_MSG_LOOP
1180 * interrupt, initialize the state of the host message
1183 ahd_fetch_devinfo(ahd
, &devinfo
);
1184 if (ahd
->msg_type
== MSG_TYPE_NONE
) {
1189 bus_phase
= ahd_inb(ahd
, SCSISIGI
) & PHASE_MASK
;
1190 if (bus_phase
!= P_MESGIN
1191 && bus_phase
!= P_MESGOUT
) {
1192 printf("ahd_intr: HOST_MSG_LOOP bad "
1193 "phase 0x%x\n", bus_phase
);
1195 * Probably transitioned to bus free before
1196 * we got here. Just punt the message.
1198 ahd_dump_card_state(ahd
);
1199 ahd_clear_intstat(ahd
);
1204 scb_index
= ahd_get_scbptr(ahd
);
1205 scb
= ahd_lookup_scb(ahd
, scb_index
);
1206 if (devinfo
.role
== ROLE_INITIATOR
) {
1207 if (bus_phase
== P_MESGOUT
)
1208 ahd_setup_initiator_msgout(ahd
,
1213 MSG_TYPE_INITIATOR_MSGIN
;
1214 ahd
->msgin_index
= 0;
1217 #ifdef AHD_TARGET_MODE
1219 if (bus_phase
== P_MESGOUT
) {
1221 MSG_TYPE_TARGET_MSGOUT
;
1222 ahd
->msgin_index
= 0;
1225 ahd_setup_target_msgin(ahd
,
1232 ahd_handle_message_phase(ahd
);
1237 /* Ensure we don't leave the selection hardware on */
1238 AHD_ASSERT_MODES(ahd
, AHD_MODE_SCSI_MSK
, AHD_MODE_SCSI_MSK
);
1239 ahd_outb(ahd
, SCSISEQ0
, ahd_inb(ahd
, SCSISEQ0
) & ~ENSELO
);
1241 printf("%s:%c:%d: no active SCB for reconnecting "
1242 "target - issuing BUS DEVICE RESET\n",
1243 ahd_name(ahd
), 'A', ahd_inb(ahd
, SELID
) >> 4);
1244 printf("SAVED_SCSIID == 0x%x, SAVED_LUN == 0x%x, "
1245 "REG0 == 0x%x ACCUM = 0x%x\n",
1246 ahd_inb(ahd
, SAVED_SCSIID
), ahd_inb(ahd
, SAVED_LUN
),
1247 ahd_inw(ahd
, REG0
), ahd_inb(ahd
, ACCUM
));
1248 printf("SEQ_FLAGS == 0x%x, SCBPTR == 0x%x, BTT == 0x%x, "
1250 ahd_inb(ahd
, SEQ_FLAGS
), ahd_get_scbptr(ahd
),
1251 ahd_find_busy_tcl(ahd
,
1252 BUILD_TCL(ahd_inb(ahd
, SAVED_SCSIID
),
1253 ahd_inb(ahd
, SAVED_LUN
))),
1254 ahd_inw(ahd
, SINDEX
));
1255 printf("SELID == 0x%x, SCB_SCSIID == 0x%x, SCB_LUN == 0x%x, "
1256 "SCB_CONTROL == 0x%x\n",
1257 ahd_inb(ahd
, SELID
), ahd_inb_scbram(ahd
, SCB_SCSIID
),
1258 ahd_inb_scbram(ahd
, SCB_LUN
),
1259 ahd_inb_scbram(ahd
, SCB_CONTROL
));
1260 printf("SCSIBUS[0] == 0x%x, SCSISIGI == 0x%x\n",
1261 ahd_inb(ahd
, SCSIBUS
), ahd_inb(ahd
, SCSISIGI
));
1262 printf("SXFRCTL0 == 0x%x\n", ahd_inb(ahd
, SXFRCTL0
));
1263 printf("SEQCTL0 == 0x%x\n", ahd_inb(ahd
, SEQCTL0
));
1264 ahd_dump_card_state(ahd
);
1265 ahd
->msgout_buf
[0] = MSG_BUS_DEV_RESET
;
1266 ahd
->msgout_len
= 1;
1267 ahd
->msgout_index
= 0;
1268 ahd
->msg_type
= MSG_TYPE_INITIATOR_MSGOUT
;
1269 ahd_outb(ahd
, MSG_OUT
, HOST_MSG
);
1270 ahd_assert_atn(ahd
);
1273 case PROTO_VIOLATION
:
1275 ahd_handle_proto_violation(ahd
);
1280 struct ahd_devinfo devinfo
;
1282 ahd_fetch_devinfo(ahd
, &devinfo
);
1283 ahd_handle_ign_wide_residue(ahd
, &devinfo
);
1290 lastphase
= ahd_inb(ahd
, LASTPHASE
);
1291 printf("%s:%c:%d: unknown scsi bus phase %x, "
1292 "lastphase = 0x%x. Attempting to continue\n",
1294 SCSIID_TARGET(ahd
, ahd_inb(ahd
, SAVED_SCSIID
)),
1295 lastphase
, ahd_inb(ahd
, SCSISIGI
));
1298 case MISSED_BUSFREE
:
1302 lastphase
= ahd_inb(ahd
, LASTPHASE
);
1303 printf("%s:%c:%d: Missed busfree. "
1304 "Lastphase = 0x%x, Curphase = 0x%x\n",
1306 SCSIID_TARGET(ahd
, ahd_inb(ahd
, SAVED_SCSIID
)),
1307 lastphase
, ahd_inb(ahd
, SCSISIGI
));
1314 * When the sequencer detects an overrun, it
1315 * places the controller in "BITBUCKET" mode
1316 * and allows the target to complete its transfer.
1317 * Unfortunately, none of the counters get updated
1318 * when the controller is in this mode, so we have
1319 * no way of knowing how large the overrun was.
1327 scbindex
= ahd_get_scbptr(ahd
);
1328 scb
= ahd_lookup_scb(ahd
, scbindex
);
1330 lastphase
= ahd_inb(ahd
, LASTPHASE
);
1331 if ((ahd_debug
& AHD_SHOW_RECOVERY
) != 0) {
1332 ahd_print_path(ahd
, scb
);
1333 printf("data overrun detected %s. Tag == 0x%x.\n",
1334 ahd_lookup_phase_entry(lastphase
)->phasemsg
,
1336 ahd_print_path(ahd
, scb
);
1337 printf("%s seen Data Phase. Length = %ld. "
1339 ahd_inb(ahd
, SEQ_FLAGS
) & DPHASE
1340 ? "Have" : "Haven't",
1341 ahd_get_transfer_length(scb
), scb
->sg_count
);
1342 ahd_dump_sglist(scb
);
1347 * Set this and it will take effect when the
1348 * target does a command complete.
1350 ahd_freeze_devq(ahd
, scb
);
1351 ahd_set_transaction_status(scb
, CAM_DATA_RUN_ERR
);
1352 ahd_freeze_scb(scb
);
1357 struct ahd_devinfo devinfo
;
1361 ahd_fetch_devinfo(ahd
, &devinfo
);
1362 printf("%s:%c:%d:%d: Attempt to issue message failed\n",
1363 ahd_name(ahd
), devinfo
.channel
, devinfo
.target
,
1365 scbid
= ahd_get_scbptr(ahd
);
1366 scb
= ahd_lookup_scb(ahd
, scbid
);
1368 && (scb
->flags
& SCB_RECOVERY_SCB
) != 0)
1370 * Ensure that we didn't put a second instance of this
1371 * SCB into the QINFIFO.
1373 ahd_search_qinfifo(ahd
, SCB_GET_TARGET(ahd
, scb
),
1374 SCB_GET_CHANNEL(ahd
, scb
),
1375 SCB_GET_LUN(scb
), SCB_GET_TAG(scb
),
1376 ROLE_INITIATOR
, /*status*/0,
1378 ahd_outb(ahd
, SCB_CONTROL
,
1379 ahd_inb_scbram(ahd
, SCB_CONTROL
) & ~MK_MESSAGE
);
1382 case TASKMGMT_FUNC_COMPLETE
:
1387 scbid
= ahd_get_scbptr(ahd
);
1388 scb
= ahd_lookup_scb(ahd
, scbid
);
1394 ahd_print_path(ahd
, scb
);
1395 printf("Task Management Func 0x%x Complete\n",
1396 scb
->hscb
->task_management
);
1397 lun
= CAM_LUN_WILDCARD
;
1398 tag
= SCB_LIST_NULL
;
1400 switch (scb
->hscb
->task_management
) {
1401 case SIU_TASKMGMT_ABORT_TASK
:
1402 tag
= SCB_GET_TAG(scb
);
1403 case SIU_TASKMGMT_ABORT_TASK_SET
:
1404 case SIU_TASKMGMT_CLEAR_TASK_SET
:
1405 lun
= scb
->hscb
->lun
;
1406 error
= CAM_REQ_ABORTED
;
1407 ahd_abort_scbs(ahd
, SCB_GET_TARGET(ahd
, scb
),
1408 'A', lun
, tag
, ROLE_INITIATOR
,
1411 case SIU_TASKMGMT_LUN_RESET
:
1412 lun
= scb
->hscb
->lun
;
1413 case SIU_TASKMGMT_TARGET_RESET
:
1415 struct ahd_devinfo devinfo
;
1417 ahd_scb_devinfo(ahd
, &devinfo
, scb
);
1418 error
= CAM_BDR_SENT
;
1419 ahd_handle_devreset(ahd
, &devinfo
, lun
,
1421 lun
!= CAM_LUN_WILDCARD
1424 /*verbose_level*/0);
1428 panic("Unexpected TaskMgmt Func\n");
1434 case TASKMGMT_CMD_CMPLT_OKAY
:
1440 * An ABORT TASK TMF failed to be delivered before
1441 * the targeted command completed normally.
1443 scbid
= ahd_get_scbptr(ahd
);
1444 scb
= ahd_lookup_scb(ahd
, scbid
);
1447 * Remove the second instance of this SCB from
1448 * the QINFIFO if it is still there.
1450 ahd_print_path(ahd
, scb
);
1451 printf("SCB completes before TMF\n");
1453 * Handle losing the race. Wait until any
1454 * current selection completes. We will then
1455 * set the TMF back to zero in this SCB so that
1456 * the sequencer doesn't bother to issue another
1457 * sequencer interrupt for its completion.
1459 while ((ahd_inb(ahd
, SCSISEQ0
) & ENSELO
) != 0
1460 && (ahd_inb(ahd
, SSTAT0
) & SELDO
) == 0
1461 && (ahd_inb(ahd
, SSTAT1
) & SELTO
) == 0)
1463 ahd_outb(ahd
, SCB_TASK_MANAGEMENT
, 0);
1464 ahd_search_qinfifo(ahd
, SCB_GET_TARGET(ahd
, scb
),
1465 SCB_GET_CHANNEL(ahd
, scb
),
1466 SCB_GET_LUN(scb
), SCB_GET_TAG(scb
),
1467 ROLE_INITIATOR
, /*status*/0,
1476 printf("%s: Tracepoint %d\n", ahd_name(ahd
),
1477 seqintcode
- TRACEPOINT0
);
1482 ahd_handle_hwerrint(ahd
);
1485 printf("%s: Unexpected SEQINTCODE %d\n", ahd_name(ahd
),
1490 * The sequencer is paused immediately on
1491 * a SEQINT, so we should restart it when
1498 ahd_handle_scsiint(struct ahd_softc
*ahd
, u_int intstat
)
1509 ahd_update_modes(ahd
);
1510 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
1512 status3
= ahd_inb(ahd
, SSTAT3
) & (NTRAMPERR
|OSRAMPERR
);
1513 status0
= ahd_inb(ahd
, SSTAT0
) & (IOERR
|OVERRUN
|SELDI
|SELDO
);
1514 status
= ahd_inb(ahd
, SSTAT1
) & (SELTO
|SCSIRSTI
|BUSFREE
|SCSIPERR
);
1515 lqistat1
= ahd_inb(ahd
, LQISTAT1
);
1516 lqostat0
= ahd_inb(ahd
, LQOSTAT0
);
1517 busfreetime
= ahd_inb(ahd
, SSTAT2
) & BUSFREETIME
;
1520 * Ignore external resets after a bus reset.
1522 if (((status
& SCSIRSTI
) != 0) && (ahd
->flags
& AHD_BUS_RESET_ACTIVE
))
1526 * Clear bus reset flag
1528 ahd
->flags
&= ~AHD_BUS_RESET_ACTIVE
;
1530 if ((status0
& (SELDI
|SELDO
)) != 0) {
1533 ahd_set_modes(ahd
, AHD_MODE_CFG
, AHD_MODE_CFG
);
1534 simode0
= ahd_inb(ahd
, SIMODE0
);
1535 status0
&= simode0
& (IOERR
|OVERRUN
|SELDI
|SELDO
);
1536 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
1538 scbid
= ahd_get_scbptr(ahd
);
1539 scb
= ahd_lookup_scb(ahd
, scbid
);
1541 && (ahd_inb(ahd
, SEQ_FLAGS
) & NOT_IDENTIFIED
) != 0)
1544 if ((status0
& IOERR
) != 0) {
1547 now_lvd
= ahd_inb(ahd
, SBLKCTL
) & ENAB40
;
1548 printf("%s: Transceiver State Has Changed to %s mode\n",
1549 ahd_name(ahd
), now_lvd
? "LVD" : "SE");
1550 ahd_outb(ahd
, CLRSINT0
, CLRIOERR
);
1552 * A change in I/O mode is equivalent to a bus reset.
1554 ahd_reset_channel(ahd
, 'A', /*Initiate Reset*/TRUE
);
1556 ahd_setup_iocell_workaround(ahd
);
1558 } else if ((status0
& OVERRUN
) != 0) {
1560 printf("%s: SCSI offset overrun detected. Resetting bus.\n",
1562 ahd_reset_channel(ahd
, 'A', /*Initiate Reset*/TRUE
);
1563 } else if ((status
& SCSIRSTI
) != 0) {
1565 printf("%s: Someone reset channel A\n", ahd_name(ahd
));
1566 ahd_reset_channel(ahd
, 'A', /*Initiate Reset*/FALSE
);
1567 } else if ((status
& SCSIPERR
) != 0) {
1569 /* Make sure the sequencer is in a safe location. */
1570 ahd_clear_critical_section(ahd
);
1572 ahd_handle_transmission_error(ahd
);
1573 } else if (lqostat0
!= 0) {
1575 printf("%s: lqostat0 == 0x%x!\n", ahd_name(ahd
), lqostat0
);
1576 ahd_outb(ahd
, CLRLQOINT0
, lqostat0
);
1577 if ((ahd
->bugs
& AHD_CLRLQO_AUTOCLR_BUG
) != 0)
1578 ahd_outb(ahd
, CLRLQOINT1
, 0);
1579 } else if ((status
& SELTO
) != 0) {
1582 /* Stop the selection */
1583 ahd_outb(ahd
, SCSISEQ0
, 0);
1585 /* Make sure the sequencer is in a safe location. */
1586 ahd_clear_critical_section(ahd
);
1588 /* No more pending messages */
1589 ahd_clear_msg_state(ahd
);
1591 /* Clear interrupt state */
1592 ahd_outb(ahd
, CLRSINT1
, CLRSELTIMEO
|CLRBUSFREE
|CLRSCSIPERR
);
1595 * Although the driver does not care about the
1596 * 'Selection in Progress' status bit, the busy
1597 * LED does. SELINGO is only cleared by a sucessfull
1598 * selection, so we must manually clear it to insure
1599 * the LED turns off just incase no future successful
1600 * selections occur (e.g. no devices on the bus).
1602 ahd_outb(ahd
, CLRSINT0
, CLRSELINGO
);
1604 scbid
= ahd_inw(ahd
, WAITING_TID_HEAD
);
1605 scb
= ahd_lookup_scb(ahd
, scbid
);
1607 printf("%s: ahd_intr - referenced scb not "
1608 "valid during SELTO scb(0x%x)\n",
1609 ahd_name(ahd
), scbid
);
1610 ahd_dump_card_state(ahd
);
1612 struct ahd_devinfo devinfo
;
1614 if ((ahd_debug
& AHD_SHOW_SELTO
) != 0) {
1615 ahd_print_path(ahd
, scb
);
1616 printf("Saw Selection Timeout for SCB 0x%x\n",
1620 ahd_scb_devinfo(ahd
, &devinfo
, scb
);
1621 ahd_set_transaction_status(scb
, CAM_SEL_TIMEOUT
);
1622 ahd_freeze_devq(ahd
, scb
);
1625 * Cancel any pending transactions on the device
1626 * now that it seems to be missing. This will
1627 * also revert us to async/narrow transfers until
1628 * we can renegotiate with the device.
1630 ahd_handle_devreset(ahd
, &devinfo
,
1633 "Selection Timeout",
1634 /*verbose_level*/1);
1636 ahd_outb(ahd
, CLRINT
, CLRSCSIINT
);
1637 ahd_iocell_first_selection(ahd
);
1639 } else if ((status0
& (SELDI
|SELDO
)) != 0) {
1641 ahd_iocell_first_selection(ahd
);
1643 } else if (status3
!= 0) {
1644 printf("%s: SCSI Cell parity error SSTAT3 == 0x%x\n",
1645 ahd_name(ahd
), status3
);
1646 ahd_outb(ahd
, CLRSINT3
, status3
);
1647 } else if ((lqistat1
& (LQIPHASE_LQ
|LQIPHASE_NLQ
)) != 0) {
1649 /* Make sure the sequencer is in a safe location. */
1650 ahd_clear_critical_section(ahd
);
1652 ahd_handle_lqiphase_error(ahd
, lqistat1
);
1653 } else if ((lqistat1
& LQICRCI_NLQ
) != 0) {
1655 * This status can be delayed during some
1656 * streaming operations. The SCSIPHASE
1657 * handler has already dealt with this case
1658 * so just clear the error.
1660 ahd_outb(ahd
, CLRLQIINT1
, CLRLQICRCI_NLQ
);
1661 } else if ((status
& BUSFREE
) != 0
1662 || (lqistat1
& LQOBUSFREE
) != 0) {
1670 * Clear our selection hardware as soon as possible.
1671 * We may have an entry in the waiting Q for this target,
1672 * that is affected by this busfree and we don't want to
1673 * go about selecting the target while we handle the event.
1675 ahd_outb(ahd
, SCSISEQ0
, 0);
1677 /* Make sure the sequencer is in a safe location. */
1678 ahd_clear_critical_section(ahd
);
1681 * Determine what we were up to at the time of
1684 mode
= AHD_MODE_SCSI
;
1685 busfreetime
= ahd_inb(ahd
, SSTAT2
) & BUSFREETIME
;
1686 lqostat1
= ahd_inb(ahd
, LQOSTAT1
);
1687 switch (busfreetime
) {
1694 mode
= busfreetime
== BUSFREE_DFF0
1695 ? AHD_MODE_DFF0
: AHD_MODE_DFF1
;
1696 ahd_set_modes(ahd
, mode
, mode
);
1697 scbid
= ahd_get_scbptr(ahd
);
1698 scb
= ahd_lookup_scb(ahd
, scbid
);
1700 printf("%s: Invalid SCB %d in DFF%d "
1701 "during unexpected busfree\n",
1702 ahd_name(ahd
), scbid
, mode
);
1705 packetized
= (scb
->flags
& SCB_PACKETIZED
) != 0;
1715 packetized
= (lqostat1
& LQOBUSFREE
) != 0;
1717 && ahd_inb(ahd
, LASTPHASE
) == P_BUSFREE
1718 && (ahd_inb(ahd
, SSTAT0
) & SELDI
) == 0
1719 && ((ahd_inb(ahd
, SSTAT0
) & SELDO
) == 0
1720 || (ahd_inb(ahd
, SCSISEQ0
) & ENSELO
) == 0))
1722 * Assume packetized if we are not
1723 * on the bus in a non-packetized
1724 * capacity and any pending selection
1725 * was a packetized selection.
1732 if ((ahd_debug
& AHD_SHOW_MISC
) != 0)
1733 printf("Saw Busfree. Busfreetime = 0x%x.\n",
1737 * Busfrees that occur in non-packetized phases are
1738 * handled by the nonpkt_busfree handler.
1740 if (packetized
&& ahd_inb(ahd
, LASTPHASE
) == P_BUSFREE
) {
1741 restart
= ahd_handle_pkt_busfree(ahd
, busfreetime
);
1744 restart
= ahd_handle_nonpkt_busfree(ahd
);
1747 * Clear the busfree interrupt status. The setting of
1748 * the interrupt is a pulse, so in a perfect world, we
1749 * would not need to muck with the ENBUSFREE logic. This
1750 * would ensure that if the bus moves on to another
1751 * connection, busfree protection is still in force. If
1752 * BUSFREEREV is broken, however, we must manually clear
1753 * the ENBUSFREE if the busfree occurred during a non-pack
1754 * connection so that we don't get false positives during
1755 * future, packetized, connections.
1757 ahd_outb(ahd
, CLRSINT1
, CLRBUSFREE
);
1759 && (ahd
->bugs
& AHD_BUSFREEREV_BUG
) != 0)
1760 ahd_outb(ahd
, SIMODE1
,
1761 ahd_inb(ahd
, SIMODE1
) & ~ENBUSFREE
);
1764 ahd_clear_fifo(ahd
, mode
);
1766 ahd_clear_msg_state(ahd
);
1767 ahd_outb(ahd
, CLRINT
, CLRSCSIINT
);
1774 printf("%s: Missing case in ahd_handle_scsiint. status = %x\n",
1775 ahd_name(ahd
), status
);
1776 ahd_dump_card_state(ahd
);
1777 ahd_clear_intstat(ahd
);
1783 ahd_handle_transmission_error(struct ahd_softc
*ahd
)
1797 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
1798 lqistat1
= ahd_inb(ahd
, LQISTAT1
) & ~(LQIPHASE_LQ
|LQIPHASE_NLQ
);
1799 lqistat2
= ahd_inb(ahd
, LQISTAT2
);
1800 if ((lqistat1
& (LQICRCI_NLQ
|LQICRCI_LQ
)) == 0
1801 && (ahd
->bugs
& AHD_NLQICRC_DELAYED_BUG
) != 0) {
1804 ahd_set_modes(ahd
, AHD_MODE_CFG
, AHD_MODE_CFG
);
1805 lqistate
= ahd_inb(ahd
, LQISTATE
);
1806 if ((lqistate
>= 0x1E && lqistate
<= 0x24)
1807 || (lqistate
== 0x29)) {
1809 if ((ahd_debug
& AHD_SHOW_RECOVERY
) != 0) {
1810 printf("%s: NLQCRC found via LQISTATE\n",
1814 lqistat1
|= LQICRCI_NLQ
;
1816 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
1819 ahd_outb(ahd
, CLRLQIINT1
, lqistat1
);
1820 lastphase
= ahd_inb(ahd
, LASTPHASE
);
1821 curphase
= ahd_inb(ahd
, SCSISIGI
) & PHASE_MASK
;
1822 perrdiag
= ahd_inb(ahd
, PERRDIAG
);
1823 msg_out
= MSG_INITIATOR_DET_ERR
;
1824 ahd_outb(ahd
, CLRSINT1
, CLRSCSIPERR
);
1827 * Try to find the SCB associated with this error.
1831 || (lqistat1
& LQICRCI_NLQ
) != 0) {
1832 if ((lqistat1
& (LQICRCI_NLQ
|LQIOVERI_NLQ
)) != 0)
1833 ahd_set_active_fifo(ahd
);
1834 scbid
= ahd_get_scbptr(ahd
);
1835 scb
= ahd_lookup_scb(ahd
, scbid
);
1836 if (scb
!= NULL
&& SCB_IS_SILENT(scb
))
1841 if (silent
== FALSE
) {
1842 printf("%s: Transmission error detected\n", ahd_name(ahd
));
1843 ahd_lqistat1_print(lqistat1
, &cur_col
, 50);
1844 ahd_lastphase_print(lastphase
, &cur_col
, 50);
1845 ahd_scsisigi_print(curphase
, &cur_col
, 50);
1846 ahd_perrdiag_print(perrdiag
, &cur_col
, 50);
1848 ahd_dump_card_state(ahd
);
1851 if ((lqistat1
& (LQIOVERI_LQ
|LQIOVERI_NLQ
)) != 0) {
1852 if (silent
== FALSE
) {
1853 printf("%s: Gross protocol error during incoming "
1854 "packet. lqistat1 == 0x%x. Resetting bus.\n",
1855 ahd_name(ahd
), lqistat1
);
1857 ahd_reset_channel(ahd
, 'A', /*Initiate Reset*/TRUE
);
1859 } else if ((lqistat1
& LQICRCI_LQ
) != 0) {
1861 * A CRC error has been detected on an incoming LQ.
1862 * The bus is currently hung on the last ACK.
1863 * Hit LQIRETRY to release the last ack, and
1864 * wait for the sequencer to determine that ATNO
1865 * is asserted while in message out to take us
1866 * to our host message loop. No NONPACKREQ or
1867 * LQIPHASE type errors will occur in this
1868 * scenario. After this first LQIRETRY, the LQI
1869 * manager will be in ISELO where it will
1870 * happily sit until another packet phase begins.
1871 * Unexpected bus free detection is enabled
1872 * through any phases that occur after we release
1873 * this last ack until the LQI manager sees a
1874 * packet phase. This implies we may have to
1875 * ignore a perfectly valid "unexected busfree"
1876 * after our "initiator detected error" message is
1877 * sent. A busfree is the expected response after
1878 * we tell the target that it's L_Q was corrupted.
1879 * (SPI4R09 10.7.3.3.3)
1881 ahd_outb(ahd
, LQCTL2
, LQIRETRY
);
1882 printf("LQIRetry for LQICRCI_LQ to release ACK\n");
1883 } else if ((lqistat1
& LQICRCI_NLQ
) != 0) {
1885 * We detected a CRC error in a NON-LQ packet.
1886 * The hardware has varying behavior in this situation
1887 * depending on whether this packet was part of a
1891 * The hardware has already acked the complete packet.
1892 * If the target honors our outstanding ATN condition,
1893 * we should be (or soon will be) in MSGOUT phase.
1894 * This will trigger the LQIPHASE_LQ status bit as the
1895 * hardware was expecting another LQ. Unexpected
1896 * busfree detection is enabled. Once LQIPHASE_LQ is
1897 * true (first entry into host message loop is much
1898 * the same), we must clear LQIPHASE_LQ and hit
1899 * LQIRETRY so the hardware is ready to handle
1900 * a future LQ. NONPACKREQ will not be asserted again
1901 * once we hit LQIRETRY until another packet is
1902 * processed. The target may either go busfree
1903 * or start another packet in response to our message.
1905 * Read Streaming P0 asserted:
1906 * If we raise ATN and the target completes the entire
1907 * stream (P0 asserted during the last packet), the
1908 * hardware will ack all data and return to the ISTART
1909 * state. When the target reponds to our ATN condition,
1910 * LQIPHASE_LQ will be asserted. We should respond to
1911 * this with an LQIRETRY to prepare for any future
1912 * packets. NONPACKREQ will not be asserted again
1913 * once we hit LQIRETRY until another packet is
1914 * processed. The target may either go busfree or
1915 * start another packet in response to our message.
1916 * Busfree detection is enabled.
1918 * Read Streaming P0 not asserted:
1919 * If we raise ATN and the target transitions to
1920 * MSGOUT in or after a packet where P0 is not
1921 * asserted, the hardware will assert LQIPHASE_NLQ.
1922 * We should respond to the LQIPHASE_NLQ with an
1923 * LQIRETRY. Should the target stay in a non-pkt
1924 * phase after we send our message, the hardware
1925 * will assert LQIPHASE_LQ. Recovery is then just as
1926 * listed above for the read streaming with P0 asserted.
1927 * Busfree detection is enabled.
1929 if (silent
== FALSE
)
1930 printf("LQICRC_NLQ\n");
1932 printf("%s: No SCB valid for LQICRC_NLQ. "
1933 "Resetting bus\n", ahd_name(ahd
));
1934 ahd_reset_channel(ahd
, 'A', /*Initiate Reset*/TRUE
);
1937 } else if ((lqistat1
& LQIBADLQI
) != 0) {
1938 printf("Need to handle BADLQI!\n");
1939 ahd_reset_channel(ahd
, 'A', /*Initiate Reset*/TRUE
);
1941 } else if ((perrdiag
& (PARITYERR
|PREVPHASE
)) == PARITYERR
) {
1942 if ((curphase
& ~P_DATAIN_DT
) != 0) {
1943 /* Ack the byte. So we can continue. */
1944 if (silent
== FALSE
)
1945 printf("Acking %s to clear perror\n",
1946 ahd_lookup_phase_entry(curphase
)->phasemsg
);
1947 ahd_inb(ahd
, SCSIDAT
);
1950 if (curphase
== P_MESGIN
)
1951 msg_out
= MSG_PARITY_ERROR
;
1955 * We've set the hardware to assert ATN if we
1956 * get a parity error on "in" phases, so all we
1957 * need to do is stuff the message buffer with
1958 * the appropriate message. "In" phases have set
1959 * mesg_out to something other than MSG_NOP.
1961 ahd
->send_msg_perror
= msg_out
;
1962 if (scb
!= NULL
&& msg_out
== MSG_INITIATOR_DET_ERR
)
1963 scb
->flags
|= SCB_TRANSMISSION_ERROR
;
1964 ahd_outb(ahd
, MSG_OUT
, HOST_MSG
);
1965 ahd_outb(ahd
, CLRINT
, CLRSCSIINT
);
1970 ahd_handle_lqiphase_error(struct ahd_softc
*ahd
, u_int lqistat1
)
1973 * Clear the sources of the interrupts.
1975 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
1976 ahd_outb(ahd
, CLRLQIINT1
, lqistat1
);
1979 * If the "illegal" phase changes were in response
1980 * to our ATN to flag a CRC error, AND we ended up
1981 * on packet boundaries, clear the error, restart the
1982 * LQI manager as appropriate, and go on our merry
1983 * way toward sending the message. Otherwise, reset
1984 * the bus to clear the error.
1986 ahd_set_active_fifo(ahd
);
1987 if ((ahd_inb(ahd
, SCSISIGO
) & ATNO
) != 0
1988 && (ahd_inb(ahd
, MDFFSTAT
) & DLZERO
) != 0) {
1989 if ((lqistat1
& LQIPHASE_LQ
) != 0) {
1990 printf("LQIRETRY for LQIPHASE_LQ\n");
1991 ahd_outb(ahd
, LQCTL2
, LQIRETRY
);
1992 } else if ((lqistat1
& LQIPHASE_NLQ
) != 0) {
1993 printf("LQIRETRY for LQIPHASE_NLQ\n");
1994 ahd_outb(ahd
, LQCTL2
, LQIRETRY
);
1996 panic("ahd_handle_lqiphase_error: No phase errors\n");
1997 ahd_dump_card_state(ahd
);
1998 ahd_outb(ahd
, CLRINT
, CLRSCSIINT
);
2001 printf("Reseting Channel for LQI Phase error\n");
2002 ahd_dump_card_state(ahd
);
2003 ahd_reset_channel(ahd
, 'A', /*Initiate Reset*/TRUE
);
2008 * Packetized unexpected or expected busfree.
2009 * Entered in mode based on busfreetime.
2012 ahd_handle_pkt_busfree(struct ahd_softc
*ahd
, u_int busfreetime
)
2016 AHD_ASSERT_MODES(ahd
, ~(AHD_MODE_UNKNOWN_MSK
|AHD_MODE_CFG_MSK
),
2017 ~(AHD_MODE_UNKNOWN_MSK
|AHD_MODE_CFG_MSK
));
2018 lqostat1
= ahd_inb(ahd
, LQOSTAT1
);
2019 if ((lqostat1
& LQOBUSFREE
) != 0) {
2028 * The LQO manager detected an unexpected busfree
2031 * 1) During an outgoing LQ.
2032 * 2) After an outgoing LQ but before the first
2033 * REQ of the command packet.
2034 * 3) During an outgoing command packet.
2036 * In all cases, CURRSCB is pointing to the
2037 * SCB that encountered the failure. Clean
2038 * up the queue, clear SELDO and LQOBUSFREE,
2039 * and allow the sequencer to restart the select
2040 * out at its lesure.
2042 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
2043 scbid
= ahd_inw(ahd
, CURRSCB
);
2044 scb
= ahd_lookup_scb(ahd
, scbid
);
2046 panic("SCB not valid during LQOBUSFREE");
2050 ahd_outb(ahd
, CLRLQOINT1
, CLRLQOBUSFREE
);
2051 if ((ahd
->bugs
& AHD_CLRLQO_AUTOCLR_BUG
) != 0)
2052 ahd_outb(ahd
, CLRLQOINT1
, 0);
2053 ahd_outb(ahd
, SCSISEQ0
, ahd_inb(ahd
, SCSISEQ0
) & ~ENSELO
);
2054 ahd_flush_device_writes(ahd
);
2055 ahd_outb(ahd
, CLRSINT0
, CLRSELDO
);
2058 * Return the LQO manager to its idle loop. It will
2059 * not do this automatically if the busfree occurs
2060 * after the first REQ of either the LQ or command
2061 * packet or between the LQ and command packet.
2063 ahd_outb(ahd
, LQCTL2
, ahd_inb(ahd
, LQCTL2
) | LQOTOIDLE
);
2066 * Update the waiting for selection queue so
2067 * we restart on the correct SCB.
2069 waiting_h
= ahd_inw(ahd
, WAITING_TID_HEAD
);
2070 saved_scbptr
= ahd_get_scbptr(ahd
);
2071 if (waiting_h
!= scbid
) {
2073 ahd_outw(ahd
, WAITING_TID_HEAD
, scbid
);
2074 waiting_t
= ahd_inw(ahd
, WAITING_TID_TAIL
);
2075 if (waiting_t
== waiting_h
) {
2076 ahd_outw(ahd
, WAITING_TID_TAIL
, scbid
);
2077 next
= SCB_LIST_NULL
;
2079 ahd_set_scbptr(ahd
, waiting_h
);
2080 next
= ahd_inw_scbram(ahd
, SCB_NEXT2
);
2082 ahd_set_scbptr(ahd
, scbid
);
2083 ahd_outw(ahd
, SCB_NEXT2
, next
);
2085 ahd_set_scbptr(ahd
, saved_scbptr
);
2086 if (scb
->crc_retry_count
< AHD_MAX_LQ_CRC_ERRORS
) {
2087 if (SCB_IS_SILENT(scb
) == FALSE
) {
2088 ahd_print_path(ahd
, scb
);
2089 printf("Probable outgoing LQ CRC error. "
2090 "Retrying command\n");
2092 scb
->crc_retry_count
++;
2094 ahd_set_transaction_status(scb
, CAM_UNCOR_PARITY
);
2095 ahd_freeze_scb(scb
);
2096 ahd_freeze_devq(ahd
, scb
);
2098 /* Return unpausing the sequencer. */
2100 } else if ((ahd_inb(ahd
, PERRDIAG
) & PARITYERR
) != 0) {
2102 * Ignore what are really parity errors that
2103 * occur on the last REQ of a free running
2104 * clock prior to going busfree. Some drives
2105 * do not properly active negate just before
2106 * going busfree resulting in a parity glitch.
2108 ahd_outb(ahd
, CLRSINT1
, CLRSCSIPERR
|CLRBUSFREE
);
2110 if ((ahd_debug
& AHD_SHOW_MASKED_ERRORS
) != 0)
2111 printf("%s: Parity on last REQ detected "
2112 "during busfree phase.\n",
2115 /* Return unpausing the sequencer. */
2118 if (ahd
->src_mode
!= AHD_MODE_SCSI
) {
2122 scbid
= ahd_get_scbptr(ahd
);
2123 scb
= ahd_lookup_scb(ahd
, scbid
);
2124 ahd_print_path(ahd
, scb
);
2125 printf("Unexpected PKT busfree condition\n");
2126 ahd_dump_card_state(ahd
);
2127 ahd_abort_scbs(ahd
, SCB_GET_TARGET(ahd
, scb
), 'A',
2128 SCB_GET_LUN(scb
), SCB_GET_TAG(scb
),
2129 ROLE_INITIATOR
, CAM_UNEXP_BUSFREE
);
2131 /* Return restarting the sequencer. */
2134 printf("%s: Unexpected PKT busfree condition\n", ahd_name(ahd
));
2135 ahd_dump_card_state(ahd
);
2136 /* Restart the sequencer. */
2141 * Non-packetized unexpected or expected busfree.
2144 ahd_handle_nonpkt_busfree(struct ahd_softc
*ahd
)
2146 struct ahd_devinfo devinfo
;
2152 u_int initiator_role_id
;
2158 * Look at what phase we were last in. If its message out,
2159 * chances are pretty good that the busfree was in response
2160 * to one of our abort requests.
2162 lastphase
= ahd_inb(ahd
, LASTPHASE
);
2163 saved_scsiid
= ahd_inb(ahd
, SAVED_SCSIID
);
2164 saved_lun
= ahd_inb(ahd
, SAVED_LUN
);
2165 target
= SCSIID_TARGET(ahd
, saved_scsiid
);
2166 initiator_role_id
= SCSIID_OUR_ID(saved_scsiid
);
2167 ahd_compile_devinfo(&devinfo
, initiator_role_id
,
2168 target
, saved_lun
, 'A', ROLE_INITIATOR
);
2171 scbid
= ahd_get_scbptr(ahd
);
2172 scb
= ahd_lookup_scb(ahd
, scbid
);
2174 && (ahd_inb(ahd
, SEQ_FLAGS
) & NOT_IDENTIFIED
) != 0)
2177 ppr_busfree
= (ahd
->msg_flags
& MSG_FLAG_EXPECT_PPR_BUSFREE
) != 0;
2178 if (lastphase
== P_MESGOUT
) {
2181 tag
= SCB_LIST_NULL
;
2182 if (ahd_sent_msg(ahd
, AHDMSG_1B
, MSG_ABORT_TAG
, TRUE
)
2183 || ahd_sent_msg(ahd
, AHDMSG_1B
, MSG_ABORT
, TRUE
)) {
2188 ahd_print_devinfo(ahd
, &devinfo
);
2189 printf("Abort for unidentified "
2190 "connection completed.\n");
2191 /* restart the sequencer. */
2194 sent_msg
= ahd
->msgout_buf
[ahd
->msgout_index
- 1];
2195 ahd_print_path(ahd
, scb
);
2196 printf("SCB %d - Abort%s Completed.\n",
2198 sent_msg
== MSG_ABORT_TAG
? "" : " Tag");
2200 if (sent_msg
== MSG_ABORT_TAG
)
2201 tag
= SCB_GET_TAG(scb
);
2203 found
= ahd_abort_scbs(ahd
, target
, 'A', saved_lun
,
2204 tag
, ROLE_INITIATOR
,
2206 printf("found == 0x%x\n", found
);
2208 } else if (ahd_sent_msg(ahd
, AHDMSG_1B
,
2209 MSG_BUS_DEV_RESET
, TRUE
)) {
2212 * Don't mark the user's request for this BDR
2213 * as completing with CAM_BDR_SENT. CAM3
2214 * specifies CAM_REQ_CMP.
2217 && scb
->io_ctx
->ccb_h
.func_code
== XPT_RESET_DEV
2218 && ahd_match_scb(ahd
, scb
, target
, 'A',
2219 CAM_LUN_WILDCARD
, SCB_LIST_NULL
,
2221 ahd_set_transaction_status(scb
, CAM_REQ_CMP
);
2223 ahd_handle_devreset(ahd
, &devinfo
, CAM_LUN_WILDCARD
,
2224 CAM_BDR_SENT
, "Bus Device Reset",
2225 /*verbose_level*/0);
2227 } else if (ahd_sent_msg(ahd
, AHDMSG_EXT
, MSG_EXT_PPR
, FALSE
)
2228 && ppr_busfree
== 0) {
2229 struct ahd_initiator_tinfo
*tinfo
;
2230 struct ahd_tmode_tstate
*tstate
;
2235 * If the previous negotiation was packetized,
2236 * this could be because the device has been
2237 * reset without our knowledge. Force our
2238 * current negotiation to async and retry the
2239 * negotiation. Otherwise retry the command
2240 * with non-ppr negotiation.
2243 if ((ahd_debug
& AHD_SHOW_MESSAGES
) != 0)
2244 printf("PPR negotiation rejected busfree.\n");
2246 tinfo
= ahd_fetch_transinfo(ahd
, devinfo
.channel
,
2248 devinfo
.target
, &tstate
);
2249 if ((tinfo
->curr
.ppr_options
& MSG_EXT_PPR_IU_REQ
)!=0) {
2250 ahd_set_width(ahd
, &devinfo
,
2251 MSG_EXT_WDTR_BUS_8_BIT
,
2254 ahd_set_syncrate(ahd
, &devinfo
,
2255 /*period*/0, /*offset*/0,
2260 * The expect PPR busfree handler below
2261 * will effect the retry and necessary
2265 tinfo
->curr
.transport_version
= 2;
2266 tinfo
->goal
.transport_version
= 2;
2267 tinfo
->goal
.ppr_options
= 0;
2269 * Remove any SCBs in the waiting for selection
2270 * queue that may also be for this target so
2271 * that command ordering is preserved.
2273 ahd_freeze_devq(ahd
, scb
);
2274 ahd_qinfifo_requeue_tail(ahd
, scb
);
2277 } else if (ahd_sent_msg(ahd
, AHDMSG_EXT
, MSG_EXT_WDTR
, FALSE
)
2278 && ppr_busfree
== 0) {
2280 * Negotiation Rejected. Go-narrow and
2284 if ((ahd_debug
& AHD_SHOW_MESSAGES
) != 0)
2285 printf("WDTR negotiation rejected busfree.\n");
2287 ahd_set_width(ahd
, &devinfo
,
2288 MSG_EXT_WDTR_BUS_8_BIT
,
2289 AHD_TRANS_CUR
|AHD_TRANS_GOAL
,
2292 * Remove any SCBs in the waiting for selection
2293 * queue that may also be for this target so that
2294 * command ordering is preserved.
2296 ahd_freeze_devq(ahd
, scb
);
2297 ahd_qinfifo_requeue_tail(ahd
, scb
);
2299 } else if (ahd_sent_msg(ahd
, AHDMSG_EXT
, MSG_EXT_SDTR
, FALSE
)
2300 && ppr_busfree
== 0) {
2302 * Negotiation Rejected. Go-async and
2306 if ((ahd_debug
& AHD_SHOW_MESSAGES
) != 0)
2307 printf("SDTR negotiation rejected busfree.\n");
2309 ahd_set_syncrate(ahd
, &devinfo
,
2310 /*period*/0, /*offset*/0,
2312 AHD_TRANS_CUR
|AHD_TRANS_GOAL
,
2315 * Remove any SCBs in the waiting for selection
2316 * queue that may also be for this target so that
2317 * command ordering is preserved.
2319 ahd_freeze_devq(ahd
, scb
);
2320 ahd_qinfifo_requeue_tail(ahd
, scb
);
2322 } else if ((ahd
->msg_flags
& MSG_FLAG_EXPECT_IDE_BUSFREE
) != 0
2323 && ahd_sent_msg(ahd
, AHDMSG_1B
,
2324 MSG_INITIATOR_DET_ERR
, TRUE
)) {
2327 if ((ahd_debug
& AHD_SHOW_MESSAGES
) != 0)
2328 printf("Expected IDE Busfree\n");
2331 } else if ((ahd
->msg_flags
& MSG_FLAG_EXPECT_QASREJ_BUSFREE
)
2332 && ahd_sent_msg(ahd
, AHDMSG_1B
,
2333 MSG_MESSAGE_REJECT
, TRUE
)) {
2336 if ((ahd_debug
& AHD_SHOW_MESSAGES
) != 0)
2337 printf("Expected QAS Reject Busfree\n");
2344 * The busfree required flag is honored at the end of
2345 * the message phases. We check it last in case we
2346 * had to send some other message that caused a busfree.
2349 && (lastphase
== P_MESGIN
|| lastphase
== P_MESGOUT
)
2350 && ((ahd
->msg_flags
& MSG_FLAG_EXPECT_PPR_BUSFREE
) != 0)) {
2352 ahd_freeze_devq(ahd
, scb
);
2353 ahd_set_transaction_status(scb
, CAM_REQUEUE_REQ
);
2354 ahd_freeze_scb(scb
);
2355 if ((ahd
->msg_flags
& MSG_FLAG_IU_REQ_CHANGED
) != 0) {
2356 ahd_abort_scbs(ahd
, SCB_GET_TARGET(ahd
, scb
),
2357 SCB_GET_CHANNEL(ahd
, scb
),
2358 SCB_GET_LUN(scb
), SCB_LIST_NULL
,
2359 ROLE_INITIATOR
, CAM_REQ_ABORTED
);
2362 if ((ahd_debug
& AHD_SHOW_MESSAGES
) != 0)
2363 printf("PPR Negotiation Busfree.\n");
2369 if (printerror
!= 0) {
2376 if ((scb
->hscb
->control
& TAG_ENB
) != 0)
2377 tag
= SCB_GET_TAG(scb
);
2379 tag
= SCB_LIST_NULL
;
2380 ahd_print_path(ahd
, scb
);
2381 aborted
= ahd_abort_scbs(ahd
, target
, 'A',
2382 SCB_GET_LUN(scb
), tag
,
2387 * We had not fully identified this connection,
2388 * so we cannot abort anything.
2390 printf("%s: ", ahd_name(ahd
));
2392 printf("Unexpected busfree %s, %d SCBs aborted, "
2393 "PRGMCNT == 0x%x\n",
2394 ahd_lookup_phase_entry(lastphase
)->phasemsg
,
2396 ahd_inw(ahd
, PRGMCNT
));
2397 ahd_dump_card_state(ahd
);
2398 if (lastphase
!= P_BUSFREE
)
2399 ahd_force_renegotiation(ahd
, &devinfo
);
2401 /* Always restart the sequencer. */
2406 ahd_handle_proto_violation(struct ahd_softc
*ahd
)
2408 struct ahd_devinfo devinfo
;
2416 ahd_fetch_devinfo(ahd
, &devinfo
);
2417 scbid
= ahd_get_scbptr(ahd
);
2418 scb
= ahd_lookup_scb(ahd
, scbid
);
2419 seq_flags
= ahd_inb(ahd
, SEQ_FLAGS
);
2420 curphase
= ahd_inb(ahd
, SCSISIGI
) & PHASE_MASK
;
2421 lastphase
= ahd_inb(ahd
, LASTPHASE
);
2422 if ((seq_flags
& NOT_IDENTIFIED
) != 0) {
2425 * The reconnecting target either did not send an
2426 * identify message, or did, but we didn't find an SCB
2429 ahd_print_devinfo(ahd
, &devinfo
);
2430 printf("Target did not send an IDENTIFY message. "
2431 "LASTPHASE = 0x%x.\n", lastphase
);
2433 } else if (scb
== NULL
) {
2435 * We don't seem to have an SCB active for this
2436 * transaction. Print an error and reset the bus.
2438 ahd_print_devinfo(ahd
, &devinfo
);
2439 printf("No SCB found during protocol violation\n");
2440 goto proto_violation_reset
;
2442 ahd_set_transaction_status(scb
, CAM_SEQUENCE_FAIL
);
2443 if ((seq_flags
& NO_CDB_SENT
) != 0) {
2444 ahd_print_path(ahd
, scb
);
2445 printf("No or incomplete CDB sent to device.\n");
2446 } else if ((ahd_inb_scbram(ahd
, SCB_CONTROL
)
2447 & STATUS_RCVD
) == 0) {
2449 * The target never bothered to provide status to
2450 * us prior to completing the command. Since we don't
2451 * know the disposition of this command, we must attempt
2452 * to abort it. Assert ATN and prepare to send an abort
2455 ahd_print_path(ahd
, scb
);
2456 printf("Completed command without status.\n");
2458 ahd_print_path(ahd
, scb
);
2459 printf("Unknown protocol violation.\n");
2460 ahd_dump_card_state(ahd
);
2463 if ((lastphase
& ~P_DATAIN_DT
) == 0
2464 || lastphase
== P_COMMAND
) {
2465 proto_violation_reset
:
2467 * Target either went directly to data
2468 * phase or didn't respond to our ATN.
2469 * The only safe thing to do is to blow
2470 * it away with a bus reset.
2472 found
= ahd_reset_channel(ahd
, 'A', TRUE
);
2473 printf("%s: Issued Channel %c Bus Reset. "
2474 "%d SCBs aborted\n", ahd_name(ahd
), 'A', found
);
2477 * Leave the selection hardware off in case
2478 * this abort attempt will affect yet to
2481 ahd_outb(ahd
, SCSISEQ0
,
2482 ahd_inb(ahd
, SCSISEQ0
) & ~ENSELO
);
2483 ahd_assert_atn(ahd
);
2484 ahd_outb(ahd
, MSG_OUT
, HOST_MSG
);
2486 ahd_print_devinfo(ahd
, &devinfo
);
2487 ahd
->msgout_buf
[0] = MSG_ABORT_TASK
;
2488 ahd
->msgout_len
= 1;
2489 ahd
->msgout_index
= 0;
2490 ahd
->msg_type
= MSG_TYPE_INITIATOR_MSGOUT
;
2492 ahd_print_path(ahd
, scb
);
2493 scb
->flags
|= SCB_ABORT
;
2495 printf("Protocol violation %s. Attempting to abort.\n",
2496 ahd_lookup_phase_entry(curphase
)->phasemsg
);
2501 * Force renegotiation to occur the next time we initiate
2502 * a command to the current device.
2505 ahd_force_renegotiation(struct ahd_softc
*ahd
, struct ahd_devinfo
*devinfo
)
2507 struct ahd_initiator_tinfo
*targ_info
;
2508 struct ahd_tmode_tstate
*tstate
;
2511 if ((ahd_debug
& AHD_SHOW_MESSAGES
) != 0) {
2512 ahd_print_devinfo(ahd
, devinfo
);
2513 printf("Forcing renegotiation\n");
2516 targ_info
= ahd_fetch_transinfo(ahd
,
2518 devinfo
->our_scsiid
,
2521 ahd_update_neg_request(ahd
, devinfo
, tstate
,
2522 targ_info
, AHD_NEG_IF_NON_ASYNC
);
2525 #define AHD_MAX_STEPS 2000
2527 ahd_clear_critical_section(struct ahd_softc
*ahd
)
2529 ahd_mode_state saved_modes
;
2541 if (ahd
->num_critical_sections
== 0)
2554 saved_modes
= ahd_save_modes(ahd
);
2560 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
2561 seqaddr
= ahd_inw(ahd
, CURADDR
);
2563 cs
= ahd
->critical_sections
;
2564 for (i
= 0; i
< ahd
->num_critical_sections
; i
++, cs
++) {
2566 if (cs
->begin
< seqaddr
&& cs
->end
>= seqaddr
)
2570 if (i
== ahd
->num_critical_sections
)
2573 if (steps
> AHD_MAX_STEPS
) {
2574 printf("%s: Infinite loop in critical section\n"
2575 "%s: First Instruction 0x%x now 0x%x\n",
2576 ahd_name(ahd
), ahd_name(ahd
), first_instr
,
2578 ahd_dump_card_state(ahd
);
2579 panic("critical section loop");
2584 if ((ahd_debug
& AHD_SHOW_MISC
) != 0)
2585 printf("%s: Single stepping at 0x%x\n", ahd_name(ahd
),
2588 if (stepping
== FALSE
) {
2590 first_instr
= seqaddr
;
2591 ahd_set_modes(ahd
, AHD_MODE_CFG
, AHD_MODE_CFG
);
2592 simode0
= ahd_inb(ahd
, SIMODE0
);
2593 simode3
= ahd_inb(ahd
, SIMODE3
);
2594 lqimode0
= ahd_inb(ahd
, LQIMODE0
);
2595 lqimode1
= ahd_inb(ahd
, LQIMODE1
);
2596 lqomode0
= ahd_inb(ahd
, LQOMODE0
);
2597 lqomode1
= ahd_inb(ahd
, LQOMODE1
);
2598 ahd_outb(ahd
, SIMODE0
, 0);
2599 ahd_outb(ahd
, SIMODE3
, 0);
2600 ahd_outb(ahd
, LQIMODE0
, 0);
2601 ahd_outb(ahd
, LQIMODE1
, 0);
2602 ahd_outb(ahd
, LQOMODE0
, 0);
2603 ahd_outb(ahd
, LQOMODE1
, 0);
2604 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
2605 simode1
= ahd_inb(ahd
, SIMODE1
);
2607 * We don't clear ENBUSFREE. Unfortunately
2608 * we cannot re-enable busfree detection within
2609 * the current connection, so we must leave it
2610 * on while single stepping.
2612 ahd_outb(ahd
, SIMODE1
, simode1
& ENBUSFREE
);
2613 ahd_outb(ahd
, SEQCTL0
, ahd_inb(ahd
, SEQCTL0
) | STEP
);
2616 ahd_outb(ahd
, CLRSINT1
, CLRBUSFREE
);
2617 ahd_outb(ahd
, CLRINT
, CLRSCSIINT
);
2618 ahd_set_modes(ahd
, ahd
->saved_src_mode
, ahd
->saved_dst_mode
);
2619 ahd_outb(ahd
, HCNTRL
, ahd
->unpause
);
2620 while (!ahd_is_paused(ahd
))
2622 ahd_update_modes(ahd
);
2625 ahd_set_modes(ahd
, AHD_MODE_CFG
, AHD_MODE_CFG
);
2626 ahd_outb(ahd
, SIMODE0
, simode0
);
2627 ahd_outb(ahd
, SIMODE3
, simode3
);
2628 ahd_outb(ahd
, LQIMODE0
, lqimode0
);
2629 ahd_outb(ahd
, LQIMODE1
, lqimode1
);
2630 ahd_outb(ahd
, LQOMODE0
, lqomode0
);
2631 ahd_outb(ahd
, LQOMODE1
, lqomode1
);
2632 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
2633 ahd_outb(ahd
, SEQCTL0
, ahd_inb(ahd
, SEQCTL0
) & ~STEP
);
2634 ahd_outb(ahd
, SIMODE1
, simode1
);
2636 * SCSIINT seems to glitch occassionally when
2637 * the interrupt masks are restored. Clear SCSIINT
2638 * one more time so that only persistent errors
2639 * are seen as a real interrupt.
2641 ahd_outb(ahd
, CLRINT
, CLRSCSIINT
);
2643 ahd_restore_modes(ahd
, saved_modes
);
2647 * Clear any pending interrupt status.
2650 ahd_clear_intstat(struct ahd_softc
*ahd
)
2652 AHD_ASSERT_MODES(ahd
, ~(AHD_MODE_UNKNOWN_MSK
|AHD_MODE_CFG_MSK
),
2653 ~(AHD_MODE_UNKNOWN_MSK
|AHD_MODE_CFG_MSK
));
2654 /* Clear any interrupt conditions this may have caused */
2655 ahd_outb(ahd
, CLRLQIINT0
, CLRLQIATNQAS
|CLRLQICRCT1
|CLRLQICRCT2
2656 |CLRLQIBADLQT
|CLRLQIATNLQ
|CLRLQIATNCMD
);
2657 ahd_outb(ahd
, CLRLQIINT1
, CLRLQIPHASE_LQ
|CLRLQIPHASE_NLQ
|CLRLIQABORT
2658 |CLRLQICRCI_LQ
|CLRLQICRCI_NLQ
|CLRLQIBADLQI
2659 |CLRLQIOVERI_LQ
|CLRLQIOVERI_NLQ
|CLRNONPACKREQ
);
2660 ahd_outb(ahd
, CLRLQOINT0
, CLRLQOTARGSCBPERR
|CLRLQOSTOPT2
|CLRLQOATNLQ
2661 |CLRLQOATNPKT
|CLRLQOTCRC
);
2662 ahd_outb(ahd
, CLRLQOINT1
, CLRLQOINITSCBPERR
|CLRLQOSTOPI2
|CLRLQOBADQAS
2663 |CLRLQOBUSFREE
|CLRLQOPHACHGINPKT
);
2664 if ((ahd
->bugs
& AHD_CLRLQO_AUTOCLR_BUG
) != 0) {
2665 ahd_outb(ahd
, CLRLQOINT0
, 0);
2666 ahd_outb(ahd
, CLRLQOINT1
, 0);
2668 ahd_outb(ahd
, CLRSINT3
, CLRNTRAMPERR
|CLROSRAMPERR
);
2669 ahd_outb(ahd
, CLRSINT1
, CLRSELTIMEO
|CLRATNO
|CLRSCSIRSTI
2670 |CLRBUSFREE
|CLRSCSIPERR
|CLRREQINIT
);
2671 ahd_outb(ahd
, CLRSINT0
, CLRSELDO
|CLRSELDI
|CLRSELINGO
2672 |CLRIOERR
|CLROVERRUN
);
2673 ahd_outb(ahd
, CLRINT
, CLRSCSIINT
);
2676 /**************************** Debugging Routines ******************************/
2678 uint32_t ahd_debug
= AHD_DEBUG_OPTS
;
2681 ahd_print_scb(struct scb
*scb
)
2683 struct hardware_scb
*hscb
;
2687 printf("scb:%p control:0x%x scsiid:0x%x lun:%d cdb_len:%d\n",
2693 printf("Shared Data: ");
2694 for (i
= 0; i
< sizeof(hscb
->shared_data
.idata
.cdb
); i
++)
2695 printf("%#02x", hscb
->shared_data
.idata
.cdb
[i
]);
2696 printf(" dataptr:%#x%x datacnt:%#x sgptr:%#x tag:%#x\n",
2697 (uint32_t)((ahd_le64toh(hscb
->dataptr
) >> 32) & 0xFFFFFFFF),
2698 (uint32_t)(ahd_le64toh(hscb
->dataptr
) & 0xFFFFFFFF),
2699 ahd_le32toh(hscb
->datacnt
),
2700 ahd_le32toh(hscb
->sgptr
),
2702 ahd_dump_sglist(scb
);
2706 ahd_dump_sglist(struct scb
*scb
)
2710 if (scb
->sg_count
> 0) {
2711 if ((scb
->ahd_softc
->flags
& AHD_64BIT_ADDRESSING
) != 0) {
2712 struct ahd_dma64_seg
*sg_list
;
2714 sg_list
= (struct ahd_dma64_seg
*)scb
->sg_list
;
2715 for (i
= 0; i
< scb
->sg_count
; i
++) {
2719 addr
= ahd_le64toh(sg_list
[i
].addr
);
2720 len
= ahd_le32toh(sg_list
[i
].len
);
2721 printf("sg[%d] - Addr 0x%x%x : Length %d%s\n",
2723 (uint32_t)((addr
>> 32) & 0xFFFFFFFF),
2724 (uint32_t)(addr
& 0xFFFFFFFF),
2725 sg_list
[i
].len
& AHD_SG_LEN_MASK
,
2726 (sg_list
[i
].len
& AHD_DMA_LAST_SEG
)
2730 struct ahd_dma_seg
*sg_list
;
2732 sg_list
= (struct ahd_dma_seg
*)scb
->sg_list
;
2733 for (i
= 0; i
< scb
->sg_count
; i
++) {
2736 len
= ahd_le32toh(sg_list
[i
].len
);
2737 printf("sg[%d] - Addr 0x%x%x : Length %d%s\n",
2739 (len
& AHD_SG_HIGH_ADDR_MASK
) >> 24,
2740 ahd_le32toh(sg_list
[i
].addr
),
2741 len
& AHD_SG_LEN_MASK
,
2742 len
& AHD_DMA_LAST_SEG
? " Last" : "");
2748 /************************* Transfer Negotiation *******************************/
2750 * Allocate per target mode instance (ID we respond to as a target)
2751 * transfer negotiation data structures.
2753 static struct ahd_tmode_tstate
*
2754 ahd_alloc_tstate(struct ahd_softc
*ahd
, u_int scsi_id
, char channel
)
2756 struct ahd_tmode_tstate
*master_tstate
;
2757 struct ahd_tmode_tstate
*tstate
;
2760 master_tstate
= ahd
->enabled_targets
[ahd
->our_id
];
2761 if (ahd
->enabled_targets
[scsi_id
] != NULL
2762 && ahd
->enabled_targets
[scsi_id
] != master_tstate
)
2763 panic("%s: ahd_alloc_tstate - Target already allocated",
2765 tstate
= malloc(sizeof(*tstate
), M_DEVBUF
, M_NOWAIT
);
2770 * If we have allocated a master tstate, copy user settings from
2771 * the master tstate (taken from SRAM or the EEPROM) for this
2772 * channel, but reset our current and goal settings to async/narrow
2773 * until an initiator talks to us.
2775 if (master_tstate
!= NULL
) {
2776 memcpy(tstate
, master_tstate
, sizeof(*tstate
));
2777 memset(tstate
->enabled_luns
, 0, sizeof(tstate
->enabled_luns
));
2778 for (i
= 0; i
< 16; i
++) {
2779 memset(&tstate
->transinfo
[i
].curr
, 0,
2780 sizeof(tstate
->transinfo
[i
].curr
));
2781 memset(&tstate
->transinfo
[i
].goal
, 0,
2782 sizeof(tstate
->transinfo
[i
].goal
));
2785 memset(tstate
, 0, sizeof(*tstate
));
2786 ahd
->enabled_targets
[scsi_id
] = tstate
;
2790 #ifdef AHD_TARGET_MODE
2792 * Free per target mode instance (ID we respond to as a target)
2793 * transfer negotiation data structures.
2796 ahd_free_tstate(struct ahd_softc
*ahd
, u_int scsi_id
, char channel
, int force
)
2798 struct ahd_tmode_tstate
*tstate
;
2801 * Don't clean up our "master" tstate.
2802 * It has our default user settings.
2804 if (scsi_id
== ahd
->our_id
2808 tstate
= ahd
->enabled_targets
[scsi_id
];
2810 free(tstate
, M_DEVBUF
);
2811 ahd
->enabled_targets
[scsi_id
] = NULL
;
2816 * Called when we have an active connection to a target on the bus,
2817 * this function finds the nearest period to the input period limited
2818 * by the capabilities of the bus connectivity of and sync settings for
2822 ahd_devlimited_syncrate(struct ahd_softc
*ahd
,
2823 struct ahd_initiator_tinfo
*tinfo
,
2824 u_int
*period
, u_int
*ppr_options
, role_t role
)
2826 struct ahd_transinfo
*transinfo
;
2829 if ((ahd_inb(ahd
, SBLKCTL
) & ENAB40
) != 0
2830 && (ahd_inb(ahd
, SSTAT2
) & EXP_ACTIVE
) == 0) {
2831 maxsync
= AHD_SYNCRATE_PACED
;
2833 maxsync
= AHD_SYNCRATE_ULTRA
;
2834 /* Can't do DT related options on an SE bus */
2835 *ppr_options
&= MSG_EXT_PPR_QAS_REQ
;
2838 * Never allow a value higher than our current goal
2839 * period otherwise we may allow a target initiated
2840 * negotiation to go above the limit as set by the
2841 * user. In the case of an initiator initiated
2842 * sync negotiation, we limit based on the user
2843 * setting. This allows the system to still accept
2844 * incoming negotiations even if target initiated
2845 * negotiation is not performed.
2847 if (role
== ROLE_TARGET
)
2848 transinfo
= &tinfo
->user
;
2850 transinfo
= &tinfo
->goal
;
2851 *ppr_options
&= (transinfo
->ppr_options
|MSG_EXT_PPR_PCOMP_EN
);
2852 if (transinfo
->width
== MSG_EXT_WDTR_BUS_8_BIT
) {
2853 maxsync
= MAX(maxsync
, AHD_SYNCRATE_ULTRA2
);
2854 *ppr_options
&= ~MSG_EXT_PPR_DT_REQ
;
2856 if (transinfo
->period
== 0) {
2860 *period
= MAX(*period
, transinfo
->period
);
2861 ahd_find_syncrate(ahd
, period
, ppr_options
, maxsync
);
2866 * Look up the valid period to SCSIRATE conversion in our table.
2867 * Return the period and offset that should be sent to the target
2868 * if this was the beginning of an SDTR.
2871 ahd_find_syncrate(struct ahd_softc
*ahd
, u_int
*period
,
2872 u_int
*ppr_options
, u_int maxsync
)
2874 if (*period
< maxsync
)
2877 if ((*ppr_options
& MSG_EXT_PPR_DT_REQ
) != 0
2878 && *period
> AHD_SYNCRATE_MIN_DT
)
2879 *ppr_options
&= ~MSG_EXT_PPR_DT_REQ
;
2881 if (*period
> AHD_SYNCRATE_MIN
)
2884 /* Honor PPR option conformance rules. */
2885 if (*period
> AHD_SYNCRATE_PACED
)
2886 *ppr_options
&= ~MSG_EXT_PPR_RTI
;
2888 if ((*ppr_options
& MSG_EXT_PPR_IU_REQ
) == 0)
2889 *ppr_options
&= (MSG_EXT_PPR_DT_REQ
|MSG_EXT_PPR_QAS_REQ
);
2891 if ((*ppr_options
& MSG_EXT_PPR_DT_REQ
) == 0)
2892 *ppr_options
&= MSG_EXT_PPR_QAS_REQ
;
2894 /* Skip all PACED only entries if IU is not available */
2895 if ((*ppr_options
& MSG_EXT_PPR_IU_REQ
) == 0
2896 && *period
< AHD_SYNCRATE_DT
)
2897 *period
= AHD_SYNCRATE_DT
;
2899 /* Skip all DT only entries if DT is not available */
2900 if ((*ppr_options
& MSG_EXT_PPR_DT_REQ
) == 0
2901 && *period
< AHD_SYNCRATE_ULTRA2
)
2902 *period
= AHD_SYNCRATE_ULTRA2
;
2906 * Truncate the given synchronous offset to a value the
2907 * current adapter type and syncrate are capable of.
2910 ahd_validate_offset(struct ahd_softc
*ahd
,
2911 struct ahd_initiator_tinfo
*tinfo
,
2912 u_int period
, u_int
*offset
, int wide
,
2917 /* Limit offset to what we can do */
2920 else if (period
<= AHD_SYNCRATE_PACED
) {
2921 if ((ahd
->bugs
& AHD_PACED_NEGTABLE_BUG
) != 0)
2922 maxoffset
= MAX_OFFSET_PACED_BUG
;
2924 maxoffset
= MAX_OFFSET_PACED
;
2926 maxoffset
= MAX_OFFSET_NON_PACED
;
2927 *offset
= MIN(*offset
, maxoffset
);
2928 if (tinfo
!= NULL
) {
2929 if (role
== ROLE_TARGET
)
2930 *offset
= MIN(*offset
, tinfo
->user
.offset
);
2932 *offset
= MIN(*offset
, tinfo
->goal
.offset
);
2937 * Truncate the given transfer width parameter to a value the
2938 * current adapter type is capable of.
2941 ahd_validate_width(struct ahd_softc
*ahd
, struct ahd_initiator_tinfo
*tinfo
,
2942 u_int
*bus_width
, role_t role
)
2944 switch (*bus_width
) {
2946 if (ahd
->features
& AHD_WIDE
) {
2948 *bus_width
= MSG_EXT_WDTR_BUS_16_BIT
;
2952 case MSG_EXT_WDTR_BUS_8_BIT
:
2953 *bus_width
= MSG_EXT_WDTR_BUS_8_BIT
;
2956 if (tinfo
!= NULL
) {
2957 if (role
== ROLE_TARGET
)
2958 *bus_width
= MIN(tinfo
->user
.width
, *bus_width
);
2960 *bus_width
= MIN(tinfo
->goal
.width
, *bus_width
);
2965 * Update the bitmask of targets for which the controller should
2966 * negotiate with at the next convenient oportunity. This currently
2967 * means the next time we send the initial identify messages for
2968 * a new transaction.
2971 ahd_update_neg_request(struct ahd_softc
*ahd
, struct ahd_devinfo
*devinfo
,
2972 struct ahd_tmode_tstate
*tstate
,
2973 struct ahd_initiator_tinfo
*tinfo
, ahd_neg_type neg_type
)
2975 u_int auto_negotiate_orig
;
2977 auto_negotiate_orig
= tstate
->auto_negotiate
;
2978 if (neg_type
== AHD_NEG_ALWAYS
) {
2980 * Force our "current" settings to be
2981 * unknown so that unless a bus reset
2982 * occurs the need to renegotiate is
2983 * recorded persistently.
2985 if ((ahd
->features
& AHD_WIDE
) != 0)
2986 tinfo
->curr
.width
= AHD_WIDTH_UNKNOWN
;
2987 tinfo
->curr
.period
= AHD_PERIOD_UNKNOWN
;
2988 tinfo
->curr
.offset
= AHD_OFFSET_UNKNOWN
;
2990 if (tinfo
->curr
.period
!= tinfo
->goal
.period
2991 || tinfo
->curr
.width
!= tinfo
->goal
.width
2992 || tinfo
->curr
.offset
!= tinfo
->goal
.offset
2993 || tinfo
->curr
.ppr_options
!= tinfo
->goal
.ppr_options
2994 || (neg_type
== AHD_NEG_IF_NON_ASYNC
2995 && (tinfo
->goal
.offset
!= 0
2996 || tinfo
->goal
.width
!= MSG_EXT_WDTR_BUS_8_BIT
2997 || tinfo
->goal
.ppr_options
!= 0)))
2998 tstate
->auto_negotiate
|= devinfo
->target_mask
;
3000 tstate
->auto_negotiate
&= ~devinfo
->target_mask
;
3002 return (auto_negotiate_orig
!= tstate
->auto_negotiate
);
3006 * Update the user/goal/curr tables of synchronous negotiation
3007 * parameters as well as, in the case of a current or active update,
3008 * any data structures on the host controller. In the case of an
3009 * active update, the specified target is currently talking to us on
3010 * the bus, so the transfer parameter update must take effect
3014 ahd_set_syncrate(struct ahd_softc
*ahd
, struct ahd_devinfo
*devinfo
,
3015 u_int period
, u_int offset
, u_int ppr_options
,
3016 u_int type
, int paused
)
3018 struct ahd_initiator_tinfo
*tinfo
;
3019 struct ahd_tmode_tstate
*tstate
;
3026 active
= (type
& AHD_TRANS_ACTIVE
) == AHD_TRANS_ACTIVE
;
3029 if (period
== 0 || offset
== 0) {
3034 tinfo
= ahd_fetch_transinfo(ahd
, devinfo
->channel
, devinfo
->our_scsiid
,
3035 devinfo
->target
, &tstate
);
3037 if ((type
& AHD_TRANS_USER
) != 0) {
3038 tinfo
->user
.period
= period
;
3039 tinfo
->user
.offset
= offset
;
3040 tinfo
->user
.ppr_options
= ppr_options
;
3043 if ((type
& AHD_TRANS_GOAL
) != 0) {
3044 tinfo
->goal
.period
= period
;
3045 tinfo
->goal
.offset
= offset
;
3046 tinfo
->goal
.ppr_options
= ppr_options
;
3049 old_period
= tinfo
->curr
.period
;
3050 old_offset
= tinfo
->curr
.offset
;
3051 old_ppr
= tinfo
->curr
.ppr_options
;
3053 if ((type
& AHD_TRANS_CUR
) != 0
3054 && (old_period
!= period
3055 || old_offset
!= offset
3056 || old_ppr
!= ppr_options
)) {
3060 tinfo
->curr
.period
= period
;
3061 tinfo
->curr
.offset
= offset
;
3062 tinfo
->curr
.ppr_options
= ppr_options
;
3064 ahd_send_async(ahd
, devinfo
->channel
, devinfo
->target
,
3065 CAM_LUN_WILDCARD
, AC_TRANSFER_NEG
, NULL
);
3070 printf("%s: target %d synchronous with "
3071 "period = 0x%x, offset = 0x%x",
3072 ahd_name(ahd
), devinfo
->target
,
3075 if ((ppr_options
& MSG_EXT_PPR_RD_STRM
) != 0) {
3079 if ((ppr_options
& MSG_EXT_PPR_DT_REQ
) != 0) {
3080 printf("%s", options
? "|DT" : "(DT");
3083 if ((ppr_options
& MSG_EXT_PPR_IU_REQ
) != 0) {
3084 printf("%s", options
? "|IU" : "(IU");
3087 if ((ppr_options
& MSG_EXT_PPR_RTI
) != 0) {
3088 printf("%s", options
? "|RTI" : "(RTI");
3091 if ((ppr_options
& MSG_EXT_PPR_QAS_REQ
) != 0) {
3092 printf("%s", options
? "|QAS" : "(QAS");
3100 printf("%s: target %d using "
3101 "asynchronous transfers%s\n",
3102 ahd_name(ahd
), devinfo
->target
,
3103 (ppr_options
& MSG_EXT_PPR_QAS_REQ
) != 0
3109 * Always refresh the neg-table to handle the case of the
3110 * sequencer setting the ENATNO bit for a MK_MESSAGE request.
3111 * We will always renegotiate in that case if this is a
3112 * packetized request. Also manage the busfree expected flag
3113 * from this common routine so that we catch changes due to
3114 * WDTR or SDTR messages.
3116 if ((type
& AHD_TRANS_CUR
) != 0) {
3119 ahd_update_neg_table(ahd
, devinfo
, &tinfo
->curr
);
3122 if (ahd
->msg_type
!= MSG_TYPE_NONE
) {
3123 if ((old_ppr
& MSG_EXT_PPR_IU_REQ
)
3124 != (ppr_options
& MSG_EXT_PPR_IU_REQ
)) {
3126 if ((ahd_debug
& AHD_SHOW_MESSAGES
) != 0) {
3127 ahd_print_devinfo(ahd
, devinfo
);
3128 printf("Expecting IU Change busfree\n");
3131 ahd
->msg_flags
|= MSG_FLAG_EXPECT_PPR_BUSFREE
3132 | MSG_FLAG_IU_REQ_CHANGED
;
3134 if ((old_ppr
& MSG_EXT_PPR_IU_REQ
) != 0) {
3136 if ((ahd_debug
& AHD_SHOW_MESSAGES
) != 0)
3137 printf("PPR with IU_REQ outstanding\n");
3139 ahd
->msg_flags
|= MSG_FLAG_EXPECT_PPR_BUSFREE
;
3144 update_needed
+= ahd_update_neg_request(ahd
, devinfo
, tstate
,
3145 tinfo
, AHD_NEG_TO_GOAL
);
3147 if (update_needed
&& active
)
3148 ahd_update_pending_scbs(ahd
);
3152 * Update the user/goal/curr tables of wide negotiation
3153 * parameters as well as, in the case of a current or active update,
3154 * any data structures on the host controller. In the case of an
3155 * active update, the specified target is currently talking to us on
3156 * the bus, so the transfer parameter update must take effect
3160 ahd_set_width(struct ahd_softc
*ahd
, struct ahd_devinfo
*devinfo
,
3161 u_int width
, u_int type
, int paused
)
3163 struct ahd_initiator_tinfo
*tinfo
;
3164 struct ahd_tmode_tstate
*tstate
;
3169 active
= (type
& AHD_TRANS_ACTIVE
) == AHD_TRANS_ACTIVE
;
3171 tinfo
= ahd_fetch_transinfo(ahd
, devinfo
->channel
, devinfo
->our_scsiid
,
3172 devinfo
->target
, &tstate
);
3174 if ((type
& AHD_TRANS_USER
) != 0)
3175 tinfo
->user
.width
= width
;
3177 if ((type
& AHD_TRANS_GOAL
) != 0)
3178 tinfo
->goal
.width
= width
;
3180 oldwidth
= tinfo
->curr
.width
;
3181 if ((type
& AHD_TRANS_CUR
) != 0 && oldwidth
!= width
) {
3185 tinfo
->curr
.width
= width
;
3186 ahd_send_async(ahd
, devinfo
->channel
, devinfo
->target
,
3187 CAM_LUN_WILDCARD
, AC_TRANSFER_NEG
, NULL
);
3189 printf("%s: target %d using %dbit transfers\n",
3190 ahd_name(ahd
), devinfo
->target
,
3191 8 * (0x01 << width
));
3195 if ((type
& AHD_TRANS_CUR
) != 0) {
3198 ahd_update_neg_table(ahd
, devinfo
, &tinfo
->curr
);
3203 update_needed
+= ahd_update_neg_request(ahd
, devinfo
, tstate
,
3204 tinfo
, AHD_NEG_TO_GOAL
);
3205 if (update_needed
&& active
)
3206 ahd_update_pending_scbs(ahd
);
3211 * Update the current state of tagged queuing for a given target.
3214 ahd_set_tags(struct ahd_softc
*ahd
, struct ahd_devinfo
*devinfo
,
3217 ahd_platform_set_tags(ahd
, devinfo
, alg
);
3218 ahd_send_async(ahd
, devinfo
->channel
, devinfo
->target
,
3219 devinfo
->lun
, AC_TRANSFER_NEG
, &alg
);
3223 ahd_update_neg_table(struct ahd_softc
*ahd
, struct ahd_devinfo
*devinfo
,
3224 struct ahd_transinfo
*tinfo
)
3226 ahd_mode_state saved_modes
;
3231 u_int saved_negoaddr
;
3232 uint8_t iocell_opts
[sizeof(ahd
->iocell_opts
)];
3234 saved_modes
= ahd_save_modes(ahd
);
3235 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
3237 saved_negoaddr
= ahd_inb(ahd
, NEGOADDR
);
3238 ahd_outb(ahd
, NEGOADDR
, devinfo
->target
);
3239 period
= tinfo
->period
;
3240 offset
= tinfo
->offset
;
3241 memcpy(iocell_opts
, ahd
->iocell_opts
, sizeof(ahd
->iocell_opts
));
3242 ppr_opts
= tinfo
->ppr_options
& (MSG_EXT_PPR_QAS_REQ
|MSG_EXT_PPR_DT_REQ
3243 |MSG_EXT_PPR_IU_REQ
|MSG_EXT_PPR_RTI
);
3246 period
= AHD_SYNCRATE_ASYNC
;
3247 if (period
== AHD_SYNCRATE_160
) {
3249 if ((ahd
->bugs
& AHD_PACED_NEGTABLE_BUG
) != 0) {
3251 * When the SPI4 spec was finalized, PACE transfers
3252 * was not made a configurable option in the PPR
3253 * message. Instead it is assumed to be enabled for
3254 * any syncrate faster than 80MHz. Nevertheless,
3255 * Harpoon2A4 allows this to be configurable.
3257 * Harpoon2A4 also assumes at most 2 data bytes per
3258 * negotiated REQ/ACK offset. Paced transfers take
3259 * 4, so we must adjust our offset.
3261 ppr_opts
|= PPROPT_PACE
;
3265 * Harpoon2A assumed that there would be a
3266 * fallback rate between 160MHz and 80Mhz,
3267 * so 7 is used as the period factor rather
3268 * than 8 for 160MHz.
3270 period
= AHD_SYNCRATE_REVA_160
;
3272 if ((tinfo
->ppr_options
& MSG_EXT_PPR_PCOMP_EN
) == 0)
3273 iocell_opts
[AHD_PRECOMP_SLEW_INDEX
] &=
3277 * Precomp should be disabled for non-paced transfers.
3279 iocell_opts
[AHD_PRECOMP_SLEW_INDEX
] &= ~AHD_PRECOMP_MASK
;
3281 if ((ahd
->features
& AHD_NEW_IOCELL_OPTS
) != 0
3282 && (ppr_opts
& MSG_EXT_PPR_DT_REQ
) != 0
3283 && (ppr_opts
& MSG_EXT_PPR_IU_REQ
) == 0) {
3285 * Slow down our CRC interval to be
3286 * compatible with non-packetized
3287 * U160 devices that can't handle a
3288 * CRC at full speed.
3290 con_opts
|= ENSLOWCRC
;
3293 if ((ahd
->bugs
& AHD_PACED_NEGTABLE_BUG
) != 0) {
3295 * On H2A4, revert to a slower slewrate
3296 * on non-paced transfers.
3298 iocell_opts
[AHD_PRECOMP_SLEW_INDEX
] &=
3303 ahd_outb(ahd
, ANNEXCOL
, AHD_ANNEXCOL_PRECOMP_SLEW
);
3304 ahd_outb(ahd
, ANNEXDAT
, iocell_opts
[AHD_PRECOMP_SLEW_INDEX
]);
3305 ahd_outb(ahd
, ANNEXCOL
, AHD_ANNEXCOL_AMPLITUDE
);
3306 ahd_outb(ahd
, ANNEXDAT
, iocell_opts
[AHD_AMPLITUDE_INDEX
]);
3308 ahd_outb(ahd
, NEGPERIOD
, period
);
3309 ahd_outb(ahd
, NEGPPROPTS
, ppr_opts
);
3310 ahd_outb(ahd
, NEGOFFSET
, offset
);
3312 if (tinfo
->width
== MSG_EXT_WDTR_BUS_16_BIT
)
3313 con_opts
|= WIDEXFER
;
3316 * Slow down our CRC interval to be
3317 * compatible with packetized U320 devices
3318 * that can't handle a CRC at full speed
3320 if (ahd
->features
& AHD_AIC79XXB_SLOWCRC
) {
3321 con_opts
|= ENSLOWCRC
;
3325 * During packetized transfers, the target will
3326 * give us the oportunity to send command packets
3327 * without us asserting attention.
3329 if ((tinfo
->ppr_options
& MSG_EXT_PPR_IU_REQ
) == 0)
3330 con_opts
|= ENAUTOATNO
;
3331 ahd_outb(ahd
, NEGCONOPTS
, con_opts
);
3332 ahd_outb(ahd
, NEGOADDR
, saved_negoaddr
);
3333 ahd_restore_modes(ahd
, saved_modes
);
3337 * When the transfer settings for a connection change, setup for
3338 * negotiation in pending SCBs to effect the change as quickly as
3339 * possible. We also cancel any negotiations that are scheduled
3340 * for inflight SCBs that have not been started yet.
3343 ahd_update_pending_scbs(struct ahd_softc
*ahd
)
3345 struct scb
*pending_scb
;
3346 int pending_scb_count
;
3349 ahd_mode_state saved_modes
;
3352 * Traverse the pending SCB list and ensure that all of the
3353 * SCBs there have the proper settings. We can only safely
3354 * clear the negotiation required flag (setting requires the
3355 * execution queue to be modified) and this is only possible
3356 * if we are not already attempting to select out for this
3357 * SCB. For this reason, all callers only call this routine
3358 * if we are changing the negotiation settings for the currently
3359 * active transaction on the bus.
3361 pending_scb_count
= 0;
3362 LIST_FOREACH(pending_scb
, &ahd
->pending_scbs
, pending_links
) {
3363 struct ahd_devinfo devinfo
;
3364 struct ahd_initiator_tinfo
*tinfo
;
3365 struct ahd_tmode_tstate
*tstate
;
3367 ahd_scb_devinfo(ahd
, &devinfo
, pending_scb
);
3368 tinfo
= ahd_fetch_transinfo(ahd
, devinfo
.channel
,
3370 devinfo
.target
, &tstate
);
3371 if ((tstate
->auto_negotiate
& devinfo
.target_mask
) == 0
3372 && (pending_scb
->flags
& SCB_AUTO_NEGOTIATE
) != 0) {
3373 pending_scb
->flags
&= ~SCB_AUTO_NEGOTIATE
;
3374 pending_scb
->hscb
->control
&= ~MK_MESSAGE
;
3376 ahd_sync_scb(ahd
, pending_scb
,
3377 BUS_DMASYNC_PREREAD
|BUS_DMASYNC_PREWRITE
);
3378 pending_scb_count
++;
3381 if (pending_scb_count
== 0)
3384 if (ahd_is_paused(ahd
)) {
3392 * Force the sequencer to reinitialize the selection for
3393 * the command at the head of the execution queue if it
3394 * has already been setup. The negotiation changes may
3395 * effect whether we select-out with ATN. It is only
3396 * safe to clear ENSELO when the bus is not free and no
3397 * selection is in progres or completed.
3399 saved_modes
= ahd_save_modes(ahd
);
3400 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
3401 if ((ahd_inb(ahd
, SCSISIGI
) & BSYI
) != 0
3402 && (ahd_inb(ahd
, SSTAT0
) & (SELDO
|SELINGO
)) == 0)
3403 ahd_outb(ahd
, SCSISEQ0
, ahd_inb(ahd
, SCSISEQ0
) & ~ENSELO
);
3404 saved_scbptr
= ahd_get_scbptr(ahd
);
3405 /* Ensure that the hscbs down on the card match the new information */
3406 LIST_FOREACH(pending_scb
, &ahd
->pending_scbs
, pending_links
) {
3410 scb_tag
= SCB_GET_TAG(pending_scb
);
3411 ahd_set_scbptr(ahd
, scb_tag
);
3412 control
= ahd_inb_scbram(ahd
, SCB_CONTROL
);
3413 control
&= ~MK_MESSAGE
;
3414 control
|= pending_scb
->hscb
->control
& MK_MESSAGE
;
3415 ahd_outb(ahd
, SCB_CONTROL
, control
);
3417 ahd_set_scbptr(ahd
, saved_scbptr
);
3418 ahd_restore_modes(ahd
, saved_modes
);
3424 /**************************** Pathing Information *****************************/
3426 ahd_fetch_devinfo(struct ahd_softc
*ahd
, struct ahd_devinfo
*devinfo
)
3428 ahd_mode_state saved_modes
;
3433 saved_modes
= ahd_save_modes(ahd
);
3434 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
3436 if (ahd_inb(ahd
, SSTAT0
) & TARGET
)
3439 role
= ROLE_INITIATOR
;
3441 if (role
== ROLE_TARGET
3442 && (ahd_inb(ahd
, SEQ_FLAGS
) & CMDPHASE_PENDING
) != 0) {
3443 /* We were selected, so pull our id from TARGIDIN */
3444 our_id
= ahd_inb(ahd
, TARGIDIN
) & OID
;
3445 } else if (role
== ROLE_TARGET
)
3446 our_id
= ahd_inb(ahd
, TOWNID
);
3448 our_id
= ahd_inb(ahd
, IOWNID
);
3450 saved_scsiid
= ahd_inb(ahd
, SAVED_SCSIID
);
3451 ahd_compile_devinfo(devinfo
,
3453 SCSIID_TARGET(ahd
, saved_scsiid
),
3454 ahd_inb(ahd
, SAVED_LUN
),
3455 SCSIID_CHANNEL(ahd
, saved_scsiid
),
3457 ahd_restore_modes(ahd
, saved_modes
);
3461 ahd_print_devinfo(struct ahd_softc
*ahd
, struct ahd_devinfo
*devinfo
)
3463 printf("%s:%c:%d:%d: ", ahd_name(ahd
), 'A',
3464 devinfo
->target
, devinfo
->lun
);
3467 struct ahd_phase_table_entry
*
3468 ahd_lookup_phase_entry(int phase
)
3470 struct ahd_phase_table_entry
*entry
;
3471 struct ahd_phase_table_entry
*last_entry
;
3474 * num_phases doesn't include the default entry which
3475 * will be returned if the phase doesn't match.
3477 last_entry
= &ahd_phase_table
[num_phases
];
3478 for (entry
= ahd_phase_table
; entry
< last_entry
; entry
++) {
3479 if (phase
== entry
->phase
)
3486 ahd_compile_devinfo(struct ahd_devinfo
*devinfo
, u_int our_id
, u_int target
,
3487 u_int lun
, char channel
, role_t role
)
3489 devinfo
->our_scsiid
= our_id
;
3490 devinfo
->target
= target
;
3492 devinfo
->target_offset
= target
;
3493 devinfo
->channel
= channel
;
3494 devinfo
->role
= role
;
3496 devinfo
->target_offset
+= 8;
3497 devinfo
->target_mask
= (0x01 << devinfo
->target_offset
);
3501 ahd_scb_devinfo(struct ahd_softc
*ahd
, struct ahd_devinfo
*devinfo
,
3507 our_id
= SCSIID_OUR_ID(scb
->hscb
->scsiid
);
3508 role
= ROLE_INITIATOR
;
3509 if ((scb
->hscb
->control
& TARGET_SCB
) != 0)
3511 ahd_compile_devinfo(devinfo
, our_id
, SCB_GET_TARGET(ahd
, scb
),
3512 SCB_GET_LUN(scb
), SCB_GET_CHANNEL(ahd
, scb
), role
);
3516 /************************ Message Phase Processing ****************************/
3518 * When an initiator transaction with the MK_MESSAGE flag either reconnects
3519 * or enters the initial message out phase, we are interrupted. Fill our
3520 * outgoing message buffer with the appropriate message and beging handing
3521 * the message phase(s) manually.
3524 ahd_setup_initiator_msgout(struct ahd_softc
*ahd
, struct ahd_devinfo
*devinfo
,
3528 * To facilitate adding multiple messages together,
3529 * each routine should increment the index and len
3530 * variables instead of setting them explicitly.
3532 ahd
->msgout_index
= 0;
3533 ahd
->msgout_len
= 0;
3535 if (ahd_currently_packetized(ahd
))
3536 ahd
->msg_flags
|= MSG_FLAG_PACKETIZED
;
3538 if (ahd
->send_msg_perror
3539 && ahd_inb(ahd
, MSG_OUT
) == HOST_MSG
) {
3540 ahd
->msgout_buf
[ahd
->msgout_index
++] = ahd
->send_msg_perror
;
3542 ahd
->msg_type
= MSG_TYPE_INITIATOR_MSGOUT
;
3544 if ((ahd_debug
& AHD_SHOW_MESSAGES
) != 0)
3545 printf("Setting up for Parity Error delivery\n");
3548 } else if (scb
== NULL
) {
3549 printf("%s: WARNING. No pending message for "
3550 "I_T msgin. Issuing NO-OP\n", ahd_name(ahd
));
3551 ahd
->msgout_buf
[ahd
->msgout_index
++] = MSG_NOOP
;
3553 ahd
->msg_type
= MSG_TYPE_INITIATOR_MSGOUT
;
3557 if ((scb
->flags
& SCB_DEVICE_RESET
) == 0
3558 && (scb
->flags
& SCB_PACKETIZED
) == 0
3559 && ahd_inb(ahd
, MSG_OUT
) == MSG_IDENTIFYFLAG
) {
3562 identify_msg
= MSG_IDENTIFYFLAG
| SCB_GET_LUN(scb
);
3563 if ((scb
->hscb
->control
& DISCENB
) != 0)
3564 identify_msg
|= MSG_IDENTIFY_DISCFLAG
;
3565 ahd
->msgout_buf
[ahd
->msgout_index
++] = identify_msg
;
3568 if ((scb
->hscb
->control
& TAG_ENB
) != 0) {
3569 ahd
->msgout_buf
[ahd
->msgout_index
++] =
3570 scb
->hscb
->control
& (TAG_ENB
|SCB_TAG_TYPE
);
3571 ahd
->msgout_buf
[ahd
->msgout_index
++] = SCB_GET_TAG(scb
);
3572 ahd
->msgout_len
+= 2;
3576 if (scb
->flags
& SCB_DEVICE_RESET
) {
3577 ahd
->msgout_buf
[ahd
->msgout_index
++] = MSG_BUS_DEV_RESET
;
3579 ahd_print_path(ahd
, scb
);
3580 printf("Bus Device Reset Message Sent\n");
3582 * Clear our selection hardware in advance of
3583 * the busfree. We may have an entry in the waiting
3584 * Q for this target, and we don't want to go about
3585 * selecting while we handle the busfree and blow it
3588 ahd_outb(ahd
, SCSISEQ0
, 0);
3589 } else if ((scb
->flags
& SCB_ABORT
) != 0) {
3591 if ((scb
->hscb
->control
& TAG_ENB
) != 0) {
3592 ahd
->msgout_buf
[ahd
->msgout_index
++] = MSG_ABORT_TAG
;
3594 ahd
->msgout_buf
[ahd
->msgout_index
++] = MSG_ABORT
;
3597 ahd_print_path(ahd
, scb
);
3598 printf("Abort%s Message Sent\n",
3599 (scb
->hscb
->control
& TAG_ENB
) != 0 ? " Tag" : "");
3601 * Clear our selection hardware in advance of
3602 * the busfree. We may have an entry in the waiting
3603 * Q for this target, and we don't want to go about
3604 * selecting while we handle the busfree and blow it
3607 ahd_outb(ahd
, SCSISEQ0
, 0);
3608 } else if ((scb
->flags
& (SCB_AUTO_NEGOTIATE
|SCB_NEGOTIATE
)) != 0) {
3609 ahd_build_transfer_msg(ahd
, devinfo
);
3611 * Clear our selection hardware in advance of potential
3612 * PPR IU status change busfree. We may have an entry in
3613 * the waiting Q for this target, and we don't want to go
3614 * about selecting while we handle the busfree and blow
3617 ahd_outb(ahd
, SCSISEQ0
, 0);
3619 printf("ahd_intr: AWAITING_MSG for an SCB that "
3620 "does not have a waiting message\n");
3621 printf("SCSIID = %x, target_mask = %x\n", scb
->hscb
->scsiid
,
3622 devinfo
->target_mask
);
3623 panic("SCB = %d, SCB Control = %x:%x, MSG_OUT = %x "
3624 "SCB flags = %x", SCB_GET_TAG(scb
), scb
->hscb
->control
,
3625 ahd_inb_scbram(ahd
, SCB_CONTROL
), ahd_inb(ahd
, MSG_OUT
),
3630 * Clear the MK_MESSAGE flag from the SCB so we aren't
3631 * asked to send this message again.
3633 ahd_outb(ahd
, SCB_CONTROL
,
3634 ahd_inb_scbram(ahd
, SCB_CONTROL
) & ~MK_MESSAGE
);
3635 scb
->hscb
->control
&= ~MK_MESSAGE
;
3636 ahd
->msgout_index
= 0;
3637 ahd
->msg_type
= MSG_TYPE_INITIATOR_MSGOUT
;
3641 * Build an appropriate transfer negotiation message for the
3642 * currently active target.
3645 ahd_build_transfer_msg(struct ahd_softc
*ahd
, struct ahd_devinfo
*devinfo
)
3648 * We need to initiate transfer negotiations.
3649 * If our current and goal settings are identical,
3650 * we want to renegotiate due to a check condition.
3652 struct ahd_initiator_tinfo
*tinfo
;
3653 struct ahd_tmode_tstate
*tstate
;
3661 tinfo
= ahd_fetch_transinfo(ahd
, devinfo
->channel
, devinfo
->our_scsiid
,
3662 devinfo
->target
, &tstate
);
3664 * Filter our period based on the current connection.
3665 * If we can't perform DT transfers on this segment (not in LVD
3666 * mode for instance), then our decision to issue a PPR message
3669 period
= tinfo
->goal
.period
;
3670 offset
= tinfo
->goal
.offset
;
3671 ppr_options
= tinfo
->goal
.ppr_options
;
3672 /* Target initiated PPR is not allowed in the SCSI spec */
3673 if (devinfo
->role
== ROLE_TARGET
)
3675 ahd_devlimited_syncrate(ahd
, tinfo
, &period
,
3676 &ppr_options
, devinfo
->role
);
3677 dowide
= tinfo
->curr
.width
!= tinfo
->goal
.width
;
3678 dosync
= tinfo
->curr
.offset
!= offset
|| tinfo
->curr
.period
!= period
;
3680 * Only use PPR if we have options that need it, even if the device
3681 * claims to support it. There might be an expander in the way
3684 doppr
= ppr_options
!= 0;
3686 if (!dowide
&& !dosync
&& !doppr
) {
3687 dowide
= tinfo
->goal
.width
!= MSG_EXT_WDTR_BUS_8_BIT
;
3688 dosync
= tinfo
->goal
.offset
!= 0;
3691 if (!dowide
&& !dosync
&& !doppr
) {
3693 * Force async with a WDTR message if we have a wide bus,
3694 * or just issue an SDTR with a 0 offset.
3696 if ((ahd
->features
& AHD_WIDE
) != 0)
3702 ahd_print_devinfo(ahd
, devinfo
);
3703 printf("Ensuring async\n");
3706 /* Target initiated PPR is not allowed in the SCSI spec */
3707 if (devinfo
->role
== ROLE_TARGET
)
3711 * Both the PPR message and SDTR message require the
3712 * goal syncrate to be limited to what the target device
3713 * is capable of handling (based on whether an LVD->SE
3714 * expander is on the bus), so combine these two cases.
3715 * Regardless, guarantee that if we are using WDTR and SDTR
3716 * messages that WDTR comes first.
3718 if (doppr
|| (dosync
&& !dowide
)) {
3720 offset
= tinfo
->goal
.offset
;
3721 ahd_validate_offset(ahd
, tinfo
, period
, &offset
,
3722 doppr
? tinfo
->goal
.width
3723 : tinfo
->curr
.width
,
3726 ahd_construct_ppr(ahd
, devinfo
, period
, offset
,
3727 tinfo
->goal
.width
, ppr_options
);
3729 ahd_construct_sdtr(ahd
, devinfo
, period
, offset
);
3732 ahd_construct_wdtr(ahd
, devinfo
, tinfo
->goal
.width
);
3737 * Build a synchronous negotiation message in our message
3738 * buffer based on the input parameters.
3741 ahd_construct_sdtr(struct ahd_softc
*ahd
, struct ahd_devinfo
*devinfo
,
3742 u_int period
, u_int offset
)
3745 period
= AHD_ASYNC_XFER_PERIOD
;
3746 ahd
->msgout_index
+= spi_populate_sync_msg(
3747 ahd
->msgout_buf
+ ahd
->msgout_index
, period
, offset
);
3748 ahd
->msgout_len
+= 5;
3750 printf("(%s:%c:%d:%d): Sending SDTR period %x, offset %x\n",
3751 ahd_name(ahd
), devinfo
->channel
, devinfo
->target
,
3752 devinfo
->lun
, period
, offset
);
3757 * Build a wide negotiateion message in our message
3758 * buffer based on the input parameters.
3761 ahd_construct_wdtr(struct ahd_softc
*ahd
, struct ahd_devinfo
*devinfo
,
3764 ahd
->msgout_index
+= spi_populate_width_msg(
3765 ahd
->msgout_buf
+ ahd
->msgout_index
, bus_width
);
3766 ahd
->msgout_len
+= 4;
3768 printf("(%s:%c:%d:%d): Sending WDTR %x\n",
3769 ahd_name(ahd
), devinfo
->channel
, devinfo
->target
,
3770 devinfo
->lun
, bus_width
);
3775 * Build a parallel protocol request message in our message
3776 * buffer based on the input parameters.
3779 ahd_construct_ppr(struct ahd_softc
*ahd
, struct ahd_devinfo
*devinfo
,
3780 u_int period
, u_int offset
, u_int bus_width
,
3784 * Always request precompensation from
3785 * the other target if we are running
3786 * at paced syncrates.
3788 if (period
<= AHD_SYNCRATE_PACED
)
3789 ppr_options
|= MSG_EXT_PPR_PCOMP_EN
;
3791 period
= AHD_ASYNC_XFER_PERIOD
;
3792 ahd
->msgout_index
+= spi_populate_ppr_msg(
3793 ahd
->msgout_buf
+ ahd
->msgout_index
, period
, offset
,
3794 bus_width
, ppr_options
);
3795 ahd
->msgout_len
+= 8;
3797 printf("(%s:%c:%d:%d): Sending PPR bus_width %x, period %x, "
3798 "offset %x, ppr_options %x\n", ahd_name(ahd
),
3799 devinfo
->channel
, devinfo
->target
, devinfo
->lun
,
3800 bus_width
, period
, offset
, ppr_options
);
3805 * Clear any active message state.
3808 ahd_clear_msg_state(struct ahd_softc
*ahd
)
3810 ahd_mode_state saved_modes
;
3812 saved_modes
= ahd_save_modes(ahd
);
3813 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
3814 ahd
->send_msg_perror
= 0;
3815 ahd
->msg_flags
= MSG_FLAG_NONE
;
3816 ahd
->msgout_len
= 0;
3817 ahd
->msgin_index
= 0;
3818 ahd
->msg_type
= MSG_TYPE_NONE
;
3819 if ((ahd_inb(ahd
, SCSISIGO
) & ATNO
) != 0) {
3821 * The target didn't care to respond to our
3822 * message request, so clear ATN.
3824 ahd_outb(ahd
, CLRSINT1
, CLRATNO
);
3826 ahd_outb(ahd
, MSG_OUT
, MSG_NOOP
);
3827 ahd_outb(ahd
, SEQ_FLAGS2
,
3828 ahd_inb(ahd
, SEQ_FLAGS2
) & ~TARGET_MSG_PENDING
);
3829 ahd_restore_modes(ahd
, saved_modes
);
3833 * Manual message loop handler.
3836 ahd_handle_message_phase(struct ahd_softc
*ahd
)
3838 struct ahd_devinfo devinfo
;
3842 ahd_fetch_devinfo(ahd
, &devinfo
);
3843 end_session
= FALSE
;
3844 bus_phase
= ahd_inb(ahd
, LASTPHASE
);
3846 if ((ahd_inb(ahd
, LQISTAT2
) & LQIPHASE_OUTPKT
) != 0) {
3847 printf("LQIRETRY for LQIPHASE_OUTPKT\n");
3848 ahd_outb(ahd
, LQCTL2
, LQIRETRY
);
3851 switch (ahd
->msg_type
) {
3852 case MSG_TYPE_INITIATOR_MSGOUT
:
3858 if (ahd
->msgout_len
== 0 && ahd
->send_msg_perror
== 0)
3859 panic("HOST_MSG_LOOP interrupt with no active message");
3862 if ((ahd_debug
& AHD_SHOW_MESSAGES
) != 0) {
3863 ahd_print_devinfo(ahd
, &devinfo
);
3864 printf("INITIATOR_MSG_OUT");
3867 phasemis
= bus_phase
!= P_MESGOUT
;
3870 if ((ahd_debug
& AHD_SHOW_MESSAGES
) != 0) {
3871 printf(" PHASEMIS %s\n",
3872 ahd_lookup_phase_entry(bus_phase
)
3876 if (bus_phase
== P_MESGIN
) {
3878 * Change gears and see if
3879 * this messages is of interest to
3880 * us or should be passed back to
3883 ahd_outb(ahd
, CLRSINT1
, CLRATNO
);
3884 ahd
->send_msg_perror
= 0;
3885 ahd
->msg_type
= MSG_TYPE_INITIATOR_MSGIN
;
3886 ahd
->msgin_index
= 0;
3893 if (ahd
->send_msg_perror
) {
3894 ahd_outb(ahd
, CLRSINT1
, CLRATNO
);
3895 ahd_outb(ahd
, CLRSINT1
, CLRREQINIT
);
3897 if ((ahd_debug
& AHD_SHOW_MESSAGES
) != 0)
3898 printf(" byte 0x%x\n", ahd
->send_msg_perror
);
3901 * If we are notifying the target of a CRC error
3902 * during packetized operations, the target is
3903 * within its rights to acknowledge our message
3906 if ((ahd
->msg_flags
& MSG_FLAG_PACKETIZED
) != 0
3907 && ahd
->send_msg_perror
== MSG_INITIATOR_DET_ERR
)
3908 ahd
->msg_flags
|= MSG_FLAG_EXPECT_IDE_BUSFREE
;
3910 ahd_outb(ahd
, RETURN_2
, ahd
->send_msg_perror
);
3911 ahd_outb(ahd
, RETURN_1
, CONT_MSG_LOOP_WRITE
);
3915 msgdone
= ahd
->msgout_index
== ahd
->msgout_len
;
3918 * The target has requested a retry.
3919 * Re-assert ATN, reset our message index to
3922 ahd
->msgout_index
= 0;
3923 ahd_assert_atn(ahd
);
3926 lastbyte
= ahd
->msgout_index
== (ahd
->msgout_len
- 1);
3928 /* Last byte is signified by dropping ATN */
3929 ahd_outb(ahd
, CLRSINT1
, CLRATNO
);
3933 * Clear our interrupt status and present
3934 * the next byte on the bus.
3936 ahd_outb(ahd
, CLRSINT1
, CLRREQINIT
);
3938 if ((ahd_debug
& AHD_SHOW_MESSAGES
) != 0)
3939 printf(" byte 0x%x\n",
3940 ahd
->msgout_buf
[ahd
->msgout_index
]);
3942 ahd_outb(ahd
, RETURN_2
, ahd
->msgout_buf
[ahd
->msgout_index
++]);
3943 ahd_outb(ahd
, RETURN_1
, CONT_MSG_LOOP_WRITE
);
3946 case MSG_TYPE_INITIATOR_MSGIN
:
3952 if ((ahd_debug
& AHD_SHOW_MESSAGES
) != 0) {
3953 ahd_print_devinfo(ahd
, &devinfo
);
3954 printf("INITIATOR_MSG_IN");
3957 phasemis
= bus_phase
!= P_MESGIN
;
3960 if ((ahd_debug
& AHD_SHOW_MESSAGES
) != 0) {
3961 printf(" PHASEMIS %s\n",
3962 ahd_lookup_phase_entry(bus_phase
)
3966 ahd
->msgin_index
= 0;
3967 if (bus_phase
== P_MESGOUT
3968 && (ahd
->send_msg_perror
!= 0
3969 || (ahd
->msgout_len
!= 0
3970 && ahd
->msgout_index
== 0))) {
3971 ahd
->msg_type
= MSG_TYPE_INITIATOR_MSGOUT
;
3978 /* Pull the byte in without acking it */
3979 ahd
->msgin_buf
[ahd
->msgin_index
] = ahd_inb(ahd
, SCSIBUS
);
3981 if ((ahd_debug
& AHD_SHOW_MESSAGES
) != 0)
3982 printf(" byte 0x%x\n",
3983 ahd
->msgin_buf
[ahd
->msgin_index
]);
3986 message_done
= ahd_parse_msg(ahd
, &devinfo
);
3990 * Clear our incoming message buffer in case there
3991 * is another message following this one.
3993 ahd
->msgin_index
= 0;
3996 * If this message illicited a response,
3997 * assert ATN so the target takes us to the
3998 * message out phase.
4000 if (ahd
->msgout_len
!= 0) {
4002 if ((ahd_debug
& AHD_SHOW_MESSAGES
) != 0) {
4003 ahd_print_devinfo(ahd
, &devinfo
);
4004 printf("Asserting ATN for response\n");
4007 ahd_assert_atn(ahd
);
4012 if (message_done
== MSGLOOP_TERMINATED
) {
4016 ahd_outb(ahd
, CLRSINT1
, CLRREQINIT
);
4017 ahd_outb(ahd
, RETURN_1
, CONT_MSG_LOOP_READ
);
4021 case MSG_TYPE_TARGET_MSGIN
:
4027 * By default, the message loop will continue.
4029 ahd_outb(ahd
, RETURN_1
, CONT_MSG_LOOP_TARG
);
4031 if (ahd
->msgout_len
== 0)
4032 panic("Target MSGIN with no active message");
4035 * If we interrupted a mesgout session, the initiator
4036 * will not know this until our first REQ. So, we
4037 * only honor mesgout requests after we've sent our
4040 if ((ahd_inb(ahd
, SCSISIGI
) & ATNI
) != 0
4041 && ahd
->msgout_index
> 0)
4042 msgout_request
= TRUE
;
4044 msgout_request
= FALSE
;
4046 if (msgout_request
) {
4049 * Change gears and see if
4050 * this messages is of interest to
4051 * us or should be passed back to
4054 ahd
->msg_type
= MSG_TYPE_TARGET_MSGOUT
;
4055 ahd_outb(ahd
, SCSISIGO
, P_MESGOUT
| BSYO
);
4056 ahd
->msgin_index
= 0;
4057 /* Dummy read to REQ for first byte */
4058 ahd_inb(ahd
, SCSIDAT
);
4059 ahd_outb(ahd
, SXFRCTL0
,
4060 ahd_inb(ahd
, SXFRCTL0
) | SPIOEN
);
4064 msgdone
= ahd
->msgout_index
== ahd
->msgout_len
;
4066 ahd_outb(ahd
, SXFRCTL0
,
4067 ahd_inb(ahd
, SXFRCTL0
) & ~SPIOEN
);
4073 * Present the next byte on the bus.
4075 ahd_outb(ahd
, SXFRCTL0
, ahd_inb(ahd
, SXFRCTL0
) | SPIOEN
);
4076 ahd_outb(ahd
, SCSIDAT
, ahd
->msgout_buf
[ahd
->msgout_index
++]);
4079 case MSG_TYPE_TARGET_MSGOUT
:
4085 * By default, the message loop will continue.
4087 ahd_outb(ahd
, RETURN_1
, CONT_MSG_LOOP_TARG
);
4090 * The initiator signals that this is
4091 * the last byte by dropping ATN.
4093 lastbyte
= (ahd_inb(ahd
, SCSISIGI
) & ATNI
) == 0;
4096 * Read the latched byte, but turn off SPIOEN first
4097 * so that we don't inadvertently cause a REQ for the
4100 ahd_outb(ahd
, SXFRCTL0
, ahd_inb(ahd
, SXFRCTL0
) & ~SPIOEN
);
4101 ahd
->msgin_buf
[ahd
->msgin_index
] = ahd_inb(ahd
, SCSIDAT
);
4102 msgdone
= ahd_parse_msg(ahd
, &devinfo
);
4103 if (msgdone
== MSGLOOP_TERMINATED
) {
4105 * The message is *really* done in that it caused
4106 * us to go to bus free. The sequencer has already
4107 * been reset at this point, so pull the ejection
4116 * XXX Read spec about initiator dropping ATN too soon
4117 * and use msgdone to detect it.
4119 if (msgdone
== MSGLOOP_MSGCOMPLETE
) {
4120 ahd
->msgin_index
= 0;
4123 * If this message illicited a response, transition
4124 * to the Message in phase and send it.
4126 if (ahd
->msgout_len
!= 0) {
4127 ahd_outb(ahd
, SCSISIGO
, P_MESGIN
| BSYO
);
4128 ahd_outb(ahd
, SXFRCTL0
,
4129 ahd_inb(ahd
, SXFRCTL0
) | SPIOEN
);
4130 ahd
->msg_type
= MSG_TYPE_TARGET_MSGIN
;
4131 ahd
->msgin_index
= 0;
4139 /* Ask for the next byte. */
4140 ahd_outb(ahd
, SXFRCTL0
,
4141 ahd_inb(ahd
, SXFRCTL0
) | SPIOEN
);
4147 panic("Unknown REQINIT message type");
4151 if ((ahd
->msg_flags
& MSG_FLAG_PACKETIZED
) != 0) {
4152 printf("%s: Returning to Idle Loop\n",
4154 ahd_clear_msg_state(ahd
);
4157 * Perform the equivalent of a clear_target_state.
4159 ahd_outb(ahd
, LASTPHASE
, P_BUSFREE
);
4160 ahd_outb(ahd
, SEQ_FLAGS
, NOT_IDENTIFIED
|NO_CDB_SENT
);
4161 ahd_outb(ahd
, SEQCTL0
, FASTMODE
|SEQRESET
);
4163 ahd_clear_msg_state(ahd
);
4164 ahd_outb(ahd
, RETURN_1
, EXIT_MSG_LOOP
);
4170 * See if we sent a particular extended message to the target.
4171 * If "full" is true, return true only if the target saw the full
4172 * message. If "full" is false, return true if the target saw at
4173 * least the first byte of the message.
4176 ahd_sent_msg(struct ahd_softc
*ahd
, ahd_msgtype type
, u_int msgval
, int full
)
4184 while (index
< ahd
->msgout_len
) {
4185 if (ahd
->msgout_buf
[index
] == MSG_EXTENDED
) {
4188 end_index
= index
+ 1 + ahd
->msgout_buf
[index
+ 1];
4189 if (ahd
->msgout_buf
[index
+2] == msgval
4190 && type
== AHDMSG_EXT
) {
4193 if (ahd
->msgout_index
> end_index
)
4195 } else if (ahd
->msgout_index
> index
)
4199 } else if (ahd
->msgout_buf
[index
] >= MSG_SIMPLE_TASK
4200 && ahd
->msgout_buf
[index
] <= MSG_IGN_WIDE_RESIDUE
) {
4202 /* Skip tag type and tag id or residue param*/
4205 /* Single byte message */
4206 if (type
== AHDMSG_1B
4207 && ahd
->msgout_index
> index
4208 && (ahd
->msgout_buf
[index
] == msgval
4209 || ((ahd
->msgout_buf
[index
] & MSG_IDENTIFYFLAG
) != 0
4210 && msgval
== MSG_IDENTIFYFLAG
)))
4222 * Wait for a complete incoming message, parse it, and respond accordingly.
4225 ahd_parse_msg(struct ahd_softc
*ahd
, struct ahd_devinfo
*devinfo
)
4227 struct ahd_initiator_tinfo
*tinfo
;
4228 struct ahd_tmode_tstate
*tstate
;
4233 done
= MSGLOOP_IN_PROG
;
4236 tinfo
= ahd_fetch_transinfo(ahd
, devinfo
->channel
, devinfo
->our_scsiid
,
4237 devinfo
->target
, &tstate
);
4240 * Parse as much of the message as is available,
4241 * rejecting it if we don't support it. When
4242 * the entire message is available and has been
4243 * handled, return MSGLOOP_MSGCOMPLETE, indicating
4244 * that we have parsed an entire message.
4246 * In the case of extended messages, we accept the length
4247 * byte outright and perform more checking once we know the
4248 * extended message type.
4250 switch (ahd
->msgin_buf
[0]) {
4251 case MSG_DISCONNECT
:
4252 case MSG_SAVEDATAPOINTER
:
4253 case MSG_CMDCOMPLETE
:
4254 case MSG_RESTOREPOINTERS
:
4255 case MSG_IGN_WIDE_RESIDUE
:
4257 * End our message loop as these are messages
4258 * the sequencer handles on its own.
4260 done
= MSGLOOP_TERMINATED
;
4262 case MSG_MESSAGE_REJECT
:
4263 response
= ahd_handle_msg_reject(ahd
, devinfo
);
4266 done
= MSGLOOP_MSGCOMPLETE
;
4270 /* Wait for enough of the message to begin validation */
4271 if (ahd
->msgin_index
< 2)
4273 switch (ahd
->msgin_buf
[2]) {
4281 if (ahd
->msgin_buf
[1] != MSG_EXT_SDTR_LEN
) {
4287 * Wait until we have both args before validating
4288 * and acting on this message.
4290 * Add one to MSG_EXT_SDTR_LEN to account for
4291 * the extended message preamble.
4293 if (ahd
->msgin_index
< (MSG_EXT_SDTR_LEN
+ 1))
4296 period
= ahd
->msgin_buf
[3];
4298 saved_offset
= offset
= ahd
->msgin_buf
[4];
4299 ahd_devlimited_syncrate(ahd
, tinfo
, &period
,
4300 &ppr_options
, devinfo
->role
);
4301 ahd_validate_offset(ahd
, tinfo
, period
, &offset
,
4302 tinfo
->curr
.width
, devinfo
->role
);
4304 printf("(%s:%c:%d:%d): Received "
4305 "SDTR period %x, offset %x\n\t"
4306 "Filtered to period %x, offset %x\n",
4307 ahd_name(ahd
), devinfo
->channel
,
4308 devinfo
->target
, devinfo
->lun
,
4309 ahd
->msgin_buf
[3], saved_offset
,
4312 ahd_set_syncrate(ahd
, devinfo
, period
,
4313 offset
, ppr_options
,
4314 AHD_TRANS_ACTIVE
|AHD_TRANS_GOAL
,
4318 * See if we initiated Sync Negotiation
4319 * and didn't have to fall down to async
4322 if (ahd_sent_msg(ahd
, AHDMSG_EXT
, MSG_EXT_SDTR
, TRUE
)) {
4324 if (saved_offset
!= offset
) {
4325 /* Went too low - force async */
4330 * Send our own SDTR in reply
4333 && devinfo
->role
== ROLE_INITIATOR
) {
4334 printf("(%s:%c:%d:%d): Target "
4336 ahd_name(ahd
), devinfo
->channel
,
4337 devinfo
->target
, devinfo
->lun
);
4339 ahd
->msgout_index
= 0;
4340 ahd
->msgout_len
= 0;
4341 ahd_construct_sdtr(ahd
, devinfo
,
4343 ahd
->msgout_index
= 0;
4346 done
= MSGLOOP_MSGCOMPLETE
;
4353 u_int sending_reply
;
4355 sending_reply
= FALSE
;
4356 if (ahd
->msgin_buf
[1] != MSG_EXT_WDTR_LEN
) {
4362 * Wait until we have our arg before validating
4363 * and acting on this message.
4365 * Add one to MSG_EXT_WDTR_LEN to account for
4366 * the extended message preamble.
4368 if (ahd
->msgin_index
< (MSG_EXT_WDTR_LEN
+ 1))
4371 bus_width
= ahd
->msgin_buf
[3];
4372 saved_width
= bus_width
;
4373 ahd_validate_width(ahd
, tinfo
, &bus_width
,
4376 printf("(%s:%c:%d:%d): Received WDTR "
4377 "%x filtered to %x\n",
4378 ahd_name(ahd
), devinfo
->channel
,
4379 devinfo
->target
, devinfo
->lun
,
4380 saved_width
, bus_width
);
4383 if (ahd_sent_msg(ahd
, AHDMSG_EXT
, MSG_EXT_WDTR
, TRUE
)) {
4385 * Don't send a WDTR back to the
4386 * target, since we asked first.
4387 * If the width went higher than our
4388 * request, reject it.
4390 if (saved_width
> bus_width
) {
4392 printf("(%s:%c:%d:%d): requested %dBit "
4393 "transfers. Rejecting...\n",
4394 ahd_name(ahd
), devinfo
->channel
,
4395 devinfo
->target
, devinfo
->lun
,
4396 8 * (0x01 << bus_width
));
4401 * Send our own WDTR in reply
4404 && devinfo
->role
== ROLE_INITIATOR
) {
4405 printf("(%s:%c:%d:%d): Target "
4407 ahd_name(ahd
), devinfo
->channel
,
4408 devinfo
->target
, devinfo
->lun
);
4410 ahd
->msgout_index
= 0;
4411 ahd
->msgout_len
= 0;
4412 ahd_construct_wdtr(ahd
, devinfo
, bus_width
);
4413 ahd
->msgout_index
= 0;
4415 sending_reply
= TRUE
;
4418 * After a wide message, we are async, but
4419 * some devices don't seem to honor this portion
4420 * of the spec. Force a renegotiation of the
4421 * sync component of our transfer agreement even
4422 * if our goal is async. By updating our width
4423 * after forcing the negotiation, we avoid
4424 * renegotiating for width.
4426 ahd_update_neg_request(ahd
, devinfo
, tstate
,
4427 tinfo
, AHD_NEG_ALWAYS
);
4428 ahd_set_width(ahd
, devinfo
, bus_width
,
4429 AHD_TRANS_ACTIVE
|AHD_TRANS_GOAL
,
4431 if (sending_reply
== FALSE
&& reject
== FALSE
) {
4434 * We will always have an SDTR to send.
4436 ahd
->msgout_index
= 0;
4437 ahd
->msgout_len
= 0;
4438 ahd_build_transfer_msg(ahd
, devinfo
);
4439 ahd
->msgout_index
= 0;
4442 done
= MSGLOOP_MSGCOMPLETE
;
4453 u_int saved_ppr_options
;
4455 if (ahd
->msgin_buf
[1] != MSG_EXT_PPR_LEN
) {
4461 * Wait until we have all args before validating
4462 * and acting on this message.
4464 * Add one to MSG_EXT_PPR_LEN to account for
4465 * the extended message preamble.
4467 if (ahd
->msgin_index
< (MSG_EXT_PPR_LEN
+ 1))
4470 period
= ahd
->msgin_buf
[3];
4471 offset
= ahd
->msgin_buf
[5];
4472 bus_width
= ahd
->msgin_buf
[6];
4473 saved_width
= bus_width
;
4474 ppr_options
= ahd
->msgin_buf
[7];
4476 * According to the spec, a DT only
4477 * period factor with no DT option
4478 * set implies async.
4480 if ((ppr_options
& MSG_EXT_PPR_DT_REQ
) == 0
4483 saved_ppr_options
= ppr_options
;
4484 saved_offset
= offset
;
4487 * Transfer options are only available if we
4488 * are negotiating wide.
4491 ppr_options
&= MSG_EXT_PPR_QAS_REQ
;
4493 ahd_validate_width(ahd
, tinfo
, &bus_width
,
4495 ahd_devlimited_syncrate(ahd
, tinfo
, &period
,
4496 &ppr_options
, devinfo
->role
);
4497 ahd_validate_offset(ahd
, tinfo
, period
, &offset
,
4498 bus_width
, devinfo
->role
);
4500 if (ahd_sent_msg(ahd
, AHDMSG_EXT
, MSG_EXT_PPR
, TRUE
)) {
4502 * If we are unable to do any of the
4503 * requested options (we went too low),
4504 * then we'll have to reject the message.
4506 if (saved_width
> bus_width
4507 || saved_offset
!= offset
4508 || saved_ppr_options
!= ppr_options
) {
4516 if (devinfo
->role
!= ROLE_TARGET
)
4517 printf("(%s:%c:%d:%d): Target "
4519 ahd_name(ahd
), devinfo
->channel
,
4520 devinfo
->target
, devinfo
->lun
);
4522 printf("(%s:%c:%d:%d): Initiator "
4524 ahd_name(ahd
), devinfo
->channel
,
4525 devinfo
->target
, devinfo
->lun
);
4526 ahd
->msgout_index
= 0;
4527 ahd
->msgout_len
= 0;
4528 ahd_construct_ppr(ahd
, devinfo
, period
, offset
,
4529 bus_width
, ppr_options
);
4530 ahd
->msgout_index
= 0;
4534 printf("(%s:%c:%d:%d): Received PPR width %x, "
4535 "period %x, offset %x,options %x\n"
4536 "\tFiltered to width %x, period %x, "
4537 "offset %x, options %x\n",
4538 ahd_name(ahd
), devinfo
->channel
,
4539 devinfo
->target
, devinfo
->lun
,
4540 saved_width
, ahd
->msgin_buf
[3],
4541 saved_offset
, saved_ppr_options
,
4542 bus_width
, period
, offset
, ppr_options
);
4544 ahd_set_width(ahd
, devinfo
, bus_width
,
4545 AHD_TRANS_ACTIVE
|AHD_TRANS_GOAL
,
4547 ahd_set_syncrate(ahd
, devinfo
, period
,
4548 offset
, ppr_options
,
4549 AHD_TRANS_ACTIVE
|AHD_TRANS_GOAL
,
4552 done
= MSGLOOP_MSGCOMPLETE
;
4556 /* Unknown extended message. Reject it. */
4562 #ifdef AHD_TARGET_MODE
4563 case MSG_BUS_DEV_RESET
:
4564 ahd_handle_devreset(ahd
, devinfo
, CAM_LUN_WILDCARD
,
4566 "Bus Device Reset Received",
4567 /*verbose_level*/0);
4569 done
= MSGLOOP_TERMINATED
;
4573 case MSG_CLEAR_QUEUE
:
4577 /* Target mode messages */
4578 if (devinfo
->role
!= ROLE_TARGET
) {
4582 tag
= SCB_LIST_NULL
;
4583 if (ahd
->msgin_buf
[0] == MSG_ABORT_TAG
)
4584 tag
= ahd_inb(ahd
, INITIATOR_TAG
);
4585 ahd_abort_scbs(ahd
, devinfo
->target
, devinfo
->channel
,
4586 devinfo
->lun
, tag
, ROLE_TARGET
,
4589 tstate
= ahd
->enabled_targets
[devinfo
->our_scsiid
];
4590 if (tstate
!= NULL
) {
4591 struct ahd_tmode_lstate
* lstate
;
4593 lstate
= tstate
->enabled_luns
[devinfo
->lun
];
4594 if (lstate
!= NULL
) {
4595 ahd_queue_lstate_event(ahd
, lstate
,
4596 devinfo
->our_scsiid
,
4599 ahd_send_lstate_events(ahd
, lstate
);
4603 done
= MSGLOOP_TERMINATED
;
4607 case MSG_QAS_REQUEST
:
4609 if ((ahd_debug
& AHD_SHOW_MESSAGES
) != 0)
4610 printf("%s: QAS request. SCSISIGI == 0x%x\n",
4611 ahd_name(ahd
), ahd_inb(ahd
, SCSISIGI
));
4613 ahd
->msg_flags
|= MSG_FLAG_EXPECT_QASREJ_BUSFREE
;
4615 case MSG_TERM_IO_PROC
:
4623 * Setup to reject the message.
4625 ahd
->msgout_index
= 0;
4626 ahd
->msgout_len
= 1;
4627 ahd
->msgout_buf
[0] = MSG_MESSAGE_REJECT
;
4628 done
= MSGLOOP_MSGCOMPLETE
;
4632 if (done
!= MSGLOOP_IN_PROG
&& !response
)
4633 /* Clear the outgoing message buffer */
4634 ahd
->msgout_len
= 0;
4640 * Process a message reject message.
4643 ahd_handle_msg_reject(struct ahd_softc
*ahd
, struct ahd_devinfo
*devinfo
)
4646 * What we care about here is if we had an
4647 * outstanding SDTR or WDTR message for this
4648 * target. If we did, this is a signal that
4649 * the target is refusing negotiation.
4652 struct ahd_initiator_tinfo
*tinfo
;
4653 struct ahd_tmode_tstate
*tstate
;
4658 scb_index
= ahd_get_scbptr(ahd
);
4659 scb
= ahd_lookup_scb(ahd
, scb_index
);
4660 tinfo
= ahd_fetch_transinfo(ahd
, devinfo
->channel
,
4661 devinfo
->our_scsiid
,
4662 devinfo
->target
, &tstate
);
4663 /* Might be necessary */
4664 last_msg
= ahd_inb(ahd
, LAST_MSG
);
4666 if (ahd_sent_msg(ahd
, AHDMSG_EXT
, MSG_EXT_PPR
, /*full*/FALSE
)) {
4667 if (ahd_sent_msg(ahd
, AHDMSG_EXT
, MSG_EXT_PPR
, /*full*/TRUE
)
4668 && tinfo
->goal
.period
<= AHD_SYNCRATE_PACED
) {
4670 * Target may not like our SPI-4 PPR Options.
4671 * Attempt to negotiate 80MHz which will turn
4672 * off these options.
4675 printf("(%s:%c:%d:%d): PPR Rejected. "
4676 "Trying simple U160 PPR\n",
4677 ahd_name(ahd
), devinfo
->channel
,
4678 devinfo
->target
, devinfo
->lun
);
4680 tinfo
->goal
.period
= AHD_SYNCRATE_DT
;
4681 tinfo
->goal
.ppr_options
&= MSG_EXT_PPR_IU_REQ
4682 | MSG_EXT_PPR_QAS_REQ
4683 | MSG_EXT_PPR_DT_REQ
;
4686 * Target does not support the PPR message.
4687 * Attempt to negotiate SPI-2 style.
4690 printf("(%s:%c:%d:%d): PPR Rejected. "
4691 "Trying WDTR/SDTR\n",
4692 ahd_name(ahd
), devinfo
->channel
,
4693 devinfo
->target
, devinfo
->lun
);
4695 tinfo
->goal
.ppr_options
= 0;
4696 tinfo
->curr
.transport_version
= 2;
4697 tinfo
->goal
.transport_version
= 2;
4699 ahd
->msgout_index
= 0;
4700 ahd
->msgout_len
= 0;
4701 ahd_build_transfer_msg(ahd
, devinfo
);
4702 ahd
->msgout_index
= 0;
4704 } else if (ahd_sent_msg(ahd
, AHDMSG_EXT
, MSG_EXT_WDTR
, /*full*/FALSE
)) {
4706 /* note 8bit xfers */
4707 printf("(%s:%c:%d:%d): refuses WIDE negotiation. Using "
4708 "8bit transfers\n", ahd_name(ahd
),
4709 devinfo
->channel
, devinfo
->target
, devinfo
->lun
);
4710 ahd_set_width(ahd
, devinfo
, MSG_EXT_WDTR_BUS_8_BIT
,
4711 AHD_TRANS_ACTIVE
|AHD_TRANS_GOAL
,
4714 * No need to clear the sync rate. If the target
4715 * did not accept the command, our syncrate is
4716 * unaffected. If the target started the negotiation,
4717 * but rejected our response, we already cleared the
4718 * sync rate before sending our WDTR.
4720 if (tinfo
->goal
.offset
!= tinfo
->curr
.offset
) {
4722 /* Start the sync negotiation */
4723 ahd
->msgout_index
= 0;
4724 ahd
->msgout_len
= 0;
4725 ahd_build_transfer_msg(ahd
, devinfo
);
4726 ahd
->msgout_index
= 0;
4729 } else if (ahd_sent_msg(ahd
, AHDMSG_EXT
, MSG_EXT_SDTR
, /*full*/FALSE
)) {
4730 /* note asynch xfers and clear flag */
4731 ahd_set_syncrate(ahd
, devinfo
, /*period*/0,
4732 /*offset*/0, /*ppr_options*/0,
4733 AHD_TRANS_ACTIVE
|AHD_TRANS_GOAL
,
4735 printf("(%s:%c:%d:%d): refuses synchronous negotiation. "
4736 "Using asynchronous transfers\n",
4737 ahd_name(ahd
), devinfo
->channel
,
4738 devinfo
->target
, devinfo
->lun
);
4739 } else if ((scb
->hscb
->control
& MSG_SIMPLE_TASK
) != 0) {
4743 tag_type
= (scb
->hscb
->control
& MSG_SIMPLE_TASK
);
4745 if (tag_type
== MSG_SIMPLE_TASK
) {
4746 printf("(%s:%c:%d:%d): refuses tagged commands. "
4747 "Performing non-tagged I/O\n", ahd_name(ahd
),
4748 devinfo
->channel
, devinfo
->target
, devinfo
->lun
);
4749 ahd_set_tags(ahd
, devinfo
, AHD_QUEUE_NONE
);
4752 printf("(%s:%c:%d:%d): refuses %s tagged commands. "
4753 "Performing simple queue tagged I/O only\n",
4754 ahd_name(ahd
), devinfo
->channel
, devinfo
->target
,
4755 devinfo
->lun
, tag_type
== MSG_ORDERED_TASK
4756 ? "ordered" : "head of queue");
4757 ahd_set_tags(ahd
, devinfo
, AHD_QUEUE_BASIC
);
4762 * Resend the identify for this CCB as the target
4763 * may believe that the selection is invalid otherwise.
4765 ahd_outb(ahd
, SCB_CONTROL
,
4766 ahd_inb_scbram(ahd
, SCB_CONTROL
) & mask
);
4767 scb
->hscb
->control
&= mask
;
4768 ahd_set_transaction_tag(scb
, /*enabled*/FALSE
,
4769 /*type*/MSG_SIMPLE_TASK
);
4770 ahd_outb(ahd
, MSG_OUT
, MSG_IDENTIFYFLAG
);
4771 ahd_assert_atn(ahd
);
4772 ahd_busy_tcl(ahd
, BUILD_TCL(scb
->hscb
->scsiid
, devinfo
->lun
),
4776 * Requeue all tagged commands for this target
4777 * currently in our posession so they can be
4778 * converted to untagged commands.
4780 ahd_search_qinfifo(ahd
, SCB_GET_TARGET(ahd
, scb
),
4781 SCB_GET_CHANNEL(ahd
, scb
),
4782 SCB_GET_LUN(scb
), /*tag*/SCB_LIST_NULL
,
4783 ROLE_INITIATOR
, CAM_REQUEUE_REQ
,
4785 } else if (ahd_sent_msg(ahd
, AHDMSG_1B
, MSG_IDENTIFYFLAG
, TRUE
)) {
4787 * Most likely the device believes that we had
4788 * previously negotiated packetized.
4790 ahd
->msg_flags
|= MSG_FLAG_EXPECT_PPR_BUSFREE
4791 | MSG_FLAG_IU_REQ_CHANGED
;
4793 ahd_force_renegotiation(ahd
, devinfo
);
4794 ahd
->msgout_index
= 0;
4795 ahd
->msgout_len
= 0;
4796 ahd_build_transfer_msg(ahd
, devinfo
);
4797 ahd
->msgout_index
= 0;
4801 * Otherwise, we ignore it.
4803 printf("%s:%c:%d: Message reject for %x -- ignored\n",
4804 ahd_name(ahd
), devinfo
->channel
, devinfo
->target
,
4811 * Process an ingnore wide residue message.
4814 ahd_handle_ign_wide_residue(struct ahd_softc
*ahd
, struct ahd_devinfo
*devinfo
)
4819 scb_index
= ahd_get_scbptr(ahd
);
4820 scb
= ahd_lookup_scb(ahd
, scb_index
);
4822 * XXX Actually check data direction in the sequencer?
4823 * Perhaps add datadir to some spare bits in the hscb?
4825 if ((ahd_inb(ahd
, SEQ_FLAGS
) & DPHASE
) == 0
4826 || ahd_get_transfer_dir(scb
) != CAM_DIR_IN
) {
4828 * Ignore the message if we haven't
4829 * seen an appropriate data phase yet.
4833 * If the residual occurred on the last
4834 * transfer and the transfer request was
4835 * expected to end on an odd count, do
4836 * nothing. Otherwise, subtract a byte
4837 * and update the residual count accordingly.
4841 sgptr
= ahd_inb_scbram(ahd
, SCB_RESIDUAL_SGPTR
);
4842 if ((sgptr
& SG_LIST_NULL
) != 0
4843 && (ahd_inb_scbram(ahd
, SCB_TASK_ATTRIBUTE
)
4844 & SCB_XFERLEN_ODD
) != 0) {
4846 * If the residual occurred on the last
4847 * transfer and the transfer request was
4848 * expected to end on an odd count, do
4856 /* Pull in the rest of the sgptr */
4857 sgptr
= ahd_inl_scbram(ahd
, SCB_RESIDUAL_SGPTR
);
4858 data_cnt
= ahd_inl_scbram(ahd
, SCB_RESIDUAL_DATACNT
);
4859 if ((sgptr
& SG_LIST_NULL
) != 0) {
4861 * The residual data count is not updated
4862 * for the command run to completion case.
4863 * Explicitly zero the count.
4865 data_cnt
&= ~AHD_SG_LEN_MASK
;
4867 data_addr
= ahd_inq(ahd
, SHADDR
);
4870 sgptr
&= SG_PTR_MASK
;
4871 if ((ahd
->flags
& AHD_64BIT_ADDRESSING
) != 0) {
4872 struct ahd_dma64_seg
*sg
;
4874 sg
= ahd_sg_bus_to_virt(ahd
, scb
, sgptr
);
4877 * The residual sg ptr points to the next S/G
4878 * to load so we must go back one.
4881 sglen
= ahd_le32toh(sg
->len
) & AHD_SG_LEN_MASK
;
4882 if (sg
!= scb
->sg_list
4883 && sglen
< (data_cnt
& AHD_SG_LEN_MASK
)) {
4886 sglen
= ahd_le32toh(sg
->len
);
4888 * Preserve High Address and SG_LIST
4889 * bits while setting the count to 1.
4891 data_cnt
= 1|(sglen
&(~AHD_SG_LEN_MASK
));
4892 data_addr
= ahd_le64toh(sg
->addr
)
4893 + (sglen
& AHD_SG_LEN_MASK
)
4897 * Increment sg so it points to the
4901 sgptr
= ahd_sg_virt_to_bus(ahd
, scb
,
4905 struct ahd_dma_seg
*sg
;
4907 sg
= ahd_sg_bus_to_virt(ahd
, scb
, sgptr
);
4910 * The residual sg ptr points to the next S/G
4911 * to load so we must go back one.
4914 sglen
= ahd_le32toh(sg
->len
) & AHD_SG_LEN_MASK
;
4915 if (sg
!= scb
->sg_list
4916 && sglen
< (data_cnt
& AHD_SG_LEN_MASK
)) {
4919 sglen
= ahd_le32toh(sg
->len
);
4921 * Preserve High Address and SG_LIST
4922 * bits while setting the count to 1.
4924 data_cnt
= 1|(sglen
&(~AHD_SG_LEN_MASK
));
4925 data_addr
= ahd_le32toh(sg
->addr
)
4926 + (sglen
& AHD_SG_LEN_MASK
)
4930 * Increment sg so it points to the
4934 sgptr
= ahd_sg_virt_to_bus(ahd
, scb
,
4939 * Toggle the "oddness" of the transfer length
4940 * to handle this mid-transfer ignore wide
4941 * residue. This ensures that the oddness is
4942 * correct for subsequent data transfers.
4944 ahd_outb(ahd
, SCB_TASK_ATTRIBUTE
,
4945 ahd_inb_scbram(ahd
, SCB_TASK_ATTRIBUTE
)
4948 ahd_outl(ahd
, SCB_RESIDUAL_SGPTR
, sgptr
);
4949 ahd_outl(ahd
, SCB_RESIDUAL_DATACNT
, data_cnt
);
4951 * The FIFO's pointers will be updated if/when the
4952 * sequencer re-enters a data phase.
4960 * Reinitialize the data pointers for the active transfer
4961 * based on its current residual.
4964 ahd_reinitialize_dataptrs(struct ahd_softc
*ahd
)
4967 ahd_mode_state saved_modes
;
4974 AHD_ASSERT_MODES(ahd
, AHD_MODE_DFF0_MSK
|AHD_MODE_DFF1_MSK
,
4975 AHD_MODE_DFF0_MSK
|AHD_MODE_DFF1_MSK
);
4977 scb_index
= ahd_get_scbptr(ahd
);
4978 scb
= ahd_lookup_scb(ahd
, scb_index
);
4981 * Release and reacquire the FIFO so we
4982 * have a clean slate.
4984 ahd_outb(ahd
, DFFSXFRCTL
, CLRCHN
);
4986 while (--wait
&& !(ahd_inb(ahd
, MDFFSTAT
) & FIFOFREE
))
4989 ahd_print_path(ahd
, scb
);
4990 printf("ahd_reinitialize_dataptrs: Forcing FIFO free.\n");
4991 ahd_outb(ahd
, DFFSXFRCTL
, RSTCHN
|CLRSHCNT
);
4993 saved_modes
= ahd_save_modes(ahd
);
4994 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
4995 ahd_outb(ahd
, DFFSTAT
,
4996 ahd_inb(ahd
, DFFSTAT
)
4997 | (saved_modes
== 0x11 ? CURRFIFO_1
: CURRFIFO_0
));
5000 * Determine initial values for data_addr and data_cnt
5001 * for resuming the data phase.
5003 sgptr
= ahd_inl_scbram(ahd
, SCB_RESIDUAL_SGPTR
);
5004 sgptr
&= SG_PTR_MASK
;
5006 resid
= (ahd_inb_scbram(ahd
, SCB_RESIDUAL_DATACNT
+ 2) << 16)
5007 | (ahd_inb_scbram(ahd
, SCB_RESIDUAL_DATACNT
+ 1) << 8)
5008 | ahd_inb_scbram(ahd
, SCB_RESIDUAL_DATACNT
);
5010 if ((ahd
->flags
& AHD_64BIT_ADDRESSING
) != 0) {
5011 struct ahd_dma64_seg
*sg
;
5013 sg
= ahd_sg_bus_to_virt(ahd
, scb
, sgptr
);
5015 /* The residual sg_ptr always points to the next sg */
5018 dataptr
= ahd_le64toh(sg
->addr
)
5019 + (ahd_le32toh(sg
->len
) & AHD_SG_LEN_MASK
)
5021 ahd_outl(ahd
, HADDR
+ 4, dataptr
>> 32);
5023 struct ahd_dma_seg
*sg
;
5025 sg
= ahd_sg_bus_to_virt(ahd
, scb
, sgptr
);
5027 /* The residual sg_ptr always points to the next sg */
5030 dataptr
= ahd_le32toh(sg
->addr
)
5031 + (ahd_le32toh(sg
->len
) & AHD_SG_LEN_MASK
)
5033 ahd_outb(ahd
, HADDR
+ 4,
5034 (ahd_le32toh(sg
->len
) & ~AHD_SG_LEN_MASK
) >> 24);
5036 ahd_outl(ahd
, HADDR
, dataptr
);
5037 ahd_outb(ahd
, HCNT
+ 2, resid
>> 16);
5038 ahd_outb(ahd
, HCNT
+ 1, resid
>> 8);
5039 ahd_outb(ahd
, HCNT
, resid
);
5043 * Handle the effects of issuing a bus device reset message.
5046 ahd_handle_devreset(struct ahd_softc
*ahd
, struct ahd_devinfo
*devinfo
,
5047 u_int lun
, cam_status status
, char *message
,
5050 #ifdef AHD_TARGET_MODE
5051 struct ahd_tmode_tstate
* tstate
;
5055 found
= ahd_abort_scbs(ahd
, devinfo
->target
, devinfo
->channel
,
5056 lun
, SCB_LIST_NULL
, devinfo
->role
,
5059 #ifdef AHD_TARGET_MODE
5061 * Send an immediate notify ccb to all target mord peripheral
5062 * drivers affected by this action.
5064 tstate
= ahd
->enabled_targets
[devinfo
->our_scsiid
];
5065 if (tstate
!= NULL
) {
5069 if (lun
!= CAM_LUN_WILDCARD
) {
5071 max_lun
= AHD_NUM_LUNS
- 1;
5076 for (cur_lun
<= max_lun
; cur_lun
++) {
5077 struct ahd_tmode_lstate
* lstate
;
5079 lstate
= tstate
->enabled_luns
[cur_lun
];
5083 ahd_queue_lstate_event(ahd
, lstate
, devinfo
->our_scsiid
,
5084 MSG_BUS_DEV_RESET
, /*arg*/0);
5085 ahd_send_lstate_events(ahd
, lstate
);
5091 * Go back to async/narrow transfers and renegotiate.
5093 ahd_set_width(ahd
, devinfo
, MSG_EXT_WDTR_BUS_8_BIT
,
5094 AHD_TRANS_CUR
, /*paused*/TRUE
);
5095 ahd_set_syncrate(ahd
, devinfo
, /*period*/0, /*offset*/0,
5096 /*ppr_options*/0, AHD_TRANS_CUR
,
5099 if (status
!= CAM_SEL_TIMEOUT
)
5100 ahd_send_async(ahd
, devinfo
->channel
, devinfo
->target
,
5101 CAM_LUN_WILDCARD
, AC_SENT_BDR
, NULL
);
5103 if (message
!= NULL
&& bootverbose
)
5104 printf("%s: %s on %c:%d. %d SCBs aborted\n", ahd_name(ahd
),
5105 message
, devinfo
->channel
, devinfo
->target
, found
);
5108 #ifdef AHD_TARGET_MODE
5110 ahd_setup_target_msgin(struct ahd_softc
*ahd
, struct ahd_devinfo
*devinfo
,
5115 * To facilitate adding multiple messages together,
5116 * each routine should increment the index and len
5117 * variables instead of setting them explicitly.
5119 ahd
->msgout_index
= 0;
5120 ahd
->msgout_len
= 0;
5122 if (scb
!= NULL
&& (scb
->flags
& SCB_AUTO_NEGOTIATE
) != 0)
5123 ahd_build_transfer_msg(ahd
, devinfo
);
5125 panic("ahd_intr: AWAITING target message with no message");
5127 ahd
->msgout_index
= 0;
5128 ahd
->msg_type
= MSG_TYPE_TARGET_MSGIN
;
5131 /**************************** Initialization **********************************/
5133 ahd_sglist_size(struct ahd_softc
*ahd
)
5135 bus_size_t list_size
;
5137 list_size
= sizeof(struct ahd_dma_seg
) * AHD_NSEG
;
5138 if ((ahd
->flags
& AHD_64BIT_ADDRESSING
) != 0)
5139 list_size
= sizeof(struct ahd_dma64_seg
) * AHD_NSEG
;
5144 * Calculate the optimum S/G List allocation size. S/G elements used
5145 * for a given transaction must be physically contiguous. Assume the
5146 * OS will allocate full pages to us, so it doesn't make sense to request
5150 ahd_sglist_allocsize(struct ahd_softc
*ahd
)
5152 bus_size_t sg_list_increment
;
5153 bus_size_t sg_list_size
;
5154 bus_size_t max_list_size
;
5155 bus_size_t best_list_size
;
5157 /* Start out with the minimum required for AHD_NSEG. */
5158 sg_list_increment
= ahd_sglist_size(ahd
);
5159 sg_list_size
= sg_list_increment
;
5161 /* Get us as close as possible to a page in size. */
5162 while ((sg_list_size
+ sg_list_increment
) <= PAGE_SIZE
)
5163 sg_list_size
+= sg_list_increment
;
5166 * Try to reduce the amount of wastage by allocating
5169 best_list_size
= sg_list_size
;
5170 max_list_size
= roundup(sg_list_increment
, PAGE_SIZE
);
5171 if (max_list_size
< 4 * PAGE_SIZE
)
5172 max_list_size
= 4 * PAGE_SIZE
;
5173 if (max_list_size
> (AHD_SCB_MAX_ALLOC
* sg_list_increment
))
5174 max_list_size
= (AHD_SCB_MAX_ALLOC
* sg_list_increment
);
5175 while ((sg_list_size
+ sg_list_increment
) <= max_list_size
5176 && (sg_list_size
% PAGE_SIZE
) != 0) {
5178 bus_size_t best_mod
;
5180 sg_list_size
+= sg_list_increment
;
5181 new_mod
= sg_list_size
% PAGE_SIZE
;
5182 best_mod
= best_list_size
% PAGE_SIZE
;
5183 if (new_mod
> best_mod
|| new_mod
== 0) {
5184 best_list_size
= sg_list_size
;
5187 return (best_list_size
);
5191 * Allocate a controller structure for a new device
5192 * and perform initial initializion.
5195 ahd_alloc(void *platform_arg
, char *name
)
5197 struct ahd_softc
*ahd
;
5200 ahd
= malloc(sizeof(*ahd
), M_DEVBUF
, M_NOWAIT
);
5202 printf("aic7xxx: cannot malloc softc!\n");
5203 free(name
, M_DEVBUF
);
5207 ahd
= device_get_softc((device_t
)platform_arg
);
5209 memset(ahd
, 0, sizeof(*ahd
));
5210 ahd
->seep_config
= malloc(sizeof(*ahd
->seep_config
),
5211 M_DEVBUF
, M_NOWAIT
);
5212 if (ahd
->seep_config
== NULL
) {
5214 free(ahd
, M_DEVBUF
);
5216 free(name
, M_DEVBUF
);
5219 LIST_INIT(&ahd
->pending_scbs
);
5220 /* We don't know our unit number until the OSM sets it */
5223 ahd
->description
= NULL
;
5224 ahd
->bus_description
= NULL
;
5226 ahd
->chip
= AHD_NONE
;
5227 ahd
->features
= AHD_FENONE
;
5228 ahd
->bugs
= AHD_BUGNONE
;
5229 ahd
->flags
= AHD_SPCHK_ENB_A
|AHD_RESET_BUS_A
|AHD_TERM_ENB_A
5230 | AHD_EXTENDED_TRANS_A
|AHD_STPWLEVEL_A
;
5231 ahd_timer_init(&ahd
->reset_timer
);
5232 ahd_timer_init(&ahd
->stat_timer
);
5233 ahd
->int_coalescing_timer
= AHD_INT_COALESCING_TIMER_DEFAULT
;
5234 ahd
->int_coalescing_maxcmds
= AHD_INT_COALESCING_MAXCMDS_DEFAULT
;
5235 ahd
->int_coalescing_mincmds
= AHD_INT_COALESCING_MINCMDS_DEFAULT
;
5236 ahd
->int_coalescing_threshold
= AHD_INT_COALESCING_THRESHOLD_DEFAULT
;
5237 ahd
->int_coalescing_stop_threshold
=
5238 AHD_INT_COALESCING_STOP_THRESHOLD_DEFAULT
;
5240 if (ahd_platform_alloc(ahd
, platform_arg
) != 0) {
5245 if ((ahd_debug
& AHD_SHOW_MEMORY
) != 0) {
5246 printf("%s: scb size = 0x%x, hscb size = 0x%x\n",
5247 ahd_name(ahd
), (u_int
)sizeof(struct scb
),
5248 (u_int
)sizeof(struct hardware_scb
));
5255 ahd_softc_init(struct ahd_softc
*ahd
)
5264 ahd_set_unit(struct ahd_softc
*ahd
, int unit
)
5270 ahd_set_name(struct ahd_softc
*ahd
, char *name
)
5272 if (ahd
->name
!= NULL
)
5273 free(ahd
->name
, M_DEVBUF
);
5278 ahd_free(struct ahd_softc
*ahd
)
5282 switch (ahd
->init_level
) {
5288 ahd_dmamap_unload(ahd
, ahd
->shared_data_dmat
,
5289 ahd
->shared_data_map
.dmamap
);
5292 ahd_dmamem_free(ahd
, ahd
->shared_data_dmat
, ahd
->qoutfifo
,
5293 ahd
->shared_data_map
.dmamap
);
5294 ahd_dmamap_destroy(ahd
, ahd
->shared_data_dmat
,
5295 ahd
->shared_data_map
.dmamap
);
5298 ahd_dma_tag_destroy(ahd
, ahd
->shared_data_dmat
);
5301 ahd_dma_tag_destroy(ahd
, ahd
->buffer_dmat
);
5309 ahd_dma_tag_destroy(ahd
, ahd
->parent_dmat
);
5311 ahd_platform_free(ahd
);
5312 ahd_fini_scbdata(ahd
);
5313 for (i
= 0; i
< AHD_NUM_TARGETS
; i
++) {
5314 struct ahd_tmode_tstate
*tstate
;
5316 tstate
= ahd
->enabled_targets
[i
];
5317 if (tstate
!= NULL
) {
5318 #ifdef AHD_TARGET_MODE
5321 for (j
= 0; j
< AHD_NUM_LUNS
; j
++) {
5322 struct ahd_tmode_lstate
*lstate
;
5324 lstate
= tstate
->enabled_luns
[j
];
5325 if (lstate
!= NULL
) {
5326 xpt_free_path(lstate
->path
);
5327 free(lstate
, M_DEVBUF
);
5331 free(tstate
, M_DEVBUF
);
5334 #ifdef AHD_TARGET_MODE
5335 if (ahd
->black_hole
!= NULL
) {
5336 xpt_free_path(ahd
->black_hole
->path
);
5337 free(ahd
->black_hole
, M_DEVBUF
);
5340 if (ahd
->name
!= NULL
)
5341 free(ahd
->name
, M_DEVBUF
);
5342 if (ahd
->seep_config
!= NULL
)
5343 free(ahd
->seep_config
, M_DEVBUF
);
5344 if (ahd
->saved_stack
!= NULL
)
5345 free(ahd
->saved_stack
, M_DEVBUF
);
5347 free(ahd
, M_DEVBUF
);
5353 ahd_shutdown(void *arg
)
5355 struct ahd_softc
*ahd
;
5357 ahd
= (struct ahd_softc
*)arg
;
5360 * Stop periodic timer callbacks.
5362 ahd_timer_stop(&ahd
->reset_timer
);
5363 ahd_timer_stop(&ahd
->stat_timer
);
5365 /* This will reset most registers to 0, but not all */
5366 ahd_reset(ahd
, /*reinit*/FALSE
);
5370 * Reset the controller and record some information about it
5371 * that is only available just after a reset. If "reinit" is
5372 * non-zero, this reset occured after initial configuration
5373 * and the caller requests that the chip be fully reinitialized
5374 * to a runable state. Chip interrupts are *not* enabled after
5375 * a reinitialization. The caller must enable interrupts via
5376 * ahd_intr_enable().
5379 ahd_reset(struct ahd_softc
*ahd
, int reinit
)
5386 * Preserve the value of the SXFRCTL1 register for all channels.
5387 * It contains settings that affect termination and we don't want
5388 * to disturb the integrity of the bus.
5391 ahd_update_modes(ahd
);
5392 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
5393 sxfrctl1
= ahd_inb(ahd
, SXFRCTL1
);
5395 cmd
= ahd_pci_read_config(ahd
->dev_softc
, PCIR_COMMAND
, /*bytes*/2);
5396 if ((ahd
->bugs
& AHD_PCIX_CHIPRST_BUG
) != 0) {
5401 * During the assertion of CHIPRST, the chip
5402 * does not disable its parity logic prior to
5403 * the start of the reset. This may cause a
5404 * parity error to be detected and thus a
5405 * spurious SERR or PERR assertion. Disble
5406 * PERR and SERR responses during the CHIPRST.
5408 mod_cmd
= cmd
& ~(PCIM_CMD_PERRESPEN
|PCIM_CMD_SERRESPEN
);
5409 ahd_pci_write_config(ahd
->dev_softc
, PCIR_COMMAND
,
5410 mod_cmd
, /*bytes*/2);
5412 ahd_outb(ahd
, HCNTRL
, CHIPRST
| ahd
->pause
);
5415 * Ensure that the reset has finished. We delay 1000us
5416 * prior to reading the register to make sure the chip
5417 * has sufficiently completed its reset to handle register
5423 } while (--wait
&& !(ahd_inb(ahd
, HCNTRL
) & CHIPRSTACK
));
5426 printf("%s: WARNING - Failed chip reset! "
5427 "Trying to initialize anyway.\n", ahd_name(ahd
));
5429 ahd_outb(ahd
, HCNTRL
, ahd
->pause
);
5431 if ((ahd
->bugs
& AHD_PCIX_CHIPRST_BUG
) != 0) {
5433 * Clear any latched PCI error status and restore
5434 * previous SERR and PERR response enables.
5436 ahd_pci_write_config(ahd
->dev_softc
, PCIR_STATUS
+ 1,
5438 ahd_pci_write_config(ahd
->dev_softc
, PCIR_COMMAND
,
5443 * Mode should be SCSI after a chip reset, but lets
5444 * set it just to be safe. We touch the MODE_PTR
5445 * register directly so as to bypass the lazy update
5446 * code in ahd_set_modes().
5448 ahd_known_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
5449 ahd_outb(ahd
, MODE_PTR
,
5450 ahd_build_mode_state(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
));
5455 * We must always initialize STPWEN to 1 before we
5456 * restore the saved values. STPWEN is initialized
5457 * to a tri-state condition which can only be cleared
5460 ahd_outb(ahd
, SXFRCTL1
, sxfrctl1
|STPWEN
);
5461 ahd_outb(ahd
, SXFRCTL1
, sxfrctl1
);
5463 /* Determine chip configuration */
5464 ahd
->features
&= ~AHD_WIDE
;
5465 if ((ahd_inb(ahd
, SBLKCTL
) & SELWIDE
) != 0)
5466 ahd
->features
|= AHD_WIDE
;
5469 * If a recovery action has forced a chip reset,
5470 * re-initialize the chip to our liking.
5479 * Determine the number of SCBs available on the controller
5482 ahd_probe_scbs(struct ahd_softc
*ahd
) {
5485 AHD_ASSERT_MODES(ahd
, ~(AHD_MODE_UNKNOWN_MSK
|AHD_MODE_CFG_MSK
),
5486 ~(AHD_MODE_UNKNOWN_MSK
|AHD_MODE_CFG_MSK
));
5487 for (i
= 0; i
< AHD_SCB_MAX
; i
++) {
5490 ahd_set_scbptr(ahd
, i
);
5491 ahd_outw(ahd
, SCB_BASE
, i
);
5492 for (j
= 2; j
< 64; j
++)
5493 ahd_outb(ahd
, SCB_BASE
+j
, 0);
5494 /* Start out life as unallocated (needing an abort) */
5495 ahd_outb(ahd
, SCB_CONTROL
, MK_MESSAGE
);
5496 if (ahd_inw_scbram(ahd
, SCB_BASE
) != i
)
5498 ahd_set_scbptr(ahd
, 0);
5499 if (ahd_inw_scbram(ahd
, SCB_BASE
) != 0)
5506 ahd_dmamap_cb(void *arg
, bus_dma_segment_t
*segs
, int nseg
, int error
)
5510 baddr
= (dma_addr_t
*)arg
;
5511 *baddr
= segs
->ds_addr
;
5515 ahd_initialize_hscbs(struct ahd_softc
*ahd
)
5519 for (i
= 0; i
< ahd
->scb_data
.maxhscbs
; i
++) {
5520 ahd_set_scbptr(ahd
, i
);
5522 /* Clear the control byte. */
5523 ahd_outb(ahd
, SCB_CONTROL
, 0);
5525 /* Set the next pointer */
5526 ahd_outw(ahd
, SCB_NEXT
, SCB_LIST_NULL
);
5531 ahd_init_scbdata(struct ahd_softc
*ahd
)
5533 struct scb_data
*scb_data
;
5536 scb_data
= &ahd
->scb_data
;
5537 TAILQ_INIT(&scb_data
->free_scbs
);
5538 for (i
= 0; i
< AHD_NUM_TARGETS
* AHD_NUM_LUNS_NONPKT
; i
++)
5539 LIST_INIT(&scb_data
->free_scb_lists
[i
]);
5540 LIST_INIT(&scb_data
->any_dev_free_scb_list
);
5541 SLIST_INIT(&scb_data
->hscb_maps
);
5542 SLIST_INIT(&scb_data
->sg_maps
);
5543 SLIST_INIT(&scb_data
->sense_maps
);
5545 /* Determine the number of hardware SCBs and initialize them */
5546 scb_data
->maxhscbs
= ahd_probe_scbs(ahd
);
5547 if (scb_data
->maxhscbs
== 0) {
5548 printf("%s: No SCB space found\n", ahd_name(ahd
));
5552 ahd_initialize_hscbs(ahd
);
5555 * Create our DMA tags. These tags define the kinds of device
5556 * accessible memory allocations and memory mappings we will
5557 * need to perform during normal operation.
5559 * Unless we need to further restrict the allocation, we rely
5560 * on the restrictions of the parent dmat, hence the common
5561 * use of MAXADDR and MAXSIZE.
5564 /* DMA tag for our hardware scb structures */
5565 if (ahd_dma_tag_create(ahd
, ahd
->parent_dmat
, /*alignment*/1,
5566 /*boundary*/BUS_SPACE_MAXADDR_32BIT
+ 1,
5567 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT
,
5568 /*highaddr*/BUS_SPACE_MAXADDR
,
5569 /*filter*/NULL
, /*filterarg*/NULL
,
5570 PAGE_SIZE
, /*nsegments*/1,
5571 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT
,
5572 /*flags*/0, &scb_data
->hscb_dmat
) != 0) {
5576 scb_data
->init_level
++;
5578 /* DMA tag for our S/G structures. */
5579 if (ahd_dma_tag_create(ahd
, ahd
->parent_dmat
, /*alignment*/8,
5580 /*boundary*/BUS_SPACE_MAXADDR_32BIT
+ 1,
5581 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT
,
5582 /*highaddr*/BUS_SPACE_MAXADDR
,
5583 /*filter*/NULL
, /*filterarg*/NULL
,
5584 ahd_sglist_allocsize(ahd
), /*nsegments*/1,
5585 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT
,
5586 /*flags*/0, &scb_data
->sg_dmat
) != 0) {
5590 if ((ahd_debug
& AHD_SHOW_MEMORY
) != 0)
5591 printf("%s: ahd_sglist_allocsize = 0x%x\n", ahd_name(ahd
),
5592 ahd_sglist_allocsize(ahd
));
5595 scb_data
->init_level
++;
5597 /* DMA tag for our sense buffers. We allocate in page sized chunks */
5598 if (ahd_dma_tag_create(ahd
, ahd
->parent_dmat
, /*alignment*/1,
5599 /*boundary*/BUS_SPACE_MAXADDR_32BIT
+ 1,
5600 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT
,
5601 /*highaddr*/BUS_SPACE_MAXADDR
,
5602 /*filter*/NULL
, /*filterarg*/NULL
,
5603 PAGE_SIZE
, /*nsegments*/1,
5604 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT
,
5605 /*flags*/0, &scb_data
->sense_dmat
) != 0) {
5609 scb_data
->init_level
++;
5611 /* Perform initial CCB allocation */
5612 ahd_alloc_scbs(ahd
);
5614 if (scb_data
->numscbs
== 0) {
5615 printf("%s: ahd_init_scbdata - "
5616 "Unable to allocate initial scbs\n",
5622 * Note that we were successfull
5632 ahd_find_scb_by_tag(struct ahd_softc
*ahd
, u_int tag
)
5637 * Look on the pending list.
5639 LIST_FOREACH(scb
, &ahd
->pending_scbs
, pending_links
) {
5640 if (SCB_GET_TAG(scb
) == tag
)
5645 * Then on all of the collision free lists.
5647 TAILQ_FOREACH(scb
, &ahd
->scb_data
.free_scbs
, links
.tqe
) {
5648 struct scb
*list_scb
;
5652 if (SCB_GET_TAG(list_scb
) == tag
)
5654 list_scb
= LIST_NEXT(list_scb
, collision_links
);
5659 * And finally on the generic free list.
5661 LIST_FOREACH(scb
, &ahd
->scb_data
.any_dev_free_scb_list
, links
.le
) {
5662 if (SCB_GET_TAG(scb
) == tag
)
5670 ahd_fini_scbdata(struct ahd_softc
*ahd
)
5672 struct scb_data
*scb_data
;
5674 scb_data
= &ahd
->scb_data
;
5675 if (scb_data
== NULL
)
5678 switch (scb_data
->init_level
) {
5682 struct map_node
*sns_map
;
5684 while ((sns_map
= SLIST_FIRST(&scb_data
->sense_maps
)) != NULL
) {
5685 SLIST_REMOVE_HEAD(&scb_data
->sense_maps
, links
);
5686 ahd_dmamap_unload(ahd
, scb_data
->sense_dmat
,
5688 ahd_dmamem_free(ahd
, scb_data
->sense_dmat
,
5689 sns_map
->vaddr
, sns_map
->dmamap
);
5690 free(sns_map
, M_DEVBUF
);
5692 ahd_dma_tag_destroy(ahd
, scb_data
->sense_dmat
);
5697 struct map_node
*sg_map
;
5699 while ((sg_map
= SLIST_FIRST(&scb_data
->sg_maps
)) != NULL
) {
5700 SLIST_REMOVE_HEAD(&scb_data
->sg_maps
, links
);
5701 ahd_dmamap_unload(ahd
, scb_data
->sg_dmat
,
5703 ahd_dmamem_free(ahd
, scb_data
->sg_dmat
,
5704 sg_map
->vaddr
, sg_map
->dmamap
);
5705 free(sg_map
, M_DEVBUF
);
5707 ahd_dma_tag_destroy(ahd
, scb_data
->sg_dmat
);
5712 struct map_node
*hscb_map
;
5714 while ((hscb_map
= SLIST_FIRST(&scb_data
->hscb_maps
)) != NULL
) {
5715 SLIST_REMOVE_HEAD(&scb_data
->hscb_maps
, links
);
5716 ahd_dmamap_unload(ahd
, scb_data
->hscb_dmat
,
5718 ahd_dmamem_free(ahd
, scb_data
->hscb_dmat
,
5719 hscb_map
->vaddr
, hscb_map
->dmamap
);
5720 free(hscb_map
, M_DEVBUF
);
5722 ahd_dma_tag_destroy(ahd
, scb_data
->hscb_dmat
);
5735 * DSP filter Bypass must be enabled until the first selection
5736 * after a change in bus mode (Razor #491 and #493).
5739 ahd_setup_iocell_workaround(struct ahd_softc
*ahd
)
5741 ahd_mode_state saved_modes
;
5743 saved_modes
= ahd_save_modes(ahd
);
5744 ahd_set_modes(ahd
, AHD_MODE_CFG
, AHD_MODE_CFG
);
5745 ahd_outb(ahd
, DSPDATACTL
, ahd_inb(ahd
, DSPDATACTL
)
5746 | BYPASSENAB
| RCVROFFSTDIS
| XMITOFFSTDIS
);
5747 ahd_outb(ahd
, SIMODE0
, ahd_inb(ahd
, SIMODE0
) | (ENSELDO
|ENSELDI
));
5749 if ((ahd_debug
& AHD_SHOW_MISC
) != 0)
5750 printf("%s: Setting up iocell workaround\n", ahd_name(ahd
));
5752 ahd_restore_modes(ahd
, saved_modes
);
5753 ahd
->flags
&= ~AHD_HAD_FIRST_SEL
;
5757 ahd_iocell_first_selection(struct ahd_softc
*ahd
)
5759 ahd_mode_state saved_modes
;
5762 if ((ahd
->flags
& AHD_HAD_FIRST_SEL
) != 0)
5764 saved_modes
= ahd_save_modes(ahd
);
5765 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
5766 sblkctl
= ahd_inb(ahd
, SBLKCTL
);
5767 ahd_set_modes(ahd
, AHD_MODE_CFG
, AHD_MODE_CFG
);
5769 if ((ahd_debug
& AHD_SHOW_MISC
) != 0)
5770 printf("%s: iocell first selection\n", ahd_name(ahd
));
5772 if ((sblkctl
& ENAB40
) != 0) {
5773 ahd_outb(ahd
, DSPDATACTL
,
5774 ahd_inb(ahd
, DSPDATACTL
) & ~BYPASSENAB
);
5776 if ((ahd_debug
& AHD_SHOW_MISC
) != 0)
5777 printf("%s: BYPASS now disabled\n", ahd_name(ahd
));
5780 ahd_outb(ahd
, SIMODE0
, ahd_inb(ahd
, SIMODE0
) & ~(ENSELDO
|ENSELDI
));
5781 ahd_outb(ahd
, CLRINT
, CLRSCSIINT
);
5782 ahd_restore_modes(ahd
, saved_modes
);
5783 ahd
->flags
|= AHD_HAD_FIRST_SEL
;
5786 /*************************** SCB Management ***********************************/
5788 ahd_add_col_list(struct ahd_softc
*ahd
, struct scb
*scb
, u_int col_idx
)
5790 struct scb_list
*free_list
;
5791 struct scb_tailq
*free_tailq
;
5792 struct scb
*first_scb
;
5794 scb
->flags
|= SCB_ON_COL_LIST
;
5795 AHD_SET_SCB_COL_IDX(scb
, col_idx
);
5796 free_list
= &ahd
->scb_data
.free_scb_lists
[col_idx
];
5797 free_tailq
= &ahd
->scb_data
.free_scbs
;
5798 first_scb
= LIST_FIRST(free_list
);
5799 if (first_scb
!= NULL
) {
5800 LIST_INSERT_AFTER(first_scb
, scb
, collision_links
);
5802 LIST_INSERT_HEAD(free_list
, scb
, collision_links
);
5803 TAILQ_INSERT_TAIL(free_tailq
, scb
, links
.tqe
);
5808 ahd_rem_col_list(struct ahd_softc
*ahd
, struct scb
*scb
)
5810 struct scb_list
*free_list
;
5811 struct scb_tailq
*free_tailq
;
5812 struct scb
*first_scb
;
5815 scb
->flags
&= ~SCB_ON_COL_LIST
;
5816 col_idx
= AHD_GET_SCB_COL_IDX(ahd
, scb
);
5817 free_list
= &ahd
->scb_data
.free_scb_lists
[col_idx
];
5818 free_tailq
= &ahd
->scb_data
.free_scbs
;
5819 first_scb
= LIST_FIRST(free_list
);
5820 if (first_scb
== scb
) {
5821 struct scb
*next_scb
;
5824 * Maintain order in the collision free
5825 * lists for fairness if this device has
5826 * other colliding tags active.
5828 next_scb
= LIST_NEXT(scb
, collision_links
);
5829 if (next_scb
!= NULL
) {
5830 TAILQ_INSERT_AFTER(free_tailq
, scb
,
5831 next_scb
, links
.tqe
);
5833 TAILQ_REMOVE(free_tailq
, scb
, links
.tqe
);
5835 LIST_REMOVE(scb
, collision_links
);
5839 * Get a free scb. If there are none, see if we can allocate a new SCB.
5842 ahd_get_scb(struct ahd_softc
*ahd
, u_int col_idx
)
5849 TAILQ_FOREACH(scb
, &ahd
->scb_data
.free_scbs
, links
.tqe
) {
5850 if (AHD_GET_SCB_COL_IDX(ahd
, scb
) != col_idx
) {
5851 ahd_rem_col_list(ahd
, scb
);
5855 if ((scb
= LIST_FIRST(&ahd
->scb_data
.any_dev_free_scb_list
)) == NULL
) {
5859 ahd_alloc_scbs(ahd
);
5862 LIST_REMOVE(scb
, links
.le
);
5863 if (col_idx
!= AHD_NEVER_COL_IDX
5864 && (scb
->col_scb
!= NULL
)
5865 && (scb
->col_scb
->flags
& SCB_ACTIVE
) == 0) {
5866 LIST_REMOVE(scb
->col_scb
, links
.le
);
5867 ahd_add_col_list(ahd
, scb
->col_scb
, col_idx
);
5870 scb
->flags
|= SCB_ACTIVE
;
5875 * Return an SCB resource to the free list.
5878 ahd_free_scb(struct ahd_softc
*ahd
, struct scb
*scb
)
5881 /* Clean up for the next user */
5882 scb
->flags
= SCB_FLAG_NONE
;
5883 scb
->hscb
->control
= 0;
5884 ahd
->scb_data
.scbindex
[SCB_GET_TAG(scb
)] = NULL
;
5886 if (scb
->col_scb
== NULL
) {
5889 * No collision possible. Just free normally.
5891 LIST_INSERT_HEAD(&ahd
->scb_data
.any_dev_free_scb_list
,
5893 } else if ((scb
->col_scb
->flags
& SCB_ON_COL_LIST
) != 0) {
5896 * The SCB we might have collided with is on
5897 * a free collision list. Put both SCBs on
5900 ahd_rem_col_list(ahd
, scb
->col_scb
);
5901 LIST_INSERT_HEAD(&ahd
->scb_data
.any_dev_free_scb_list
,
5903 LIST_INSERT_HEAD(&ahd
->scb_data
.any_dev_free_scb_list
,
5904 scb
->col_scb
, links
.le
);
5905 } else if ((scb
->col_scb
->flags
5906 & (SCB_PACKETIZED
|SCB_ACTIVE
)) == SCB_ACTIVE
5907 && (scb
->col_scb
->hscb
->control
& TAG_ENB
) != 0) {
5910 * The SCB we might collide with on the next allocation
5911 * is still active in a non-packetized, tagged, context.
5912 * Put us on the SCB collision list.
5914 ahd_add_col_list(ahd
, scb
,
5915 AHD_GET_SCB_COL_IDX(ahd
, scb
->col_scb
));
5918 * The SCB we might collide with on the next allocation
5919 * is either active in a packetized context, or free.
5920 * Since we can't collide, put this SCB on the generic
5923 LIST_INSERT_HEAD(&ahd
->scb_data
.any_dev_free_scb_list
,
5927 ahd_platform_scb_free(ahd
, scb
);
5931 ahd_alloc_scbs(struct ahd_softc
*ahd
)
5933 struct scb_data
*scb_data
;
5934 struct scb
*next_scb
;
5935 struct hardware_scb
*hscb
;
5936 struct map_node
*hscb_map
;
5937 struct map_node
*sg_map
;
5938 struct map_node
*sense_map
;
5940 uint8_t *sense_data
;
5941 dma_addr_t hscb_busaddr
;
5942 dma_addr_t sg_busaddr
;
5943 dma_addr_t sense_busaddr
;
5947 scb_data
= &ahd
->scb_data
;
5948 if (scb_data
->numscbs
>= AHD_SCB_MAX_ALLOC
)
5949 /* Can't allocate any more */
5952 if (scb_data
->scbs_left
!= 0) {
5955 offset
= (PAGE_SIZE
/ sizeof(*hscb
)) - scb_data
->scbs_left
;
5956 hscb_map
= SLIST_FIRST(&scb_data
->hscb_maps
);
5957 hscb
= &((struct hardware_scb
*)hscb_map
->vaddr
)[offset
];
5958 hscb_busaddr
= hscb_map
->physaddr
+ (offset
* sizeof(*hscb
));
5960 hscb_map
= malloc(sizeof(*hscb_map
), M_DEVBUF
, M_NOWAIT
);
5962 if (hscb_map
== NULL
)
5965 /* Allocate the next batch of hardware SCBs */
5966 if (ahd_dmamem_alloc(ahd
, scb_data
->hscb_dmat
,
5967 (void **)&hscb_map
->vaddr
,
5968 BUS_DMA_NOWAIT
, &hscb_map
->dmamap
) != 0) {
5969 free(hscb_map
, M_DEVBUF
);
5973 SLIST_INSERT_HEAD(&scb_data
->hscb_maps
, hscb_map
, links
);
5975 ahd_dmamap_load(ahd
, scb_data
->hscb_dmat
, hscb_map
->dmamap
,
5976 hscb_map
->vaddr
, PAGE_SIZE
, ahd_dmamap_cb
,
5977 &hscb_map
->physaddr
, /*flags*/0);
5979 hscb
= (struct hardware_scb
*)hscb_map
->vaddr
;
5980 hscb_busaddr
= hscb_map
->physaddr
;
5981 scb_data
->scbs_left
= PAGE_SIZE
/ sizeof(*hscb
);
5984 if (scb_data
->sgs_left
!= 0) {
5987 offset
= ((ahd_sglist_allocsize(ahd
) / ahd_sglist_size(ahd
))
5988 - scb_data
->sgs_left
) * ahd_sglist_size(ahd
);
5989 sg_map
= SLIST_FIRST(&scb_data
->sg_maps
);
5990 segs
= sg_map
->vaddr
+ offset
;
5991 sg_busaddr
= sg_map
->physaddr
+ offset
;
5993 sg_map
= malloc(sizeof(*sg_map
), M_DEVBUF
, M_NOWAIT
);
5998 /* Allocate the next batch of S/G lists */
5999 if (ahd_dmamem_alloc(ahd
, scb_data
->sg_dmat
,
6000 (void **)&sg_map
->vaddr
,
6001 BUS_DMA_NOWAIT
, &sg_map
->dmamap
) != 0) {
6002 free(sg_map
, M_DEVBUF
);
6006 SLIST_INSERT_HEAD(&scb_data
->sg_maps
, sg_map
, links
);
6008 ahd_dmamap_load(ahd
, scb_data
->sg_dmat
, sg_map
->dmamap
,
6009 sg_map
->vaddr
, ahd_sglist_allocsize(ahd
),
6010 ahd_dmamap_cb
, &sg_map
->physaddr
, /*flags*/0);
6012 segs
= sg_map
->vaddr
;
6013 sg_busaddr
= sg_map
->physaddr
;
6014 scb_data
->sgs_left
=
6015 ahd_sglist_allocsize(ahd
) / ahd_sglist_size(ahd
);
6017 if (ahd_debug
& AHD_SHOW_MEMORY
)
6018 printf("Mapped SG data\n");
6022 if (scb_data
->sense_left
!= 0) {
6025 offset
= PAGE_SIZE
- (AHD_SENSE_BUFSIZE
* scb_data
->sense_left
);
6026 sense_map
= SLIST_FIRST(&scb_data
->sense_maps
);
6027 sense_data
= sense_map
->vaddr
+ offset
;
6028 sense_busaddr
= sense_map
->physaddr
+ offset
;
6030 sense_map
= malloc(sizeof(*sense_map
), M_DEVBUF
, M_NOWAIT
);
6032 if (sense_map
== NULL
)
6035 /* Allocate the next batch of sense buffers */
6036 if (ahd_dmamem_alloc(ahd
, scb_data
->sense_dmat
,
6037 (void **)&sense_map
->vaddr
,
6038 BUS_DMA_NOWAIT
, &sense_map
->dmamap
) != 0) {
6039 free(sense_map
, M_DEVBUF
);
6043 SLIST_INSERT_HEAD(&scb_data
->sense_maps
, sense_map
, links
);
6045 ahd_dmamap_load(ahd
, scb_data
->sense_dmat
, sense_map
->dmamap
,
6046 sense_map
->vaddr
, PAGE_SIZE
, ahd_dmamap_cb
,
6047 &sense_map
->physaddr
, /*flags*/0);
6049 sense_data
= sense_map
->vaddr
;
6050 sense_busaddr
= sense_map
->physaddr
;
6051 scb_data
->sense_left
= PAGE_SIZE
/ AHD_SENSE_BUFSIZE
;
6053 if (ahd_debug
& AHD_SHOW_MEMORY
)
6054 printf("Mapped sense data\n");
6058 newcount
= MIN(scb_data
->sense_left
, scb_data
->scbs_left
);
6059 newcount
= MIN(newcount
, scb_data
->sgs_left
);
6060 newcount
= MIN(newcount
, (AHD_SCB_MAX_ALLOC
- scb_data
->numscbs
));
6061 for (i
= 0; i
< newcount
; i
++) {
6062 struct scb_platform_data
*pdata
;
6068 next_scb
= (struct scb
*)malloc(sizeof(*next_scb
),
6069 M_DEVBUF
, M_NOWAIT
);
6070 if (next_scb
== NULL
)
6073 pdata
= (struct scb_platform_data
*)malloc(sizeof(*pdata
),
6074 M_DEVBUF
, M_NOWAIT
);
6075 if (pdata
== NULL
) {
6076 free(next_scb
, M_DEVBUF
);
6079 next_scb
->platform_data
= pdata
;
6080 next_scb
->hscb_map
= hscb_map
;
6081 next_scb
->sg_map
= sg_map
;
6082 next_scb
->sense_map
= sense_map
;
6083 next_scb
->sg_list
= segs
;
6084 next_scb
->sense_data
= sense_data
;
6085 next_scb
->sense_busaddr
= sense_busaddr
;
6086 memset(hscb
, 0, sizeof(*hscb
));
6087 next_scb
->hscb
= hscb
;
6088 hscb
->hscb_busaddr
= ahd_htole32(hscb_busaddr
);
6091 * The sequencer always starts with the second entry.
6092 * The first entry is embedded in the scb.
6094 next_scb
->sg_list_busaddr
= sg_busaddr
;
6095 if ((ahd
->flags
& AHD_64BIT_ADDRESSING
) != 0)
6096 next_scb
->sg_list_busaddr
6097 += sizeof(struct ahd_dma64_seg
);
6099 next_scb
->sg_list_busaddr
+= sizeof(struct ahd_dma_seg
);
6100 next_scb
->ahd_softc
= ahd
;
6101 next_scb
->flags
= SCB_FLAG_NONE
;
6103 error
= ahd_dmamap_create(ahd
, ahd
->buffer_dmat
, /*flags*/0,
6106 free(next_scb
, M_DEVBUF
);
6107 free(pdata
, M_DEVBUF
);
6111 next_scb
->hscb
->tag
= ahd_htole16(scb_data
->numscbs
);
6112 col_tag
= scb_data
->numscbs
^ 0x100;
6113 next_scb
->col_scb
= ahd_find_scb_by_tag(ahd
, col_tag
);
6114 if (next_scb
->col_scb
!= NULL
)
6115 next_scb
->col_scb
->col_scb
= next_scb
;
6116 ahd_free_scb(ahd
, next_scb
);
6118 hscb_busaddr
+= sizeof(*hscb
);
6119 segs
+= ahd_sglist_size(ahd
);
6120 sg_busaddr
+= ahd_sglist_size(ahd
);
6121 sense_data
+= AHD_SENSE_BUFSIZE
;
6122 sense_busaddr
+= AHD_SENSE_BUFSIZE
;
6123 scb_data
->numscbs
++;
6124 scb_data
->sense_left
--;
6125 scb_data
->scbs_left
--;
6126 scb_data
->sgs_left
--;
6131 ahd_controller_info(struct ahd_softc
*ahd
, char *buf
)
6137 len
= sprintf(buf
, "%s: ", ahd_chip_names
[ahd
->chip
& AHD_CHIPID_MASK
]);
6140 speed
= "Ultra320 ";
6141 if ((ahd
->features
& AHD_WIDE
) != 0) {
6146 len
= sprintf(buf
, "%s%sChannel %c, SCSI Id=%d, ",
6147 speed
, type
, ahd
->channel
, ahd
->our_id
);
6150 sprintf(buf
, "%s, %d SCBs", ahd
->bus_description
,
6151 ahd
->scb_data
.maxhscbs
);
6154 static const char *channel_strings
[] = {
6161 static const char *termstat_strings
[] = {
6162 "Terminated Correctly",
6169 * Start the board, ready for normal operation
6172 ahd_init(struct ahd_softc
*ahd
)
6174 uint8_t *next_vaddr
;
6175 dma_addr_t next_baddr
;
6176 size_t driver_data_size
;
6180 uint8_t current_sensing
;
6183 AHD_ASSERT_MODES(ahd
, AHD_MODE_SCSI_MSK
, AHD_MODE_SCSI_MSK
);
6185 ahd
->stack_size
= ahd_probe_stack_size(ahd
);
6186 ahd
->saved_stack
= malloc(ahd
->stack_size
* sizeof(uint16_t),
6187 M_DEVBUF
, M_NOWAIT
);
6188 if (ahd
->saved_stack
== NULL
)
6192 * Verify that the compiler hasn't over-agressively
6193 * padded important structures.
6195 if (sizeof(struct hardware_scb
) != 64)
6196 panic("Hardware SCB size is incorrect");
6199 if ((ahd_debug
& AHD_DEBUG_SEQUENCER
) != 0)
6200 ahd
->flags
|= AHD_SEQUENCER_DEBUG
;
6204 * Default to allowing initiator operations.
6206 ahd
->flags
|= AHD_INITIATORROLE
;
6209 * Only allow target mode features if this unit has them enabled.
6211 if ((AHD_TMODE_ENABLE
& (0x1 << ahd
->unit
)) == 0)
6212 ahd
->features
&= ~AHD_TARGETMODE
;
6215 /* DMA tag for mapping buffers into device visible space. */
6216 if (ahd_dma_tag_create(ahd
, ahd
->parent_dmat
, /*alignment*/1,
6217 /*boundary*/BUS_SPACE_MAXADDR_32BIT
+ 1,
6218 /*lowaddr*/ahd
->flags
& AHD_39BIT_ADDRESSING
6219 ? (dma_addr_t
)0x7FFFFFFFFFULL
6220 : BUS_SPACE_MAXADDR_32BIT
,
6221 /*highaddr*/BUS_SPACE_MAXADDR
,
6222 /*filter*/NULL
, /*filterarg*/NULL
,
6223 /*maxsize*/(AHD_NSEG
- 1) * PAGE_SIZE
,
6224 /*nsegments*/AHD_NSEG
,
6225 /*maxsegsz*/AHD_MAXTRANSFER_SIZE
,
6226 /*flags*/BUS_DMA_ALLOCNOW
,
6227 &ahd
->buffer_dmat
) != 0) {
6235 * DMA tag for our command fifos and other data in system memory
6236 * the card's sequencer must be able to access. For initiator
6237 * roles, we need to allocate space for the qoutfifo. When providing
6238 * for the target mode role, we must additionally provide space for
6239 * the incoming target command fifo.
6241 driver_data_size
= AHD_SCB_MAX
* sizeof(*ahd
->qoutfifo
)
6242 + sizeof(struct hardware_scb
);
6243 if ((ahd
->features
& AHD_TARGETMODE
) != 0)
6244 driver_data_size
+= AHD_TMODE_CMDS
* sizeof(struct target_cmd
);
6245 if ((ahd
->bugs
& AHD_PKT_BITBUCKET_BUG
) != 0)
6246 driver_data_size
+= PKT_OVERRUN_BUFSIZE
;
6247 if (ahd_dma_tag_create(ahd
, ahd
->parent_dmat
, /*alignment*/1,
6248 /*boundary*/BUS_SPACE_MAXADDR_32BIT
+ 1,
6249 /*lowaddr*/BUS_SPACE_MAXADDR_32BIT
,
6250 /*highaddr*/BUS_SPACE_MAXADDR
,
6251 /*filter*/NULL
, /*filterarg*/NULL
,
6254 /*maxsegsz*/BUS_SPACE_MAXSIZE_32BIT
,
6255 /*flags*/0, &ahd
->shared_data_dmat
) != 0) {
6261 /* Allocation of driver data */
6262 if (ahd_dmamem_alloc(ahd
, ahd
->shared_data_dmat
,
6263 (void **)&ahd
->shared_data_map
.vaddr
,
6265 &ahd
->shared_data_map
.dmamap
) != 0) {
6271 /* And permanently map it in */
6272 ahd_dmamap_load(ahd
, ahd
->shared_data_dmat
, ahd
->shared_data_map
.dmamap
,
6273 ahd
->shared_data_map
.vaddr
, driver_data_size
,
6274 ahd_dmamap_cb
, &ahd
->shared_data_map
.physaddr
,
6276 ahd
->qoutfifo
= (struct ahd_completion
*)ahd
->shared_data_map
.vaddr
;
6277 next_vaddr
= (uint8_t *)&ahd
->qoutfifo
[AHD_QOUT_SIZE
];
6278 next_baddr
= ahd
->shared_data_map
.physaddr
6279 + AHD_QOUT_SIZE
*sizeof(struct ahd_completion
);
6280 if ((ahd
->features
& AHD_TARGETMODE
) != 0) {
6281 ahd
->targetcmds
= (struct target_cmd
*)next_vaddr
;
6282 next_vaddr
+= AHD_TMODE_CMDS
* sizeof(struct target_cmd
);
6283 next_baddr
+= AHD_TMODE_CMDS
* sizeof(struct target_cmd
);
6286 if ((ahd
->bugs
& AHD_PKT_BITBUCKET_BUG
) != 0) {
6287 ahd
->overrun_buf
= next_vaddr
;
6288 next_vaddr
+= PKT_OVERRUN_BUFSIZE
;
6289 next_baddr
+= PKT_OVERRUN_BUFSIZE
;
6293 * We need one SCB to serve as the "next SCB". Since the
6294 * tag identifier in this SCB will never be used, there is
6295 * no point in using a valid HSCB tag from an SCB pulled from
6296 * the standard free pool. So, we allocate this "sentinel"
6297 * specially from the DMA safe memory chunk used for the QOUTFIFO.
6299 ahd
->next_queued_hscb
= (struct hardware_scb
*)next_vaddr
;
6300 ahd
->next_queued_hscb_map
= &ahd
->shared_data_map
;
6301 ahd
->next_queued_hscb
->hscb_busaddr
= ahd_htole32(next_baddr
);
6305 /* Allocate SCB data now that buffer_dmat is initialized */
6306 if (ahd_init_scbdata(ahd
) != 0)
6309 if ((ahd
->flags
& AHD_INITIATORROLE
) == 0)
6310 ahd
->flags
&= ~AHD_RESET_BUS_A
;
6313 * Before committing these settings to the chip, give
6314 * the OSM one last chance to modify our configuration.
6316 ahd_platform_init(ahd
);
6318 /* Bring up the chip. */
6321 AHD_ASSERT_MODES(ahd
, AHD_MODE_SCSI_MSK
, AHD_MODE_SCSI_MSK
);
6323 if ((ahd
->flags
& AHD_CURRENT_SENSING
) == 0)
6327 * Verify termination based on current draw and
6328 * warn user if the bus is over/under terminated.
6330 error
= ahd_write_flexport(ahd
, FLXADDR_ROMSTAT_CURSENSECTL
,
6333 printf("%s: current sensing timeout 1\n", ahd_name(ahd
));
6336 for (i
= 20, fstat
= FLX_FSTAT_BUSY
;
6337 (fstat
& FLX_FSTAT_BUSY
) != 0 && i
; i
--) {
6338 error
= ahd_read_flexport(ahd
, FLXADDR_FLEXSTAT
, &fstat
);
6340 printf("%s: current sensing timeout 2\n",
6346 printf("%s: Timedout during current-sensing test\n",
6351 /* Latch Current Sensing status. */
6352 error
= ahd_read_flexport(ahd
, FLXADDR_CURRENT_STAT
, ¤t_sensing
);
6354 printf("%s: current sensing timeout 3\n", ahd_name(ahd
));
6358 /* Diable current sensing. */
6359 ahd_write_flexport(ahd
, FLXADDR_ROMSTAT_CURSENSECTL
, 0);
6362 if ((ahd_debug
& AHD_SHOW_TERMCTL
) != 0) {
6363 printf("%s: current_sensing == 0x%x\n",
6364 ahd_name(ahd
), current_sensing
);
6368 for (i
= 0; i
< 4; i
++, current_sensing
>>= FLX_CSTAT_SHIFT
) {
6371 term_stat
= (current_sensing
& FLX_CSTAT_MASK
);
6372 switch (term_stat
) {
6373 case FLX_CSTAT_OVER
:
6374 case FLX_CSTAT_UNDER
:
6376 case FLX_CSTAT_INVALID
:
6377 case FLX_CSTAT_OKAY
:
6378 if (warn_user
== 0 && bootverbose
== 0)
6380 printf("%s: %s Channel %s\n", ahd_name(ahd
),
6381 channel_strings
[i
], termstat_strings
[term_stat
]);
6386 printf("%s: WARNING. Termination is not configured correctly.\n"
6387 "%s: WARNING. SCSI bus operations may FAIL.\n",
6388 ahd_name(ahd
), ahd_name(ahd
));
6392 ahd_timer_reset(&ahd
->stat_timer
, AHD_STAT_UPDATE_US
,
6393 ahd_stat_timer
, ahd
);
6398 * (Re)initialize chip state after a chip reset.
6401 ahd_chip_init(struct ahd_softc
*ahd
)
6405 u_int scsiseq_template
;
6410 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
6412 * Take the LED out of diagnostic mode
6414 ahd_outb(ahd
, SBLKCTL
, ahd_inb(ahd
, SBLKCTL
) & ~(DIAGLEDEN
|DIAGLEDON
));
6417 * Return HS_MAILBOX to its default value.
6419 ahd
->hs_mailbox
= 0;
6420 ahd_outb(ahd
, HS_MAILBOX
, 0);
6422 /* Set the SCSI Id, SXFRCTL0, SXFRCTL1, and SIMODE1. */
6423 ahd_outb(ahd
, IOWNID
, ahd
->our_id
);
6424 ahd_outb(ahd
, TOWNID
, ahd
->our_id
);
6425 sxfrctl1
= (ahd
->flags
& AHD_TERM_ENB_A
) != 0 ? STPWEN
: 0;
6426 sxfrctl1
|= (ahd
->flags
& AHD_SPCHK_ENB_A
) != 0 ? ENSPCHK
: 0;
6427 if ((ahd
->bugs
& AHD_LONG_SETIMO_BUG
)
6428 && (ahd
->seltime
!= STIMESEL_MIN
)) {
6430 * The selection timer duration is twice as long
6431 * as it should be. Halve it by adding "1" to
6432 * the user specified setting.
6434 sxfrctl1
|= ahd
->seltime
+ STIMESEL_BUG_ADJ
;
6436 sxfrctl1
|= ahd
->seltime
;
6439 ahd_outb(ahd
, SXFRCTL0
, DFON
);
6440 ahd_outb(ahd
, SXFRCTL1
, sxfrctl1
|ahd
->seltime
|ENSTIMER
|ACTNEGEN
);
6441 ahd_outb(ahd
, SIMODE1
, ENSELTIMO
|ENSCSIRST
|ENSCSIPERR
);
6444 * Now that termination is set, wait for up
6445 * to 500ms for our transceivers to settle. If
6446 * the adapter does not have a cable attached,
6447 * the transceivers may never settle, so don't
6448 * complain if we fail here.
6451 (ahd_inb(ahd
, SBLKCTL
) & (ENAB40
|ENAB20
)) == 0 && wait
;
6455 /* Clear any false bus resets due to the transceivers settling */
6456 ahd_outb(ahd
, CLRSINT1
, CLRSCSIRSTI
);
6457 ahd_outb(ahd
, CLRINT
, CLRSCSIINT
);
6459 /* Initialize mode specific S/G state. */
6460 for (i
= 0; i
< 2; i
++) {
6461 ahd_set_modes(ahd
, AHD_MODE_DFF0
+ i
, AHD_MODE_DFF0
+ i
);
6462 ahd_outb(ahd
, LONGJMP_ADDR
+ 1, INVALID_ADDR
);
6463 ahd_outb(ahd
, SG_STATE
, 0);
6464 ahd_outb(ahd
, CLRSEQINTSRC
, 0xFF);
6465 ahd_outb(ahd
, SEQIMODE
,
6466 ENSAVEPTRS
|ENCFG4DATA
|ENCFG4ISTAT
6467 |ENCFG4TSTAT
|ENCFG4ICMD
|ENCFG4TCMD
);
6470 ahd_set_modes(ahd
, AHD_MODE_CFG
, AHD_MODE_CFG
);
6471 ahd_outb(ahd
, DSCOMMAND0
, ahd_inb(ahd
, DSCOMMAND0
)|MPARCKEN
|CACHETHEN
);
6472 ahd_outb(ahd
, DFF_THRSH
, RD_DFTHRSH_75
|WR_DFTHRSH_75
);
6473 ahd_outb(ahd
, SIMODE0
, ENIOERR
|ENOVERRUN
);
6474 ahd_outb(ahd
, SIMODE3
, ENNTRAMPERR
|ENOSRAMPERR
);
6475 if ((ahd
->bugs
& AHD_BUSFREEREV_BUG
) != 0) {
6476 ahd_outb(ahd
, OPTIONMODE
, AUTOACKEN
|AUTO_MSGOUT_DE
);
6478 ahd_outb(ahd
, OPTIONMODE
, AUTOACKEN
|BUSFREEREV
|AUTO_MSGOUT_DE
);
6480 ahd_outb(ahd
, SCSCHKN
, CURRFIFODEF
|WIDERESEN
|SHVALIDSTDIS
);
6481 if ((ahd
->chip
& AHD_BUS_MASK
) == AHD_PCIX
)
6483 * Do not issue a target abort when a split completion
6484 * error occurs. Let our PCIX interrupt handler deal
6485 * with it instead. H2A4 Razor #625
6487 ahd_outb(ahd
, PCIXCTL
, ahd_inb(ahd
, PCIXCTL
) | SPLTSTADIS
);
6489 if ((ahd
->bugs
& AHD_LQOOVERRUN_BUG
) != 0)
6490 ahd_outb(ahd
, LQOSCSCTL
, LQONOCHKOVER
);
6493 * Tweak IOCELL settings.
6495 if ((ahd
->flags
& AHD_HP_BOARD
) != 0) {
6496 for (i
= 0; i
< NUMDSPS
; i
++) {
6497 ahd_outb(ahd
, DSPSELECT
, i
);
6498 ahd_outb(ahd
, WRTBIASCTL
, WRTBIASCTL_HP_DEFAULT
);
6501 if ((ahd_debug
& AHD_SHOW_MISC
) != 0)
6502 printf("%s: WRTBIASCTL now 0x%x\n", ahd_name(ahd
),
6503 WRTBIASCTL_HP_DEFAULT
);
6506 ahd_setup_iocell_workaround(ahd
);
6509 * Enable LQI Manager interrupts.
6511 ahd_outb(ahd
, LQIMODE1
, ENLQIPHASE_LQ
|ENLQIPHASE_NLQ
|ENLIQABORT
6512 | ENLQICRCI_LQ
|ENLQICRCI_NLQ
|ENLQIBADLQI
6513 | ENLQIOVERI_LQ
|ENLQIOVERI_NLQ
);
6514 ahd_outb(ahd
, LQOMODE0
, ENLQOATNLQ
|ENLQOATNPKT
|ENLQOTCRC
);
6516 * We choose to have the sequencer catch LQOPHCHGINPKT errors
6517 * manually for the command phase at the start of a packetized
6518 * selection case. ENLQOBUSFREE should be made redundant by
6519 * the BUSFREE interrupt, but it seems that some LQOBUSFREE
6520 * events fail to assert the BUSFREE interrupt so we must
6521 * also enable LQOBUSFREE interrupts.
6523 ahd_outb(ahd
, LQOMODE1
, ENLQOBUSFREE
);
6526 * Setup sequencer interrupt handlers.
6528 ahd_outw(ahd
, INTVEC1_ADDR
, ahd_resolve_seqaddr(ahd
, LABEL_seq_isr
));
6529 ahd_outw(ahd
, INTVEC2_ADDR
, ahd_resolve_seqaddr(ahd
, LABEL_timer_isr
));
6532 * Setup SCB Offset registers.
6534 if ((ahd
->bugs
& AHD_PKT_LUN_BUG
) != 0) {
6535 ahd_outb(ahd
, LUNPTR
, offsetof(struct hardware_scb
,
6538 ahd_outb(ahd
, LUNPTR
, offsetof(struct hardware_scb
, lun
));
6540 ahd_outb(ahd
, CMDLENPTR
, offsetof(struct hardware_scb
, cdb_len
));
6541 ahd_outb(ahd
, ATTRPTR
, offsetof(struct hardware_scb
, task_attribute
));
6542 ahd_outb(ahd
, FLAGPTR
, offsetof(struct hardware_scb
, task_management
));
6543 ahd_outb(ahd
, CMDPTR
, offsetof(struct hardware_scb
,
6544 shared_data
.idata
.cdb
));
6545 ahd_outb(ahd
, QNEXTPTR
,
6546 offsetof(struct hardware_scb
, next_hscb_busaddr
));
6547 ahd_outb(ahd
, ABRTBITPTR
, MK_MESSAGE_BIT_OFFSET
);
6548 ahd_outb(ahd
, ABRTBYTEPTR
, offsetof(struct hardware_scb
, control
));
6549 if ((ahd
->bugs
& AHD_PKT_LUN_BUG
) != 0) {
6550 ahd_outb(ahd
, LUNLEN
,
6551 sizeof(ahd
->next_queued_hscb
->pkt_long_lun
) - 1);
6553 ahd_outb(ahd
, LUNLEN
, LUNLEN_SINGLE_LEVEL_LUN
);
6555 ahd_outb(ahd
, CDBLIMIT
, SCB_CDB_LEN_PTR
- 1);
6556 ahd_outb(ahd
, MAXCMD
, 0xFF);
6557 ahd_outb(ahd
, SCBAUTOPTR
,
6558 AUSCBPTR_EN
| offsetof(struct hardware_scb
, tag
));
6560 /* We haven't been enabled for target mode yet. */
6561 ahd_outb(ahd
, MULTARGID
, 0);
6562 ahd_outb(ahd
, MULTARGID
+ 1, 0);
6564 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
6565 /* Initialize the negotiation table. */
6566 if ((ahd
->features
& AHD_NEW_IOCELL_OPTS
) == 0) {
6568 * Clear the spare bytes in the neg table to avoid
6569 * spurious parity errors.
6571 for (target
= 0; target
< AHD_NUM_TARGETS
; target
++) {
6572 ahd_outb(ahd
, NEGOADDR
, target
);
6573 ahd_outb(ahd
, ANNEXCOL
, AHD_ANNEXCOL_PER_DEV0
);
6574 for (i
= 0; i
< AHD_NUM_PER_DEV_ANNEXCOLS
; i
++)
6575 ahd_outb(ahd
, ANNEXDAT
, 0);
6578 for (target
= 0; target
< AHD_NUM_TARGETS
; target
++) {
6579 struct ahd_devinfo devinfo
;
6580 struct ahd_initiator_tinfo
*tinfo
;
6581 struct ahd_tmode_tstate
*tstate
;
6583 tinfo
= ahd_fetch_transinfo(ahd
, 'A', ahd
->our_id
,
6585 ahd_compile_devinfo(&devinfo
, ahd
->our_id
,
6586 target
, CAM_LUN_WILDCARD
,
6587 'A', ROLE_INITIATOR
);
6588 ahd_update_neg_table(ahd
, &devinfo
, &tinfo
->curr
);
6591 ahd_outb(ahd
, CLRSINT3
, NTRAMPERR
|OSRAMPERR
);
6592 ahd_outb(ahd
, CLRINT
, CLRSCSIINT
);
6594 #ifdef NEEDS_MORE_TESTING
6596 * Always enable abort on incoming L_Qs if this feature is
6597 * supported. We use this to catch invalid SCB references.
6599 if ((ahd
->bugs
& AHD_ABORT_LQI_BUG
) == 0)
6600 ahd_outb(ahd
, LQCTL1
, ABORTPENDING
);
6603 ahd_outb(ahd
, LQCTL1
, 0);
6605 /* All of our queues are empty */
6606 ahd
->qoutfifonext
= 0;
6607 ahd
->qoutfifonext_valid_tag
= QOUTFIFO_ENTRY_VALID
;
6608 ahd_outb(ahd
, QOUTFIFO_ENTRY_VALID_TAG
, QOUTFIFO_ENTRY_VALID
);
6609 for (i
= 0; i
< AHD_QOUT_SIZE
; i
++)
6610 ahd
->qoutfifo
[i
].valid_tag
= 0;
6611 ahd_sync_qoutfifo(ahd
, BUS_DMASYNC_PREREAD
);
6613 ahd
->qinfifonext
= 0;
6614 for (i
= 0; i
< AHD_QIN_SIZE
; i
++)
6615 ahd
->qinfifo
[i
] = SCB_LIST_NULL
;
6617 if ((ahd
->features
& AHD_TARGETMODE
) != 0) {
6618 /* All target command blocks start out invalid. */
6619 for (i
= 0; i
< AHD_TMODE_CMDS
; i
++)
6620 ahd
->targetcmds
[i
].cmd_valid
= 0;
6621 ahd_sync_tqinfifo(ahd
, BUS_DMASYNC_PREREAD
);
6622 ahd
->tqinfifonext
= 1;
6623 ahd_outb(ahd
, KERNEL_TQINPOS
, ahd
->tqinfifonext
- 1);
6624 ahd_outb(ahd
, TQINPOS
, ahd
->tqinfifonext
);
6627 /* Initialize Scratch Ram. */
6628 ahd_outb(ahd
, SEQ_FLAGS
, 0);
6629 ahd_outb(ahd
, SEQ_FLAGS2
, 0);
6631 /* We don't have any waiting selections */
6632 ahd_outw(ahd
, WAITING_TID_HEAD
, SCB_LIST_NULL
);
6633 ahd_outw(ahd
, WAITING_TID_TAIL
, SCB_LIST_NULL
);
6634 ahd_outw(ahd
, MK_MESSAGE_SCB
, SCB_LIST_NULL
);
6635 ahd_outw(ahd
, MK_MESSAGE_SCSIID
, 0xFF);
6636 for (i
= 0; i
< AHD_NUM_TARGETS
; i
++)
6637 ahd_outw(ahd
, WAITING_SCB_TAILS
+ (2 * i
), SCB_LIST_NULL
);
6640 * Nobody is waiting to be DMAed into the QOUTFIFO.
6642 ahd_outw(ahd
, COMPLETE_SCB_HEAD
, SCB_LIST_NULL
);
6643 ahd_outw(ahd
, COMPLETE_SCB_DMAINPROG_HEAD
, SCB_LIST_NULL
);
6644 ahd_outw(ahd
, COMPLETE_DMA_SCB_HEAD
, SCB_LIST_NULL
);
6645 ahd_outw(ahd
, COMPLETE_DMA_SCB_TAIL
, SCB_LIST_NULL
);
6646 ahd_outw(ahd
, COMPLETE_ON_QFREEZE_HEAD
, SCB_LIST_NULL
);
6649 * The Freeze Count is 0.
6651 ahd
->qfreeze_cnt
= 0;
6652 ahd_outw(ahd
, QFREEZE_COUNT
, 0);
6653 ahd_outw(ahd
, KERNEL_QFREEZE_COUNT
, 0);
6656 * Tell the sequencer where it can find our arrays in memory.
6658 busaddr
= ahd
->shared_data_map
.physaddr
;
6659 ahd_outl(ahd
, SHARED_DATA_ADDR
, busaddr
);
6660 ahd_outl(ahd
, QOUTFIFO_NEXT_ADDR
, busaddr
);
6663 * Setup the allowed SCSI Sequences based on operational mode.
6664 * If we are a target, we'll enable select in operations once
6665 * we've had a lun enabled.
6667 scsiseq_template
= ENAUTOATNP
;
6668 if ((ahd
->flags
& AHD_INITIATORROLE
) != 0)
6669 scsiseq_template
|= ENRSELI
;
6670 ahd_outb(ahd
, SCSISEQ_TEMPLATE
, scsiseq_template
);
6672 /* There are no busy SCBs yet. */
6673 for (target
= 0; target
< AHD_NUM_TARGETS
; target
++) {
6676 for (lun
= 0; lun
< AHD_NUM_LUNS_NONPKT
; lun
++)
6677 ahd_unbusy_tcl(ahd
, BUILD_TCL_RAW(target
, 'A', lun
));
6681 * Initialize the group code to command length table.
6682 * Vendor Unique codes are set to 0 so we only capture
6683 * the first byte of the cdb. These can be overridden
6684 * when target mode is enabled.
6686 ahd_outb(ahd
, CMDSIZE_TABLE
, 5);
6687 ahd_outb(ahd
, CMDSIZE_TABLE
+ 1, 9);
6688 ahd_outb(ahd
, CMDSIZE_TABLE
+ 2, 9);
6689 ahd_outb(ahd
, CMDSIZE_TABLE
+ 3, 0);
6690 ahd_outb(ahd
, CMDSIZE_TABLE
+ 4, 15);
6691 ahd_outb(ahd
, CMDSIZE_TABLE
+ 5, 11);
6692 ahd_outb(ahd
, CMDSIZE_TABLE
+ 6, 0);
6693 ahd_outb(ahd
, CMDSIZE_TABLE
+ 7, 0);
6695 /* Tell the sequencer of our initial queue positions */
6696 ahd_set_modes(ahd
, AHD_MODE_CCHAN
, AHD_MODE_CCHAN
);
6697 ahd_outb(ahd
, QOFF_CTLSTA
, SCB_QSIZE_512
);
6698 ahd
->qinfifonext
= 0;
6699 ahd_set_hnscb_qoff(ahd
, ahd
->qinfifonext
);
6700 ahd_set_hescb_qoff(ahd
, 0);
6701 ahd_set_snscb_qoff(ahd
, 0);
6702 ahd_set_sescb_qoff(ahd
, 0);
6703 ahd_set_sdscb_qoff(ahd
, 0);
6706 * Tell the sequencer which SCB will be the next one it receives.
6708 busaddr
= ahd_le32toh(ahd
->next_queued_hscb
->hscb_busaddr
);
6709 ahd_outl(ahd
, NEXT_QUEUED_SCB_ADDR
, busaddr
);
6712 * Default to coalescing disabled.
6714 ahd_outw(ahd
, INT_COALESCING_CMDCOUNT
, 0);
6715 ahd_outw(ahd
, CMDS_PENDING
, 0);
6716 ahd_update_coalescing_values(ahd
, ahd
->int_coalescing_timer
,
6717 ahd
->int_coalescing_maxcmds
,
6718 ahd
->int_coalescing_mincmds
);
6719 ahd_enable_coalescing(ahd
, FALSE
);
6722 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
6724 if (ahd
->features
& AHD_AIC79XXB_SLOWCRC
) {
6725 u_int negodat3
= ahd_inb(ahd
, NEGCONOPTS
);
6727 negodat3
|= ENSLOWCRC
;
6728 ahd_outb(ahd
, NEGCONOPTS
, negodat3
);
6729 negodat3
= ahd_inb(ahd
, NEGCONOPTS
);
6730 if (!(negodat3
& ENSLOWCRC
))
6731 printf("aic79xx: failed to set the SLOWCRC bit\n");
6733 printf("aic79xx: SLOWCRC bit set\n");
6738 * Setup default device and controller settings.
6739 * This should only be called if our probe has
6740 * determined that no configuration data is available.
6743 ahd_default_config(struct ahd_softc
*ahd
)
6750 * Allocate a tstate to house information for our
6751 * initiator presence on the bus as well as the user
6752 * data for any target mode initiator.
6754 if (ahd_alloc_tstate(ahd
, ahd
->our_id
, 'A') == NULL
) {
6755 printf("%s: unable to allocate ahd_tmode_tstate. "
6756 "Failing attach\n", ahd_name(ahd
));
6760 for (targ
= 0; targ
< AHD_NUM_TARGETS
; targ
++) {
6761 struct ahd_devinfo devinfo
;
6762 struct ahd_initiator_tinfo
*tinfo
;
6763 struct ahd_tmode_tstate
*tstate
;
6764 uint16_t target_mask
;
6766 tinfo
= ahd_fetch_transinfo(ahd
, 'A', ahd
->our_id
,
6769 * We support SPC2 and SPI4.
6771 tinfo
->user
.protocol_version
= 4;
6772 tinfo
->user
.transport_version
= 4;
6774 target_mask
= 0x01 << targ
;
6775 ahd
->user_discenable
|= target_mask
;
6776 tstate
->discenable
|= target_mask
;
6777 ahd
->user_tagenable
|= target_mask
;
6778 #ifdef AHD_FORCE_160
6779 tinfo
->user
.period
= AHD_SYNCRATE_DT
;
6781 tinfo
->user
.period
= AHD_SYNCRATE_160
;
6783 tinfo
->user
.offset
= MAX_OFFSET
;
6784 tinfo
->user
.ppr_options
= MSG_EXT_PPR_RD_STRM
6785 | MSG_EXT_PPR_WR_FLOW
6786 | MSG_EXT_PPR_HOLD_MCS
6787 | MSG_EXT_PPR_IU_REQ
6788 | MSG_EXT_PPR_QAS_REQ
6789 | MSG_EXT_PPR_DT_REQ
;
6790 if ((ahd
->features
& AHD_RTI
) != 0)
6791 tinfo
->user
.ppr_options
|= MSG_EXT_PPR_RTI
;
6793 tinfo
->user
.width
= MSG_EXT_WDTR_BUS_16_BIT
;
6796 * Start out Async/Narrow/Untagged and with
6797 * conservative protocol support.
6799 tinfo
->goal
.protocol_version
= 2;
6800 tinfo
->goal
.transport_version
= 2;
6801 tinfo
->curr
.protocol_version
= 2;
6802 tinfo
->curr
.transport_version
= 2;
6803 ahd_compile_devinfo(&devinfo
, ahd
->our_id
,
6804 targ
, CAM_LUN_WILDCARD
,
6805 'A', ROLE_INITIATOR
);
6806 tstate
->tagenable
&= ~target_mask
;
6807 ahd_set_width(ahd
, &devinfo
, MSG_EXT_WDTR_BUS_8_BIT
,
6808 AHD_TRANS_CUR
|AHD_TRANS_GOAL
, /*paused*/TRUE
);
6809 ahd_set_syncrate(ahd
, &devinfo
, /*period*/0, /*offset*/0,
6810 /*ppr_options*/0, AHD_TRANS_CUR
|AHD_TRANS_GOAL
,
6817 * Parse device configuration information.
6820 ahd_parse_cfgdata(struct ahd_softc
*ahd
, struct seeprom_config
*sc
)
6825 max_targ
= sc
->max_targets
& CFMAXTARG
;
6826 ahd
->our_id
= sc
->brtime_id
& CFSCSIID
;
6829 * Allocate a tstate to house information for our
6830 * initiator presence on the bus as well as the user
6831 * data for any target mode initiator.
6833 if (ahd_alloc_tstate(ahd
, ahd
->our_id
, 'A') == NULL
) {
6834 printf("%s: unable to allocate ahd_tmode_tstate. "
6835 "Failing attach\n", ahd_name(ahd
));
6839 for (targ
= 0; targ
< max_targ
; targ
++) {
6840 struct ahd_devinfo devinfo
;
6841 struct ahd_initiator_tinfo
*tinfo
;
6842 struct ahd_transinfo
*user_tinfo
;
6843 struct ahd_tmode_tstate
*tstate
;
6844 uint16_t target_mask
;
6846 tinfo
= ahd_fetch_transinfo(ahd
, 'A', ahd
->our_id
,
6848 user_tinfo
= &tinfo
->user
;
6851 * We support SPC2 and SPI4.
6853 tinfo
->user
.protocol_version
= 4;
6854 tinfo
->user
.transport_version
= 4;
6856 target_mask
= 0x01 << targ
;
6857 ahd
->user_discenable
&= ~target_mask
;
6858 tstate
->discenable
&= ~target_mask
;
6859 ahd
->user_tagenable
&= ~target_mask
;
6860 if (sc
->device_flags
[targ
] & CFDISC
) {
6861 tstate
->discenable
|= target_mask
;
6862 ahd
->user_discenable
|= target_mask
;
6863 ahd
->user_tagenable
|= target_mask
;
6866 * Cannot be packetized without disconnection.
6868 sc
->device_flags
[targ
] &= ~CFPACKETIZED
;
6871 user_tinfo
->ppr_options
= 0;
6872 user_tinfo
->period
= (sc
->device_flags
[targ
] & CFXFER
);
6873 if (user_tinfo
->period
< CFXFER_ASYNC
) {
6874 if (user_tinfo
->period
<= AHD_PERIOD_10MHz
)
6875 user_tinfo
->ppr_options
|= MSG_EXT_PPR_DT_REQ
;
6876 user_tinfo
->offset
= MAX_OFFSET
;
6878 user_tinfo
->offset
= 0;
6879 user_tinfo
->period
= AHD_ASYNC_XFER_PERIOD
;
6881 #ifdef AHD_FORCE_160
6882 if (user_tinfo
->period
<= AHD_SYNCRATE_160
)
6883 user_tinfo
->period
= AHD_SYNCRATE_DT
;
6886 if ((sc
->device_flags
[targ
] & CFPACKETIZED
) != 0) {
6887 user_tinfo
->ppr_options
|= MSG_EXT_PPR_RD_STRM
6888 | MSG_EXT_PPR_WR_FLOW
6889 | MSG_EXT_PPR_HOLD_MCS
6890 | MSG_EXT_PPR_IU_REQ
;
6891 if ((ahd
->features
& AHD_RTI
) != 0)
6892 user_tinfo
->ppr_options
|= MSG_EXT_PPR_RTI
;
6895 if ((sc
->device_flags
[targ
] & CFQAS
) != 0)
6896 user_tinfo
->ppr_options
|= MSG_EXT_PPR_QAS_REQ
;
6898 if ((sc
->device_flags
[targ
] & CFWIDEB
) != 0)
6899 user_tinfo
->width
= MSG_EXT_WDTR_BUS_16_BIT
;
6901 user_tinfo
->width
= MSG_EXT_WDTR_BUS_8_BIT
;
6903 if ((ahd_debug
& AHD_SHOW_MISC
) != 0)
6904 printf("(%d): %x:%x:%x:%x\n", targ
, user_tinfo
->width
,
6905 user_tinfo
->period
, user_tinfo
->offset
,
6906 user_tinfo
->ppr_options
);
6909 * Start out Async/Narrow/Untagged and with
6910 * conservative protocol support.
6912 tstate
->tagenable
&= ~target_mask
;
6913 tinfo
->goal
.protocol_version
= 2;
6914 tinfo
->goal
.transport_version
= 2;
6915 tinfo
->curr
.protocol_version
= 2;
6916 tinfo
->curr
.transport_version
= 2;
6917 ahd_compile_devinfo(&devinfo
, ahd
->our_id
,
6918 targ
, CAM_LUN_WILDCARD
,
6919 'A', ROLE_INITIATOR
);
6920 ahd_set_width(ahd
, &devinfo
, MSG_EXT_WDTR_BUS_8_BIT
,
6921 AHD_TRANS_CUR
|AHD_TRANS_GOAL
, /*paused*/TRUE
);
6922 ahd_set_syncrate(ahd
, &devinfo
, /*period*/0, /*offset*/0,
6923 /*ppr_options*/0, AHD_TRANS_CUR
|AHD_TRANS_GOAL
,
6927 ahd
->flags
&= ~AHD_SPCHK_ENB_A
;
6928 if (sc
->bios_control
& CFSPARITY
)
6929 ahd
->flags
|= AHD_SPCHK_ENB_A
;
6931 ahd
->flags
&= ~AHD_RESET_BUS_A
;
6932 if (sc
->bios_control
& CFRESETB
)
6933 ahd
->flags
|= AHD_RESET_BUS_A
;
6935 ahd
->flags
&= ~AHD_EXTENDED_TRANS_A
;
6936 if (sc
->bios_control
& CFEXTEND
)
6937 ahd
->flags
|= AHD_EXTENDED_TRANS_A
;
6939 ahd
->flags
&= ~AHD_BIOS_ENABLED
;
6940 if ((sc
->bios_control
& CFBIOSSTATE
) == CFBS_ENABLED
)
6941 ahd
->flags
|= AHD_BIOS_ENABLED
;
6943 ahd
->flags
&= ~AHD_STPWLEVEL_A
;
6944 if ((sc
->adapter_control
& CFSTPWLEVEL
) != 0)
6945 ahd
->flags
|= AHD_STPWLEVEL_A
;
6951 * Parse device configuration information.
6954 ahd_parse_vpddata(struct ahd_softc
*ahd
, struct vpd_config
*vpd
)
6958 error
= ahd_verify_vpd_cksum(vpd
);
6961 if ((vpd
->bios_flags
& VPDBOOTHOST
) != 0)
6962 ahd
->flags
|= AHD_BOOT_CHANNEL
;
6967 ahd_intr_enable(struct ahd_softc
*ahd
, int enable
)
6971 hcntrl
= ahd_inb(ahd
, HCNTRL
);
6973 ahd
->pause
&= ~INTEN
;
6974 ahd
->unpause
&= ~INTEN
;
6977 ahd
->pause
|= INTEN
;
6978 ahd
->unpause
|= INTEN
;
6980 ahd_outb(ahd
, HCNTRL
, hcntrl
);
6984 ahd_update_coalescing_values(struct ahd_softc
*ahd
, u_int timer
, u_int maxcmds
,
6987 if (timer
> AHD_TIMER_MAX_US
)
6988 timer
= AHD_TIMER_MAX_US
;
6989 ahd
->int_coalescing_timer
= timer
;
6991 if (maxcmds
> AHD_INT_COALESCING_MAXCMDS_MAX
)
6992 maxcmds
= AHD_INT_COALESCING_MAXCMDS_MAX
;
6993 if (mincmds
> AHD_INT_COALESCING_MINCMDS_MAX
)
6994 mincmds
= AHD_INT_COALESCING_MINCMDS_MAX
;
6995 ahd
->int_coalescing_maxcmds
= maxcmds
;
6996 ahd_outw(ahd
, INT_COALESCING_TIMER
, timer
/ AHD_TIMER_US_PER_TICK
);
6997 ahd_outb(ahd
, INT_COALESCING_MAXCMDS
, -maxcmds
);
6998 ahd_outb(ahd
, INT_COALESCING_MINCMDS
, -mincmds
);
7002 ahd_enable_coalescing(struct ahd_softc
*ahd
, int enable
)
7005 ahd
->hs_mailbox
&= ~ENINT_COALESCE
;
7007 ahd
->hs_mailbox
|= ENINT_COALESCE
;
7008 ahd_outb(ahd
, HS_MAILBOX
, ahd
->hs_mailbox
);
7009 ahd_flush_device_writes(ahd
);
7010 ahd_run_qoutfifo(ahd
);
7014 * Ensure that the card is paused in a location
7015 * outside of all critical sections and that all
7016 * pending work is completed prior to returning.
7017 * This routine should only be called from outside
7018 * an interrupt context.
7021 ahd_pause_and_flushwork(struct ahd_softc
*ahd
)
7027 ahd
->flags
|= AHD_ALL_INTERRUPTS
;
7030 * Freeze the outgoing selections. We do this only
7031 * until we are safely paused without further selections
7035 ahd_outw(ahd
, KERNEL_QFREEZE_COUNT
, ahd
->qfreeze_cnt
);
7036 ahd_outb(ahd
, SEQ_FLAGS2
, ahd_inb(ahd
, SEQ_FLAGS2
) | SELECTOUT_QFROZEN
);
7041 * Give the sequencer some time to service
7042 * any active selections.
7048 intstat
= ahd_inb(ahd
, INTSTAT
);
7049 if ((intstat
& INT_PEND
) == 0) {
7050 ahd_clear_critical_section(ahd
);
7051 intstat
= ahd_inb(ahd
, INTSTAT
);
7054 && (intstat
!= 0xFF || (ahd
->features
& AHD_REMOVABLE
) == 0)
7055 && ((intstat
& INT_PEND
) != 0
7056 || (ahd_inb(ahd
, SCSISEQ0
) & ENSELO
) != 0
7057 || (ahd_inb(ahd
, SSTAT0
) & (SELDO
|SELINGO
)) != 0));
7059 if (maxloops
== 0) {
7060 printf("Infinite interrupt loop, INTSTAT = %x",
7061 ahd_inb(ahd
, INTSTAT
));
7064 ahd_outw(ahd
, KERNEL_QFREEZE_COUNT
, ahd
->qfreeze_cnt
);
7066 ahd_flush_qoutfifo(ahd
);
7068 ahd
->flags
&= ~AHD_ALL_INTERRUPTS
;
7072 ahd_suspend(struct ahd_softc
*ahd
)
7075 ahd_pause_and_flushwork(ahd
);
7077 if (LIST_FIRST(&ahd
->pending_scbs
) != NULL
) {
7086 ahd_resume(struct ahd_softc
*ahd
)
7089 ahd_reset(ahd
, /*reinit*/TRUE
);
7090 ahd_intr_enable(ahd
, TRUE
);
7095 /************************** Busy Target Table *********************************/
7097 * Set SCBPTR to the SCB that contains the busy
7098 * table entry for TCL. Return the offset into
7099 * the SCB that contains the entry for TCL.
7100 * saved_scbid is dereferenced and set to the
7101 * scbid that should be restored once manipualtion
7102 * of the TCL entry is complete.
7104 static __inline u_int
7105 ahd_index_busy_tcl(struct ahd_softc
*ahd
, u_int
*saved_scbid
, u_int tcl
)
7108 * Index to the SCB that contains the busy entry.
7110 AHD_ASSERT_MODES(ahd
, AHD_MODE_SCSI_MSK
, AHD_MODE_SCSI_MSK
);
7111 *saved_scbid
= ahd_get_scbptr(ahd
);
7112 ahd_set_scbptr(ahd
, TCL_LUN(tcl
)
7113 | ((TCL_TARGET_OFFSET(tcl
) & 0xC) << 4));
7116 * And now calculate the SCB offset to the entry.
7117 * Each entry is 2 bytes wide, hence the
7118 * multiplication by 2.
7120 return (((TCL_TARGET_OFFSET(tcl
) & 0x3) << 1) + SCB_DISCONNECTED_LISTS
);
7124 * Return the untagged transaction id for a given target/channel lun.
7127 ahd_find_busy_tcl(struct ahd_softc
*ahd
, u_int tcl
)
7133 scb_offset
= ahd_index_busy_tcl(ahd
, &saved_scbptr
, tcl
);
7134 scbid
= ahd_inw_scbram(ahd
, scb_offset
);
7135 ahd_set_scbptr(ahd
, saved_scbptr
);
7140 ahd_busy_tcl(struct ahd_softc
*ahd
, u_int tcl
, u_int scbid
)
7145 scb_offset
= ahd_index_busy_tcl(ahd
, &saved_scbptr
, tcl
);
7146 ahd_outw(ahd
, scb_offset
, scbid
);
7147 ahd_set_scbptr(ahd
, saved_scbptr
);
7150 /************************** SCB and SCB queue management **********************/
7152 ahd_match_scb(struct ahd_softc
*ahd
, struct scb
*scb
, int target
,
7153 char channel
, int lun
, u_int tag
, role_t role
)
7155 int targ
= SCB_GET_TARGET(ahd
, scb
);
7156 char chan
= SCB_GET_CHANNEL(ahd
, scb
);
7157 int slun
= SCB_GET_LUN(scb
);
7160 match
= ((chan
== channel
) || (channel
== ALL_CHANNELS
));
7162 match
= ((targ
== target
) || (target
== CAM_TARGET_WILDCARD
));
7164 match
= ((lun
== slun
) || (lun
== CAM_LUN_WILDCARD
));
7166 #ifdef AHD_TARGET_MODE
7169 group
= XPT_FC_GROUP(scb
->io_ctx
->ccb_h
.func_code
);
7170 if (role
== ROLE_INITIATOR
) {
7171 match
= (group
!= XPT_FC_GROUP_TMODE
)
7172 && ((tag
== SCB_GET_TAG(scb
))
7173 || (tag
== SCB_LIST_NULL
));
7174 } else if (role
== ROLE_TARGET
) {
7175 match
= (group
== XPT_FC_GROUP_TMODE
)
7176 && ((tag
== scb
->io_ctx
->csio
.tag_id
)
7177 || (tag
== SCB_LIST_NULL
));
7179 #else /* !AHD_TARGET_MODE */
7180 match
= ((tag
== SCB_GET_TAG(scb
)) || (tag
== SCB_LIST_NULL
));
7181 #endif /* AHD_TARGET_MODE */
7188 ahd_freeze_devq(struct ahd_softc
*ahd
, struct scb
*scb
)
7194 target
= SCB_GET_TARGET(ahd
, scb
);
7195 lun
= SCB_GET_LUN(scb
);
7196 channel
= SCB_GET_CHANNEL(ahd
, scb
);
7198 ahd_search_qinfifo(ahd
, target
, channel
, lun
,
7199 /*tag*/SCB_LIST_NULL
, ROLE_UNKNOWN
,
7200 CAM_REQUEUE_REQ
, SEARCH_COMPLETE
);
7202 ahd_platform_freeze_devq(ahd
, scb
);
7206 ahd_qinfifo_requeue_tail(struct ahd_softc
*ahd
, struct scb
*scb
)
7208 struct scb
*prev_scb
;
7209 ahd_mode_state saved_modes
;
7211 saved_modes
= ahd_save_modes(ahd
);
7212 ahd_set_modes(ahd
, AHD_MODE_CCHAN
, AHD_MODE_CCHAN
);
7214 if (ahd_qinfifo_count(ahd
) != 0) {
7218 prev_pos
= AHD_QIN_WRAP(ahd
->qinfifonext
- 1);
7219 prev_tag
= ahd
->qinfifo
[prev_pos
];
7220 prev_scb
= ahd_lookup_scb(ahd
, prev_tag
);
7222 ahd_qinfifo_requeue(ahd
, prev_scb
, scb
);
7223 ahd_set_hnscb_qoff(ahd
, ahd
->qinfifonext
);
7224 ahd_restore_modes(ahd
, saved_modes
);
7228 ahd_qinfifo_requeue(struct ahd_softc
*ahd
, struct scb
*prev_scb
,
7231 if (prev_scb
== NULL
) {
7234 busaddr
= ahd_le32toh(scb
->hscb
->hscb_busaddr
);
7235 ahd_outl(ahd
, NEXT_QUEUED_SCB_ADDR
, busaddr
);
7237 prev_scb
->hscb
->next_hscb_busaddr
= scb
->hscb
->hscb_busaddr
;
7238 ahd_sync_scb(ahd
, prev_scb
,
7239 BUS_DMASYNC_PREREAD
|BUS_DMASYNC_PREWRITE
);
7241 ahd
->qinfifo
[AHD_QIN_WRAP(ahd
->qinfifonext
)] = SCB_GET_TAG(scb
);
7243 scb
->hscb
->next_hscb_busaddr
= ahd
->next_queued_hscb
->hscb_busaddr
;
7244 ahd_sync_scb(ahd
, scb
, BUS_DMASYNC_PREREAD
|BUS_DMASYNC_PREWRITE
);
7248 ahd_qinfifo_count(struct ahd_softc
*ahd
)
7252 u_int wrap_qinfifonext
;
7254 AHD_ASSERT_MODES(ahd
, AHD_MODE_CCHAN_MSK
, AHD_MODE_CCHAN_MSK
);
7255 qinpos
= ahd_get_snscb_qoff(ahd
);
7256 wrap_qinpos
= AHD_QIN_WRAP(qinpos
);
7257 wrap_qinfifonext
= AHD_QIN_WRAP(ahd
->qinfifonext
);
7258 if (wrap_qinfifonext
>= wrap_qinpos
)
7259 return (wrap_qinfifonext
- wrap_qinpos
);
7261 return (wrap_qinfifonext
7262 + NUM_ELEMENTS(ahd
->qinfifo
) - wrap_qinpos
);
7266 ahd_reset_cmds_pending(struct ahd_softc
*ahd
)
7269 ahd_mode_state saved_modes
;
7272 saved_modes
= ahd_save_modes(ahd
);
7273 ahd_set_modes(ahd
, AHD_MODE_CCHAN
, AHD_MODE_CCHAN
);
7276 * Don't count any commands as outstanding that the
7277 * sequencer has already marked for completion.
7279 ahd_flush_qoutfifo(ahd
);
7282 LIST_FOREACH(scb
, &ahd
->pending_scbs
, pending_links
) {
7285 ahd_outw(ahd
, CMDS_PENDING
, pending_cmds
- ahd_qinfifo_count(ahd
));
7286 ahd_restore_modes(ahd
, saved_modes
);
7287 ahd
->flags
&= ~AHD_UPDATE_PEND_CMDS
;
7291 ahd_done_with_status(struct ahd_softc
*ahd
, struct scb
*scb
, uint32_t status
)
7296 ostat
= ahd_get_transaction_status(scb
);
7297 if (ostat
== CAM_REQ_INPROG
)
7298 ahd_set_transaction_status(scb
, status
);
7299 cstat
= ahd_get_transaction_status(scb
);
7300 if (cstat
!= CAM_REQ_CMP
)
7301 ahd_freeze_scb(scb
);
7306 ahd_search_qinfifo(struct ahd_softc
*ahd
, int target
, char channel
,
7307 int lun
, u_int tag
, role_t role
, uint32_t status
,
7308 ahd_search_action action
)
7311 struct scb
*mk_msg_scb
;
7312 struct scb
*prev_scb
;
7313 ahd_mode_state saved_modes
;
7326 /* Must be in CCHAN mode */
7327 saved_modes
= ahd_save_modes(ahd
);
7328 ahd_set_modes(ahd
, AHD_MODE_CCHAN
, AHD_MODE_CCHAN
);
7331 * Halt any pending SCB DMA. The sequencer will reinitiate
7332 * this dma if the qinfifo is not empty once we unpause.
7334 if ((ahd_inb(ahd
, CCSCBCTL
) & (CCARREN
|CCSCBEN
|CCSCBDIR
))
7335 == (CCARREN
|CCSCBEN
|CCSCBDIR
)) {
7336 ahd_outb(ahd
, CCSCBCTL
,
7337 ahd_inb(ahd
, CCSCBCTL
) & ~(CCARREN
|CCSCBEN
));
7338 while ((ahd_inb(ahd
, CCSCBCTL
) & (CCARREN
|CCSCBEN
)) != 0)
7341 /* Determine sequencer's position in the qinfifo. */
7342 qintail
= AHD_QIN_WRAP(ahd
->qinfifonext
);
7343 qinstart
= ahd_get_snscb_qoff(ahd
);
7344 qinpos
= AHD_QIN_WRAP(qinstart
);
7348 if (action
== SEARCH_PRINT
) {
7349 printf("qinstart = %d qinfifonext = %d\nQINFIFO:",
7350 qinstart
, ahd
->qinfifonext
);
7354 * Start with an empty queue. Entries that are not chosen
7355 * for removal will be re-added to the queue as we go.
7357 ahd
->qinfifonext
= qinstart
;
7358 busaddr
= ahd_le32toh(ahd
->next_queued_hscb
->hscb_busaddr
);
7359 ahd_outl(ahd
, NEXT_QUEUED_SCB_ADDR
, busaddr
);
7361 while (qinpos
!= qintail
) {
7362 scb
= ahd_lookup_scb(ahd
, ahd
->qinfifo
[qinpos
]);
7364 printf("qinpos = %d, SCB index = %d\n",
7365 qinpos
, ahd
->qinfifo
[qinpos
]);
7369 if (ahd_match_scb(ahd
, scb
, target
, channel
, lun
, tag
, role
)) {
7371 * We found an scb that needs to be acted on.
7375 case SEARCH_COMPLETE
:
7376 if ((scb
->flags
& SCB_ACTIVE
) == 0)
7377 printf("Inactive SCB in qinfifo\n");
7378 ahd_done_with_status(ahd
, scb
, status
);
7383 printf(" 0x%x", ahd
->qinfifo
[qinpos
]);
7386 ahd_qinfifo_requeue(ahd
, prev_scb
, scb
);
7391 ahd_qinfifo_requeue(ahd
, prev_scb
, scb
);
7394 qinpos
= AHD_QIN_WRAP(qinpos
+1);
7397 ahd_set_hnscb_qoff(ahd
, ahd
->qinfifonext
);
7399 if (action
== SEARCH_PRINT
)
7400 printf("\nWAITING_TID_QUEUES:\n");
7403 * Search waiting for selection lists. We traverse the
7404 * list of "their ids" waiting for selection and, if
7405 * appropriate, traverse the SCBs of each "their id"
7406 * looking for matches.
7408 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
7409 seq_flags2
= ahd_inb(ahd
, SEQ_FLAGS2
);
7410 if ((seq_flags2
& PENDING_MK_MESSAGE
) != 0) {
7411 scbid
= ahd_inw(ahd
, MK_MESSAGE_SCB
);
7412 mk_msg_scb
= ahd_lookup_scb(ahd
, scbid
);
7415 savedscbptr
= ahd_get_scbptr(ahd
);
7416 tid_next
= ahd_inw(ahd
, WAITING_TID_HEAD
);
7417 tid_prev
= SCB_LIST_NULL
;
7419 for (scbid
= tid_next
; !SCBID_IS_NULL(scbid
); scbid
= tid_next
) {
7424 if (targets
> AHD_NUM_TARGETS
)
7425 panic("TID LIST LOOP");
7427 if (scbid
>= ahd
->scb_data
.numscbs
) {
7428 printf("%s: Waiting TID List inconsistency. "
7429 "SCB index == 0x%x, yet numscbs == 0x%x.",
7430 ahd_name(ahd
), scbid
, ahd
->scb_data
.numscbs
);
7431 ahd_dump_card_state(ahd
);
7432 panic("for safety");
7434 scb
= ahd_lookup_scb(ahd
, scbid
);
7436 printf("%s: SCB = 0x%x Not Active!\n",
7437 ahd_name(ahd
), scbid
);
7438 panic("Waiting TID List traversal\n");
7440 ahd_set_scbptr(ahd
, scbid
);
7441 tid_next
= ahd_inw_scbram(ahd
, SCB_NEXT2
);
7442 if (ahd_match_scb(ahd
, scb
, target
, channel
, CAM_LUN_WILDCARD
,
7443 SCB_LIST_NULL
, ROLE_UNKNOWN
) == 0) {
7449 * We found a list of scbs that needs to be searched.
7451 if (action
== SEARCH_PRINT
)
7452 printf(" %d ( ", SCB_GET_TARGET(ahd
, scb
));
7454 found
+= ahd_search_scb_list(ahd
, target
, channel
,
7455 lun
, tag
, role
, status
,
7456 action
, &tid_head
, &tid_tail
,
7457 SCB_GET_TARGET(ahd
, scb
));
7459 * Check any MK_MESSAGE SCB that is still waiting to
7460 * enter this target's waiting for selection queue.
7462 if (mk_msg_scb
!= NULL
7463 && ahd_match_scb(ahd
, mk_msg_scb
, target
, channel
,
7467 * We found an scb that needs to be acted on.
7471 case SEARCH_COMPLETE
:
7472 if ((mk_msg_scb
->flags
& SCB_ACTIVE
) == 0)
7473 printf("Inactive SCB pending MK_MSG\n");
7474 ahd_done_with_status(ahd
, mk_msg_scb
, status
);
7480 printf("Removing MK_MSG scb\n");
7483 * Reset our tail to the tail of the
7484 * main per-target list.
7486 tail_offset
= WAITING_SCB_TAILS
7487 + (2 * SCB_GET_TARGET(ahd
, mk_msg_scb
));
7488 ahd_outw(ahd
, tail_offset
, tid_tail
);
7490 seq_flags2
&= ~PENDING_MK_MESSAGE
;
7491 ahd_outb(ahd
, SEQ_FLAGS2
, seq_flags2
);
7492 ahd_outw(ahd
, CMDS_PENDING
,
7493 ahd_inw(ahd
, CMDS_PENDING
)-1);
7498 printf(" 0x%x", SCB_GET_TAG(scb
));
7505 if (mk_msg_scb
!= NULL
7506 && SCBID_IS_NULL(tid_head
)
7507 && ahd_match_scb(ahd
, scb
, target
, channel
, CAM_LUN_WILDCARD
,
7508 SCB_LIST_NULL
, ROLE_UNKNOWN
)) {
7511 * When removing the last SCB for a target
7512 * queue with a pending MK_MESSAGE scb, we
7513 * must queue the MK_MESSAGE scb.
7515 printf("Queueing mk_msg_scb\n");
7516 tid_head
= ahd_inw(ahd
, MK_MESSAGE_SCB
);
7517 seq_flags2
&= ~PENDING_MK_MESSAGE
;
7518 ahd_outb(ahd
, SEQ_FLAGS2
, seq_flags2
);
7521 if (tid_head
!= scbid
)
7522 ahd_stitch_tid_list(ahd
, tid_prev
, tid_head
, tid_next
);
7523 if (!SCBID_IS_NULL(tid_head
))
7524 tid_prev
= tid_head
;
7525 if (action
== SEARCH_PRINT
)
7529 /* Restore saved state. */
7530 ahd_set_scbptr(ahd
, savedscbptr
);
7531 ahd_restore_modes(ahd
, saved_modes
);
7536 ahd_search_scb_list(struct ahd_softc
*ahd
, int target
, char channel
,
7537 int lun
, u_int tag
, role_t role
, uint32_t status
,
7538 ahd_search_action action
, u_int
*list_head
,
7539 u_int
*list_tail
, u_int tid
)
7547 AHD_ASSERT_MODES(ahd
, AHD_MODE_SCSI_MSK
, AHD_MODE_SCSI_MSK
);
7549 prev
= SCB_LIST_NULL
;
7551 *list_tail
= SCB_LIST_NULL
;
7552 for (scbid
= next
; !SCBID_IS_NULL(scbid
); scbid
= next
) {
7553 if (scbid
>= ahd
->scb_data
.numscbs
) {
7554 printf("%s:SCB List inconsistency. "
7555 "SCB == 0x%x, yet numscbs == 0x%x.",
7556 ahd_name(ahd
), scbid
, ahd
->scb_data
.numscbs
);
7557 ahd_dump_card_state(ahd
);
7558 panic("for safety");
7560 scb
= ahd_lookup_scb(ahd
, scbid
);
7562 printf("%s: SCB = %d Not Active!\n",
7563 ahd_name(ahd
), scbid
);
7564 panic("Waiting List traversal\n");
7566 ahd_set_scbptr(ahd
, scbid
);
7568 next
= ahd_inw_scbram(ahd
, SCB_NEXT
);
7569 if (ahd_match_scb(ahd
, scb
, target
, channel
,
7570 lun
, SCB_LIST_NULL
, role
) == 0) {
7576 case SEARCH_COMPLETE
:
7577 if ((scb
->flags
& SCB_ACTIVE
) == 0)
7578 printf("Inactive SCB in Waiting List\n");
7579 ahd_done_with_status(ahd
, scb
, status
);
7582 ahd_rem_wscb(ahd
, scbid
, prev
, next
, tid
);
7584 if (SCBID_IS_NULL(prev
))
7588 printf("0x%x ", scbid
);
7593 if (found
> AHD_SCB_MAX
)
7594 panic("SCB LIST LOOP");
7596 if (action
== SEARCH_COMPLETE
7597 || action
== SEARCH_REMOVE
)
7598 ahd_outw(ahd
, CMDS_PENDING
, ahd_inw(ahd
, CMDS_PENDING
) - found
);
7603 ahd_stitch_tid_list(struct ahd_softc
*ahd
, u_int tid_prev
,
7604 u_int tid_cur
, u_int tid_next
)
7606 AHD_ASSERT_MODES(ahd
, AHD_MODE_SCSI_MSK
, AHD_MODE_SCSI_MSK
);
7608 if (SCBID_IS_NULL(tid_cur
)) {
7610 /* Bypass current TID list */
7611 if (SCBID_IS_NULL(tid_prev
)) {
7612 ahd_outw(ahd
, WAITING_TID_HEAD
, tid_next
);
7614 ahd_set_scbptr(ahd
, tid_prev
);
7615 ahd_outw(ahd
, SCB_NEXT2
, tid_next
);
7617 if (SCBID_IS_NULL(tid_next
))
7618 ahd_outw(ahd
, WAITING_TID_TAIL
, tid_prev
);
7621 /* Stitch through tid_cur */
7622 if (SCBID_IS_NULL(tid_prev
)) {
7623 ahd_outw(ahd
, WAITING_TID_HEAD
, tid_cur
);
7625 ahd_set_scbptr(ahd
, tid_prev
);
7626 ahd_outw(ahd
, SCB_NEXT2
, tid_cur
);
7628 ahd_set_scbptr(ahd
, tid_cur
);
7629 ahd_outw(ahd
, SCB_NEXT2
, tid_next
);
7631 if (SCBID_IS_NULL(tid_next
))
7632 ahd_outw(ahd
, WAITING_TID_TAIL
, tid_cur
);
7637 * Manipulate the waiting for selection list and return the
7638 * scb that follows the one that we remove.
7641 ahd_rem_wscb(struct ahd_softc
*ahd
, u_int scbid
,
7642 u_int prev
, u_int next
, u_int tid
)
7646 AHD_ASSERT_MODES(ahd
, AHD_MODE_SCSI_MSK
, AHD_MODE_SCSI_MSK
);
7647 if (!SCBID_IS_NULL(prev
)) {
7648 ahd_set_scbptr(ahd
, prev
);
7649 ahd_outw(ahd
, SCB_NEXT
, next
);
7653 * SCBs that have MK_MESSAGE set in them may
7654 * cause the tail pointer to be updated without
7655 * setting the next pointer of the previous tail.
7656 * Only clear the tail if the removed SCB was
7659 tail_offset
= WAITING_SCB_TAILS
+ (2 * tid
);
7660 if (SCBID_IS_NULL(next
)
7661 && ahd_inw(ahd
, tail_offset
) == scbid
)
7662 ahd_outw(ahd
, tail_offset
, prev
);
7664 ahd_add_scb_to_free_list(ahd
, scbid
);
7669 * Add the SCB as selected by SCBPTR onto the on chip list of
7670 * free hardware SCBs. This list is empty/unused if we are not
7671 * performing SCB paging.
7674 ahd_add_scb_to_free_list(struct ahd_softc
*ahd
, u_int scbid
)
7676 /* XXX Need some other mechanism to designate "free". */
7678 * Invalidate the tag so that our abort
7679 * routines don't think it's active.
7680 ahd_outb(ahd, SCB_TAG, SCB_LIST_NULL);
7684 /******************************** Error Handling ******************************/
7686 * Abort all SCBs that match the given description (target/channel/lun/tag),
7687 * setting their status to the passed in status if the status has not already
7688 * been modified from CAM_REQ_INPROG. This routine assumes that the sequencer
7689 * is paused before it is called.
7692 ahd_abort_scbs(struct ahd_softc
*ahd
, int target
, char channel
,
7693 int lun
, u_int tag
, role_t role
, uint32_t status
)
7696 struct scb
*scbp_next
;
7702 ahd_mode_state saved_modes
;
7704 /* restore this when we're done */
7705 saved_modes
= ahd_save_modes(ahd
);
7706 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
7708 found
= ahd_search_qinfifo(ahd
, target
, channel
, lun
, SCB_LIST_NULL
,
7709 role
, CAM_REQUEUE_REQ
, SEARCH_COMPLETE
);
7712 * Clean out the busy target table for any untagged commands.
7716 if (target
!= CAM_TARGET_WILDCARD
) {
7723 if (lun
== CAM_LUN_WILDCARD
) {
7725 maxlun
= AHD_NUM_LUNS_NONPKT
;
7726 } else if (lun
>= AHD_NUM_LUNS_NONPKT
) {
7727 minlun
= maxlun
= 0;
7733 if (role
!= ROLE_TARGET
) {
7734 for (;i
< maxtarget
; i
++) {
7735 for (j
= minlun
;j
< maxlun
; j
++) {
7739 tcl
= BUILD_TCL_RAW(i
, 'A', j
);
7740 scbid
= ahd_find_busy_tcl(ahd
, tcl
);
7741 scbp
= ahd_lookup_scb(ahd
, scbid
);
7743 || ahd_match_scb(ahd
, scbp
, target
, channel
,
7744 lun
, tag
, role
) == 0)
7746 ahd_unbusy_tcl(ahd
, BUILD_TCL_RAW(i
, 'A', j
));
7752 * Don't abort commands that have already completed,
7753 * but haven't quite made it up to the host yet.
7755 ahd_flush_qoutfifo(ahd
);
7758 * Go through the pending CCB list and look for
7759 * commands for this target that are still active.
7760 * These are other tagged commands that were
7761 * disconnected when the reset occurred.
7763 scbp_next
= LIST_FIRST(&ahd
->pending_scbs
);
7764 while (scbp_next
!= NULL
) {
7766 scbp_next
= LIST_NEXT(scbp
, pending_links
);
7767 if (ahd_match_scb(ahd
, scbp
, target
, channel
, lun
, tag
, role
)) {
7770 ostat
= ahd_get_transaction_status(scbp
);
7771 if (ostat
== CAM_REQ_INPROG
)
7772 ahd_set_transaction_status(scbp
, status
);
7773 if (ahd_get_transaction_status(scbp
) != CAM_REQ_CMP
)
7774 ahd_freeze_scb(scbp
);
7775 if ((scbp
->flags
& SCB_ACTIVE
) == 0)
7776 printf("Inactive SCB on pending list\n");
7777 ahd_done(ahd
, scbp
);
7781 ahd_restore_modes(ahd
, saved_modes
);
7782 ahd_platform_abort_scbs(ahd
, target
, channel
, lun
, tag
, role
, status
);
7783 ahd
->flags
|= AHD_UPDATE_PEND_CMDS
;
7788 ahd_reset_current_bus(struct ahd_softc
*ahd
)
7792 AHD_ASSERT_MODES(ahd
, AHD_MODE_SCSI_MSK
, AHD_MODE_SCSI_MSK
);
7793 ahd_outb(ahd
, SIMODE1
, ahd_inb(ahd
, SIMODE1
) & ~ENSCSIRST
);
7794 scsiseq
= ahd_inb(ahd
, SCSISEQ0
) & ~(ENSELO
|ENARBO
|SCSIRSTO
);
7795 ahd_outb(ahd
, SCSISEQ0
, scsiseq
| SCSIRSTO
);
7796 ahd_flush_device_writes(ahd
);
7797 ahd_delay(AHD_BUSRESET_DELAY
);
7798 /* Turn off the bus reset */
7799 ahd_outb(ahd
, SCSISEQ0
, scsiseq
);
7800 ahd_flush_device_writes(ahd
);
7801 ahd_delay(AHD_BUSRESET_DELAY
);
7802 if ((ahd
->bugs
& AHD_SCSIRST_BUG
) != 0) {
7805 * Certain chip state is not cleared for
7806 * SCSI bus resets that we initiate, so
7807 * we must reset the chip.
7809 ahd_reset(ahd
, /*reinit*/TRUE
);
7810 ahd_intr_enable(ahd
, /*enable*/TRUE
);
7811 AHD_ASSERT_MODES(ahd
, AHD_MODE_SCSI_MSK
, AHD_MODE_SCSI_MSK
);
7814 ahd_clear_intstat(ahd
);
7818 ahd_reset_channel(struct ahd_softc
*ahd
, char channel
, int initiate_reset
)
7820 struct ahd_devinfo devinfo
;
7830 * Check if the last bus reset is cleared
7832 if (ahd
->flags
& AHD_BUS_RESET_ACTIVE
) {
7833 printf("%s: bus reset still active\n",
7837 ahd
->flags
|= AHD_BUS_RESET_ACTIVE
;
7839 ahd
->pending_device
= NULL
;
7841 ahd_compile_devinfo(&devinfo
,
7842 CAM_TARGET_WILDCARD
,
7843 CAM_TARGET_WILDCARD
,
7845 channel
, ROLE_UNKNOWN
);
7848 /* Make sure the sequencer is in a safe location. */
7849 ahd_clear_critical_section(ahd
);
7852 * Run our command complete fifos to ensure that we perform
7853 * completion processing on any commands that 'completed'
7854 * before the reset occurred.
7856 ahd_run_qoutfifo(ahd
);
7857 #ifdef AHD_TARGET_MODE
7858 if ((ahd
->flags
& AHD_TARGETROLE
) != 0) {
7859 ahd_run_tqinfifo(ahd
, /*paused*/TRUE
);
7862 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
7865 * Disable selections so no automatic hardware
7866 * functions will modify chip state.
7868 ahd_outb(ahd
, SCSISEQ0
, 0);
7869 ahd_outb(ahd
, SCSISEQ1
, 0);
7872 * Safely shut down our DMA engines. Always start with
7873 * the FIFO that is not currently active (if any are
7874 * actively connected).
7876 next_fifo
= fifo
= ahd_inb(ahd
, DFFSTAT
) & CURRFIFO
;
7877 if (next_fifo
> CURRFIFO_1
)
7878 /* If disconneced, arbitrarily start with FIFO1. */
7879 next_fifo
= fifo
= 0;
7881 next_fifo
^= CURRFIFO_1
;
7882 ahd_set_modes(ahd
, next_fifo
, next_fifo
);
7883 ahd_outb(ahd
, DFCNTRL
,
7884 ahd_inb(ahd
, DFCNTRL
) & ~(SCSIEN
|HDMAEN
));
7885 while ((ahd_inb(ahd
, DFCNTRL
) & HDMAENACK
) != 0)
7888 * Set CURRFIFO to the now inactive channel.
7890 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
7891 ahd_outb(ahd
, DFFSTAT
, next_fifo
);
7892 } while (next_fifo
!= fifo
);
7895 * Reset the bus if we are initiating this reset
7897 ahd_clear_msg_state(ahd
);
7898 ahd_outb(ahd
, SIMODE1
,
7899 ahd_inb(ahd
, SIMODE1
) & ~(ENBUSFREE
|ENSCSIRST
));
7902 ahd_reset_current_bus(ahd
);
7904 ahd_clear_intstat(ahd
);
7907 * Clean up all the state information for the
7908 * pending transactions on this bus.
7910 found
= ahd_abort_scbs(ahd
, CAM_TARGET_WILDCARD
, channel
,
7911 CAM_LUN_WILDCARD
, SCB_LIST_NULL
,
7912 ROLE_UNKNOWN
, CAM_SCSI_BUS_RESET
);
7915 * Cleanup anything left in the FIFOs.
7917 ahd_clear_fifo(ahd
, 0);
7918 ahd_clear_fifo(ahd
, 1);
7921 * Reenable selections
7923 ahd_outb(ahd
, SIMODE1
, ahd_inb(ahd
, SIMODE1
) | ENSCSIRST
);
7924 scsiseq
= ahd_inb(ahd
, SCSISEQ_TEMPLATE
);
7925 ahd_outb(ahd
, SCSISEQ1
, scsiseq
& (ENSELI
|ENRSELI
|ENAUTOATNP
));
7927 max_scsiid
= (ahd
->features
& AHD_WIDE
) ? 15 : 7;
7928 #ifdef AHD_TARGET_MODE
7930 * Send an immediate notify ccb to all target more peripheral
7931 * drivers affected by this action.
7933 for (target
= 0; target
<= max_scsiid
; target
++) {
7934 struct ahd_tmode_tstate
* tstate
;
7937 tstate
= ahd
->enabled_targets
[target
];
7940 for (lun
= 0; lun
< AHD_NUM_LUNS
; lun
++) {
7941 struct ahd_tmode_lstate
* lstate
;
7943 lstate
= tstate
->enabled_luns
[lun
];
7947 ahd_queue_lstate_event(ahd
, lstate
, CAM_TARGET_WILDCARD
,
7948 EVENT_TYPE_BUS_RESET
, /*arg*/0);
7949 ahd_send_lstate_events(ahd
, lstate
);
7953 /* Notify the XPT that a bus reset occurred */
7954 ahd_send_async(ahd
, devinfo
.channel
, CAM_TARGET_WILDCARD
,
7955 CAM_LUN_WILDCARD
, AC_BUS_RESET
, NULL
);
7958 * Revert to async/narrow transfers until we renegotiate.
7960 for (target
= 0; target
<= max_scsiid
; target
++) {
7962 if (ahd
->enabled_targets
[target
] == NULL
)
7964 for (initiator
= 0; initiator
<= max_scsiid
; initiator
++) {
7965 struct ahd_devinfo devinfo
;
7967 ahd_compile_devinfo(&devinfo
, target
, initiator
,
7970 ahd_set_width(ahd
, &devinfo
, MSG_EXT_WDTR_BUS_8_BIT
,
7971 AHD_TRANS_CUR
, /*paused*/TRUE
);
7972 ahd_set_syncrate(ahd
, &devinfo
, /*period*/0,
7973 /*offset*/0, /*ppr_options*/0,
7974 AHD_TRANS_CUR
, /*paused*/TRUE
);
7983 /**************************** Statistics Processing ***************************/
7985 ahd_stat_timer(void *arg
)
7987 struct ahd_softc
*ahd
= arg
;
7993 enint_coal
= ahd
->hs_mailbox
& ENINT_COALESCE
;
7994 if (ahd
->cmdcmplt_total
> ahd
->int_coalescing_threshold
)
7995 enint_coal
|= ENINT_COALESCE
;
7996 else if (ahd
->cmdcmplt_total
< ahd
->int_coalescing_stop_threshold
)
7997 enint_coal
&= ~ENINT_COALESCE
;
7999 if (enint_coal
!= (ahd
->hs_mailbox
& ENINT_COALESCE
)) {
8000 ahd_enable_coalescing(ahd
, enint_coal
);
8002 if ((ahd_debug
& AHD_SHOW_INT_COALESCING
) != 0)
8003 printf("%s: Interrupt coalescing "
8004 "now %sabled. Cmds %d\n",
8006 (enint_coal
& ENINT_COALESCE
) ? "en" : "dis",
8007 ahd
->cmdcmplt_total
);
8011 ahd
->cmdcmplt_bucket
= (ahd
->cmdcmplt_bucket
+1) & (AHD_STAT_BUCKETS
-1);
8012 ahd
->cmdcmplt_total
-= ahd
->cmdcmplt_counts
[ahd
->cmdcmplt_bucket
];
8013 ahd
->cmdcmplt_counts
[ahd
->cmdcmplt_bucket
] = 0;
8014 ahd_timer_reset(&ahd
->stat_timer
, AHD_STAT_UPDATE_US
,
8015 ahd_stat_timer
, ahd
);
8016 ahd_unlock(ahd
, &s
);
8019 /****************************** Status Processing *****************************/
8021 ahd_handle_scb_status(struct ahd_softc
*ahd
, struct scb
*scb
)
8023 if (scb
->hscb
->shared_data
.istatus
.scsi_status
!= 0) {
8024 ahd_handle_scsi_status(ahd
, scb
);
8026 ahd_calc_residual(ahd
, scb
);
8032 ahd_handle_scsi_status(struct ahd_softc
*ahd
, struct scb
*scb
)
8034 struct hardware_scb
*hscb
;
8038 * The sequencer freezes its select-out queue
8039 * anytime a SCSI status error occurs. We must
8040 * handle the error and increment our qfreeze count
8041 * to allow the sequencer to continue. We don't
8042 * bother clearing critical sections here since all
8043 * operations are on data structures that the sequencer
8044 * is not touching once the queue is frozen.
8048 if (ahd_is_paused(ahd
)) {
8055 /* Freeze the queue until the client sees the error. */
8056 ahd_freeze_devq(ahd
, scb
);
8057 ahd_freeze_scb(scb
);
8059 ahd_outw(ahd
, KERNEL_QFREEZE_COUNT
, ahd
->qfreeze_cnt
);
8064 /* Don't want to clobber the original sense code */
8065 if ((scb
->flags
& SCB_SENSE
) != 0) {
8067 * Clear the SCB_SENSE Flag and perform
8068 * a normal command completion.
8070 scb
->flags
&= ~SCB_SENSE
;
8071 ahd_set_transaction_status(scb
, CAM_AUTOSENSE_FAIL
);
8075 ahd_set_transaction_status(scb
, CAM_SCSI_STATUS_ERROR
);
8076 ahd_set_scsi_status(scb
, hscb
->shared_data
.istatus
.scsi_status
);
8077 switch (hscb
->shared_data
.istatus
.scsi_status
) {
8078 case STATUS_PKT_SENSE
:
8080 struct scsi_status_iu_header
*siu
;
8082 ahd_sync_sense(ahd
, scb
, BUS_DMASYNC_POSTREAD
);
8083 siu
= (struct scsi_status_iu_header
*)scb
->sense_data
;
8084 ahd_set_scsi_status(scb
, siu
->status
);
8086 if ((ahd_debug
& AHD_SHOW_SENSE
) != 0) {
8087 ahd_print_path(ahd
, scb
);
8088 printf("SCB 0x%x Received PKT Status of 0x%x\n",
8089 SCB_GET_TAG(scb
), siu
->status
);
8090 printf("\tflags = 0x%x, sense len = 0x%x, "
8092 siu
->flags
, scsi_4btoul(siu
->sense_length
),
8093 scsi_4btoul(siu
->pkt_failures_length
));
8096 if ((siu
->flags
& SIU_RSPVALID
) != 0) {
8097 ahd_print_path(ahd
, scb
);
8098 if (scsi_4btoul(siu
->pkt_failures_length
) < 4) {
8099 printf("Unable to parse pkt_failures\n");
8102 switch (SIU_PKTFAIL_CODE(siu
)) {
8104 printf("No packet failure found\n");
8106 case SIU_PFC_CIU_FIELDS_INVALID
:
8107 printf("Invalid Command IU Field\n");
8109 case SIU_PFC_TMF_NOT_SUPPORTED
:
8110 printf("TMF not supportd\n");
8112 case SIU_PFC_TMF_FAILED
:
8113 printf("TMF failed\n");
8115 case SIU_PFC_INVALID_TYPE_CODE
:
8116 printf("Invalid L_Q Type code\n");
8118 case SIU_PFC_ILLEGAL_REQUEST
:
8119 printf("Illegal request\n");
8124 if (siu
->status
== SCSI_STATUS_OK
)
8125 ahd_set_transaction_status(scb
,
8128 if ((siu
->flags
& SIU_SNSVALID
) != 0) {
8129 scb
->flags
|= SCB_PKT_SENSE
;
8131 if ((ahd_debug
& AHD_SHOW_SENSE
) != 0)
8132 printf("Sense data available\n");
8138 case SCSI_STATUS_CMD_TERMINATED
:
8139 case SCSI_STATUS_CHECK_COND
:
8141 struct ahd_devinfo devinfo
;
8142 struct ahd_dma_seg
*sg
;
8143 struct scsi_sense
*sc
;
8144 struct ahd_initiator_tinfo
*targ_info
;
8145 struct ahd_tmode_tstate
*tstate
;
8146 struct ahd_transinfo
*tinfo
;
8148 if (ahd_debug
& AHD_SHOW_SENSE
) {
8149 ahd_print_path(ahd
, scb
);
8150 printf("SCB %d: requests Check Status\n",
8155 if (ahd_perform_autosense(scb
) == 0)
8158 ahd_compile_devinfo(&devinfo
, SCB_GET_OUR_ID(scb
),
8159 SCB_GET_TARGET(ahd
, scb
),
8161 SCB_GET_CHANNEL(ahd
, scb
),
8163 targ_info
= ahd_fetch_transinfo(ahd
,
8168 tinfo
= &targ_info
->curr
;
8170 sc
= (struct scsi_sense
*)hscb
->shared_data
.idata
.cdb
;
8172 * Save off the residual if there is one.
8174 ahd_update_residual(ahd
, scb
);
8176 if (ahd_debug
& AHD_SHOW_SENSE
) {
8177 ahd_print_path(ahd
, scb
);
8178 printf("Sending Sense\n");
8182 sg
= ahd_sg_setup(ahd
, scb
, sg
, ahd_get_sense_bufaddr(ahd
, scb
),
8183 ahd_get_sense_bufsize(ahd
, scb
),
8185 sc
->opcode
= REQUEST_SENSE
;
8187 if (tinfo
->protocol_version
<= SCSI_REV_2
8188 && SCB_GET_LUN(scb
) < 8)
8189 sc
->byte2
= SCB_GET_LUN(scb
) << 5;
8192 sc
->length
= ahd_get_sense_bufsize(ahd
, scb
);
8196 * We can't allow the target to disconnect.
8197 * This will be an untagged transaction and
8198 * having the target disconnect will make this
8199 * transaction indestinguishable from outstanding
8200 * tagged transactions.
8205 * This request sense could be because the
8206 * the device lost power or in some other
8207 * way has lost our transfer negotiations.
8208 * Renegotiate if appropriate. Unit attention
8209 * errors will be reported before any data
8212 if (ahd_get_residual(scb
) == ahd_get_transfer_length(scb
)) {
8213 ahd_update_neg_request(ahd
, &devinfo
,
8215 AHD_NEG_IF_NON_ASYNC
);
8217 if (tstate
->auto_negotiate
& devinfo
.target_mask
) {
8218 hscb
->control
|= MK_MESSAGE
;
8220 ~(SCB_NEGOTIATE
|SCB_ABORT
|SCB_DEVICE_RESET
);
8221 scb
->flags
|= SCB_AUTO_NEGOTIATE
;
8223 hscb
->cdb_len
= sizeof(*sc
);
8224 ahd_setup_data_scb(ahd
, scb
);
8225 scb
->flags
|= SCB_SENSE
;
8226 ahd_queue_scb(ahd
, scb
);
8229 case SCSI_STATUS_OK
:
8230 printf("%s: Interrupted for staus of 0???\n",
8240 * Calculate the residual for a just completed SCB.
8243 ahd_calc_residual(struct ahd_softc
*ahd
, struct scb
*scb
)
8245 struct hardware_scb
*hscb
;
8246 struct initiator_status
*spkt
;
8248 uint32_t resid_sgptr
;
8254 * SG_STATUS_VALID clear in sgptr.
8255 * 2) Transferless command
8256 * 3) Never performed any transfers.
8257 * sgptr has SG_FULL_RESID set.
8258 * 4) No residual but target did not
8259 * save data pointers after the
8260 * last transfer, so sgptr was
8262 * 5) We have a partial residual.
8263 * Use residual_sgptr to determine
8268 sgptr
= ahd_le32toh(hscb
->sgptr
);
8269 if ((sgptr
& SG_STATUS_VALID
) == 0)
8272 sgptr
&= ~SG_STATUS_VALID
;
8274 if ((sgptr
& SG_LIST_NULL
) != 0)
8279 * Residual fields are the same in both
8280 * target and initiator status packets,
8281 * so we can always use the initiator fields
8282 * regardless of the role for this SCB.
8284 spkt
= &hscb
->shared_data
.istatus
;
8285 resid_sgptr
= ahd_le32toh(spkt
->residual_sgptr
);
8286 if ((sgptr
& SG_FULL_RESID
) != 0) {
8288 resid
= ahd_get_transfer_length(scb
);
8289 } else if ((resid_sgptr
& SG_LIST_NULL
) != 0) {
8292 } else if ((resid_sgptr
& SG_OVERRUN_RESID
) != 0) {
8293 ahd_print_path(ahd
, scb
);
8294 printf("data overrun detected Tag == 0x%x.\n",
8296 ahd_freeze_devq(ahd
, scb
);
8297 ahd_set_transaction_status(scb
, CAM_DATA_RUN_ERR
);
8298 ahd_freeze_scb(scb
);
8300 } else if ((resid_sgptr
& ~SG_PTR_MASK
) != 0) {
8301 panic("Bogus resid sgptr value 0x%x\n", resid_sgptr
);
8304 struct ahd_dma_seg
*sg
;
8307 * Remainder of the SG where the transfer
8310 resid
= ahd_le32toh(spkt
->residual_datacnt
) & AHD_SG_LEN_MASK
;
8311 sg
= ahd_sg_bus_to_virt(ahd
, scb
, resid_sgptr
& SG_PTR_MASK
);
8313 /* The residual sg_ptr always points to the next sg */
8317 * Add up the contents of all residual
8318 * SG segments that are after the SG where
8319 * the transfer stopped.
8321 while ((ahd_le32toh(sg
->len
) & AHD_DMA_LAST_SEG
) == 0) {
8323 resid
+= ahd_le32toh(sg
->len
) & AHD_SG_LEN_MASK
;
8326 if ((scb
->flags
& SCB_SENSE
) == 0)
8327 ahd_set_residual(scb
, resid
);
8329 ahd_set_sense_residual(scb
, resid
);
8332 if ((ahd_debug
& AHD_SHOW_MISC
) != 0) {
8333 ahd_print_path(ahd
, scb
);
8334 printf("Handled %sResidual of %d bytes\n",
8335 (scb
->flags
& SCB_SENSE
) ? "Sense " : "", resid
);
8340 /******************************* Target Mode **********************************/
8341 #ifdef AHD_TARGET_MODE
8343 * Add a target mode event to this lun's queue
8346 ahd_queue_lstate_event(struct ahd_softc
*ahd
, struct ahd_tmode_lstate
*lstate
,
8347 u_int initiator_id
, u_int event_type
, u_int event_arg
)
8349 struct ahd_tmode_event
*event
;
8352 xpt_freeze_devq(lstate
->path
, /*count*/1);
8353 if (lstate
->event_w_idx
>= lstate
->event_r_idx
)
8354 pending
= lstate
->event_w_idx
- lstate
->event_r_idx
;
8356 pending
= AHD_TMODE_EVENT_BUFFER_SIZE
+ 1
8357 - (lstate
->event_r_idx
- lstate
->event_w_idx
);
8359 if (event_type
== EVENT_TYPE_BUS_RESET
8360 || event_type
== MSG_BUS_DEV_RESET
) {
8362 * Any earlier events are irrelevant, so reset our buffer.
8363 * This has the effect of allowing us to deal with reset
8364 * floods (an external device holding down the reset line)
8365 * without losing the event that is really interesting.
8367 lstate
->event_r_idx
= 0;
8368 lstate
->event_w_idx
= 0;
8369 xpt_release_devq(lstate
->path
, pending
, /*runqueue*/FALSE
);
8372 if (pending
== AHD_TMODE_EVENT_BUFFER_SIZE
) {
8373 xpt_print_path(lstate
->path
);
8374 printf("immediate event %x:%x lost\n",
8375 lstate
->event_buffer
[lstate
->event_r_idx
].event_type
,
8376 lstate
->event_buffer
[lstate
->event_r_idx
].event_arg
);
8377 lstate
->event_r_idx
++;
8378 if (lstate
->event_r_idx
== AHD_TMODE_EVENT_BUFFER_SIZE
)
8379 lstate
->event_r_idx
= 0;
8380 xpt_release_devq(lstate
->path
, /*count*/1, /*runqueue*/FALSE
);
8383 event
= &lstate
->event_buffer
[lstate
->event_w_idx
];
8384 event
->initiator_id
= initiator_id
;
8385 event
->event_type
= event_type
;
8386 event
->event_arg
= event_arg
;
8387 lstate
->event_w_idx
++;
8388 if (lstate
->event_w_idx
== AHD_TMODE_EVENT_BUFFER_SIZE
)
8389 lstate
->event_w_idx
= 0;
8393 * Send any target mode events queued up waiting
8394 * for immediate notify resources.
8397 ahd_send_lstate_events(struct ahd_softc
*ahd
, struct ahd_tmode_lstate
*lstate
)
8399 struct ccb_hdr
*ccbh
;
8400 struct ccb_immed_notify
*inot
;
8402 while (lstate
->event_r_idx
!= lstate
->event_w_idx
8403 && (ccbh
= SLIST_FIRST(&lstate
->immed_notifies
)) != NULL
) {
8404 struct ahd_tmode_event
*event
;
8406 event
= &lstate
->event_buffer
[lstate
->event_r_idx
];
8407 SLIST_REMOVE_HEAD(&lstate
->immed_notifies
, sim_links
.sle
);
8408 inot
= (struct ccb_immed_notify
*)ccbh
;
8409 switch (event
->event_type
) {
8410 case EVENT_TYPE_BUS_RESET
:
8411 ccbh
->status
= CAM_SCSI_BUS_RESET
|CAM_DEV_QFRZN
;
8414 ccbh
->status
= CAM_MESSAGE_RECV
|CAM_DEV_QFRZN
;
8415 inot
->message_args
[0] = event
->event_type
;
8416 inot
->message_args
[1] = event
->event_arg
;
8419 inot
->initiator_id
= event
->initiator_id
;
8420 inot
->sense_len
= 0;
8421 xpt_done((union ccb
*)inot
);
8422 lstate
->event_r_idx
++;
8423 if (lstate
->event_r_idx
== AHD_TMODE_EVENT_BUFFER_SIZE
)
8424 lstate
->event_r_idx
= 0;
8429 /******************** Sequencer Program Patching/Download *********************/
8433 ahd_dumpseq(struct ahd_softc
* ahd
)
8440 ahd_outb(ahd
, SEQCTL0
, PERRORDIS
|FAILDIS
|FASTMODE
|LOADRAM
);
8441 ahd_outw(ahd
, PRGMCNT
, 0);
8442 for (i
= 0; i
< max_prog
; i
++) {
8443 uint8_t ins_bytes
[4];
8445 ahd_insb(ahd
, SEQRAM
, ins_bytes
, 4);
8446 printf("0x%08x\n", ins_bytes
[0] << 24
8447 | ins_bytes
[1] << 16
8455 ahd_loadseq(struct ahd_softc
*ahd
)
8457 struct cs cs_table
[num_critical_sections
];
8458 u_int begin_set
[num_critical_sections
];
8459 u_int end_set
[num_critical_sections
];
8460 struct patch
*cur_patch
;
8466 u_int sg_prefetch_cnt
;
8467 u_int sg_prefetch_cnt_limit
;
8468 u_int sg_prefetch_align
;
8470 u_int cacheline_mask
;
8471 uint8_t download_consts
[DOWNLOAD_CONST_COUNT
];
8474 printf("%s: Downloading Sequencer Program...",
8477 #if DOWNLOAD_CONST_COUNT != 8
8478 #error "Download Const Mismatch"
8481 * Start out with 0 critical sections
8482 * that apply to this firmware load.
8486 memset(begin_set
, 0, sizeof(begin_set
));
8487 memset(end_set
, 0, sizeof(end_set
));
8490 * Setup downloadable constant table.
8492 * The computation for the S/G prefetch variables is
8493 * a bit complicated. We would like to always fetch
8494 * in terms of cachelined sized increments. However,
8495 * if the cacheline is not an even multiple of the
8496 * SG element size or is larger than our SG RAM, using
8497 * just the cache size might leave us with only a portion
8498 * of an SG element at the tail of a prefetch. If the
8499 * cacheline is larger than our S/G prefetch buffer less
8500 * the size of an SG element, we may round down to a cacheline
8501 * that doesn't contain any or all of the S/G of interest
8502 * within the bounds of our S/G ram. Provide variables to
8503 * the sequencer that will allow it to handle these edge
8506 /* Start by aligning to the nearest cacheline. */
8507 sg_prefetch_align
= ahd
->pci_cachesize
;
8508 if (sg_prefetch_align
== 0)
8509 sg_prefetch_align
= 8;
8510 /* Round down to the nearest power of 2. */
8511 while (powerof2(sg_prefetch_align
) == 0)
8512 sg_prefetch_align
--;
8514 cacheline_mask
= sg_prefetch_align
- 1;
8517 * If the cacheline boundary is greater than half our prefetch RAM
8518 * we risk not being able to fetch even a single complete S/G
8519 * segment if we align to that boundary.
8521 if (sg_prefetch_align
> CCSGADDR_MAX
/2)
8522 sg_prefetch_align
= CCSGADDR_MAX
/2;
8523 /* Start by fetching a single cacheline. */
8524 sg_prefetch_cnt
= sg_prefetch_align
;
8526 * Increment the prefetch count by cachelines until
8527 * at least one S/G element will fit.
8529 sg_size
= sizeof(struct ahd_dma_seg
);
8530 if ((ahd
->flags
& AHD_64BIT_ADDRESSING
) != 0)
8531 sg_size
= sizeof(struct ahd_dma64_seg
);
8532 while (sg_prefetch_cnt
< sg_size
)
8533 sg_prefetch_cnt
+= sg_prefetch_align
;
8535 * If the cacheline is not an even multiple of
8536 * the S/G size, we may only get a partial S/G when
8537 * we align. Add a cacheline if this is the case.
8539 if ((sg_prefetch_align
% sg_size
) != 0
8540 && (sg_prefetch_cnt
< CCSGADDR_MAX
))
8541 sg_prefetch_cnt
+= sg_prefetch_align
;
8543 * Lastly, compute a value that the sequencer can use
8544 * to determine if the remainder of the CCSGRAM buffer
8545 * has a full S/G element in it.
8547 sg_prefetch_cnt_limit
= -(sg_prefetch_cnt
- sg_size
+ 1);
8548 download_consts
[SG_PREFETCH_CNT
] = sg_prefetch_cnt
;
8549 download_consts
[SG_PREFETCH_CNT_LIMIT
] = sg_prefetch_cnt_limit
;
8550 download_consts
[SG_PREFETCH_ALIGN_MASK
] = ~(sg_prefetch_align
- 1);
8551 download_consts
[SG_PREFETCH_ADDR_MASK
] = (sg_prefetch_align
- 1);
8552 download_consts
[SG_SIZEOF
] = sg_size
;
8553 download_consts
[PKT_OVERRUN_BUFOFFSET
] =
8554 (ahd
->overrun_buf
- (uint8_t *)ahd
->qoutfifo
) / 256;
8555 download_consts
[SCB_TRANSFER_SIZE
] = SCB_TRANSFER_SIZE_1BYTE_LUN
;
8556 download_consts
[CACHELINE_MASK
] = cacheline_mask
;
8557 cur_patch
= patches
;
8560 ahd_outb(ahd
, SEQCTL0
, PERRORDIS
|FAILDIS
|FASTMODE
|LOADRAM
);
8561 ahd_outw(ahd
, PRGMCNT
, 0);
8563 for (i
= 0; i
< sizeof(seqprog
)/4; i
++) {
8564 if (ahd_check_patch(ahd
, &cur_patch
, i
, &skip_addr
) == 0) {
8566 * Don't download this instruction as it
8567 * is in a patch that was removed.
8572 * Move through the CS table until we find a CS
8573 * that might apply to this instruction.
8575 for (; cur_cs
< num_critical_sections
; cur_cs
++) {
8576 if (critical_sections
[cur_cs
].end
<= i
) {
8577 if (begin_set
[cs_count
] == TRUE
8578 && end_set
[cs_count
] == FALSE
) {
8579 cs_table
[cs_count
].end
= downloaded
;
8580 end_set
[cs_count
] = TRUE
;
8585 if (critical_sections
[cur_cs
].begin
<= i
8586 && begin_set
[cs_count
] == FALSE
) {
8587 cs_table
[cs_count
].begin
= downloaded
;
8588 begin_set
[cs_count
] = TRUE
;
8592 ahd_download_instr(ahd
, i
, download_consts
);
8596 ahd
->num_critical_sections
= cs_count
;
8597 if (cs_count
!= 0) {
8599 cs_count
*= sizeof(struct cs
);
8600 ahd
->critical_sections
= malloc(cs_count
, M_DEVBUF
, M_NOWAIT
);
8601 if (ahd
->critical_sections
== NULL
)
8602 panic("ahd_loadseq: Could not malloc");
8603 memcpy(ahd
->critical_sections
, cs_table
, cs_count
);
8605 ahd_outb(ahd
, SEQCTL0
, PERRORDIS
|FAILDIS
|FASTMODE
);
8608 printf(" %d instructions downloaded\n", downloaded
);
8609 printf("%s: Features 0x%x, Bugs 0x%x, Flags 0x%x\n",
8610 ahd_name(ahd
), ahd
->features
, ahd
->bugs
, ahd
->flags
);
8615 ahd_check_patch(struct ahd_softc
*ahd
, struct patch
**start_patch
,
8616 u_int start_instr
, u_int
*skip_addr
)
8618 struct patch
*cur_patch
;
8619 struct patch
*last_patch
;
8622 num_patches
= sizeof(patches
)/sizeof(struct patch
);
8623 last_patch
= &patches
[num_patches
];
8624 cur_patch
= *start_patch
;
8626 while (cur_patch
< last_patch
&& start_instr
== cur_patch
->begin
) {
8628 if (cur_patch
->patch_func(ahd
) == 0) {
8630 /* Start rejecting code */
8631 *skip_addr
= start_instr
+ cur_patch
->skip_instr
;
8632 cur_patch
+= cur_patch
->skip_patch
;
8634 /* Accepted this patch. Advance to the next
8635 * one and wait for our intruction pointer to
8642 *start_patch
= cur_patch
;
8643 if (start_instr
< *skip_addr
)
8644 /* Still skipping */
8651 ahd_resolve_seqaddr(struct ahd_softc
*ahd
, u_int address
)
8653 struct patch
*cur_patch
;
8659 cur_patch
= patches
;
8662 for (i
= 0; i
< address
;) {
8664 ahd_check_patch(ahd
, &cur_patch
, i
, &skip_addr
);
8666 if (skip_addr
> i
) {
8669 end_addr
= MIN(address
, skip_addr
);
8670 address_offset
+= end_addr
- i
;
8676 return (address
- address_offset
);
8680 ahd_download_instr(struct ahd_softc
*ahd
, u_int instrptr
, uint8_t *dconsts
)
8682 union ins_formats instr
;
8683 struct ins_format1
*fmt1_ins
;
8684 struct ins_format3
*fmt3_ins
;
8688 * The firmware is always compiled into a little endian format.
8690 instr
.integer
= ahd_le32toh(*(uint32_t*)&seqprog
[instrptr
* 4]);
8692 fmt1_ins
= &instr
.format1
;
8695 /* Pull the opcode */
8696 opcode
= instr
.format1
.opcode
;
8707 fmt3_ins
= &instr
.format3
;
8708 fmt3_ins
->address
= ahd_resolve_seqaddr(ahd
, fmt3_ins
->address
);
8717 if (fmt1_ins
->parity
!= 0) {
8718 fmt1_ins
->immediate
= dconsts
[fmt1_ins
->immediate
];
8720 fmt1_ins
->parity
= 0;
8726 /* Calculate odd parity for the instruction */
8727 for (i
= 0, count
= 0; i
< 31; i
++) {
8731 if ((instr
.integer
& mask
) != 0)
8734 if ((count
& 0x01) == 0)
8735 instr
.format1
.parity
= 1;
8737 /* The sequencer is a little endian cpu */
8738 instr
.integer
= ahd_htole32(instr
.integer
);
8739 ahd_outsb(ahd
, SEQRAM
, instr
.bytes
, 4);
8743 panic("Unknown opcode encountered in seq program");
8749 ahd_probe_stack_size(struct ahd_softc
*ahd
)
8758 * We avoid using 0 as a pattern to avoid
8759 * confusion if the stack implementation
8760 * "back-fills" with zeros when "poping'
8763 for (i
= 1; i
<= last_probe
+1; i
++) {
8764 ahd_outb(ahd
, STACK
, i
& 0xFF);
8765 ahd_outb(ahd
, STACK
, (i
>> 8) & 0xFF);
8769 for (i
= last_probe
+1; i
> 0; i
--) {
8772 stack_entry
= ahd_inb(ahd
, STACK
)
8773 |(ahd_inb(ahd
, STACK
) << 8);
8774 if (stack_entry
!= i
)
8780 return (last_probe
);
8784 ahd_print_register(ahd_reg_parse_entry_t
*table
, u_int num_entries
,
8785 const char *name
, u_int address
, u_int value
,
8786 u_int
*cur_column
, u_int wrap_point
)
8791 if (cur_column
!= NULL
&& *cur_column
>= wrap_point
) {
8795 printed
= printf("%s[0x%x]", name
, value
);
8796 if (table
== NULL
) {
8797 printed
+= printf(" ");
8798 *cur_column
+= printed
;
8802 while (printed_mask
!= 0xFF) {
8805 for (entry
= 0; entry
< num_entries
; entry
++) {
8806 if (((value
& table
[entry
].mask
)
8807 != table
[entry
].value
)
8808 || ((printed_mask
& table
[entry
].mask
)
8809 == table
[entry
].mask
))
8812 printed
+= printf("%s%s",
8813 printed_mask
== 0 ? ":(" : "|",
8815 printed_mask
|= table
[entry
].mask
;
8819 if (entry
>= num_entries
)
8822 if (printed_mask
!= 0)
8823 printed
+= printf(") ");
8825 printed
+= printf(" ");
8826 if (cur_column
!= NULL
)
8827 *cur_column
+= printed
;
8832 ahd_dump_card_state(struct ahd_softc
*ahd
)
8835 ahd_mode_state saved_modes
;
8839 u_int saved_scb_index
;
8843 if (ahd_is_paused(ahd
)) {
8849 saved_modes
= ahd_save_modes(ahd
);
8850 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
8851 printf(">>>>>>>>>>>>>>>>>> Dump Card State Begins <<<<<<<<<<<<<<<<<\n"
8852 "%s: Dumping Card State at program address 0x%x Mode 0x%x\n",
8854 ahd_inw(ahd
, CURADDR
),
8855 ahd_build_mode_state(ahd
, ahd
->saved_src_mode
,
8856 ahd
->saved_dst_mode
));
8858 printf("Card was paused\n");
8860 if (ahd_check_cmdcmpltqueues(ahd
))
8861 printf("Completions are pending\n");
8864 * Mode independent registers.
8867 ahd_intstat_print(ahd_inb(ahd
, INTSTAT
), &cur_col
, 50);
8868 ahd_seloid_print(ahd_inb(ahd
, SELOID
), &cur_col
, 50);
8869 ahd_selid_print(ahd_inb(ahd
, SELID
), &cur_col
, 50);
8870 ahd_hs_mailbox_print(ahd_inb(ahd
, LOCAL_HS_MAILBOX
), &cur_col
, 50);
8871 ahd_intctl_print(ahd_inb(ahd
, INTCTL
), &cur_col
, 50);
8872 ahd_seqintstat_print(ahd_inb(ahd
, SEQINTSTAT
), &cur_col
, 50);
8873 ahd_saved_mode_print(ahd_inb(ahd
, SAVED_MODE
), &cur_col
, 50);
8874 ahd_dffstat_print(ahd_inb(ahd
, DFFSTAT
), &cur_col
, 50);
8875 ahd_scsisigi_print(ahd_inb(ahd
, SCSISIGI
), &cur_col
, 50);
8876 ahd_scsiphase_print(ahd_inb(ahd
, SCSIPHASE
), &cur_col
, 50);
8877 ahd_scsibus_print(ahd_inb(ahd
, SCSIBUS
), &cur_col
, 50);
8878 ahd_lastphase_print(ahd_inb(ahd
, LASTPHASE
), &cur_col
, 50);
8879 ahd_scsiseq0_print(ahd_inb(ahd
, SCSISEQ0
), &cur_col
, 50);
8880 ahd_scsiseq1_print(ahd_inb(ahd
, SCSISEQ1
), &cur_col
, 50);
8881 ahd_seqctl0_print(ahd_inb(ahd
, SEQCTL0
), &cur_col
, 50);
8882 ahd_seqintctl_print(ahd_inb(ahd
, SEQINTCTL
), &cur_col
, 50);
8883 ahd_seq_flags_print(ahd_inb(ahd
, SEQ_FLAGS
), &cur_col
, 50);
8884 ahd_seq_flags2_print(ahd_inb(ahd
, SEQ_FLAGS2
), &cur_col
, 50);
8885 ahd_qfreeze_count_print(ahd_inw(ahd
, QFREEZE_COUNT
), &cur_col
, 50);
8886 ahd_kernel_qfreeze_count_print(ahd_inw(ahd
, KERNEL_QFREEZE_COUNT
),
8888 ahd_mk_message_scb_print(ahd_inw(ahd
, MK_MESSAGE_SCB
), &cur_col
, 50);
8889 ahd_mk_message_scsiid_print(ahd_inb(ahd
, MK_MESSAGE_SCSIID
),
8891 ahd_sstat0_print(ahd_inb(ahd
, SSTAT0
), &cur_col
, 50);
8892 ahd_sstat1_print(ahd_inb(ahd
, SSTAT1
), &cur_col
, 50);
8893 ahd_sstat2_print(ahd_inb(ahd
, SSTAT2
), &cur_col
, 50);
8894 ahd_sstat3_print(ahd_inb(ahd
, SSTAT3
), &cur_col
, 50);
8895 ahd_perrdiag_print(ahd_inb(ahd
, PERRDIAG
), &cur_col
, 50);
8896 ahd_simode1_print(ahd_inb(ahd
, SIMODE1
), &cur_col
, 50);
8897 ahd_lqistat0_print(ahd_inb(ahd
, LQISTAT0
), &cur_col
, 50);
8898 ahd_lqistat1_print(ahd_inb(ahd
, LQISTAT1
), &cur_col
, 50);
8899 ahd_lqistat2_print(ahd_inb(ahd
, LQISTAT2
), &cur_col
, 50);
8900 ahd_lqostat0_print(ahd_inb(ahd
, LQOSTAT0
), &cur_col
, 50);
8901 ahd_lqostat1_print(ahd_inb(ahd
, LQOSTAT1
), &cur_col
, 50);
8902 ahd_lqostat2_print(ahd_inb(ahd
, LQOSTAT2
), &cur_col
, 50);
8904 printf("\nSCB Count = %d CMDS_PENDING = %d LASTSCB 0x%x "
8905 "CURRSCB 0x%x NEXTSCB 0x%x\n",
8906 ahd
->scb_data
.numscbs
, ahd_inw(ahd
, CMDS_PENDING
),
8907 ahd_inw(ahd
, LASTSCB
), ahd_inw(ahd
, CURRSCB
),
8908 ahd_inw(ahd
, NEXTSCB
));
8911 ahd_search_qinfifo(ahd
, CAM_TARGET_WILDCARD
, ALL_CHANNELS
,
8912 CAM_LUN_WILDCARD
, SCB_LIST_NULL
,
8913 ROLE_UNKNOWN
, /*status*/0, SEARCH_PRINT
);
8914 saved_scb_index
= ahd_get_scbptr(ahd
);
8915 printf("Pending list:");
8917 LIST_FOREACH(scb
, &ahd
->pending_scbs
, pending_links
) {
8918 if (i
++ > AHD_SCB_MAX
)
8920 cur_col
= printf("\n%3d FIFO_USE[0x%x] ", SCB_GET_TAG(scb
),
8921 ahd_inb_scbram(ahd
, SCB_FIFO_USE_COUNT
));
8922 ahd_set_scbptr(ahd
, SCB_GET_TAG(scb
));
8923 ahd_scb_control_print(ahd_inb_scbram(ahd
, SCB_CONTROL
),
8925 ahd_scb_scsiid_print(ahd_inb_scbram(ahd
, SCB_SCSIID
),
8928 printf("\nTotal %d\n", i
);
8930 printf("Kernel Free SCB list: ");
8932 TAILQ_FOREACH(scb
, &ahd
->scb_data
.free_scbs
, links
.tqe
) {
8933 struct scb
*list_scb
;
8937 printf("%d ", SCB_GET_TAG(list_scb
));
8938 list_scb
= LIST_NEXT(list_scb
, collision_links
);
8939 } while (list_scb
&& i
++ < AHD_SCB_MAX
);
8942 LIST_FOREACH(scb
, &ahd
->scb_data
.any_dev_free_scb_list
, links
.le
) {
8943 if (i
++ > AHD_SCB_MAX
)
8945 printf("%d ", SCB_GET_TAG(scb
));
8949 printf("Sequencer Complete DMA-inprog list: ");
8950 scb_index
= ahd_inw(ahd
, COMPLETE_SCB_DMAINPROG_HEAD
);
8952 while (!SCBID_IS_NULL(scb_index
) && i
++ < AHD_SCB_MAX
) {
8953 ahd_set_scbptr(ahd
, scb_index
);
8954 printf("%d ", scb_index
);
8955 scb_index
= ahd_inw_scbram(ahd
, SCB_NEXT_COMPLETE
);
8959 printf("Sequencer Complete list: ");
8960 scb_index
= ahd_inw(ahd
, COMPLETE_SCB_HEAD
);
8962 while (!SCBID_IS_NULL(scb_index
) && i
++ < AHD_SCB_MAX
) {
8963 ahd_set_scbptr(ahd
, scb_index
);
8964 printf("%d ", scb_index
);
8965 scb_index
= ahd_inw_scbram(ahd
, SCB_NEXT_COMPLETE
);
8970 printf("Sequencer DMA-Up and Complete list: ");
8971 scb_index
= ahd_inw(ahd
, COMPLETE_DMA_SCB_HEAD
);
8973 while (!SCBID_IS_NULL(scb_index
) && i
++ < AHD_SCB_MAX
) {
8974 ahd_set_scbptr(ahd
, scb_index
);
8975 printf("%d ", scb_index
);
8976 scb_index
= ahd_inw_scbram(ahd
, SCB_NEXT_COMPLETE
);
8979 printf("Sequencer On QFreeze and Complete list: ");
8980 scb_index
= ahd_inw(ahd
, COMPLETE_ON_QFREEZE_HEAD
);
8982 while (!SCBID_IS_NULL(scb_index
) && i
++ < AHD_SCB_MAX
) {
8983 ahd_set_scbptr(ahd
, scb_index
);
8984 printf("%d ", scb_index
);
8985 scb_index
= ahd_inw_scbram(ahd
, SCB_NEXT_COMPLETE
);
8988 ahd_set_scbptr(ahd
, saved_scb_index
);
8989 dffstat
= ahd_inb(ahd
, DFFSTAT
);
8990 for (i
= 0; i
< 2; i
++) {
8992 struct scb
*fifo_scb
;
8996 ahd_set_modes(ahd
, AHD_MODE_DFF0
+ i
, AHD_MODE_DFF0
+ i
);
8997 fifo_scbptr
= ahd_get_scbptr(ahd
);
8998 printf("\n\n%s: FIFO%d %s, LONGJMP == 0x%x, SCB 0x%x\n",
9000 (dffstat
& (FIFO0FREE
<< i
)) ? "Free" : "Active",
9001 ahd_inw(ahd
, LONGJMP_ADDR
), fifo_scbptr
);
9003 ahd_seqimode_print(ahd_inb(ahd
, SEQIMODE
), &cur_col
, 50);
9004 ahd_seqintsrc_print(ahd_inb(ahd
, SEQINTSRC
), &cur_col
, 50);
9005 ahd_dfcntrl_print(ahd_inb(ahd
, DFCNTRL
), &cur_col
, 50);
9006 ahd_dfstatus_print(ahd_inb(ahd
, DFSTATUS
), &cur_col
, 50);
9007 ahd_sg_cache_shadow_print(ahd_inb(ahd
, SG_CACHE_SHADOW
),
9009 ahd_sg_state_print(ahd_inb(ahd
, SG_STATE
), &cur_col
, 50);
9010 ahd_dffsxfrctl_print(ahd_inb(ahd
, DFFSXFRCTL
), &cur_col
, 50);
9011 ahd_soffcnt_print(ahd_inb(ahd
, SOFFCNT
), &cur_col
, 50);
9012 ahd_mdffstat_print(ahd_inb(ahd
, MDFFSTAT
), &cur_col
, 50);
9017 cur_col
+= printf("SHADDR = 0x%x%x, SHCNT = 0x%x ",
9018 ahd_inl(ahd
, SHADDR
+4),
9019 ahd_inl(ahd
, SHADDR
),
9020 (ahd_inb(ahd
, SHCNT
)
9021 | (ahd_inb(ahd
, SHCNT
+ 1) << 8)
9022 | (ahd_inb(ahd
, SHCNT
+ 2) << 16)));
9027 cur_col
+= printf("HADDR = 0x%x%x, HCNT = 0x%x ",
9028 ahd_inl(ahd
, HADDR
+4),
9029 ahd_inl(ahd
, HADDR
),
9031 | (ahd_inb(ahd
, HCNT
+ 1) << 8)
9032 | (ahd_inb(ahd
, HCNT
+ 2) << 16)));
9033 ahd_ccsgctl_print(ahd_inb(ahd
, CCSGCTL
), &cur_col
, 50);
9035 if ((ahd_debug
& AHD_SHOW_SG
) != 0) {
9036 fifo_scb
= ahd_lookup_scb(ahd
, fifo_scbptr
);
9037 if (fifo_scb
!= NULL
)
9038 ahd_dump_sglist(fifo_scb
);
9043 for (i
= 0; i
< 20; i
++)
9044 printf("0x%x ", ahd_inb(ahd
, LQIN
+ i
));
9046 ahd_set_modes(ahd
, AHD_MODE_CFG
, AHD_MODE_CFG
);
9047 printf("%s: LQISTATE = 0x%x, LQOSTATE = 0x%x, OPTIONMODE = 0x%x\n",
9048 ahd_name(ahd
), ahd_inb(ahd
, LQISTATE
), ahd_inb(ahd
, LQOSTATE
),
9049 ahd_inb(ahd
, OPTIONMODE
));
9050 printf("%s: OS_SPACE_CNT = 0x%x MAXCMDCNT = 0x%x\n",
9051 ahd_name(ahd
), ahd_inb(ahd
, OS_SPACE_CNT
),
9052 ahd_inb(ahd
, MAXCMDCNT
));
9053 printf("%s: SAVED_SCSIID = 0x%x SAVED_LUN = 0x%x\n",
9054 ahd_name(ahd
), ahd_inb(ahd
, SAVED_SCSIID
),
9055 ahd_inb(ahd
, SAVED_LUN
));
9056 ahd_simode0_print(ahd_inb(ahd
, SIMODE0
), &cur_col
, 50);
9058 ahd_set_modes(ahd
, AHD_MODE_CCHAN
, AHD_MODE_CCHAN
);
9060 ahd_ccscbctl_print(ahd_inb(ahd
, CCSCBCTL
), &cur_col
, 50);
9062 ahd_set_modes(ahd
, ahd
->saved_src_mode
, ahd
->saved_dst_mode
);
9063 printf("%s: REG0 == 0x%x, SINDEX = 0x%x, DINDEX = 0x%x\n",
9064 ahd_name(ahd
), ahd_inw(ahd
, REG0
), ahd_inw(ahd
, SINDEX
),
9065 ahd_inw(ahd
, DINDEX
));
9066 printf("%s: SCBPTR == 0x%x, SCB_NEXT == 0x%x, SCB_NEXT2 == 0x%x\n",
9067 ahd_name(ahd
), ahd_get_scbptr(ahd
),
9068 ahd_inw_scbram(ahd
, SCB_NEXT
),
9069 ahd_inw_scbram(ahd
, SCB_NEXT2
));
9070 printf("CDB %x %x %x %x %x %x\n",
9071 ahd_inb_scbram(ahd
, SCB_CDB_STORE
),
9072 ahd_inb_scbram(ahd
, SCB_CDB_STORE
+1),
9073 ahd_inb_scbram(ahd
, SCB_CDB_STORE
+2),
9074 ahd_inb_scbram(ahd
, SCB_CDB_STORE
+3),
9075 ahd_inb_scbram(ahd
, SCB_CDB_STORE
+4),
9076 ahd_inb_scbram(ahd
, SCB_CDB_STORE
+5));
9078 for (i
= 0; i
< ahd
->stack_size
; i
++) {
9079 ahd
->saved_stack
[i
] =
9080 ahd_inb(ahd
, STACK
)|(ahd_inb(ahd
, STACK
) << 8);
9081 printf(" 0x%x", ahd
->saved_stack
[i
]);
9083 for (i
= ahd
->stack_size
-1; i
>= 0; i
--) {
9084 ahd_outb(ahd
, STACK
, ahd
->saved_stack
[i
] & 0xFF);
9085 ahd_outb(ahd
, STACK
, (ahd
->saved_stack
[i
] >> 8) & 0xFF);
9087 printf("\n<<<<<<<<<<<<<<<<< Dump Card State Ends >>>>>>>>>>>>>>>>>>\n");
9088 ahd_restore_modes(ahd
, saved_modes
);
9094 ahd_dump_scbs(struct ahd_softc
*ahd
)
9096 ahd_mode_state saved_modes
;
9097 u_int saved_scb_index
;
9100 saved_modes
= ahd_save_modes(ahd
);
9101 ahd_set_modes(ahd
, AHD_MODE_SCSI
, AHD_MODE_SCSI
);
9102 saved_scb_index
= ahd_get_scbptr(ahd
);
9103 for (i
= 0; i
< AHD_SCB_MAX
; i
++) {
9104 ahd_set_scbptr(ahd
, i
);
9106 printf("(CTRL 0x%x ID 0x%x N 0x%x N2 0x%x SG 0x%x, RSG 0x%x)\n",
9107 ahd_inb_scbram(ahd
, SCB_CONTROL
),
9108 ahd_inb_scbram(ahd
, SCB_SCSIID
),
9109 ahd_inw_scbram(ahd
, SCB_NEXT
),
9110 ahd_inw_scbram(ahd
, SCB_NEXT2
),
9111 ahd_inl_scbram(ahd
, SCB_SGPTR
),
9112 ahd_inl_scbram(ahd
, SCB_RESIDUAL_SGPTR
));
9115 ahd_set_scbptr(ahd
, saved_scb_index
);
9116 ahd_restore_modes(ahd
, saved_modes
);
9119 /**************************** Flexport Logic **********************************/
9121 * Read count 16bit words from 16bit word address start_addr from the
9122 * SEEPROM attached to the controller, into buf, using the controller's
9123 * SEEPROM reading state machine. Optionally treat the data as a byte
9124 * stream in terms of byte order.
9127 ahd_read_seeprom(struct ahd_softc
*ahd
, uint16_t *buf
,
9128 u_int start_addr
, u_int count
, int bytestream
)
9135 * If we never make it through the loop even once,
9136 * we were passed invalid arguments.
9139 AHD_ASSERT_MODES(ahd
, AHD_MODE_SCSI_MSK
, AHD_MODE_SCSI_MSK
);
9140 end_addr
= start_addr
+ count
;
9141 for (cur_addr
= start_addr
; cur_addr
< end_addr
; cur_addr
++) {
9143 ahd_outb(ahd
, SEEADR
, cur_addr
);
9144 ahd_outb(ahd
, SEECTL
, SEEOP_READ
| SEESTART
);
9146 error
= ahd_wait_seeprom(ahd
);
9149 if (bytestream
!= 0) {
9150 uint8_t *bytestream_ptr
;
9152 bytestream_ptr
= (uint8_t *)buf
;
9153 *bytestream_ptr
++ = ahd_inb(ahd
, SEEDAT
);
9154 *bytestream_ptr
= ahd_inb(ahd
, SEEDAT
+1);
9157 * ahd_inw() already handles machine byte order.
9159 *buf
= ahd_inw(ahd
, SEEDAT
);
9167 * Write count 16bit words from buf, into SEEPROM attache to the
9168 * controller starting at 16bit word address start_addr, using the
9169 * controller's SEEPROM writing state machine.
9172 ahd_write_seeprom(struct ahd_softc
*ahd
, uint16_t *buf
,
9173 u_int start_addr
, u_int count
)
9180 AHD_ASSERT_MODES(ahd
, AHD_MODE_SCSI_MSK
, AHD_MODE_SCSI_MSK
);
9183 /* Place the chip into write-enable mode */
9184 ahd_outb(ahd
, SEEADR
, SEEOP_EWEN_ADDR
);
9185 ahd_outb(ahd
, SEECTL
, SEEOP_EWEN
| SEESTART
);
9186 error
= ahd_wait_seeprom(ahd
);
9191 * Write the data. If we don't get throught the loop at
9192 * least once, the arguments were invalid.
9195 end_addr
= start_addr
+ count
;
9196 for (cur_addr
= start_addr
; cur_addr
< end_addr
; cur_addr
++) {
9197 ahd_outw(ahd
, SEEDAT
, *buf
++);
9198 ahd_outb(ahd
, SEEADR
, cur_addr
);
9199 ahd_outb(ahd
, SEECTL
, SEEOP_WRITE
| SEESTART
);
9201 retval
= ahd_wait_seeprom(ahd
);
9209 ahd_outb(ahd
, SEEADR
, SEEOP_EWDS_ADDR
);
9210 ahd_outb(ahd
, SEECTL
, SEEOP_EWDS
| SEESTART
);
9211 error
= ahd_wait_seeprom(ahd
);
9218 * Wait ~100us for the serial eeprom to satisfy our request.
9221 ahd_wait_seeprom(struct ahd_softc
*ahd
)
9226 while ((ahd_inb(ahd
, SEESTAT
) & (SEEARBACK
|SEEBUSY
)) != 0 && --cnt
)
9235 * Validate the two checksums in the per_channel
9236 * vital product data struct.
9239 ahd_verify_vpd_cksum(struct vpd_config
*vpd
)
9246 vpdarray
= (uint8_t *)vpd
;
9247 maxaddr
= offsetof(struct vpd_config
, vpd_checksum
);
9249 for (i
= offsetof(struct vpd_config
, resource_type
); i
< maxaddr
; i
++)
9250 checksum
= checksum
+ vpdarray
[i
];
9252 || (-checksum
& 0xFF) != vpd
->vpd_checksum
)
9256 maxaddr
= offsetof(struct vpd_config
, checksum
);
9257 for (i
= offsetof(struct vpd_config
, default_target_flags
);
9259 checksum
= checksum
+ vpdarray
[i
];
9261 || (-checksum
& 0xFF) != vpd
->checksum
)
9267 ahd_verify_cksum(struct seeprom_config
*sc
)
9274 maxaddr
= (sizeof(*sc
)/2) - 1;
9276 scarray
= (uint16_t *)sc
;
9278 for (i
= 0; i
< maxaddr
; i
++)
9279 checksum
= checksum
+ scarray
[i
];
9281 || (checksum
& 0xFFFF) != sc
->checksum
) {
9289 ahd_acquire_seeprom(struct ahd_softc
*ahd
)
9292 * We should be able to determine the SEEPROM type
9293 * from the flexport logic, but unfortunately not
9294 * all implementations have this logic and there is
9295 * no programatic method for determining if the logic
9303 error
= ahd_read_flexport(ahd
, FLXADDR_ROMSTAT_CURSENSECTL
, &seetype
);
9305 || ((seetype
& FLX_ROMSTAT_SEECFG
) == FLX_ROMSTAT_SEE_NONE
))
9312 ahd_release_seeprom(struct ahd_softc
*ahd
)
9314 /* Currently a no-op */
9318 ahd_write_flexport(struct ahd_softc
*ahd
, u_int addr
, u_int value
)
9322 AHD_ASSERT_MODES(ahd
, AHD_MODE_SCSI_MSK
, AHD_MODE_SCSI_MSK
);
9324 panic("ahd_write_flexport: address out of range");
9325 ahd_outb(ahd
, BRDCTL
, BRDEN
|(addr
<< 3));
9326 error
= ahd_wait_flexport(ahd
);
9329 ahd_outb(ahd
, BRDDAT
, value
);
9330 ahd_flush_device_writes(ahd
);
9331 ahd_outb(ahd
, BRDCTL
, BRDSTB
|BRDEN
|(addr
<< 3));
9332 ahd_flush_device_writes(ahd
);
9333 ahd_outb(ahd
, BRDCTL
, BRDEN
|(addr
<< 3));
9334 ahd_flush_device_writes(ahd
);
9335 ahd_outb(ahd
, BRDCTL
, 0);
9336 ahd_flush_device_writes(ahd
);
9341 ahd_read_flexport(struct ahd_softc
*ahd
, u_int addr
, uint8_t *value
)
9345 AHD_ASSERT_MODES(ahd
, AHD_MODE_SCSI_MSK
, AHD_MODE_SCSI_MSK
);
9347 panic("ahd_read_flexport: address out of range");
9348 ahd_outb(ahd
, BRDCTL
, BRDRW
|BRDEN
|(addr
<< 3));
9349 error
= ahd_wait_flexport(ahd
);
9352 *value
= ahd_inb(ahd
, BRDDAT
);
9353 ahd_outb(ahd
, BRDCTL
, 0);
9354 ahd_flush_device_writes(ahd
);
9359 * Wait at most 2 seconds for flexport arbitration to succeed.
9362 ahd_wait_flexport(struct ahd_softc
*ahd
)
9366 AHD_ASSERT_MODES(ahd
, AHD_MODE_SCSI_MSK
, AHD_MODE_SCSI_MSK
);
9367 cnt
= 1000000 * 2 / 5;
9368 while ((ahd_inb(ahd
, BRDCTL
) & FLXARBACK
) == 0 && --cnt
)
9376 /************************* Target Mode ****************************************/
9377 #ifdef AHD_TARGET_MODE
9379 ahd_find_tmode_devs(struct ahd_softc
*ahd
, struct cam_sim
*sim
, union ccb
*ccb
,
9380 struct ahd_tmode_tstate
**tstate
,
9381 struct ahd_tmode_lstate
**lstate
,
9382 int notfound_failure
)
9385 if ((ahd
->features
& AHD_TARGETMODE
) == 0)
9386 return (CAM_REQ_INVALID
);
9389 * Handle the 'black hole' device that sucks up
9390 * requests to unattached luns on enabled targets.
9392 if (ccb
->ccb_h
.target_id
== CAM_TARGET_WILDCARD
9393 && ccb
->ccb_h
.target_lun
== CAM_LUN_WILDCARD
) {
9395 *lstate
= ahd
->black_hole
;
9399 max_id
= (ahd
->features
& AHD_WIDE
) ? 15 : 7;
9400 if (ccb
->ccb_h
.target_id
> max_id
)
9401 return (CAM_TID_INVALID
);
9403 if (ccb
->ccb_h
.target_lun
>= AHD_NUM_LUNS
)
9404 return (CAM_LUN_INVALID
);
9406 *tstate
= ahd
->enabled_targets
[ccb
->ccb_h
.target_id
];
9408 if (*tstate
!= NULL
)
9410 (*tstate
)->enabled_luns
[ccb
->ccb_h
.target_lun
];
9413 if (notfound_failure
!= 0 && *lstate
== NULL
)
9414 return (CAM_PATH_INVALID
);
9416 return (CAM_REQ_CMP
);
9420 ahd_handle_en_lun(struct ahd_softc
*ahd
, struct cam_sim
*sim
, union ccb
*ccb
)
9423 struct ahd_tmode_tstate
*tstate
;
9424 struct ahd_tmode_lstate
*lstate
;
9425 struct ccb_en_lun
*cel
;
9433 status
= ahd_find_tmode_devs(ahd
, sim
, ccb
, &tstate
, &lstate
,
9434 /*notfound_failure*/FALSE
);
9436 if (status
!= CAM_REQ_CMP
) {
9437 ccb
->ccb_h
.status
= status
;
9441 if ((ahd
->features
& AHD_MULTIROLE
) != 0) {
9444 our_id
= ahd
->our_id
;
9445 if (ccb
->ccb_h
.target_id
!= our_id
) {
9446 if ((ahd
->features
& AHD_MULTI_TID
) != 0
9447 && (ahd
->flags
& AHD_INITIATORROLE
) != 0) {
9449 * Only allow additional targets if
9450 * the initiator role is disabled.
9451 * The hardware cannot handle a re-select-in
9452 * on the initiator id during a re-select-out
9453 * on a different target id.
9455 status
= CAM_TID_INVALID
;
9456 } else if ((ahd
->flags
& AHD_INITIATORROLE
) != 0
9457 || ahd
->enabled_luns
> 0) {
9459 * Only allow our target id to change
9460 * if the initiator role is not configured
9461 * and there are no enabled luns which
9462 * are attached to the currently registered
9465 status
= CAM_TID_INVALID
;
9470 if (status
!= CAM_REQ_CMP
) {
9471 ccb
->ccb_h
.status
= status
;
9476 * We now have an id that is valid.
9477 * If we aren't in target mode, switch modes.
9479 if ((ahd
->flags
& AHD_TARGETROLE
) == 0
9480 && ccb
->ccb_h
.target_id
!= CAM_TARGET_WILDCARD
) {
9483 printf("Configuring Target Mode\n");
9485 if (LIST_FIRST(&ahd
->pending_scbs
) != NULL
) {
9486 ccb
->ccb_h
.status
= CAM_BUSY
;
9487 ahd_unlock(ahd
, &s
);
9490 ahd
->flags
|= AHD_TARGETROLE
;
9491 if ((ahd
->features
& AHD_MULTIROLE
) == 0)
9492 ahd
->flags
&= ~AHD_INITIATORROLE
;
9496 ahd_unlock(ahd
, &s
);
9499 target
= ccb
->ccb_h
.target_id
;
9500 lun
= ccb
->ccb_h
.target_lun
;
9501 channel
= SIM_CHANNEL(ahd
, sim
);
9502 target_mask
= 0x01 << target
;
9506 if (cel
->enable
!= 0) {
9509 /* Are we already enabled?? */
9510 if (lstate
!= NULL
) {
9511 xpt_print_path(ccb
->ccb_h
.path
);
9512 printf("Lun already enabled\n");
9513 ccb
->ccb_h
.status
= CAM_LUN_ALRDY_ENA
;
9517 if (cel
->grp6_len
!= 0
9518 || cel
->grp7_len
!= 0) {
9520 * Don't (yet?) support vendor
9521 * specific commands.
9523 ccb
->ccb_h
.status
= CAM_REQ_INVALID
;
9524 printf("Non-zero Group Codes\n");
9530 * Setup our data structures.
9532 if (target
!= CAM_TARGET_WILDCARD
&& tstate
== NULL
) {
9533 tstate
= ahd_alloc_tstate(ahd
, target
, channel
);
9534 if (tstate
== NULL
) {
9535 xpt_print_path(ccb
->ccb_h
.path
);
9536 printf("Couldn't allocate tstate\n");
9537 ccb
->ccb_h
.status
= CAM_RESRC_UNAVAIL
;
9541 lstate
= malloc(sizeof(*lstate
), M_DEVBUF
, M_NOWAIT
);
9542 if (lstate
== NULL
) {
9543 xpt_print_path(ccb
->ccb_h
.path
);
9544 printf("Couldn't allocate lstate\n");
9545 ccb
->ccb_h
.status
= CAM_RESRC_UNAVAIL
;
9548 memset(lstate
, 0, sizeof(*lstate
));
9549 status
= xpt_create_path(&lstate
->path
, /*periph*/NULL
,
9550 xpt_path_path_id(ccb
->ccb_h
.path
),
9551 xpt_path_target_id(ccb
->ccb_h
.path
),
9552 xpt_path_lun_id(ccb
->ccb_h
.path
));
9553 if (status
!= CAM_REQ_CMP
) {
9554 free(lstate
, M_DEVBUF
);
9555 xpt_print_path(ccb
->ccb_h
.path
);
9556 printf("Couldn't allocate path\n");
9557 ccb
->ccb_h
.status
= CAM_RESRC_UNAVAIL
;
9560 SLIST_INIT(&lstate
->accept_tios
);
9561 SLIST_INIT(&lstate
->immed_notifies
);
9564 if (target
!= CAM_TARGET_WILDCARD
) {
9565 tstate
->enabled_luns
[lun
] = lstate
;
9566 ahd
->enabled_luns
++;
9568 if ((ahd
->features
& AHD_MULTI_TID
) != 0) {
9571 targid_mask
= ahd_inw(ahd
, TARGID
);
9572 targid_mask
|= target_mask
;
9573 ahd_outw(ahd
, TARGID
, targid_mask
);
9574 ahd_update_scsiid(ahd
, targid_mask
);
9579 channel
= SIM_CHANNEL(ahd
, sim
);
9580 our_id
= SIM_SCSI_ID(ahd
, sim
);
9583 * This can only happen if selections
9586 if (target
!= our_id
) {
9591 sblkctl
= ahd_inb(ahd
, SBLKCTL
);
9592 cur_channel
= (sblkctl
& SELBUSB
)
9594 if ((ahd
->features
& AHD_TWIN
) == 0)
9596 swap
= cur_channel
!= channel
;
9597 ahd
->our_id
= target
;
9600 ahd_outb(ahd
, SBLKCTL
,
9603 ahd_outb(ahd
, SCSIID
, target
);
9606 ahd_outb(ahd
, SBLKCTL
, sblkctl
);
9610 ahd
->black_hole
= lstate
;
9611 /* Allow select-in operations */
9612 if (ahd
->black_hole
!= NULL
&& ahd
->enabled_luns
> 0) {
9613 scsiseq1
= ahd_inb(ahd
, SCSISEQ_TEMPLATE
);
9615 ahd_outb(ahd
, SCSISEQ_TEMPLATE
, scsiseq1
);
9616 scsiseq1
= ahd_inb(ahd
, SCSISEQ1
);
9618 ahd_outb(ahd
, SCSISEQ1
, scsiseq1
);
9621 ahd_unlock(ahd
, &s
);
9622 ccb
->ccb_h
.status
= CAM_REQ_CMP
;
9623 xpt_print_path(ccb
->ccb_h
.path
);
9624 printf("Lun now enabled for target mode\n");
9629 if (lstate
== NULL
) {
9630 ccb
->ccb_h
.status
= CAM_LUN_INVALID
;
9636 ccb
->ccb_h
.status
= CAM_REQ_CMP
;
9637 LIST_FOREACH(scb
, &ahd
->pending_scbs
, pending_links
) {
9638 struct ccb_hdr
*ccbh
;
9640 ccbh
= &scb
->io_ctx
->ccb_h
;
9641 if (ccbh
->func_code
== XPT_CONT_TARGET_IO
9642 && !xpt_path_comp(ccbh
->path
, ccb
->ccb_h
.path
)){
9643 printf("CTIO pending\n");
9644 ccb
->ccb_h
.status
= CAM_REQ_INVALID
;
9645 ahd_unlock(ahd
, &s
);
9650 if (SLIST_FIRST(&lstate
->accept_tios
) != NULL
) {
9651 printf("ATIOs pending\n");
9652 ccb
->ccb_h
.status
= CAM_REQ_INVALID
;
9655 if (SLIST_FIRST(&lstate
->immed_notifies
) != NULL
) {
9656 printf("INOTs pending\n");
9657 ccb
->ccb_h
.status
= CAM_REQ_INVALID
;
9660 if (ccb
->ccb_h
.status
!= CAM_REQ_CMP
) {
9661 ahd_unlock(ahd
, &s
);
9665 xpt_print_path(ccb
->ccb_h
.path
);
9666 printf("Target mode disabled\n");
9667 xpt_free_path(lstate
->path
);
9668 free(lstate
, M_DEVBUF
);
9671 /* Can we clean up the target too? */
9672 if (target
!= CAM_TARGET_WILDCARD
) {
9673 tstate
->enabled_luns
[lun
] = NULL
;
9674 ahd
->enabled_luns
--;
9675 for (empty
= 1, i
= 0; i
< 8; i
++)
9676 if (tstate
->enabled_luns
[i
] != NULL
) {
9682 ahd_free_tstate(ahd
, target
, channel
,
9684 if (ahd
->features
& AHD_MULTI_TID
) {
9687 targid_mask
= ahd_inw(ahd
, TARGID
);
9688 targid_mask
&= ~target_mask
;
9689 ahd_outw(ahd
, TARGID
, targid_mask
);
9690 ahd_update_scsiid(ahd
, targid_mask
);
9695 ahd
->black_hole
= NULL
;
9698 * We can't allow selections without
9699 * our black hole device.
9703 if (ahd
->enabled_luns
== 0) {
9704 /* Disallow select-in */
9707 scsiseq1
= ahd_inb(ahd
, SCSISEQ_TEMPLATE
);
9708 scsiseq1
&= ~ENSELI
;
9709 ahd_outb(ahd
, SCSISEQ_TEMPLATE
, scsiseq1
);
9710 scsiseq1
= ahd_inb(ahd
, SCSISEQ1
);
9711 scsiseq1
&= ~ENSELI
;
9712 ahd_outb(ahd
, SCSISEQ1
, scsiseq1
);
9714 if ((ahd
->features
& AHD_MULTIROLE
) == 0) {
9715 printf("Configuring Initiator Mode\n");
9716 ahd
->flags
&= ~AHD_TARGETROLE
;
9717 ahd
->flags
|= AHD_INITIATORROLE
;
9722 * Unpaused. The extra unpause
9723 * that follows is harmless.
9728 ahd_unlock(ahd
, &s
);
9734 ahd_update_scsiid(struct ahd_softc
*ahd
, u_int targid_mask
)
9740 if ((ahd
->features
& AHD_MULTI_TID
) == 0)
9741 panic("ahd_update_scsiid called on non-multitid unit\n");
9744 * Since we will rely on the TARGID mask
9745 * for selection enables, ensure that OID
9746 * in SCSIID is not set to some other ID
9747 * that we don't want to allow selections on.
9749 if ((ahd
->features
& AHD_ULTRA2
) != 0)
9750 scsiid
= ahd_inb(ahd
, SCSIID_ULTRA2
);
9752 scsiid
= ahd_inb(ahd
, SCSIID
);
9753 scsiid_mask
= 0x1 << (scsiid
& OID
);
9754 if ((targid_mask
& scsiid_mask
) == 0) {
9757 /* ffs counts from 1 */
9758 our_id
= ffs(targid_mask
);
9760 our_id
= ahd
->our_id
;
9766 if ((ahd
->features
& AHD_ULTRA2
) != 0)
9767 ahd_outb(ahd
, SCSIID_ULTRA2
, scsiid
);
9769 ahd_outb(ahd
, SCSIID
, scsiid
);
9774 ahd_run_tqinfifo(struct ahd_softc
*ahd
, int paused
)
9776 struct target_cmd
*cmd
;
9778 ahd_sync_tqinfifo(ahd
, BUS_DMASYNC_POSTREAD
);
9779 while ((cmd
= &ahd
->targetcmds
[ahd
->tqinfifonext
])->cmd_valid
!= 0) {
9782 * Only advance through the queue if we
9783 * have the resources to process the command.
9785 if (ahd_handle_target_cmd(ahd
, cmd
) != 0)
9789 ahd_dmamap_sync(ahd
, ahd
->shared_data_dmat
,
9790 ahd
->shared_data_map
.dmamap
,
9791 ahd_targetcmd_offset(ahd
, ahd
->tqinfifonext
),
9792 sizeof(struct target_cmd
),
9793 BUS_DMASYNC_PREREAD
);
9794 ahd
->tqinfifonext
++;
9797 * Lazily update our position in the target mode incoming
9798 * command queue as seen by the sequencer.
9800 if ((ahd
->tqinfifonext
& (HOST_TQINPOS
- 1)) == 1) {
9803 hs_mailbox
= ahd_inb(ahd
, HS_MAILBOX
);
9804 hs_mailbox
&= ~HOST_TQINPOS
;
9805 hs_mailbox
|= ahd
->tqinfifonext
& HOST_TQINPOS
;
9806 ahd_outb(ahd
, HS_MAILBOX
, hs_mailbox
);
9812 ahd_handle_target_cmd(struct ahd_softc
*ahd
, struct target_cmd
*cmd
)
9814 struct ahd_tmode_tstate
*tstate
;
9815 struct ahd_tmode_lstate
*lstate
;
9816 struct ccb_accept_tio
*atio
;
9822 initiator
= SCSIID_TARGET(ahd
, cmd
->scsiid
);
9823 target
= SCSIID_OUR_ID(cmd
->scsiid
);
9824 lun
= (cmd
->identify
& MSG_IDENTIFY_LUNMASK
);
9827 tstate
= ahd
->enabled_targets
[target
];
9830 lstate
= tstate
->enabled_luns
[lun
];
9833 * Commands for disabled luns go to the black hole driver.
9836 lstate
= ahd
->black_hole
;
9838 atio
= (struct ccb_accept_tio
*)SLIST_FIRST(&lstate
->accept_tios
);
9840 ahd
->flags
|= AHD_TQINFIFO_BLOCKED
;
9842 * Wait for more ATIOs from the peripheral driver for this lun.
9846 ahd
->flags
&= ~AHD_TQINFIFO_BLOCKED
;
9848 if ((ahd_debug
& AHD_SHOW_TQIN
) != 0)
9849 printf("Incoming command from %d for %d:%d%s\n",
9850 initiator
, target
, lun
,
9851 lstate
== ahd
->black_hole
? "(Black Holed)" : "");
9853 SLIST_REMOVE_HEAD(&lstate
->accept_tios
, sim_links
.sle
);
9855 if (lstate
== ahd
->black_hole
) {
9856 /* Fill in the wildcards */
9857 atio
->ccb_h
.target_id
= target
;
9858 atio
->ccb_h
.target_lun
= lun
;
9862 * Package it up and send it off to
9863 * whomever has this lun enabled.
9865 atio
->sense_len
= 0;
9866 atio
->init_id
= initiator
;
9867 if (byte
[0] != 0xFF) {
9868 /* Tag was included */
9869 atio
->tag_action
= *byte
++;
9870 atio
->tag_id
= *byte
++;
9871 atio
->ccb_h
.flags
= CAM_TAG_ACTION_VALID
;
9873 atio
->ccb_h
.flags
= 0;
9877 /* Okay. Now determine the cdb size based on the command code */
9878 switch (*byte
>> CMD_GROUP_CODE_SHIFT
) {
9894 /* Only copy the opcode. */
9896 printf("Reserved or VU command code type encountered\n");
9900 memcpy(atio
->cdb_io
.cdb_bytes
, byte
, atio
->cdb_len
);
9902 atio
->ccb_h
.status
|= CAM_CDB_RECVD
;
9904 if ((cmd
->identify
& MSG_IDENTIFY_DISCFLAG
) == 0) {
9906 * We weren't allowed to disconnect.
9907 * We're hanging on the bus until a
9908 * continue target I/O comes in response
9909 * to this accept tio.
9912 if ((ahd_debug
& AHD_SHOW_TQIN
) != 0)
9913 printf("Received Immediate Command %d:%d:%d - %p\n",
9914 initiator
, target
, lun
, ahd
->pending_device
);
9916 ahd
->pending_device
= lstate
;
9917 ahd_freeze_ccb((union ccb
*)atio
);
9918 atio
->ccb_h
.flags
|= CAM_DIS_DISCONNECT
;
9920 xpt_done((union ccb
*)atio
);