2 * pdc_adma.c - Pacific Digital Corporation ADMA
4 * Maintained by: Mark Lord <mlord@pobox.com>
6 * Copyright 2005 Mark Lord
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2, or (at your option)
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
18 * You should have received a copy of the GNU General Public License
19 * along with this program; see the file COPYING. If not, write to
20 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
23 * libata documentation is available via 'make {ps|pdf}docs',
24 * as Documentation/DocBook/libata.*
27 * Supports ATA disks in single-packet ADMA mode.
28 * Uses PIO for everything else.
30 * TODO: Use ADMA transfers for ATAPI devices, when possible.
31 * This requires careful attention to a number of quirks of the chip.
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/init.h>
39 #include <linux/blkdev.h>
40 #include <linux/delay.h>
41 #include <linux/interrupt.h>
42 #include <linux/sched.h>
43 #include <linux/device.h>
44 #include <scsi/scsi_host.h>
46 #include <linux/libata.h>
48 #define DRV_NAME "pdc_adma"
49 #define DRV_VERSION "0.03"
51 /* macro to calculate base address for ATA regs */
52 #define ADMA_ATA_REGS(base,port_no) ((base) + ((port_no) * 0x40))
54 /* macro to calculate base address for ADMA regs */
55 #define ADMA_REGS(base,port_no) ((base) + 0x80 + ((port_no) * 0x20))
60 ADMA_PRD_BYTES
= LIBATA_MAX_PRD
* 16,
61 ADMA_PKT_BYTES
= ADMA_CPB_BYTES
+ ADMA_PRD_BYTES
,
63 ADMA_DMA_BOUNDARY
= 0xffffffff,
65 /* global register offsets */
66 ADMA_MODE_LOCK
= 0x00c7,
68 /* per-channel register offsets */
69 ADMA_CONTROL
= 0x0000, /* ADMA control */
70 ADMA_STATUS
= 0x0002, /* ADMA status */
71 ADMA_CPB_COUNT
= 0x0004, /* CPB count */
72 ADMA_CPB_CURRENT
= 0x000c, /* current CPB address */
73 ADMA_CPB_NEXT
= 0x000c, /* next CPB address */
74 ADMA_CPB_LOOKUP
= 0x0010, /* CPB lookup table */
75 ADMA_FIFO_IN
= 0x0014, /* input FIFO threshold */
76 ADMA_FIFO_OUT
= 0x0016, /* output FIFO threshold */
78 /* ADMA_CONTROL register bits */
79 aNIEN
= (1 << 8), /* irq mask: 1==masked */
80 aGO
= (1 << 7), /* packet trigger ("Go!") */
81 aRSTADM
= (1 << 5), /* ADMA logic reset */
82 aPIOMD4
= 0x0003, /* PIO mode 4 */
84 /* ADMA_STATUS register bits */
100 /* ATA register flags */
104 /* ATA register addresses */
105 ADMA_REGS_CONTROL
= 0x0e,
106 ADMA_REGS_SECTOR_COUNT
= 0x12,
107 ADMA_REGS_LBA_LOW
= 0x13,
108 ADMA_REGS_LBA_MID
= 0x14,
109 ADMA_REGS_LBA_HIGH
= 0x15,
110 ADMA_REGS_DEVICE
= 0x16,
111 ADMA_REGS_COMMAND
= 0x17,
114 board_1841_idx
= 0, /* ADMA 2-port controller */
117 typedef enum { adma_state_idle
, adma_state_pkt
, adma_state_mmio
} adma_state_t
;
119 struct adma_port_priv
{
125 static int adma_ata_init_one (struct pci_dev
*pdev
,
126 const struct pci_device_id
*ent
);
127 static irqreturn_t
adma_intr (int irq
, void *dev_instance
,
128 struct pt_regs
*regs
);
129 static int adma_port_start(struct ata_port
*ap
);
130 static void adma_host_stop(struct ata_host_set
*host_set
);
131 static void adma_port_stop(struct ata_port
*ap
);
132 static void adma_phy_reset(struct ata_port
*ap
);
133 static void adma_qc_prep(struct ata_queued_cmd
*qc
);
134 static unsigned int adma_qc_issue(struct ata_queued_cmd
*qc
);
135 static int adma_check_atapi_dma(struct ata_queued_cmd
*qc
);
136 static void adma_bmdma_stop(struct ata_queued_cmd
*qc
);
137 static u8
adma_bmdma_status(struct ata_port
*ap
);
138 static void adma_irq_clear(struct ata_port
*ap
);
139 static void adma_eng_timeout(struct ata_port
*ap
);
141 static struct scsi_host_template adma_ata_sht
= {
142 .module
= THIS_MODULE
,
144 .ioctl
= ata_scsi_ioctl
,
145 .queuecommand
= ata_scsi_queuecmd
,
146 .can_queue
= ATA_DEF_QUEUE
,
147 .this_id
= ATA_SHT_THIS_ID
,
148 .sg_tablesize
= LIBATA_MAX_PRD
,
149 .cmd_per_lun
= ATA_SHT_CMD_PER_LUN
,
150 .emulated
= ATA_SHT_EMULATED
,
151 .use_clustering
= ENABLE_CLUSTERING
,
152 .proc_name
= DRV_NAME
,
153 .dma_boundary
= ADMA_DMA_BOUNDARY
,
154 .slave_configure
= ata_scsi_slave_config
,
155 .bios_param
= ata_std_bios_param
,
158 static const struct ata_port_operations adma_ata_ops
= {
159 .port_disable
= ata_port_disable
,
160 .tf_load
= ata_tf_load
,
161 .tf_read
= ata_tf_read
,
162 .check_status
= ata_check_status
,
163 .check_atapi_dma
= adma_check_atapi_dma
,
164 .exec_command
= ata_exec_command
,
165 .dev_select
= ata_std_dev_select
,
166 .phy_reset
= adma_phy_reset
,
167 .qc_prep
= adma_qc_prep
,
168 .qc_issue
= adma_qc_issue
,
169 .eng_timeout
= adma_eng_timeout
,
170 .irq_handler
= adma_intr
,
171 .irq_clear
= adma_irq_clear
,
172 .port_start
= adma_port_start
,
173 .port_stop
= adma_port_stop
,
174 .host_stop
= adma_host_stop
,
175 .bmdma_stop
= adma_bmdma_stop
,
176 .bmdma_status
= adma_bmdma_status
,
179 static struct ata_port_info adma_port_info
[] = {
182 .sht
= &adma_ata_sht
,
183 .host_flags
= ATA_FLAG_SLAVE_POSS
| ATA_FLAG_SRST
|
184 ATA_FLAG_NO_LEGACY
| ATA_FLAG_MMIO
,
185 .pio_mask
= 0x10, /* pio4 */
186 .udma_mask
= 0x1f, /* udma0-4 */
187 .port_ops
= &adma_ata_ops
,
191 static const struct pci_device_id adma_ata_pci_tbl
[] = {
192 { PCI_VENDOR_ID_PDC
, 0x1841, PCI_ANY_ID
, PCI_ANY_ID
, 0, 0,
195 { } /* terminate list */
198 static struct pci_driver adma_ata_pci_driver
= {
200 .id_table
= adma_ata_pci_tbl
,
201 .probe
= adma_ata_init_one
,
202 .remove
= ata_pci_remove_one
,
205 static int adma_check_atapi_dma(struct ata_queued_cmd
*qc
)
207 return 1; /* ATAPI DMA not yet supported */
210 static void adma_bmdma_stop(struct ata_queued_cmd
*qc
)
215 static u8
adma_bmdma_status(struct ata_port
*ap
)
220 static void adma_irq_clear(struct ata_port
*ap
)
225 static void adma_reset_engine(void __iomem
*chan
)
227 /* reset ADMA to idle state */
228 writew(aPIOMD4
| aNIEN
| aRSTADM
, chan
+ ADMA_CONTROL
);
230 writew(aPIOMD4
, chan
+ ADMA_CONTROL
);
234 static void adma_reinit_engine(struct ata_port
*ap
)
236 struct adma_port_priv
*pp
= ap
->private_data
;
237 void __iomem
*mmio_base
= ap
->host_set
->mmio_base
;
238 void __iomem
*chan
= ADMA_REGS(mmio_base
, ap
->port_no
);
240 /* mask/clear ATA interrupts */
241 writeb(ATA_NIEN
, (void __iomem
*)ap
->ioaddr
.ctl_addr
);
242 ata_check_status(ap
);
244 /* reset the ADMA engine */
245 adma_reset_engine(chan
);
247 /* set in-FIFO threshold to 0x100 */
248 writew(0x100, chan
+ ADMA_FIFO_IN
);
250 /* set CPB pointer */
251 writel((u32
)pp
->pkt_dma
, chan
+ ADMA_CPB_NEXT
);
253 /* set out-FIFO threshold to 0x100 */
254 writew(0x100, chan
+ ADMA_FIFO_OUT
);
257 writew(1, chan
+ ADMA_CPB_COUNT
);
259 /* read/discard ADMA status */
260 readb(chan
+ ADMA_STATUS
);
263 static inline void adma_enter_reg_mode(struct ata_port
*ap
)
265 void __iomem
*chan
= ADMA_REGS(ap
->host_set
->mmio_base
, ap
->port_no
);
267 writew(aPIOMD4
, chan
+ ADMA_CONTROL
);
268 readb(chan
+ ADMA_STATUS
); /* flush */
271 static void adma_phy_reset(struct ata_port
*ap
)
273 struct adma_port_priv
*pp
= ap
->private_data
;
275 pp
->state
= adma_state_idle
;
276 adma_reinit_engine(ap
);
281 static void adma_eng_timeout(struct ata_port
*ap
)
283 struct adma_port_priv
*pp
= ap
->private_data
;
285 if (pp
->state
!= adma_state_idle
) /* healthy paranoia */
286 pp
->state
= adma_state_mmio
;
287 adma_reinit_engine(ap
);
291 static int adma_fill_sg(struct ata_queued_cmd
*qc
)
293 struct scatterlist
*sg
;
294 struct ata_port
*ap
= qc
->ap
;
295 struct adma_port_priv
*pp
= ap
->private_data
;
297 int i
= (2 + buf
[3]) * 8;
298 u8 pFLAGS
= pORD
| ((qc
->tf
.flags
& ATA_TFLAG_WRITE
) ? pDIRO
: 0);
300 ata_for_each_sg(sg
, qc
) {
304 addr
= (u32
)sg_dma_address(sg
);
305 *(__le32
*)(buf
+ i
) = cpu_to_le32(addr
);
308 len
= sg_dma_len(sg
) >> 3;
309 *(__le32
*)(buf
+ i
) = cpu_to_le32(len
);
312 if (ata_sg_is_last(sg
, qc
))
315 buf
[i
++] = qc
->dev
->dma_mode
& 0xf;
316 buf
[i
++] = 0; /* pPKLW */
317 buf
[i
++] = 0; /* reserved */
320 = (pFLAGS
& pEND
) ? 0 : cpu_to_le32(pp
->pkt_dma
+ i
+ 4);
323 VPRINTK("PRD[%u] = (0x%lX, 0x%X)\n", i
/4,
324 (unsigned long)addr
, len
);
329 static void adma_qc_prep(struct ata_queued_cmd
*qc
)
331 struct adma_port_priv
*pp
= qc
->ap
->private_data
;
333 u32 pkt_dma
= (u32
)pp
->pkt_dma
;
338 adma_enter_reg_mode(qc
->ap
);
339 if (qc
->tf
.protocol
!= ATA_PROT_DMA
) {
344 buf
[i
++] = 0; /* Response flags */
345 buf
[i
++] = 0; /* reserved */
346 buf
[i
++] = cVLD
| cDAT
| cIEN
;
347 i
++; /* cLEN, gets filled in below */
349 *(__le32
*)(buf
+i
) = cpu_to_le32(pkt_dma
); /* cNCPB */
351 i
+= 4; /* cPRD, gets filled in below */
353 buf
[i
++] = 0; /* reserved */
354 buf
[i
++] = 0; /* reserved */
355 buf
[i
++] = 0; /* reserved */
356 buf
[i
++] = 0; /* reserved */
358 /* ATA registers; must be a multiple of 4 */
359 buf
[i
++] = qc
->tf
.device
;
360 buf
[i
++] = ADMA_REGS_DEVICE
;
361 if ((qc
->tf
.flags
& ATA_TFLAG_LBA48
)) {
362 buf
[i
++] = qc
->tf
.hob_nsect
;
363 buf
[i
++] = ADMA_REGS_SECTOR_COUNT
;
364 buf
[i
++] = qc
->tf
.hob_lbal
;
365 buf
[i
++] = ADMA_REGS_LBA_LOW
;
366 buf
[i
++] = qc
->tf
.hob_lbam
;
367 buf
[i
++] = ADMA_REGS_LBA_MID
;
368 buf
[i
++] = qc
->tf
.hob_lbah
;
369 buf
[i
++] = ADMA_REGS_LBA_HIGH
;
371 buf
[i
++] = qc
->tf
.nsect
;
372 buf
[i
++] = ADMA_REGS_SECTOR_COUNT
;
373 buf
[i
++] = qc
->tf
.lbal
;
374 buf
[i
++] = ADMA_REGS_LBA_LOW
;
375 buf
[i
++] = qc
->tf
.lbam
;
376 buf
[i
++] = ADMA_REGS_LBA_MID
;
377 buf
[i
++] = qc
->tf
.lbah
;
378 buf
[i
++] = ADMA_REGS_LBA_HIGH
;
380 buf
[i
++] = ADMA_REGS_CONTROL
;
383 buf
[i
++] = qc
->tf
.command
;
384 buf
[i
++] = ADMA_REGS_COMMAND
| rEND
;
386 buf
[3] = (i
>> 3) - 2; /* cLEN */
387 *(__le32
*)(buf
+8) = cpu_to_le32(pkt_dma
+ i
); /* cPRD */
389 i
= adma_fill_sg(qc
);
390 wmb(); /* flush PRDs and pkt to memory */
392 /* dump out CPB + PRDs for debug */
395 static char obuf
[2048];
396 for (j
= 0; j
< i
; ++j
) {
397 len
+= sprintf(obuf
+len
, "%02x ", buf
[j
]);
399 printk("%s\n", obuf
);
404 printk("%s\n", obuf
);
409 static inline void adma_packet_start(struct ata_queued_cmd
*qc
)
411 struct ata_port
*ap
= qc
->ap
;
412 void __iomem
*chan
= ADMA_REGS(ap
->host_set
->mmio_base
, ap
->port_no
);
414 VPRINTK("ENTER, ap %p\n", ap
);
416 /* fire up the ADMA engine */
417 writew(aPIOMD4
| aGO
, chan
+ ADMA_CONTROL
);
420 static unsigned int adma_qc_issue(struct ata_queued_cmd
*qc
)
422 struct adma_port_priv
*pp
= qc
->ap
->private_data
;
424 switch (qc
->tf
.protocol
) {
426 pp
->state
= adma_state_pkt
;
427 adma_packet_start(qc
);
430 case ATA_PROT_ATAPI_DMA
:
438 pp
->state
= adma_state_mmio
;
439 return ata_qc_issue_prot(qc
);
442 static inline unsigned int adma_intr_pkt(struct ata_host_set
*host_set
)
444 unsigned int handled
= 0, port_no
;
445 u8 __iomem
*mmio_base
= host_set
->mmio_base
;
447 for (port_no
= 0; port_no
< host_set
->n_ports
; ++port_no
) {
448 struct ata_port
*ap
= host_set
->ports
[port_no
];
449 struct adma_port_priv
*pp
;
450 struct ata_queued_cmd
*qc
;
451 void __iomem
*chan
= ADMA_REGS(mmio_base
, port_no
);
452 u8 status
= readb(chan
+ ADMA_STATUS
);
457 adma_enter_reg_mode(ap
);
458 if (ap
->flags
& (ATA_FLAG_PORT_DISABLED
| ATA_FLAG_NOINTR
))
460 pp
= ap
->private_data
;
461 if (!pp
|| pp
->state
!= adma_state_pkt
)
463 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
464 if (qc
&& (!(qc
->tf
.ctl
& ATA_NIEN
))) {
465 if ((status
& (aPERR
| aPSD
| aUIRQ
)))
466 qc
->err_mask
|= AC_ERR_OTHER
;
467 else if (pp
->pkt
[0] != cDONE
)
468 qc
->err_mask
|= AC_ERR_OTHER
;
476 static inline unsigned int adma_intr_mmio(struct ata_host_set
*host_set
)
478 unsigned int handled
= 0, port_no
;
480 for (port_no
= 0; port_no
< host_set
->n_ports
; ++port_no
) {
482 ap
= host_set
->ports
[port_no
];
483 if (ap
&& (!(ap
->flags
& (ATA_FLAG_PORT_DISABLED
| ATA_FLAG_NOINTR
)))) {
484 struct ata_queued_cmd
*qc
;
485 struct adma_port_priv
*pp
= ap
->private_data
;
486 if (!pp
|| pp
->state
!= adma_state_mmio
)
488 qc
= ata_qc_from_tag(ap
, ap
->active_tag
);
489 if (qc
&& (!(qc
->tf
.ctl
& ATA_NIEN
))) {
491 /* check main status, clearing INTRQ */
492 u8 status
= ata_check_status(ap
);
493 if ((status
& ATA_BUSY
))
495 DPRINTK("ata%u: protocol %d (dev_stat 0x%X)\n",
496 ap
->id
, qc
->tf
.protocol
, status
);
498 /* complete taskfile transaction */
499 pp
->state
= adma_state_idle
;
500 qc
->err_mask
|= ac_err_mask(status
);
509 static irqreturn_t
adma_intr(int irq
, void *dev_instance
, struct pt_regs
*regs
)
511 struct ata_host_set
*host_set
= dev_instance
;
512 unsigned int handled
= 0;
516 spin_lock(&host_set
->lock
);
517 handled
= adma_intr_pkt(host_set
) | adma_intr_mmio(host_set
);
518 spin_unlock(&host_set
->lock
);
522 return IRQ_RETVAL(handled
);
525 static void adma_ata_setup_port(struct ata_ioports
*port
, unsigned long base
)
528 port
->data_addr
= base
+ 0x000;
530 port
->feature_addr
= base
+ 0x004;
531 port
->nsect_addr
= base
+ 0x008;
532 port
->lbal_addr
= base
+ 0x00c;
533 port
->lbam_addr
= base
+ 0x010;
534 port
->lbah_addr
= base
+ 0x014;
535 port
->device_addr
= base
+ 0x018;
537 port
->command_addr
= base
+ 0x01c;
538 port
->altstatus_addr
=
539 port
->ctl_addr
= base
+ 0x038;
542 static int adma_port_start(struct ata_port
*ap
)
544 struct device
*dev
= ap
->host_set
->dev
;
545 struct adma_port_priv
*pp
;
548 rc
= ata_port_start(ap
);
551 adma_enter_reg_mode(ap
);
553 pp
= kcalloc(1, sizeof(*pp
), GFP_KERNEL
);
556 pp
->pkt
= dma_alloc_coherent(dev
, ADMA_PKT_BYTES
, &pp
->pkt_dma
,
561 if ((pp
->pkt_dma
& 7) != 0) {
562 printk("bad alignment for pp->pkt_dma: %08x\n",
564 dma_free_coherent(dev
, ADMA_PKT_BYTES
,
565 pp
->pkt
, pp
->pkt_dma
);
568 memset(pp
->pkt
, 0, ADMA_PKT_BYTES
);
569 ap
->private_data
= pp
;
570 adma_reinit_engine(ap
);
580 static void adma_port_stop(struct ata_port
*ap
)
582 struct device
*dev
= ap
->host_set
->dev
;
583 struct adma_port_priv
*pp
= ap
->private_data
;
585 adma_reset_engine(ADMA_REGS(ap
->host_set
->mmio_base
, ap
->port_no
));
587 ap
->private_data
= NULL
;
589 dma_free_coherent(dev
, ADMA_PKT_BYTES
,
590 pp
->pkt
, pp
->pkt_dma
);
596 static void adma_host_stop(struct ata_host_set
*host_set
)
598 unsigned int port_no
;
600 for (port_no
= 0; port_no
< ADMA_PORTS
; ++port_no
)
601 adma_reset_engine(ADMA_REGS(host_set
->mmio_base
, port_no
));
603 ata_pci_host_stop(host_set
);
606 static void adma_host_init(unsigned int chip_id
,
607 struct ata_probe_ent
*probe_ent
)
609 unsigned int port_no
;
610 void __iomem
*mmio_base
= probe_ent
->mmio_base
;
612 /* enable/lock aGO operation */
613 writeb(7, mmio_base
+ ADMA_MODE_LOCK
);
615 /* reset the ADMA logic */
616 for (port_no
= 0; port_no
< ADMA_PORTS
; ++port_no
)
617 adma_reset_engine(ADMA_REGS(mmio_base
, port_no
));
620 static int adma_set_dma_masks(struct pci_dev
*pdev
, void __iomem
*mmio_base
)
624 rc
= pci_set_dma_mask(pdev
, DMA_32BIT_MASK
);
626 dev_printk(KERN_ERR
, &pdev
->dev
,
627 "32-bit DMA enable failed\n");
630 rc
= pci_set_consistent_dma_mask(pdev
, DMA_32BIT_MASK
);
632 dev_printk(KERN_ERR
, &pdev
->dev
,
633 "32-bit consistent DMA enable failed\n");
639 static int adma_ata_init_one(struct pci_dev
*pdev
,
640 const struct pci_device_id
*ent
)
642 static int printed_version
;
643 struct ata_probe_ent
*probe_ent
= NULL
;
644 void __iomem
*mmio_base
;
645 unsigned int board_idx
= (unsigned int) ent
->driver_data
;
648 if (!printed_version
++)
649 dev_printk(KERN_DEBUG
, &pdev
->dev
, "version " DRV_VERSION
"\n");
651 rc
= pci_enable_device(pdev
);
655 rc
= pci_request_regions(pdev
, DRV_NAME
);
659 if ((pci_resource_flags(pdev
, 4) & IORESOURCE_MEM
) == 0) {
661 goto err_out_regions
;
664 mmio_base
= pci_iomap(pdev
, 4, 0);
665 if (mmio_base
== NULL
) {
667 goto err_out_regions
;
670 rc
= adma_set_dma_masks(pdev
, mmio_base
);
672 goto err_out_iounmap
;
674 probe_ent
= kcalloc(1, sizeof(*probe_ent
), GFP_KERNEL
);
675 if (probe_ent
== NULL
) {
677 goto err_out_iounmap
;
680 probe_ent
->dev
= pci_dev_to_dev(pdev
);
681 INIT_LIST_HEAD(&probe_ent
->node
);
683 probe_ent
->sht
= adma_port_info
[board_idx
].sht
;
684 probe_ent
->host_flags
= adma_port_info
[board_idx
].host_flags
;
685 probe_ent
->pio_mask
= adma_port_info
[board_idx
].pio_mask
;
686 probe_ent
->mwdma_mask
= adma_port_info
[board_idx
].mwdma_mask
;
687 probe_ent
->udma_mask
= adma_port_info
[board_idx
].udma_mask
;
688 probe_ent
->port_ops
= adma_port_info
[board_idx
].port_ops
;
690 probe_ent
->irq
= pdev
->irq
;
691 probe_ent
->irq_flags
= SA_SHIRQ
;
692 probe_ent
->mmio_base
= mmio_base
;
693 probe_ent
->n_ports
= ADMA_PORTS
;
695 for (port_no
= 0; port_no
< probe_ent
->n_ports
; ++port_no
) {
696 adma_ata_setup_port(&probe_ent
->port
[port_no
],
697 ADMA_ATA_REGS((unsigned long)mmio_base
, port_no
));
700 pci_set_master(pdev
);
702 /* initialize adapter */
703 adma_host_init(board_idx
, probe_ent
);
705 rc
= ata_device_add(probe_ent
);
707 if (rc
!= ADMA_PORTS
)
708 goto err_out_iounmap
;
712 pci_iounmap(pdev
, mmio_base
);
714 pci_release_regions(pdev
);
716 pci_disable_device(pdev
);
720 static int __init
adma_ata_init(void)
722 return pci_module_init(&adma_ata_pci_driver
);
725 static void __exit
adma_ata_exit(void)
727 pci_unregister_driver(&adma_ata_pci_driver
);
730 MODULE_AUTHOR("Mark Lord");
731 MODULE_DESCRIPTION("Pacific Digital Corporation ADMA low-level driver");
732 MODULE_LICENSE("GPL");
733 MODULE_DEVICE_TABLE(pci
, adma_ata_pci_tbl
);
734 MODULE_VERSION(DRV_VERSION
);
736 module_init(adma_ata_init
);
737 module_exit(adma_ata_exit
);