1 /* b44.c: Broadcom 4400 device driver.
3 * Copyright (C) 2002 David S. Miller (davem@redhat.com)
4 * Fixed by Pekka Pietikainen (pp@ee.oulu.fi)
6 * Distribute under GPL.
9 #include <linux/kernel.h>
10 #include <linux/module.h>
11 #include <linux/moduleparam.h>
12 #include <linux/types.h>
13 #include <linux/netdevice.h>
14 #include <linux/ethtool.h>
15 #include <linux/mii.h>
16 #include <linux/if_ether.h>
17 #include <linux/etherdevice.h>
18 #include <linux/pci.h>
19 #include <linux/delay.h>
20 #include <linux/init.h>
21 #include <linux/version.h>
22 #include <linux/dma-mapping.h>
24 #include <asm/uaccess.h>
30 #define DRV_MODULE_NAME "b44"
31 #define PFX DRV_MODULE_NAME ": "
32 #define DRV_MODULE_VERSION "0.95"
33 #define DRV_MODULE_RELDATE "Aug 3, 2004"
35 #define B44_DEF_MSG_ENABLE \
45 /* length of time before we decide the hardware is borked,
46 * and dev->tx_timeout() should be called to fix the problem
48 #define B44_TX_TIMEOUT (5 * HZ)
50 /* hardware minimum and maximum for a single frame's data payload */
51 #define B44_MIN_MTU 60
52 #define B44_MAX_MTU 1500
54 #define B44_RX_RING_SIZE 512
55 #define B44_DEF_RX_RING_PENDING 200
56 #define B44_RX_RING_BYTES (sizeof(struct dma_desc) * \
58 #define B44_TX_RING_SIZE 512
59 #define B44_DEF_TX_RING_PENDING (B44_TX_RING_SIZE - 1)
60 #define B44_TX_RING_BYTES (sizeof(struct dma_desc) * \
62 #define B44_DMA_MASK 0x3fffffff
64 #define TX_RING_GAP(BP) \
65 (B44_TX_RING_SIZE - (BP)->tx_pending)
66 #define TX_BUFFS_AVAIL(BP) \
67 (((BP)->tx_cons <= (BP)->tx_prod) ? \
68 (BP)->tx_cons + (BP)->tx_pending - (BP)->tx_prod : \
69 (BP)->tx_cons - (BP)->tx_prod - TX_RING_GAP(BP))
70 #define NEXT_TX(N) (((N) + 1) & (B44_TX_RING_SIZE - 1))
72 #define RX_PKT_BUF_SZ (1536 + bp->rx_offset + 64)
73 #define TX_PKT_BUF_SZ (B44_MAX_MTU + ETH_HLEN + 8)
75 /* minimum number of free TX descriptors required to wake up TX process */
76 #define B44_TX_WAKEUP_THRESH (B44_TX_RING_SIZE / 4)
78 static char version
[] __devinitdata
=
79 DRV_MODULE_NAME
".c:v" DRV_MODULE_VERSION
" (" DRV_MODULE_RELDATE
")\n";
81 MODULE_AUTHOR("Florian Schirmer, Pekka Pietikainen, David S. Miller");
82 MODULE_DESCRIPTION("Broadcom 4400 10/100 PCI ethernet driver");
83 MODULE_LICENSE("GPL");
84 MODULE_VERSION(DRV_MODULE_VERSION
);
86 static int b44_debug
= -1; /* -1 == use B44_DEF_MSG_ENABLE as value */
87 module_param(b44_debug
, int, 0);
88 MODULE_PARM_DESC(b44_debug
, "B44 bitmapped debugging message enable value");
90 static struct pci_device_id b44_pci_tbl
[] = {
91 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_BCM4401
,
92 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
93 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_BCM4401B0
,
94 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
95 { PCI_VENDOR_ID_BROADCOM
, PCI_DEVICE_ID_BCM4401B1
,
96 PCI_ANY_ID
, PCI_ANY_ID
, 0, 0, 0UL },
97 { } /* terminate list with empty entry */
100 MODULE_DEVICE_TABLE(pci
, b44_pci_tbl
);
102 static void b44_halt(struct b44
*);
103 static void b44_init_rings(struct b44
*);
104 static void b44_init_hw(struct b44
*);
106 static int dma_desc_align_mask
;
107 static int dma_desc_sync_size
;
109 static const char b44_gstrings
[][ETH_GSTRING_LEN
] = {
110 #define _B44(x...) # x,
115 static inline void b44_sync_dma_desc_for_device(struct pci_dev
*pdev
,
117 unsigned long offset
,
118 enum dma_data_direction dir
)
120 dma_sync_single_range_for_device(&pdev
->dev
, dma_base
,
121 offset
& dma_desc_align_mask
,
122 dma_desc_sync_size
, dir
);
125 static inline void b44_sync_dma_desc_for_cpu(struct pci_dev
*pdev
,
127 unsigned long offset
,
128 enum dma_data_direction dir
)
130 dma_sync_single_range_for_cpu(&pdev
->dev
, dma_base
,
131 offset
& dma_desc_align_mask
,
132 dma_desc_sync_size
, dir
);
135 static inline unsigned long br32(const struct b44
*bp
, unsigned long reg
)
137 return readl(bp
->regs
+ reg
);
140 static inline void bw32(const struct b44
*bp
,
141 unsigned long reg
, unsigned long val
)
143 writel(val
, bp
->regs
+ reg
);
146 static int b44_wait_bit(struct b44
*bp
, unsigned long reg
,
147 u32 bit
, unsigned long timeout
, const int clear
)
151 for (i
= 0; i
< timeout
; i
++) {
152 u32 val
= br32(bp
, reg
);
154 if (clear
&& !(val
& bit
))
156 if (!clear
&& (val
& bit
))
161 printk(KERN_ERR PFX
"%s: BUG! Timeout waiting for bit %08x of register "
165 (clear
? "clear" : "set"));
171 /* Sonics SiliconBackplane support routines. ROFL, you should see all the
172 * buzz words used on this company's website :-)
174 * All of these routines must be invoked with bp->lock held and
175 * interrupts disabled.
178 #define SB_PCI_DMA 0x40000000 /* Client Mode PCI memory access space (1 GB) */
179 #define BCM4400_PCI_CORE_ADDR 0x18002000 /* Address of PCI core on BCM4400 cards */
181 static u32
ssb_get_core_rev(struct b44
*bp
)
183 return (br32(bp
, B44_SBIDHIGH
) & SBIDHIGH_RC_MASK
);
186 static u32
ssb_pci_setup(struct b44
*bp
, u32 cores
)
188 u32 bar_orig
, pci_rev
, val
;
190 pci_read_config_dword(bp
->pdev
, SSB_BAR0_WIN
, &bar_orig
);
191 pci_write_config_dword(bp
->pdev
, SSB_BAR0_WIN
, BCM4400_PCI_CORE_ADDR
);
192 pci_rev
= ssb_get_core_rev(bp
);
194 val
= br32(bp
, B44_SBINTVEC
);
196 bw32(bp
, B44_SBINTVEC
, val
);
198 val
= br32(bp
, SSB_PCI_TRANS_2
);
199 val
|= SSB_PCI_PREF
| SSB_PCI_BURST
;
200 bw32(bp
, SSB_PCI_TRANS_2
, val
);
202 pci_write_config_dword(bp
->pdev
, SSB_BAR0_WIN
, bar_orig
);
207 static void ssb_core_disable(struct b44
*bp
)
209 if (br32(bp
, B44_SBTMSLOW
) & SBTMSLOW_RESET
)
212 bw32(bp
, B44_SBTMSLOW
, (SBTMSLOW_REJECT
| SBTMSLOW_CLOCK
));
213 b44_wait_bit(bp
, B44_SBTMSLOW
, SBTMSLOW_REJECT
, 100000, 0);
214 b44_wait_bit(bp
, B44_SBTMSHIGH
, SBTMSHIGH_BUSY
, 100000, 1);
215 bw32(bp
, B44_SBTMSLOW
, (SBTMSLOW_FGC
| SBTMSLOW_CLOCK
|
216 SBTMSLOW_REJECT
| SBTMSLOW_RESET
));
217 br32(bp
, B44_SBTMSLOW
);
219 bw32(bp
, B44_SBTMSLOW
, (SBTMSLOW_REJECT
| SBTMSLOW_RESET
));
220 br32(bp
, B44_SBTMSLOW
);
224 static void ssb_core_reset(struct b44
*bp
)
228 ssb_core_disable(bp
);
229 bw32(bp
, B44_SBTMSLOW
, (SBTMSLOW_RESET
| SBTMSLOW_CLOCK
| SBTMSLOW_FGC
));
230 br32(bp
, B44_SBTMSLOW
);
233 /* Clear SERR if set, this is a hw bug workaround. */
234 if (br32(bp
, B44_SBTMSHIGH
) & SBTMSHIGH_SERR
)
235 bw32(bp
, B44_SBTMSHIGH
, 0);
237 val
= br32(bp
, B44_SBIMSTATE
);
238 if (val
& (SBIMSTATE_IBE
| SBIMSTATE_TO
))
239 bw32(bp
, B44_SBIMSTATE
, val
& ~(SBIMSTATE_IBE
| SBIMSTATE_TO
));
241 bw32(bp
, B44_SBTMSLOW
, (SBTMSLOW_CLOCK
| SBTMSLOW_FGC
));
242 br32(bp
, B44_SBTMSLOW
);
245 bw32(bp
, B44_SBTMSLOW
, (SBTMSLOW_CLOCK
));
246 br32(bp
, B44_SBTMSLOW
);
250 static int ssb_core_unit(struct b44
*bp
)
253 u32 val
= br32(bp
, B44_SBADMATCH0
);
256 type
= val
& SBADMATCH0_TYPE_MASK
;
259 base
= val
& SBADMATCH0_BS0_MASK
;
263 base
= val
& SBADMATCH0_BS1_MASK
;
268 base
= val
& SBADMATCH0_BS2_MASK
;
275 static int ssb_is_core_up(struct b44
*bp
)
277 return ((br32(bp
, B44_SBTMSLOW
) & (SBTMSLOW_RESET
| SBTMSLOW_REJECT
| SBTMSLOW_CLOCK
))
281 static void __b44_cam_write(struct b44
*bp
, unsigned char *data
, int index
)
285 val
= ((u32
) data
[2]) << 24;
286 val
|= ((u32
) data
[3]) << 16;
287 val
|= ((u32
) data
[4]) << 8;
288 val
|= ((u32
) data
[5]) << 0;
289 bw32(bp
, B44_CAM_DATA_LO
, val
);
290 val
= (CAM_DATA_HI_VALID
|
291 (((u32
) data
[0]) << 8) |
292 (((u32
) data
[1]) << 0));
293 bw32(bp
, B44_CAM_DATA_HI
, val
);
294 bw32(bp
, B44_CAM_CTRL
, (CAM_CTRL_WRITE
|
295 (index
<< CAM_CTRL_INDEX_SHIFT
)));
296 b44_wait_bit(bp
, B44_CAM_CTRL
, CAM_CTRL_BUSY
, 100, 1);
299 static inline void __b44_disable_ints(struct b44
*bp
)
301 bw32(bp
, B44_IMASK
, 0);
304 static void b44_disable_ints(struct b44
*bp
)
306 __b44_disable_ints(bp
);
308 /* Flush posted writes. */
312 static void b44_enable_ints(struct b44
*bp
)
314 bw32(bp
, B44_IMASK
, bp
->imask
);
317 static int b44_readphy(struct b44
*bp
, int reg
, u32
*val
)
321 bw32(bp
, B44_EMAC_ISTAT
, EMAC_INT_MII
);
322 bw32(bp
, B44_MDIO_DATA
, (MDIO_DATA_SB_START
|
323 (MDIO_OP_READ
<< MDIO_DATA_OP_SHIFT
) |
324 (bp
->phy_addr
<< MDIO_DATA_PMD_SHIFT
) |
325 (reg
<< MDIO_DATA_RA_SHIFT
) |
326 (MDIO_TA_VALID
<< MDIO_DATA_TA_SHIFT
)));
327 err
= b44_wait_bit(bp
, B44_EMAC_ISTAT
, EMAC_INT_MII
, 100, 0);
328 *val
= br32(bp
, B44_MDIO_DATA
) & MDIO_DATA_DATA
;
333 static int b44_writephy(struct b44
*bp
, int reg
, u32 val
)
335 bw32(bp
, B44_EMAC_ISTAT
, EMAC_INT_MII
);
336 bw32(bp
, B44_MDIO_DATA
, (MDIO_DATA_SB_START
|
337 (MDIO_OP_WRITE
<< MDIO_DATA_OP_SHIFT
) |
338 (bp
->phy_addr
<< MDIO_DATA_PMD_SHIFT
) |
339 (reg
<< MDIO_DATA_RA_SHIFT
) |
340 (MDIO_TA_VALID
<< MDIO_DATA_TA_SHIFT
) |
341 (val
& MDIO_DATA_DATA
)));
342 return b44_wait_bit(bp
, B44_EMAC_ISTAT
, EMAC_INT_MII
, 100, 0);
345 /* miilib interface */
346 /* FIXME FIXME: phy_id is ignored, bp->phy_addr use is unconditional
347 * due to code existing before miilib use was added to this driver.
348 * Someone should remove this artificial driver limitation in
349 * b44_{read,write}phy. bp->phy_addr itself is fine (and needed).
351 static int b44_mii_read(struct net_device
*dev
, int phy_id
, int location
)
354 struct b44
*bp
= netdev_priv(dev
);
355 int rc
= b44_readphy(bp
, location
, &val
);
361 static void b44_mii_write(struct net_device
*dev
, int phy_id
, int location
,
364 struct b44
*bp
= netdev_priv(dev
);
365 b44_writephy(bp
, location
, val
);
368 static int b44_phy_reset(struct b44
*bp
)
373 err
= b44_writephy(bp
, MII_BMCR
, BMCR_RESET
);
377 err
= b44_readphy(bp
, MII_BMCR
, &val
);
379 if (val
& BMCR_RESET
) {
380 printk(KERN_ERR PFX
"%s: PHY Reset would not complete.\n",
389 static void __b44_set_flow_ctrl(struct b44
*bp
, u32 pause_flags
)
393 bp
->flags
&= ~(B44_FLAG_TX_PAUSE
| B44_FLAG_RX_PAUSE
);
394 bp
->flags
|= pause_flags
;
396 val
= br32(bp
, B44_RXCONFIG
);
397 if (pause_flags
& B44_FLAG_RX_PAUSE
)
398 val
|= RXCONFIG_FLOW
;
400 val
&= ~RXCONFIG_FLOW
;
401 bw32(bp
, B44_RXCONFIG
, val
);
403 val
= br32(bp
, B44_MAC_FLOW
);
404 if (pause_flags
& B44_FLAG_TX_PAUSE
)
405 val
|= (MAC_FLOW_PAUSE_ENAB
|
406 (0xc0 & MAC_FLOW_RX_HI_WATER
));
408 val
&= ~MAC_FLOW_PAUSE_ENAB
;
409 bw32(bp
, B44_MAC_FLOW
, val
);
412 static void b44_set_flow_ctrl(struct b44
*bp
, u32 local
, u32 remote
)
414 u32 pause_enab
= bp
->flags
& (B44_FLAG_TX_PAUSE
|
417 if (local
& ADVERTISE_PAUSE_CAP
) {
418 if (local
& ADVERTISE_PAUSE_ASYM
) {
419 if (remote
& LPA_PAUSE_CAP
)
420 pause_enab
|= (B44_FLAG_TX_PAUSE
|
422 else if (remote
& LPA_PAUSE_ASYM
)
423 pause_enab
|= B44_FLAG_RX_PAUSE
;
425 if (remote
& LPA_PAUSE_CAP
)
426 pause_enab
|= (B44_FLAG_TX_PAUSE
|
429 } else if (local
& ADVERTISE_PAUSE_ASYM
) {
430 if ((remote
& LPA_PAUSE_CAP
) &&
431 (remote
& LPA_PAUSE_ASYM
))
432 pause_enab
|= B44_FLAG_TX_PAUSE
;
435 __b44_set_flow_ctrl(bp
, pause_enab
);
438 static int b44_setup_phy(struct b44
*bp
)
443 if ((err
= b44_readphy(bp
, B44_MII_ALEDCTRL
, &val
)) != 0)
445 if ((err
= b44_writephy(bp
, B44_MII_ALEDCTRL
,
446 val
& MII_ALEDCTRL_ALLMSK
)) != 0)
448 if ((err
= b44_readphy(bp
, B44_MII_TLEDCTRL
, &val
)) != 0)
450 if ((err
= b44_writephy(bp
, B44_MII_TLEDCTRL
,
451 val
| MII_TLEDCTRL_ENABLE
)) != 0)
454 if (!(bp
->flags
& B44_FLAG_FORCE_LINK
)) {
455 u32 adv
= ADVERTISE_CSMA
;
457 if (bp
->flags
& B44_FLAG_ADV_10HALF
)
458 adv
|= ADVERTISE_10HALF
;
459 if (bp
->flags
& B44_FLAG_ADV_10FULL
)
460 adv
|= ADVERTISE_10FULL
;
461 if (bp
->flags
& B44_FLAG_ADV_100HALF
)
462 adv
|= ADVERTISE_100HALF
;
463 if (bp
->flags
& B44_FLAG_ADV_100FULL
)
464 adv
|= ADVERTISE_100FULL
;
466 if (bp
->flags
& B44_FLAG_PAUSE_AUTO
)
467 adv
|= ADVERTISE_PAUSE_CAP
| ADVERTISE_PAUSE_ASYM
;
469 if ((err
= b44_writephy(bp
, MII_ADVERTISE
, adv
)) != 0)
471 if ((err
= b44_writephy(bp
, MII_BMCR
, (BMCR_ANENABLE
|
472 BMCR_ANRESTART
))) != 0)
477 if ((err
= b44_readphy(bp
, MII_BMCR
, &bmcr
)) != 0)
479 bmcr
&= ~(BMCR_FULLDPLX
| BMCR_ANENABLE
| BMCR_SPEED100
);
480 if (bp
->flags
& B44_FLAG_100_BASE_T
)
481 bmcr
|= BMCR_SPEED100
;
482 if (bp
->flags
& B44_FLAG_FULL_DUPLEX
)
483 bmcr
|= BMCR_FULLDPLX
;
484 if ((err
= b44_writephy(bp
, MII_BMCR
, bmcr
)) != 0)
487 /* Since we will not be negotiating there is no safe way
488 * to determine if the link partner supports flow control
489 * or not. So just disable it completely in this case.
491 b44_set_flow_ctrl(bp
, 0, 0);
498 static void b44_stats_update(struct b44
*bp
)
503 val
= &bp
->hw_stats
.tx_good_octets
;
504 for (reg
= B44_TX_GOOD_O
; reg
<= B44_TX_PAUSE
; reg
+= 4UL) {
505 *val
++ += br32(bp
, reg
);
511 for (reg
= B44_RX_GOOD_O
; reg
<= B44_RX_NPAUSE
; reg
+= 4UL) {
512 *val
++ += br32(bp
, reg
);
516 static void b44_link_report(struct b44
*bp
)
518 if (!netif_carrier_ok(bp
->dev
)) {
519 printk(KERN_INFO PFX
"%s: Link is down.\n", bp
->dev
->name
);
521 printk(KERN_INFO PFX
"%s: Link is up at %d Mbps, %s duplex.\n",
523 (bp
->flags
& B44_FLAG_100_BASE_T
) ? 100 : 10,
524 (bp
->flags
& B44_FLAG_FULL_DUPLEX
) ? "full" : "half");
526 printk(KERN_INFO PFX
"%s: Flow control is %s for TX and "
529 (bp
->flags
& B44_FLAG_TX_PAUSE
) ? "on" : "off",
530 (bp
->flags
& B44_FLAG_RX_PAUSE
) ? "on" : "off");
534 static void b44_check_phy(struct b44
*bp
)
538 if (!b44_readphy(bp
, MII_BMSR
, &bmsr
) &&
539 !b44_readphy(bp
, B44_MII_AUXCTRL
, &aux
) &&
541 if (aux
& MII_AUXCTRL_SPEED
)
542 bp
->flags
|= B44_FLAG_100_BASE_T
;
544 bp
->flags
&= ~B44_FLAG_100_BASE_T
;
545 if (aux
& MII_AUXCTRL_DUPLEX
)
546 bp
->flags
|= B44_FLAG_FULL_DUPLEX
;
548 bp
->flags
&= ~B44_FLAG_FULL_DUPLEX
;
550 if (!netif_carrier_ok(bp
->dev
) &&
551 (bmsr
& BMSR_LSTATUS
)) {
552 u32 val
= br32(bp
, B44_TX_CTRL
);
553 u32 local_adv
, remote_adv
;
555 if (bp
->flags
& B44_FLAG_FULL_DUPLEX
)
556 val
|= TX_CTRL_DUPLEX
;
558 val
&= ~TX_CTRL_DUPLEX
;
559 bw32(bp
, B44_TX_CTRL
, val
);
561 if (!(bp
->flags
& B44_FLAG_FORCE_LINK
) &&
562 !b44_readphy(bp
, MII_ADVERTISE
, &local_adv
) &&
563 !b44_readphy(bp
, MII_LPA
, &remote_adv
))
564 b44_set_flow_ctrl(bp
, local_adv
, remote_adv
);
567 netif_carrier_on(bp
->dev
);
569 } else if (netif_carrier_ok(bp
->dev
) && !(bmsr
& BMSR_LSTATUS
)) {
571 netif_carrier_off(bp
->dev
);
575 if (bmsr
& BMSR_RFAULT
)
576 printk(KERN_WARNING PFX
"%s: Remote fault detected in PHY\n",
579 printk(KERN_WARNING PFX
"%s: Jabber detected in PHY\n",
584 static void b44_timer(unsigned long __opaque
)
586 struct b44
*bp
= (struct b44
*) __opaque
;
588 spin_lock_irq(&bp
->lock
);
592 b44_stats_update(bp
);
594 spin_unlock_irq(&bp
->lock
);
596 bp
->timer
.expires
= jiffies
+ HZ
;
597 add_timer(&bp
->timer
);
600 static void b44_tx(struct b44
*bp
)
604 cur
= br32(bp
, B44_DMATX_STAT
) & DMATX_STAT_CDMASK
;
605 cur
/= sizeof(struct dma_desc
);
607 /* XXX needs updating when NETIF_F_SG is supported */
608 for (cons
= bp
->tx_cons
; cons
!= cur
; cons
= NEXT_TX(cons
)) {
609 struct ring_info
*rp
= &bp
->tx_buffers
[cons
];
610 struct sk_buff
*skb
= rp
->skb
;
612 if (unlikely(skb
== NULL
))
615 pci_unmap_single(bp
->pdev
,
616 pci_unmap_addr(rp
, mapping
),
620 dev_kfree_skb_irq(skb
);
624 if (netif_queue_stopped(bp
->dev
) &&
625 TX_BUFFS_AVAIL(bp
) > B44_TX_WAKEUP_THRESH
)
626 netif_wake_queue(bp
->dev
);
628 bw32(bp
, B44_GPTIMER
, 0);
631 /* Works like this. This chip writes a 'struct rx_header" 30 bytes
632 * before the DMA address you give it. So we allocate 30 more bytes
633 * for the RX buffer, DMA map all of it, skb_reserve the 30 bytes, then
634 * point the chip at 30 bytes past where the rx_header will go.
636 static int b44_alloc_rx_skb(struct b44
*bp
, int src_idx
, u32 dest_idx_unmasked
)
639 struct ring_info
*src_map
, *map
;
640 struct rx_header
*rh
;
648 src_map
= &bp
->rx_buffers
[src_idx
];
649 dest_idx
= dest_idx_unmasked
& (B44_RX_RING_SIZE
- 1);
650 map
= &bp
->rx_buffers
[dest_idx
];
651 skb
= dev_alloc_skb(RX_PKT_BUF_SZ
);
655 mapping
= pci_map_single(bp
->pdev
, skb
->data
,
659 /* Hardware bug work-around, the chip is unable to do PCI DMA
660 to/from anything above 1GB :-( */
661 if (mapping
+ RX_PKT_BUF_SZ
> B44_DMA_MASK
) {
663 pci_unmap_single(bp
->pdev
, mapping
, RX_PKT_BUF_SZ
,PCI_DMA_FROMDEVICE
);
664 dev_kfree_skb_any(skb
);
665 skb
= __dev_alloc_skb(RX_PKT_BUF_SZ
,GFP_DMA
);
668 mapping
= pci_map_single(bp
->pdev
, skb
->data
,
671 if (mapping
+ RX_PKT_BUF_SZ
> B44_DMA_MASK
) {
672 pci_unmap_single(bp
->pdev
, mapping
, RX_PKT_BUF_SZ
,PCI_DMA_FROMDEVICE
);
673 dev_kfree_skb_any(skb
);
679 skb_reserve(skb
, bp
->rx_offset
);
681 rh
= (struct rx_header
*)
682 (skb
->data
- bp
->rx_offset
);
687 pci_unmap_addr_set(map
, mapping
, mapping
);
692 ctrl
= (DESC_CTRL_LEN
& (RX_PKT_BUF_SZ
- bp
->rx_offset
));
693 if (dest_idx
== (B44_RX_RING_SIZE
- 1))
694 ctrl
|= DESC_CTRL_EOT
;
696 dp
= &bp
->rx_ring
[dest_idx
];
697 dp
->ctrl
= cpu_to_le32(ctrl
);
698 dp
->addr
= cpu_to_le32((u32
) mapping
+ bp
->rx_offset
+ bp
->dma_offset
);
700 if (bp
->flags
& B44_FLAG_RX_RING_HACK
)
701 b44_sync_dma_desc_for_device(bp
->pdev
, bp
->rx_ring_dma
,
702 dest_idx
* sizeof(dp
),
705 return RX_PKT_BUF_SZ
;
708 static void b44_recycle_rx(struct b44
*bp
, int src_idx
, u32 dest_idx_unmasked
)
710 struct dma_desc
*src_desc
, *dest_desc
;
711 struct ring_info
*src_map
, *dest_map
;
712 struct rx_header
*rh
;
716 dest_idx
= dest_idx_unmasked
& (B44_RX_RING_SIZE
- 1);
717 dest_desc
= &bp
->rx_ring
[dest_idx
];
718 dest_map
= &bp
->rx_buffers
[dest_idx
];
719 src_desc
= &bp
->rx_ring
[src_idx
];
720 src_map
= &bp
->rx_buffers
[src_idx
];
722 dest_map
->skb
= src_map
->skb
;
723 rh
= (struct rx_header
*) src_map
->skb
->data
;
726 pci_unmap_addr_set(dest_map
, mapping
,
727 pci_unmap_addr(src_map
, mapping
));
729 if (bp
->flags
& B44_FLAG_RX_RING_HACK
)
730 b44_sync_dma_desc_for_cpu(bp
->pdev
, bp
->rx_ring_dma
,
731 src_idx
* sizeof(src_desc
),
734 ctrl
= src_desc
->ctrl
;
735 if (dest_idx
== (B44_RX_RING_SIZE
- 1))
736 ctrl
|= cpu_to_le32(DESC_CTRL_EOT
);
738 ctrl
&= cpu_to_le32(~DESC_CTRL_EOT
);
740 dest_desc
->ctrl
= ctrl
;
741 dest_desc
->addr
= src_desc
->addr
;
745 if (bp
->flags
& B44_FLAG_RX_RING_HACK
)
746 b44_sync_dma_desc_for_device(bp
->pdev
, bp
->rx_ring_dma
,
747 dest_idx
* sizeof(dest_desc
),
750 pci_dma_sync_single_for_device(bp
->pdev
, src_desc
->addr
,
755 static int b44_rx(struct b44
*bp
, int budget
)
761 prod
= br32(bp
, B44_DMARX_STAT
) & DMARX_STAT_CDMASK
;
762 prod
/= sizeof(struct dma_desc
);
765 while (cons
!= prod
&& budget
> 0) {
766 struct ring_info
*rp
= &bp
->rx_buffers
[cons
];
767 struct sk_buff
*skb
= rp
->skb
;
768 dma_addr_t map
= pci_unmap_addr(rp
, mapping
);
769 struct rx_header
*rh
;
772 pci_dma_sync_single_for_cpu(bp
->pdev
, map
,
775 rh
= (struct rx_header
*) skb
->data
;
776 len
= cpu_to_le16(rh
->len
);
777 if ((len
> (RX_PKT_BUF_SZ
- bp
->rx_offset
)) ||
778 (rh
->flags
& cpu_to_le16(RX_FLAG_ERRORS
))) {
780 b44_recycle_rx(bp
, cons
, bp
->rx_prod
);
782 bp
->stats
.rx_dropped
++;
792 len
= cpu_to_le16(rh
->len
);
793 } while (len
== 0 && i
++ < 5);
801 if (len
> RX_COPY_THRESHOLD
) {
803 skb_size
= b44_alloc_rx_skb(bp
, cons
, bp
->rx_prod
);
806 pci_unmap_single(bp
->pdev
, map
,
807 skb_size
, PCI_DMA_FROMDEVICE
);
808 /* Leave out rx_header */
809 skb_put(skb
, len
+bp
->rx_offset
);
810 skb_pull(skb
,bp
->rx_offset
);
812 struct sk_buff
*copy_skb
;
814 b44_recycle_rx(bp
, cons
, bp
->rx_prod
);
815 copy_skb
= dev_alloc_skb(len
+ 2);
816 if (copy_skb
== NULL
)
817 goto drop_it_no_recycle
;
819 copy_skb
->dev
= bp
->dev
;
820 skb_reserve(copy_skb
, 2);
821 skb_put(copy_skb
, len
);
822 /* DMA sync done above, copy just the actual packet */
823 memcpy(copy_skb
->data
, skb
->data
+bp
->rx_offset
, len
);
827 skb
->ip_summed
= CHECKSUM_NONE
;
828 skb
->protocol
= eth_type_trans(skb
, bp
->dev
);
829 netif_receive_skb(skb
);
830 bp
->dev
->last_rx
= jiffies
;
834 bp
->rx_prod
= (bp
->rx_prod
+ 1) &
835 (B44_RX_RING_SIZE
- 1);
836 cons
= (cons
+ 1) & (B44_RX_RING_SIZE
- 1);
840 bw32(bp
, B44_DMARX_PTR
, cons
* sizeof(struct dma_desc
));
845 static int b44_poll(struct net_device
*netdev
, int *budget
)
847 struct b44
*bp
= netdev_priv(netdev
);
850 spin_lock_irq(&bp
->lock
);
852 if (bp
->istat
& (ISTAT_TX
| ISTAT_TO
)) {
853 /* spin_lock(&bp->tx_lock); */
855 /* spin_unlock(&bp->tx_lock); */
857 spin_unlock_irq(&bp
->lock
);
860 if (bp
->istat
& ISTAT_RX
) {
861 int orig_budget
= *budget
;
864 if (orig_budget
> netdev
->quota
)
865 orig_budget
= netdev
->quota
;
867 work_done
= b44_rx(bp
, orig_budget
);
869 *budget
-= work_done
;
870 netdev
->quota
-= work_done
;
872 if (work_done
>= orig_budget
)
876 if (bp
->istat
& ISTAT_ERRORS
) {
877 spin_lock_irq(&bp
->lock
);
881 netif_wake_queue(bp
->dev
);
882 spin_unlock_irq(&bp
->lock
);
887 netif_rx_complete(netdev
);
891 return (done
? 0 : 1);
894 static irqreturn_t
b44_interrupt(int irq
, void *dev_id
, struct pt_regs
*regs
)
896 struct net_device
*dev
= dev_id
;
897 struct b44
*bp
= netdev_priv(dev
);
902 spin_lock_irqsave(&bp
->lock
, flags
);
904 istat
= br32(bp
, B44_ISTAT
);
905 imask
= br32(bp
, B44_IMASK
);
907 /* ??? What the fuck is the purpose of the interrupt mask
908 * ??? register if we have to mask it out by hand anyways?
913 if (netif_rx_schedule_prep(dev
)) {
914 /* NOTE: These writes are posted by the readback of
915 * the ISTAT register below.
918 __b44_disable_ints(bp
);
919 __netif_rx_schedule(dev
);
921 printk(KERN_ERR PFX
"%s: Error, poll already scheduled\n",
925 bw32(bp
, B44_ISTAT
, istat
);
928 spin_unlock_irqrestore(&bp
->lock
, flags
);
929 return IRQ_RETVAL(handled
);
932 static void b44_tx_timeout(struct net_device
*dev
)
934 struct b44
*bp
= netdev_priv(dev
);
936 printk(KERN_ERR PFX
"%s: transmit timed out, resetting\n",
939 spin_lock_irq(&bp
->lock
);
945 spin_unlock_irq(&bp
->lock
);
949 netif_wake_queue(dev
);
952 static int b44_start_xmit(struct sk_buff
*skb
, struct net_device
*dev
)
954 struct b44
*bp
= netdev_priv(dev
);
955 struct sk_buff
*bounce_skb
;
956 int rc
= NETDEV_TX_OK
;
958 u32 len
, entry
, ctrl
;
961 spin_lock_irq(&bp
->lock
);
963 /* This is a hard error, log it. */
964 if (unlikely(TX_BUFFS_AVAIL(bp
) < 1)) {
965 netif_stop_queue(dev
);
966 printk(KERN_ERR PFX
"%s: BUG! Tx Ring full when queue awake!\n",
971 mapping
= pci_map_single(bp
->pdev
, skb
->data
, len
, PCI_DMA_TODEVICE
);
972 if (mapping
+ len
> B44_DMA_MASK
) {
973 /* Chip can't handle DMA to/from >1GB, use bounce buffer */
974 pci_unmap_single(bp
->pdev
, mapping
, len
, PCI_DMA_TODEVICE
);
976 bounce_skb
= __dev_alloc_skb(TX_PKT_BUF_SZ
,
981 mapping
= pci_map_single(bp
->pdev
, bounce_skb
->data
,
982 len
, PCI_DMA_TODEVICE
);
983 if (mapping
+ len
> B44_DMA_MASK
) {
984 pci_unmap_single(bp
->pdev
, mapping
,
985 len
, PCI_DMA_TODEVICE
);
986 dev_kfree_skb_any(bounce_skb
);
990 memcpy(skb_put(bounce_skb
, len
), skb
->data
, skb
->len
);
991 dev_kfree_skb_any(skb
);
996 bp
->tx_buffers
[entry
].skb
= skb
;
997 pci_unmap_addr_set(&bp
->tx_buffers
[entry
], mapping
, mapping
);
999 ctrl
= (len
& DESC_CTRL_LEN
);
1000 ctrl
|= DESC_CTRL_IOC
| DESC_CTRL_SOF
| DESC_CTRL_EOF
;
1001 if (entry
== (B44_TX_RING_SIZE
- 1))
1002 ctrl
|= DESC_CTRL_EOT
;
1004 bp
->tx_ring
[entry
].ctrl
= cpu_to_le32(ctrl
);
1005 bp
->tx_ring
[entry
].addr
= cpu_to_le32((u32
) mapping
+bp
->dma_offset
);
1007 if (bp
->flags
& B44_FLAG_TX_RING_HACK
)
1008 b44_sync_dma_desc_for_device(bp
->pdev
, bp
->tx_ring_dma
,
1009 entry
* sizeof(bp
->tx_ring
[0]),
1012 entry
= NEXT_TX(entry
);
1014 bp
->tx_prod
= entry
;
1018 bw32(bp
, B44_DMATX_PTR
, entry
* sizeof(struct dma_desc
));
1019 if (bp
->flags
& B44_FLAG_BUGGY_TXPTR
)
1020 bw32(bp
, B44_DMATX_PTR
, entry
* sizeof(struct dma_desc
));
1021 if (bp
->flags
& B44_FLAG_REORDER_BUG
)
1022 br32(bp
, B44_DMATX_PTR
);
1024 if (TX_BUFFS_AVAIL(bp
) < 1)
1025 netif_stop_queue(dev
);
1027 dev
->trans_start
= jiffies
;
1030 spin_unlock_irq(&bp
->lock
);
1035 rc
= NETDEV_TX_BUSY
;
1039 static int b44_change_mtu(struct net_device
*dev
, int new_mtu
)
1041 struct b44
*bp
= netdev_priv(dev
);
1043 if (new_mtu
< B44_MIN_MTU
|| new_mtu
> B44_MAX_MTU
)
1046 if (!netif_running(dev
)) {
1047 /* We'll just catch it later when the
1054 spin_lock_irq(&bp
->lock
);
1059 spin_unlock_irq(&bp
->lock
);
1061 b44_enable_ints(bp
);
1066 /* Free up pending packets in all rx/tx rings.
1068 * The chip has been shut down and the driver detached from
1069 * the networking, so no interrupts or new tx packets will
1070 * end up in the driver. bp->lock is not held and we are not
1071 * in an interrupt context and thus may sleep.
1073 static void b44_free_rings(struct b44
*bp
)
1075 struct ring_info
*rp
;
1078 for (i
= 0; i
< B44_RX_RING_SIZE
; i
++) {
1079 rp
= &bp
->rx_buffers
[i
];
1081 if (rp
->skb
== NULL
)
1083 pci_unmap_single(bp
->pdev
,
1084 pci_unmap_addr(rp
, mapping
),
1086 PCI_DMA_FROMDEVICE
);
1087 dev_kfree_skb_any(rp
->skb
);
1091 /* XXX needs changes once NETIF_F_SG is set... */
1092 for (i
= 0; i
< B44_TX_RING_SIZE
; i
++) {
1093 rp
= &bp
->tx_buffers
[i
];
1095 if (rp
->skb
== NULL
)
1097 pci_unmap_single(bp
->pdev
,
1098 pci_unmap_addr(rp
, mapping
),
1101 dev_kfree_skb_any(rp
->skb
);
1106 /* Initialize tx/rx rings for packet processing.
1108 * The chip has been shut down and the driver detached from
1109 * the networking, so no interrupts or new tx packets will
1110 * end up in the driver.
1112 static void b44_init_rings(struct b44
*bp
)
1118 memset(bp
->rx_ring
, 0, B44_RX_RING_BYTES
);
1119 memset(bp
->tx_ring
, 0, B44_TX_RING_BYTES
);
1121 if (bp
->flags
& B44_FLAG_RX_RING_HACK
)
1122 dma_sync_single_for_device(&bp
->pdev
->dev
, bp
->rx_ring_dma
,
1124 PCI_DMA_BIDIRECTIONAL
);
1126 if (bp
->flags
& B44_FLAG_TX_RING_HACK
)
1127 dma_sync_single_for_device(&bp
->pdev
->dev
, bp
->tx_ring_dma
,
1131 for (i
= 0; i
< bp
->rx_pending
; i
++) {
1132 if (b44_alloc_rx_skb(bp
, -1, i
) < 0)
1138 * Must not be invoked with interrupt sources disabled and
1139 * the hardware shutdown down.
1141 static void b44_free_consistent(struct b44
*bp
)
1143 kfree(bp
->rx_buffers
);
1144 bp
->rx_buffers
= NULL
;
1145 kfree(bp
->tx_buffers
);
1146 bp
->tx_buffers
= NULL
;
1148 if (bp
->flags
& B44_FLAG_RX_RING_HACK
) {
1149 dma_unmap_single(&bp
->pdev
->dev
, bp
->rx_ring_dma
,
1154 pci_free_consistent(bp
->pdev
, DMA_TABLE_BYTES
,
1155 bp
->rx_ring
, bp
->rx_ring_dma
);
1157 bp
->flags
&= ~B44_FLAG_RX_RING_HACK
;
1160 if (bp
->flags
& B44_FLAG_TX_RING_HACK
) {
1161 dma_unmap_single(&bp
->pdev
->dev
, bp
->tx_ring_dma
,
1166 pci_free_consistent(bp
->pdev
, DMA_TABLE_BYTES
,
1167 bp
->tx_ring
, bp
->tx_ring_dma
);
1169 bp
->flags
&= ~B44_FLAG_TX_RING_HACK
;
1174 * Must not be invoked with interrupt sources disabled and
1175 * the hardware shutdown down. Can sleep.
1177 static int b44_alloc_consistent(struct b44
*bp
)
1181 size
= B44_RX_RING_SIZE
* sizeof(struct ring_info
);
1182 bp
->rx_buffers
= kzalloc(size
, GFP_KERNEL
);
1183 if (!bp
->rx_buffers
)
1186 size
= B44_TX_RING_SIZE
* sizeof(struct ring_info
);
1187 bp
->tx_buffers
= kzalloc(size
, GFP_KERNEL
);
1188 if (!bp
->tx_buffers
)
1191 size
= DMA_TABLE_BYTES
;
1192 bp
->rx_ring
= pci_alloc_consistent(bp
->pdev
, size
, &bp
->rx_ring_dma
);
1194 /* Allocation may have failed due to pci_alloc_consistent
1195 insisting on use of GFP_DMA, which is more restrictive
1196 than necessary... */
1197 struct dma_desc
*rx_ring
;
1198 dma_addr_t rx_ring_dma
;
1200 rx_ring
= kzalloc(size
, GFP_KERNEL
);
1204 rx_ring_dma
= dma_map_single(&bp
->pdev
->dev
, rx_ring
,
1208 if (rx_ring_dma
+ size
> B44_DMA_MASK
) {
1213 bp
->rx_ring
= rx_ring
;
1214 bp
->rx_ring_dma
= rx_ring_dma
;
1215 bp
->flags
|= B44_FLAG_RX_RING_HACK
;
1218 bp
->tx_ring
= pci_alloc_consistent(bp
->pdev
, size
, &bp
->tx_ring_dma
);
1220 /* Allocation may have failed due to pci_alloc_consistent
1221 insisting on use of GFP_DMA, which is more restrictive
1222 than necessary... */
1223 struct dma_desc
*tx_ring
;
1224 dma_addr_t tx_ring_dma
;
1226 tx_ring
= kzalloc(size
, GFP_KERNEL
);
1230 tx_ring_dma
= dma_map_single(&bp
->pdev
->dev
, tx_ring
,
1234 if (tx_ring_dma
+ size
> B44_DMA_MASK
) {
1239 bp
->tx_ring
= tx_ring
;
1240 bp
->tx_ring_dma
= tx_ring_dma
;
1241 bp
->flags
|= B44_FLAG_TX_RING_HACK
;
1247 b44_free_consistent(bp
);
1251 /* bp->lock is held. */
1252 static void b44_clear_stats(struct b44
*bp
)
1256 bw32(bp
, B44_MIB_CTRL
, MIB_CTRL_CLR_ON_READ
);
1257 for (reg
= B44_TX_GOOD_O
; reg
<= B44_TX_PAUSE
; reg
+= 4UL)
1259 for (reg
= B44_RX_GOOD_O
; reg
<= B44_RX_NPAUSE
; reg
+= 4UL)
1263 /* bp->lock is held. */
1264 static void b44_chip_reset(struct b44
*bp
)
1266 if (ssb_is_core_up(bp
)) {
1267 bw32(bp
, B44_RCV_LAZY
, 0);
1268 bw32(bp
, B44_ENET_CTRL
, ENET_CTRL_DISABLE
);
1269 b44_wait_bit(bp
, B44_ENET_CTRL
, ENET_CTRL_DISABLE
, 100, 1);
1270 bw32(bp
, B44_DMATX_CTRL
, 0);
1271 bp
->tx_prod
= bp
->tx_cons
= 0;
1272 if (br32(bp
, B44_DMARX_STAT
) & DMARX_STAT_EMASK
) {
1273 b44_wait_bit(bp
, B44_DMARX_STAT
, DMARX_STAT_SIDLE
,
1276 bw32(bp
, B44_DMARX_CTRL
, 0);
1277 bp
->rx_prod
= bp
->rx_cons
= 0;
1279 ssb_pci_setup(bp
, (bp
->core_unit
== 0 ?
1286 b44_clear_stats(bp
);
1288 /* Make PHY accessible. */
1289 bw32(bp
, B44_MDIO_CTRL
, (MDIO_CTRL_PREAMBLE
|
1290 (0x0d & MDIO_CTRL_MAXF_MASK
)));
1291 br32(bp
, B44_MDIO_CTRL
);
1293 if (!(br32(bp
, B44_DEVCTRL
) & DEVCTRL_IPP
)) {
1294 bw32(bp
, B44_ENET_CTRL
, ENET_CTRL_EPSEL
);
1295 br32(bp
, B44_ENET_CTRL
);
1296 bp
->flags
&= ~B44_FLAG_INTERNAL_PHY
;
1298 u32 val
= br32(bp
, B44_DEVCTRL
);
1300 if (val
& DEVCTRL_EPR
) {
1301 bw32(bp
, B44_DEVCTRL
, (val
& ~DEVCTRL_EPR
));
1302 br32(bp
, B44_DEVCTRL
);
1305 bp
->flags
|= B44_FLAG_INTERNAL_PHY
;
1309 /* bp->lock is held. */
1310 static void b44_halt(struct b44
*bp
)
1312 b44_disable_ints(bp
);
1316 /* bp->lock is held. */
1317 static void __b44_set_mac_addr(struct b44
*bp
)
1319 bw32(bp
, B44_CAM_CTRL
, 0);
1320 if (!(bp
->dev
->flags
& IFF_PROMISC
)) {
1323 __b44_cam_write(bp
, bp
->dev
->dev_addr
, 0);
1324 val
= br32(bp
, B44_CAM_CTRL
);
1325 bw32(bp
, B44_CAM_CTRL
, val
| CAM_CTRL_ENABLE
);
1329 static int b44_set_mac_addr(struct net_device
*dev
, void *p
)
1331 struct b44
*bp
= netdev_priv(dev
);
1332 struct sockaddr
*addr
= p
;
1334 if (netif_running(dev
))
1337 memcpy(dev
->dev_addr
, addr
->sa_data
, dev
->addr_len
);
1339 spin_lock_irq(&bp
->lock
);
1340 __b44_set_mac_addr(bp
);
1341 spin_unlock_irq(&bp
->lock
);
1346 /* Called at device open time to get the chip ready for
1347 * packet processing. Invoked with bp->lock held.
1349 static void __b44_set_rx_mode(struct net_device
*);
1350 static void b44_init_hw(struct b44
*bp
)
1358 /* Enable CRC32, set proper LED modes and power on PHY */
1359 bw32(bp
, B44_MAC_CTRL
, MAC_CTRL_CRC32_ENAB
| MAC_CTRL_PHY_LEDCTRL
);
1360 bw32(bp
, B44_RCV_LAZY
, (1 << RCV_LAZY_FC_SHIFT
));
1362 /* This sets the MAC address too. */
1363 __b44_set_rx_mode(bp
->dev
);
1365 /* MTU + eth header + possible VLAN tag + struct rx_header */
1366 bw32(bp
, B44_RXMAXLEN
, bp
->dev
->mtu
+ ETH_HLEN
+ 8 + RX_HEADER_LEN
);
1367 bw32(bp
, B44_TXMAXLEN
, bp
->dev
->mtu
+ ETH_HLEN
+ 8 + RX_HEADER_LEN
);
1369 bw32(bp
, B44_TX_WMARK
, 56); /* XXX magic */
1370 bw32(bp
, B44_DMATX_CTRL
, DMATX_CTRL_ENABLE
);
1371 bw32(bp
, B44_DMATX_ADDR
, bp
->tx_ring_dma
+ bp
->dma_offset
);
1372 bw32(bp
, B44_DMARX_CTRL
, (DMARX_CTRL_ENABLE
|
1373 (bp
->rx_offset
<< DMARX_CTRL_ROSHIFT
)));
1374 bw32(bp
, B44_DMARX_ADDR
, bp
->rx_ring_dma
+ bp
->dma_offset
);
1376 bw32(bp
, B44_DMARX_PTR
, bp
->rx_pending
);
1377 bp
->rx_prod
= bp
->rx_pending
;
1379 bw32(bp
, B44_MIB_CTRL
, MIB_CTRL_CLR_ON_READ
);
1381 val
= br32(bp
, B44_ENET_CTRL
);
1382 bw32(bp
, B44_ENET_CTRL
, (val
| ENET_CTRL_ENABLE
));
1385 static int b44_open(struct net_device
*dev
)
1387 struct b44
*bp
= netdev_priv(dev
);
1390 err
= b44_alloc_consistent(bp
);
1394 err
= request_irq(dev
->irq
, b44_interrupt
, SA_SHIRQ
, dev
->name
, dev
);
1398 spin_lock_irq(&bp
->lock
);
1402 bp
->flags
|= B44_FLAG_INIT_COMPLETE
;
1404 netif_carrier_off(dev
);
1407 spin_unlock_irq(&bp
->lock
);
1409 init_timer(&bp
->timer
);
1410 bp
->timer
.expires
= jiffies
+ HZ
;
1411 bp
->timer
.data
= (unsigned long) bp
;
1412 bp
->timer
.function
= b44_timer
;
1413 add_timer(&bp
->timer
);
1415 b44_enable_ints(bp
);
1420 b44_free_consistent(bp
);
1425 /*static*/ void b44_dump_state(struct b44
*bp
)
1427 u32 val32
, val32_2
, val32_3
, val32_4
, val32_5
;
1430 pci_read_config_word(bp
->pdev
, PCI_STATUS
, &val16
);
1431 printk("DEBUG: PCI status [%04x] \n", val16
);
1436 #ifdef CONFIG_NET_POLL_CONTROLLER
1438 * Polling receive - used by netconsole and other diagnostic tools
1439 * to allow network i/o with interrupts disabled.
1441 static void b44_poll_controller(struct net_device
*dev
)
1443 disable_irq(dev
->irq
);
1444 b44_interrupt(dev
->irq
, dev
, NULL
);
1445 enable_irq(dev
->irq
);
1449 static int b44_close(struct net_device
*dev
)
1451 struct b44
*bp
= netdev_priv(dev
);
1453 netif_stop_queue(dev
);
1455 del_timer_sync(&bp
->timer
);
1457 spin_lock_irq(&bp
->lock
);
1464 bp
->flags
&= ~B44_FLAG_INIT_COMPLETE
;
1465 netif_carrier_off(bp
->dev
);
1467 spin_unlock_irq(&bp
->lock
);
1469 free_irq(dev
->irq
, dev
);
1471 b44_free_consistent(bp
);
1476 static struct net_device_stats
*b44_get_stats(struct net_device
*dev
)
1478 struct b44
*bp
= netdev_priv(dev
);
1479 struct net_device_stats
*nstat
= &bp
->stats
;
1480 struct b44_hw_stats
*hwstat
= &bp
->hw_stats
;
1482 /* Convert HW stats into netdevice stats. */
1483 nstat
->rx_packets
= hwstat
->rx_pkts
;
1484 nstat
->tx_packets
= hwstat
->tx_pkts
;
1485 nstat
->rx_bytes
= hwstat
->rx_octets
;
1486 nstat
->tx_bytes
= hwstat
->tx_octets
;
1487 nstat
->tx_errors
= (hwstat
->tx_jabber_pkts
+
1488 hwstat
->tx_oversize_pkts
+
1489 hwstat
->tx_underruns
+
1490 hwstat
->tx_excessive_cols
+
1491 hwstat
->tx_late_cols
);
1492 nstat
->multicast
= hwstat
->tx_multicast_pkts
;
1493 nstat
->collisions
= hwstat
->tx_total_cols
;
1495 nstat
->rx_length_errors
= (hwstat
->rx_oversize_pkts
+
1496 hwstat
->rx_undersize
);
1497 nstat
->rx_over_errors
= hwstat
->rx_missed_pkts
;
1498 nstat
->rx_frame_errors
= hwstat
->rx_align_errs
;
1499 nstat
->rx_crc_errors
= hwstat
->rx_crc_errs
;
1500 nstat
->rx_errors
= (hwstat
->rx_jabber_pkts
+
1501 hwstat
->rx_oversize_pkts
+
1502 hwstat
->rx_missed_pkts
+
1503 hwstat
->rx_crc_align_errs
+
1504 hwstat
->rx_undersize
+
1505 hwstat
->rx_crc_errs
+
1506 hwstat
->rx_align_errs
+
1507 hwstat
->rx_symbol_errs
);
1509 nstat
->tx_aborted_errors
= hwstat
->tx_underruns
;
1511 /* Carrier lost counter seems to be broken for some devices */
1512 nstat
->tx_carrier_errors
= hwstat
->tx_carrier_lost
;
1518 static int __b44_load_mcast(struct b44
*bp
, struct net_device
*dev
)
1520 struct dev_mc_list
*mclist
;
1523 num_ents
= min_t(int, dev
->mc_count
, B44_MCAST_TABLE_SIZE
);
1524 mclist
= dev
->mc_list
;
1525 for (i
= 0; mclist
&& i
< num_ents
; i
++, mclist
= mclist
->next
) {
1526 __b44_cam_write(bp
, mclist
->dmi_addr
, i
+ 1);
1531 static void __b44_set_rx_mode(struct net_device
*dev
)
1533 struct b44
*bp
= netdev_priv(dev
);
1536 val
= br32(bp
, B44_RXCONFIG
);
1537 val
&= ~(RXCONFIG_PROMISC
| RXCONFIG_ALLMULTI
);
1538 if (dev
->flags
& IFF_PROMISC
) {
1539 val
|= RXCONFIG_PROMISC
;
1540 bw32(bp
, B44_RXCONFIG
, val
);
1542 unsigned char zero
[6] = {0, 0, 0, 0, 0, 0};
1545 __b44_set_mac_addr(bp
);
1547 if (dev
->flags
& IFF_ALLMULTI
)
1548 val
|= RXCONFIG_ALLMULTI
;
1550 i
= __b44_load_mcast(bp
, dev
);
1552 for (; i
< 64; i
++) {
1553 __b44_cam_write(bp
, zero
, i
);
1555 bw32(bp
, B44_RXCONFIG
, val
);
1556 val
= br32(bp
, B44_CAM_CTRL
);
1557 bw32(bp
, B44_CAM_CTRL
, val
| CAM_CTRL_ENABLE
);
1561 static void b44_set_rx_mode(struct net_device
*dev
)
1563 struct b44
*bp
= netdev_priv(dev
);
1565 spin_lock_irq(&bp
->lock
);
1566 __b44_set_rx_mode(dev
);
1567 spin_unlock_irq(&bp
->lock
);
1570 static u32
b44_get_msglevel(struct net_device
*dev
)
1572 struct b44
*bp
= netdev_priv(dev
);
1573 return bp
->msg_enable
;
1576 static void b44_set_msglevel(struct net_device
*dev
, u32 value
)
1578 struct b44
*bp
= netdev_priv(dev
);
1579 bp
->msg_enable
= value
;
1582 static void b44_get_drvinfo (struct net_device
*dev
, struct ethtool_drvinfo
*info
)
1584 struct b44
*bp
= netdev_priv(dev
);
1585 struct pci_dev
*pci_dev
= bp
->pdev
;
1587 strcpy (info
->driver
, DRV_MODULE_NAME
);
1588 strcpy (info
->version
, DRV_MODULE_VERSION
);
1589 strcpy (info
->bus_info
, pci_name(pci_dev
));
1592 static int b44_nway_reset(struct net_device
*dev
)
1594 struct b44
*bp
= netdev_priv(dev
);
1598 spin_lock_irq(&bp
->lock
);
1599 b44_readphy(bp
, MII_BMCR
, &bmcr
);
1600 b44_readphy(bp
, MII_BMCR
, &bmcr
);
1602 if (bmcr
& BMCR_ANENABLE
) {
1603 b44_writephy(bp
, MII_BMCR
,
1604 bmcr
| BMCR_ANRESTART
);
1607 spin_unlock_irq(&bp
->lock
);
1612 static int b44_get_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1614 struct b44
*bp
= netdev_priv(dev
);
1616 if (!(bp
->flags
& B44_FLAG_INIT_COMPLETE
))
1618 cmd
->supported
= (SUPPORTED_Autoneg
);
1619 cmd
->supported
|= (SUPPORTED_100baseT_Half
|
1620 SUPPORTED_100baseT_Full
|
1621 SUPPORTED_10baseT_Half
|
1622 SUPPORTED_10baseT_Full
|
1625 cmd
->advertising
= 0;
1626 if (bp
->flags
& B44_FLAG_ADV_10HALF
)
1627 cmd
->advertising
|= ADVERTISED_10baseT_Half
;
1628 if (bp
->flags
& B44_FLAG_ADV_10FULL
)
1629 cmd
->advertising
|= ADVERTISED_10baseT_Full
;
1630 if (bp
->flags
& B44_FLAG_ADV_100HALF
)
1631 cmd
->advertising
|= ADVERTISED_100baseT_Half
;
1632 if (bp
->flags
& B44_FLAG_ADV_100FULL
)
1633 cmd
->advertising
|= ADVERTISED_100baseT_Full
;
1634 cmd
->advertising
|= ADVERTISED_Pause
| ADVERTISED_Asym_Pause
;
1635 cmd
->speed
= (bp
->flags
& B44_FLAG_100_BASE_T
) ?
1636 SPEED_100
: SPEED_10
;
1637 cmd
->duplex
= (bp
->flags
& B44_FLAG_FULL_DUPLEX
) ?
1638 DUPLEX_FULL
: DUPLEX_HALF
;
1640 cmd
->phy_address
= bp
->phy_addr
;
1641 cmd
->transceiver
= (bp
->flags
& B44_FLAG_INTERNAL_PHY
) ?
1642 XCVR_INTERNAL
: XCVR_EXTERNAL
;
1643 cmd
->autoneg
= (bp
->flags
& B44_FLAG_FORCE_LINK
) ?
1644 AUTONEG_DISABLE
: AUTONEG_ENABLE
;
1650 static int b44_set_settings(struct net_device
*dev
, struct ethtool_cmd
*cmd
)
1652 struct b44
*bp
= netdev_priv(dev
);
1654 if (!(bp
->flags
& B44_FLAG_INIT_COMPLETE
))
1657 /* We do not support gigabit. */
1658 if (cmd
->autoneg
== AUTONEG_ENABLE
) {
1659 if (cmd
->advertising
&
1660 (ADVERTISED_1000baseT_Half
|
1661 ADVERTISED_1000baseT_Full
))
1663 } else if ((cmd
->speed
!= SPEED_100
&&
1664 cmd
->speed
!= SPEED_10
) ||
1665 (cmd
->duplex
!= DUPLEX_HALF
&&
1666 cmd
->duplex
!= DUPLEX_FULL
)) {
1670 spin_lock_irq(&bp
->lock
);
1672 if (cmd
->autoneg
== AUTONEG_ENABLE
) {
1673 bp
->flags
&= ~B44_FLAG_FORCE_LINK
;
1674 bp
->flags
&= ~(B44_FLAG_ADV_10HALF
|
1675 B44_FLAG_ADV_10FULL
|
1676 B44_FLAG_ADV_100HALF
|
1677 B44_FLAG_ADV_100FULL
);
1678 if (cmd
->advertising
& ADVERTISE_10HALF
)
1679 bp
->flags
|= B44_FLAG_ADV_10HALF
;
1680 if (cmd
->advertising
& ADVERTISE_10FULL
)
1681 bp
->flags
|= B44_FLAG_ADV_10FULL
;
1682 if (cmd
->advertising
& ADVERTISE_100HALF
)
1683 bp
->flags
|= B44_FLAG_ADV_100HALF
;
1684 if (cmd
->advertising
& ADVERTISE_100FULL
)
1685 bp
->flags
|= B44_FLAG_ADV_100FULL
;
1687 bp
->flags
|= B44_FLAG_FORCE_LINK
;
1688 if (cmd
->speed
== SPEED_100
)
1689 bp
->flags
|= B44_FLAG_100_BASE_T
;
1690 if (cmd
->duplex
== DUPLEX_FULL
)
1691 bp
->flags
|= B44_FLAG_FULL_DUPLEX
;
1696 spin_unlock_irq(&bp
->lock
);
1701 static void b44_get_ringparam(struct net_device
*dev
,
1702 struct ethtool_ringparam
*ering
)
1704 struct b44
*bp
= netdev_priv(dev
);
1706 ering
->rx_max_pending
= B44_RX_RING_SIZE
- 1;
1707 ering
->rx_pending
= bp
->rx_pending
;
1709 /* XXX ethtool lacks a tx_max_pending, oops... */
1712 static int b44_set_ringparam(struct net_device
*dev
,
1713 struct ethtool_ringparam
*ering
)
1715 struct b44
*bp
= netdev_priv(dev
);
1717 if ((ering
->rx_pending
> B44_RX_RING_SIZE
- 1) ||
1718 (ering
->rx_mini_pending
!= 0) ||
1719 (ering
->rx_jumbo_pending
!= 0) ||
1720 (ering
->tx_pending
> B44_TX_RING_SIZE
- 1))
1723 spin_lock_irq(&bp
->lock
);
1725 bp
->rx_pending
= ering
->rx_pending
;
1726 bp
->tx_pending
= ering
->tx_pending
;
1731 netif_wake_queue(bp
->dev
);
1732 spin_unlock_irq(&bp
->lock
);
1734 b44_enable_ints(bp
);
1739 static void b44_get_pauseparam(struct net_device
*dev
,
1740 struct ethtool_pauseparam
*epause
)
1742 struct b44
*bp
= netdev_priv(dev
);
1745 (bp
->flags
& B44_FLAG_PAUSE_AUTO
) != 0;
1747 (bp
->flags
& B44_FLAG_RX_PAUSE
) != 0;
1749 (bp
->flags
& B44_FLAG_TX_PAUSE
) != 0;
1752 static int b44_set_pauseparam(struct net_device
*dev
,
1753 struct ethtool_pauseparam
*epause
)
1755 struct b44
*bp
= netdev_priv(dev
);
1757 spin_lock_irq(&bp
->lock
);
1758 if (epause
->autoneg
)
1759 bp
->flags
|= B44_FLAG_PAUSE_AUTO
;
1761 bp
->flags
&= ~B44_FLAG_PAUSE_AUTO
;
1762 if (epause
->rx_pause
)
1763 bp
->flags
|= B44_FLAG_RX_PAUSE
;
1765 bp
->flags
&= ~B44_FLAG_RX_PAUSE
;
1766 if (epause
->tx_pause
)
1767 bp
->flags
|= B44_FLAG_TX_PAUSE
;
1769 bp
->flags
&= ~B44_FLAG_TX_PAUSE
;
1770 if (bp
->flags
& B44_FLAG_PAUSE_AUTO
) {
1775 __b44_set_flow_ctrl(bp
, bp
->flags
);
1777 spin_unlock_irq(&bp
->lock
);
1779 b44_enable_ints(bp
);
1784 static void b44_get_strings(struct net_device
*dev
, u32 stringset
, u8
*data
)
1788 memcpy(data
, *b44_gstrings
, sizeof(b44_gstrings
));
1793 static int b44_get_stats_count(struct net_device
*dev
)
1795 return ARRAY_SIZE(b44_gstrings
);
1798 static void b44_get_ethtool_stats(struct net_device
*dev
,
1799 struct ethtool_stats
*stats
, u64
*data
)
1801 struct b44
*bp
= netdev_priv(dev
);
1802 u32
*val
= &bp
->hw_stats
.tx_good_octets
;
1805 spin_lock_irq(&bp
->lock
);
1807 b44_stats_update(bp
);
1809 for (i
= 0; i
< ARRAY_SIZE(b44_gstrings
); i
++)
1812 spin_unlock_irq(&bp
->lock
);
1815 static struct ethtool_ops b44_ethtool_ops
= {
1816 .get_drvinfo
= b44_get_drvinfo
,
1817 .get_settings
= b44_get_settings
,
1818 .set_settings
= b44_set_settings
,
1819 .nway_reset
= b44_nway_reset
,
1820 .get_link
= ethtool_op_get_link
,
1821 .get_ringparam
= b44_get_ringparam
,
1822 .set_ringparam
= b44_set_ringparam
,
1823 .get_pauseparam
= b44_get_pauseparam
,
1824 .set_pauseparam
= b44_set_pauseparam
,
1825 .get_msglevel
= b44_get_msglevel
,
1826 .set_msglevel
= b44_set_msglevel
,
1827 .get_strings
= b44_get_strings
,
1828 .get_stats_count
= b44_get_stats_count
,
1829 .get_ethtool_stats
= b44_get_ethtool_stats
,
1830 .get_perm_addr
= ethtool_op_get_perm_addr
,
1833 static int b44_ioctl(struct net_device
*dev
, struct ifreq
*ifr
, int cmd
)
1835 struct mii_ioctl_data
*data
= if_mii(ifr
);
1836 struct b44
*bp
= netdev_priv(dev
);
1839 spin_lock_irq(&bp
->lock
);
1840 err
= generic_mii_ioctl(&bp
->mii_if
, data
, cmd
, NULL
);
1841 spin_unlock_irq(&bp
->lock
);
1846 /* Read 128-bytes of EEPROM. */
1847 static int b44_read_eeprom(struct b44
*bp
, u8
*data
)
1850 u16
*ptr
= (u16
*) data
;
1852 for (i
= 0; i
< 128; i
+= 2)
1853 ptr
[i
/ 2] = readw(bp
->regs
+ 4096 + i
);
1858 static int __devinit
b44_get_invariants(struct b44
*bp
)
1863 err
= b44_read_eeprom(bp
, &eeprom
[0]);
1867 bp
->dev
->dev_addr
[0] = eeprom
[79];
1868 bp
->dev
->dev_addr
[1] = eeprom
[78];
1869 bp
->dev
->dev_addr
[2] = eeprom
[81];
1870 bp
->dev
->dev_addr
[3] = eeprom
[80];
1871 bp
->dev
->dev_addr
[4] = eeprom
[83];
1872 bp
->dev
->dev_addr
[5] = eeprom
[82];
1873 memcpy(bp
->dev
->perm_addr
, bp
->dev
->dev_addr
, bp
->dev
->addr_len
);
1875 bp
->phy_addr
= eeprom
[90] & 0x1f;
1877 /* With this, plus the rx_header prepended to the data by the
1878 * hardware, we'll land the ethernet header on a 2-byte boundary.
1882 bp
->imask
= IMASK_DEF
;
1884 bp
->core_unit
= ssb_core_unit(bp
);
1885 bp
->dma_offset
= SB_PCI_DMA
;
1887 /* XXX - really required?
1888 bp->flags |= B44_FLAG_BUGGY_TXPTR;
1894 static int __devinit
b44_init_one(struct pci_dev
*pdev
,
1895 const struct pci_device_id
*ent
)
1897 static int b44_version_printed
= 0;
1898 unsigned long b44reg_base
, b44reg_len
;
1899 struct net_device
*dev
;
1903 if (b44_version_printed
++ == 0)
1904 printk(KERN_INFO
"%s", version
);
1906 err
= pci_enable_device(pdev
);
1908 printk(KERN_ERR PFX
"Cannot enable PCI device, "
1913 if (!(pci_resource_flags(pdev
, 0) & IORESOURCE_MEM
)) {
1914 printk(KERN_ERR PFX
"Cannot find proper PCI device "
1915 "base address, aborting.\n");
1917 goto err_out_disable_pdev
;
1920 err
= pci_request_regions(pdev
, DRV_MODULE_NAME
);
1922 printk(KERN_ERR PFX
"Cannot obtain PCI resources, "
1924 goto err_out_disable_pdev
;
1927 pci_set_master(pdev
);
1929 err
= pci_set_dma_mask(pdev
, (u64
) B44_DMA_MASK
);
1931 printk(KERN_ERR PFX
"No usable DMA configuration, "
1933 goto err_out_free_res
;
1936 err
= pci_set_consistent_dma_mask(pdev
, (u64
) B44_DMA_MASK
);
1938 printk(KERN_ERR PFX
"No usable DMA configuration, "
1940 goto err_out_free_res
;
1943 b44reg_base
= pci_resource_start(pdev
, 0);
1944 b44reg_len
= pci_resource_len(pdev
, 0);
1946 dev
= alloc_etherdev(sizeof(*bp
));
1948 printk(KERN_ERR PFX
"Etherdev alloc failed, aborting.\n");
1950 goto err_out_free_res
;
1953 SET_MODULE_OWNER(dev
);
1954 SET_NETDEV_DEV(dev
,&pdev
->dev
);
1956 /* No interesting netdevice features in this card... */
1959 bp
= netdev_priv(dev
);
1963 bp
->msg_enable
= netif_msg_init(b44_debug
, B44_DEF_MSG_ENABLE
);
1965 spin_lock_init(&bp
->lock
);
1967 bp
->regs
= ioremap(b44reg_base
, b44reg_len
);
1968 if (bp
->regs
== 0UL) {
1969 printk(KERN_ERR PFX
"Cannot map device registers, "
1972 goto err_out_free_dev
;
1975 bp
->rx_pending
= B44_DEF_RX_RING_PENDING
;
1976 bp
->tx_pending
= B44_DEF_TX_RING_PENDING
;
1978 dev
->open
= b44_open
;
1979 dev
->stop
= b44_close
;
1980 dev
->hard_start_xmit
= b44_start_xmit
;
1981 dev
->get_stats
= b44_get_stats
;
1982 dev
->set_multicast_list
= b44_set_rx_mode
;
1983 dev
->set_mac_address
= b44_set_mac_addr
;
1984 dev
->do_ioctl
= b44_ioctl
;
1985 dev
->tx_timeout
= b44_tx_timeout
;
1986 dev
->poll
= b44_poll
;
1988 dev
->watchdog_timeo
= B44_TX_TIMEOUT
;
1989 #ifdef CONFIG_NET_POLL_CONTROLLER
1990 dev
->poll_controller
= b44_poll_controller
;
1992 dev
->change_mtu
= b44_change_mtu
;
1993 dev
->irq
= pdev
->irq
;
1994 SET_ETHTOOL_OPS(dev
, &b44_ethtool_ops
);
1996 err
= b44_get_invariants(bp
);
1998 printk(KERN_ERR PFX
"Problem fetching invariants of chip, "
2000 goto err_out_iounmap
;
2003 bp
->mii_if
.dev
= dev
;
2004 bp
->mii_if
.mdio_read
= b44_mii_read
;
2005 bp
->mii_if
.mdio_write
= b44_mii_write
;
2006 bp
->mii_if
.phy_id
= bp
->phy_addr
;
2007 bp
->mii_if
.phy_id_mask
= 0x1f;
2008 bp
->mii_if
.reg_num_mask
= 0x1f;
2010 /* By default, advertise all speed/duplex settings. */
2011 bp
->flags
|= (B44_FLAG_ADV_10HALF
| B44_FLAG_ADV_10FULL
|
2012 B44_FLAG_ADV_100HALF
| B44_FLAG_ADV_100FULL
);
2014 /* By default, auto-negotiate PAUSE. */
2015 bp
->flags
|= B44_FLAG_PAUSE_AUTO
;
2017 err
= register_netdev(dev
);
2019 printk(KERN_ERR PFX
"Cannot register net device, "
2021 goto err_out_iounmap
;
2024 pci_set_drvdata(pdev
, dev
);
2026 pci_save_state(bp
->pdev
);
2028 printk(KERN_INFO
"%s: Broadcom 4400 10/100BaseT Ethernet ", dev
->name
);
2029 for (i
= 0; i
< 6; i
++)
2030 printk("%2.2x%c", dev
->dev_addr
[i
],
2031 i
== 5 ? '\n' : ':');
2042 pci_release_regions(pdev
);
2044 err_out_disable_pdev
:
2045 pci_disable_device(pdev
);
2046 pci_set_drvdata(pdev
, NULL
);
2050 static void __devexit
b44_remove_one(struct pci_dev
*pdev
)
2052 struct net_device
*dev
= pci_get_drvdata(pdev
);
2053 struct b44
*bp
= netdev_priv(dev
);
2055 unregister_netdev(dev
);
2058 pci_release_regions(pdev
);
2059 pci_disable_device(pdev
);
2060 pci_set_drvdata(pdev
, NULL
);
2063 static int b44_suspend(struct pci_dev
*pdev
, pm_message_t state
)
2065 struct net_device
*dev
= pci_get_drvdata(pdev
);
2066 struct b44
*bp
= netdev_priv(dev
);
2068 if (!netif_running(dev
))
2071 del_timer_sync(&bp
->timer
);
2073 spin_lock_irq(&bp
->lock
);
2076 netif_carrier_off(bp
->dev
);
2077 netif_device_detach(bp
->dev
);
2080 spin_unlock_irq(&bp
->lock
);
2082 free_irq(dev
->irq
, dev
);
2083 pci_disable_device(pdev
);
2087 static int b44_resume(struct pci_dev
*pdev
)
2089 struct net_device
*dev
= pci_get_drvdata(pdev
);
2090 struct b44
*bp
= netdev_priv(dev
);
2092 pci_restore_state(pdev
);
2093 pci_enable_device(pdev
);
2094 pci_set_master(pdev
);
2096 if (!netif_running(dev
))
2099 if (request_irq(dev
->irq
, b44_interrupt
, SA_SHIRQ
, dev
->name
, dev
))
2100 printk(KERN_ERR PFX
"%s: request_irq failed\n", dev
->name
);
2102 spin_lock_irq(&bp
->lock
);
2106 netif_device_attach(bp
->dev
);
2107 spin_unlock_irq(&bp
->lock
);
2109 bp
->timer
.expires
= jiffies
+ HZ
;
2110 add_timer(&bp
->timer
);
2112 b44_enable_ints(bp
);
2116 static struct pci_driver b44_driver
= {
2117 .name
= DRV_MODULE_NAME
,
2118 .id_table
= b44_pci_tbl
,
2119 .probe
= b44_init_one
,
2120 .remove
= __devexit_p(b44_remove_one
),
2121 .suspend
= b44_suspend
,
2122 .resume
= b44_resume
,
2125 static int __init
b44_init(void)
2127 unsigned int dma_desc_align_size
= dma_get_cache_alignment();
2129 /* Setup paramaters for syncing RX/TX DMA descriptors */
2130 dma_desc_align_mask
= ~(dma_desc_align_size
- 1);
2131 dma_desc_sync_size
= max(dma_desc_align_size
, sizeof(struct dma_desc
));
2133 return pci_module_init(&b44_driver
);
2136 static void __exit
b44_cleanup(void)
2138 pci_unregister_driver(&b44_driver
);
2141 module_init(b44_init
);
2142 module_exit(b44_cleanup
);