1 /* $Id: diva.c,v 1.33.2.6 2004/02/11 13:21:33 keil Exp $
3 * low level stuff for Eicon.Diehl Diva Family ISDN cards
6 * Copyright by Karsten Keil <keil@isdn4linux.de>
8 * This software may be used and distributed according to the terms
9 * of the GNU General Public License, incorporated herein by reference.
11 * For changes and modifications please read
12 * Documentation/isdn/HiSax.cert
14 * Thanks to Eicon Technology for documents and information
18 #include <linux/init.h>
25 #include <linux/pci.h>
26 #include <linux/isapnp.h>
28 extern const char *CardType
[];
30 static const char *Diva_revision
= "$Revision: 1.33.2.6 $";
32 #define byteout(addr,val) outb(val,addr)
33 #define bytein(addr) inb(addr)
35 #define DIVA_HSCX_DATA 0
36 #define DIVA_HSCX_ADR 4
37 #define DIVA_ISA_ISAC_DATA 2
38 #define DIVA_ISA_ISAC_ADR 6
39 #define DIVA_ISA_CTRL 7
40 #define DIVA_IPAC_ADR 0
41 #define DIVA_IPAC_DATA 1
43 #define DIVA_PCI_ISAC_DATA 8
44 #define DIVA_PCI_ISAC_ADR 0xc
45 #define DIVA_PCI_CTRL 0x10
50 #define DIVA_IPAC_ISA 3
51 #define DIVA_IPAC_PCI 4
52 #define DIVA_IPACX_PCI 5
55 #define DIVA_IRQ_STAT 0x01
56 #define DIVA_EEPROM_SDA 0x02
59 #define DIVA_IRQ_REQ 0x01
60 #define DIVA_RESET 0x08
61 #define DIVA_EEPROM_CLK 0x40
62 #define DIVA_PCI_LED_A 0x10
63 #define DIVA_PCI_LED_B 0x20
64 #define DIVA_ISA_LED_A 0x20
65 #define DIVA_ISA_LED_B 0x40
66 #define DIVA_IRQ_CLR 0x80
69 #define PITA_MISC_REG 0x1c
71 #define PITA_PARA_SOFTRESET 0x00000001
72 #define PITA_SER_SOFTRESET 0x00000002
73 #define PITA_PARA_MPX_MODE 0x00000004
74 #define PITA_INT0_ENABLE 0x00000200
76 #define PITA_PARA_SOFTRESET 0x01000000
77 #define PITA_SER_SOFTRESET 0x02000000
78 #define PITA_PARA_MPX_MODE 0x04000000
79 #define PITA_INT0_ENABLE 0x00020000
81 #define PITA_INT0_STATUS 0x02
84 readreg(unsigned int ale
, unsigned int adr
, u_char off
)
94 readfifo(unsigned int ale
, unsigned int adr
, u_char off
, u_char
* data
, int size
)
97 insb(adr
, data
, size
);
102 writereg(unsigned int ale
, unsigned int adr
, u_char off
, u_char data
)
109 writefifo(unsigned int ale
, unsigned int adr
, u_char off
, u_char
*data
, int size
)
112 outsb(adr
, data
, size
);
116 memreadreg(unsigned long adr
, u_char off
)
118 return(*((unsigned char *)
119 (((unsigned int *)adr
) + off
)));
123 memwritereg(unsigned long adr
, u_char off
, u_char data
)
127 p
= (unsigned char *)(((unsigned int *)adr
) + off
);
131 /* Interface functions */
134 ReadISAC(struct IsdnCardState
*cs
, u_char offset
)
136 return(readreg(cs
->hw
.diva
.isac_adr
, cs
->hw
.diva
.isac
, offset
));
140 WriteISAC(struct IsdnCardState
*cs
, u_char offset
, u_char value
)
142 writereg(cs
->hw
.diva
.isac_adr
, cs
->hw
.diva
.isac
, offset
, value
);
146 ReadISACfifo(struct IsdnCardState
*cs
, u_char
*data
, int size
)
148 readfifo(cs
->hw
.diva
.isac_adr
, cs
->hw
.diva
.isac
, 0, data
, size
);
152 WriteISACfifo(struct IsdnCardState
*cs
, u_char
*data
, int size
)
154 writefifo(cs
->hw
.diva
.isac_adr
, cs
->hw
.diva
.isac
, 0, data
, size
);
158 ReadISAC_IPAC(struct IsdnCardState
*cs
, u_char offset
)
160 return (readreg(cs
->hw
.diva
.isac_adr
, cs
->hw
.diva
.isac
, offset
+0x80));
164 WriteISAC_IPAC(struct IsdnCardState
*cs
, u_char offset
, u_char value
)
166 writereg(cs
->hw
.diva
.isac_adr
, cs
->hw
.diva
.isac
, offset
|0x80, value
);
170 ReadISACfifo_IPAC(struct IsdnCardState
*cs
, u_char
* data
, int size
)
172 readfifo(cs
->hw
.diva
.isac_adr
, cs
->hw
.diva
.isac
, 0x80, data
, size
);
176 WriteISACfifo_IPAC(struct IsdnCardState
*cs
, u_char
* data
, int size
)
178 writefifo(cs
->hw
.diva
.isac_adr
, cs
->hw
.diva
.isac
, 0x80, data
, size
);
182 ReadHSCX(struct IsdnCardState
*cs
, int hscx
, u_char offset
)
184 return(readreg(cs
->hw
.diva
.hscx_adr
,
185 cs
->hw
.diva
.hscx
, offset
+ (hscx
? 0x40 : 0)));
189 WriteHSCX(struct IsdnCardState
*cs
, int hscx
, u_char offset
, u_char value
)
191 writereg(cs
->hw
.diva
.hscx_adr
,
192 cs
->hw
.diva
.hscx
, offset
+ (hscx
? 0x40 : 0), value
);
196 MemReadISAC_IPAC(struct IsdnCardState
*cs
, u_char offset
)
198 return (memreadreg(cs
->hw
.diva
.cfg_reg
, offset
+0x80));
202 MemWriteISAC_IPAC(struct IsdnCardState
*cs
, u_char offset
, u_char value
)
204 memwritereg(cs
->hw
.diva
.cfg_reg
, offset
|0x80, value
);
208 MemReadISACfifo_IPAC(struct IsdnCardState
*cs
, u_char
* data
, int size
)
211 *data
++ = memreadreg(cs
->hw
.diva
.cfg_reg
, 0x80);
215 MemWriteISACfifo_IPAC(struct IsdnCardState
*cs
, u_char
* data
, int size
)
218 memwritereg(cs
->hw
.diva
.cfg_reg
, 0x80, *data
++);
222 MemReadHSCX(struct IsdnCardState
*cs
, int hscx
, u_char offset
)
224 return(memreadreg(cs
->hw
.diva
.cfg_reg
, offset
+ (hscx
? 0x40 : 0)));
228 MemWriteHSCX(struct IsdnCardState
*cs
, int hscx
, u_char offset
, u_char value
)
230 memwritereg(cs
->hw
.diva
.cfg_reg
, offset
+ (hscx
? 0x40 : 0), value
);
233 /* IO-Functions for IPACX type cards */
235 MemReadISAC_IPACX(struct IsdnCardState
*cs
, u_char offset
)
237 return (memreadreg(cs
->hw
.diva
.cfg_reg
, offset
));
241 MemWriteISAC_IPACX(struct IsdnCardState
*cs
, u_char offset
, u_char value
)
243 memwritereg(cs
->hw
.diva
.cfg_reg
, offset
, value
);
247 MemReadISACfifo_IPACX(struct IsdnCardState
*cs
, u_char
* data
, int size
)
250 *data
++ = memreadreg(cs
->hw
.diva
.cfg_reg
, 0);
254 MemWriteISACfifo_IPACX(struct IsdnCardState
*cs
, u_char
* data
, int size
)
257 memwritereg(cs
->hw
.diva
.cfg_reg
, 0, *data
++);
261 MemReadHSCX_IPACX(struct IsdnCardState
*cs
, int hscx
, u_char offset
)
263 return(memreadreg(cs
->hw
.diva
.cfg_reg
, offset
+
264 (hscx
? IPACX_OFF_B2
: IPACX_OFF_B1
)));
268 MemWriteHSCX_IPACX(struct IsdnCardState
*cs
, int hscx
, u_char offset
, u_char value
)
270 memwritereg(cs
->hw
.diva
.cfg_reg
, offset
+
271 (hscx
? IPACX_OFF_B2
: IPACX_OFF_B1
), value
);
275 * fast interrupt HSCX stuff goes here
278 #define READHSCX(cs, nr, reg) readreg(cs->hw.diva.hscx_adr, \
279 cs->hw.diva.hscx, reg + (nr ? 0x40 : 0))
280 #define WRITEHSCX(cs, nr, reg, data) writereg(cs->hw.diva.hscx_adr, \
281 cs->hw.diva.hscx, reg + (nr ? 0x40 : 0), data)
283 #define READHSCXFIFO(cs, nr, ptr, cnt) readfifo(cs->hw.diva.hscx_adr, \
284 cs->hw.diva.hscx, (nr ? 0x40 : 0), ptr, cnt)
286 #define WRITEHSCXFIFO(cs, nr, ptr, cnt) writefifo(cs->hw.diva.hscx_adr, \
287 cs->hw.diva.hscx, (nr ? 0x40 : 0), ptr, cnt)
289 #include "hscx_irq.c"
292 diva_interrupt(int intno
, void *dev_id
, struct pt_regs
*regs
)
294 struct IsdnCardState
*cs
= dev_id
;
299 spin_lock_irqsave(&cs
->lock
, flags
);
300 while (((sval
= bytein(cs
->hw
.diva
.ctrl
)) & DIVA_IRQ_REQ
) && cnt
) {
301 val
= readreg(cs
->hw
.diva
.hscx_adr
, cs
->hw
.diva
.hscx
, HSCX_ISTA
+ 0x40);
303 hscx_int_main(cs
, val
);
304 val
= readreg(cs
->hw
.diva
.isac_adr
, cs
->hw
.diva
.isac
, ISAC_ISTA
);
306 isac_interrupt(cs
, val
);
310 printk(KERN_WARNING
"Diva: IRQ LOOP\n");
311 writereg(cs
->hw
.diva
.hscx_adr
, cs
->hw
.diva
.hscx
, HSCX_MASK
, 0xFF);
312 writereg(cs
->hw
.diva
.hscx_adr
, cs
->hw
.diva
.hscx
, HSCX_MASK
+ 0x40, 0xFF);
313 writereg(cs
->hw
.diva
.isac_adr
, cs
->hw
.diva
.isac
, ISAC_MASK
, 0xFF);
314 writereg(cs
->hw
.diva
.isac_adr
, cs
->hw
.diva
.isac
, ISAC_MASK
, 0x0);
315 writereg(cs
->hw
.diva
.hscx_adr
, cs
->hw
.diva
.hscx
, HSCX_MASK
, 0x0);
316 writereg(cs
->hw
.diva
.hscx_adr
, cs
->hw
.diva
.hscx
, HSCX_MASK
+ 0x40, 0x0);
317 spin_unlock_irqrestore(&cs
->lock
, flags
);
322 diva_irq_ipac_isa(int intno
, void *dev_id
, struct pt_regs
*regs
)
324 struct IsdnCardState
*cs
= dev_id
;
329 spin_lock_irqsave(&cs
->lock
, flags
);
330 ista
= readreg(cs
->hw
.diva
.isac_adr
, cs
->hw
.diva
.isac
, IPAC_ISTA
);
332 if (cs
->debug
& L1_DEB_IPAC
)
333 debugl1(cs
, "IPAC ISTA %02X", ista
);
335 val
= readreg(cs
->hw
.diva
.isac_adr
, cs
->hw
.diva
.isac
, HSCX_ISTA
+ 0x40);
343 hscx_int_main(cs
, val
);
346 val
= 0xfe & readreg(cs
->hw
.diva
.isac_adr
, cs
->hw
.diva
.isac
, ISAC_ISTA
+ 0x80);
348 isac_interrupt(cs
, val
);
353 isac_interrupt(cs
, val
);
355 ista
= readreg(cs
->hw
.diva
.isac_adr
, cs
->hw
.diva
.isac
, IPAC_ISTA
);
356 if ((ista
& 0x3f) && icnt
) {
361 printk(KERN_WARNING
"DIVA IPAC IRQ LOOP\n");
362 writereg(cs
->hw
.diva
.isac_adr
, cs
->hw
.diva
.isac
, IPAC_MASK
, 0xFF);
363 writereg(cs
->hw
.diva
.isac_adr
, cs
->hw
.diva
.isac
, IPAC_MASK
, 0xC0);
364 spin_unlock_irqrestore(&cs
->lock
, flags
);
369 MemwaitforCEC(struct IsdnCardState
*cs
, int hscx
)
373 while ((MemReadHSCX(cs
, hscx
, HSCX_STAR
) & 0x04) && to
) {
378 printk(KERN_WARNING
"HiSax: waitforCEC timeout\n");
383 MemwaitforXFW(struct IsdnCardState
*cs
, int hscx
)
387 while ((!(MemReadHSCX(cs
, hscx
, HSCX_STAR
) & 0x44) == 0x40) && to
) {
392 printk(KERN_WARNING
"HiSax: waitforXFW timeout\n");
396 MemWriteHSCXCMDR(struct IsdnCardState
*cs
, int hscx
, u_char data
)
398 MemwaitforCEC(cs
, hscx
);
399 MemWriteHSCX(cs
, hscx
, HSCX_CMDR
, data
);
403 Memhscx_empty_fifo(struct BCState
*bcs
, int count
)
406 struct IsdnCardState
*cs
= bcs
->cs
;
409 if ((cs
->debug
& L1_DEB_HSCX
) && !(cs
->debug
& L1_DEB_HSCX_FIFO
))
410 debugl1(cs
, "hscx_empty_fifo");
412 if (bcs
->hw
.hscx
.rcvidx
+ count
> HSCX_BUFMAX
) {
413 if (cs
->debug
& L1_DEB_WARN
)
414 debugl1(cs
, "hscx_empty_fifo: incoming packet too large");
415 MemWriteHSCXCMDR(cs
, bcs
->hw
.hscx
.hscx
, 0x80);
416 bcs
->hw
.hscx
.rcvidx
= 0;
419 ptr
= bcs
->hw
.hscx
.rcvbuf
+ bcs
->hw
.hscx
.rcvidx
;
422 *ptr
++ = memreadreg(cs
->hw
.diva
.cfg_reg
, bcs
->hw
.hscx
.hscx
? 0x40 : 0);
423 MemWriteHSCXCMDR(cs
, bcs
->hw
.hscx
.hscx
, 0x80);
424 ptr
= bcs
->hw
.hscx
.rcvbuf
+ bcs
->hw
.hscx
.rcvidx
;
425 bcs
->hw
.hscx
.rcvidx
+= count
;
426 if (cs
->debug
& L1_DEB_HSCX_FIFO
) {
429 t
+= sprintf(t
, "hscx_empty_fifo %c cnt %d",
430 bcs
->hw
.hscx
.hscx
? 'B' : 'A', count
);
431 QuickHex(t
, ptr
, count
);
432 debugl1(cs
, bcs
->blog
);
437 Memhscx_fill_fifo(struct BCState
*bcs
)
439 struct IsdnCardState
*cs
= bcs
->cs
;
440 int more
, count
, cnt
;
441 int fifo_size
= test_bit(HW_IPAC
, &cs
->HW_Flags
)? 64: 32;
444 if ((cs
->debug
& L1_DEB_HSCX
) && !(cs
->debug
& L1_DEB_HSCX_FIFO
))
445 debugl1(cs
, "hscx_fill_fifo");
449 if (bcs
->tx_skb
->len
<= 0)
452 more
= (bcs
->mode
== L1_MODE_TRANS
) ? 1 : 0;
453 if (bcs
->tx_skb
->len
> fifo_size
) {
457 count
= bcs
->tx_skb
->len
;
459 MemwaitforXFW(cs
, bcs
->hw
.hscx
.hscx
);
460 p
= ptr
= bcs
->tx_skb
->data
;
461 skb_pull(bcs
->tx_skb
, count
);
462 bcs
->tx_cnt
-= count
;
463 bcs
->hw
.hscx
.count
+= count
;
465 memwritereg(cs
->hw
.diva
.cfg_reg
, bcs
->hw
.hscx
.hscx
? 0x40 : 0,
467 MemWriteHSCXCMDR(cs
, bcs
->hw
.hscx
.hscx
, more
? 0x8 : 0xa);
468 if (cs
->debug
& L1_DEB_HSCX_FIFO
) {
471 t
+= sprintf(t
, "hscx_fill_fifo %c cnt %d",
472 bcs
->hw
.hscx
.hscx
? 'B' : 'A', count
);
473 QuickHex(t
, ptr
, count
);
474 debugl1(cs
, bcs
->blog
);
479 Memhscx_interrupt(struct IsdnCardState
*cs
, u_char val
, u_char hscx
)
482 struct BCState
*bcs
= cs
->bcs
+ hscx
;
484 int fifo_size
= test_bit(HW_IPAC
, &cs
->HW_Flags
)? 64: 32;
487 if (!test_bit(BC_FLG_INIT
, &bcs
->Flag
))
490 if (val
& 0x80) { /* RME */
491 r
= MemReadHSCX(cs
, hscx
, HSCX_RSTA
);
492 if ((r
& 0xf0) != 0xa0) {
494 if (cs
->debug
& L1_DEB_WARN
)
495 debugl1(cs
, "HSCX invalid frame");
496 if ((r
& 0x40) && bcs
->mode
)
497 if (cs
->debug
& L1_DEB_WARN
)
498 debugl1(cs
, "HSCX RDO mode=%d",
501 if (cs
->debug
& L1_DEB_WARN
)
502 debugl1(cs
, "HSCX CRC error");
503 MemWriteHSCXCMDR(cs
, hscx
, 0x80);
505 count
= MemReadHSCX(cs
, hscx
, HSCX_RBCL
) & (
506 test_bit(HW_IPAC
, &cs
->HW_Flags
)? 0x3f: 0x1f);
509 Memhscx_empty_fifo(bcs
, count
);
510 if ((count
= bcs
->hw
.hscx
.rcvidx
- 1) > 0) {
511 if (cs
->debug
& L1_DEB_HSCX_FIFO
)
512 debugl1(cs
, "HX Frame %d", count
);
513 if (!(skb
= dev_alloc_skb(count
)))
514 printk(KERN_WARNING
"HSCX: receive out of memory\n");
516 memcpy(skb_put(skb
, count
), bcs
->hw
.hscx
.rcvbuf
, count
);
517 skb_queue_tail(&bcs
->rqueue
, skb
);
521 bcs
->hw
.hscx
.rcvidx
= 0;
522 schedule_event(bcs
, B_RCVBUFREADY
);
524 if (val
& 0x40) { /* RPF */
525 Memhscx_empty_fifo(bcs
, fifo_size
);
526 if (bcs
->mode
== L1_MODE_TRANS
) {
527 /* receive audio data */
528 if (!(skb
= dev_alloc_skb(fifo_size
)))
529 printk(KERN_WARNING
"HiSax: receive out of memory\n");
531 memcpy(skb_put(skb
, fifo_size
), bcs
->hw
.hscx
.rcvbuf
, fifo_size
);
532 skb_queue_tail(&bcs
->rqueue
, skb
);
534 bcs
->hw
.hscx
.rcvidx
= 0;
535 schedule_event(bcs
, B_RCVBUFREADY
);
538 if (val
& 0x10) { /* XPR */
540 if (bcs
->tx_skb
->len
) {
541 Memhscx_fill_fifo(bcs
);
544 if (test_bit(FLG_LLI_L1WAKEUP
,&bcs
->st
->lli
.flag
) &&
545 (PACKET_NOACK
!= bcs
->tx_skb
->pkt_type
)) {
547 spin_lock_irqsave(&bcs
->aclock
, flags
);
548 bcs
->ackcnt
+= bcs
->hw
.hscx
.count
;
549 spin_unlock_irqrestore(&bcs
->aclock
, flags
);
550 schedule_event(bcs
, B_ACKPENDING
);
552 dev_kfree_skb_irq(bcs
->tx_skb
);
553 bcs
->hw
.hscx
.count
= 0;
557 if ((bcs
->tx_skb
= skb_dequeue(&bcs
->squeue
))) {
558 bcs
->hw
.hscx
.count
= 0;
559 test_and_set_bit(BC_FLG_BUSY
, &bcs
->Flag
);
560 Memhscx_fill_fifo(bcs
);
562 test_and_clear_bit(BC_FLG_BUSY
, &bcs
->Flag
);
563 schedule_event(bcs
, B_XMTBUFREADY
);
569 Memhscx_int_main(struct IsdnCardState
*cs
, u_char val
)
575 if (val
& 0x01) { // EXB
577 exval
= MemReadHSCX(cs
, 1, HSCX_EXIR
);
580 Memhscx_fill_fifo(bcs
);
582 /* Here we lost an TX interrupt, so
583 * restart transmitting the whole frame.
586 skb_push(bcs
->tx_skb
, bcs
->hw
.hscx
.count
);
587 bcs
->tx_cnt
+= bcs
->hw
.hscx
.count
;
588 bcs
->hw
.hscx
.count
= 0;
590 MemWriteHSCXCMDR(cs
, bcs
->hw
.hscx
.hscx
, 0x01);
591 if (cs
->debug
& L1_DEB_WARN
)
592 debugl1(cs
, "HSCX B EXIR %x Lost TX", exval
);
594 } else if (cs
->debug
& L1_DEB_HSCX
)
595 debugl1(cs
, "HSCX B EXIR %x", exval
);
598 if (cs
->debug
& L1_DEB_HSCX
)
599 debugl1(cs
, "HSCX B interrupt %x", val
);
600 Memhscx_interrupt(cs
, val
, 1);
602 if (val
& 0x02) { // EXA
604 exval
= MemReadHSCX(cs
, 0, HSCX_EXIR
);
606 if (bcs
->mode
== L1_MODE_TRANS
)
607 Memhscx_fill_fifo(bcs
);
609 /* Here we lost an TX interrupt, so
610 * restart transmitting the whole frame.
613 skb_push(bcs
->tx_skb
, bcs
->hw
.hscx
.count
);
614 bcs
->tx_cnt
+= bcs
->hw
.hscx
.count
;
615 bcs
->hw
.hscx
.count
= 0;
617 MemWriteHSCXCMDR(cs
, bcs
->hw
.hscx
.hscx
, 0x01);
618 if (cs
->debug
& L1_DEB_WARN
)
619 debugl1(cs
, "HSCX A EXIR %x Lost TX", exval
);
621 } else if (cs
->debug
& L1_DEB_HSCX
)
622 debugl1(cs
, "HSCX A EXIR %x", exval
);
624 if (val
& 0x04) { // ICA
625 exval
= MemReadHSCX(cs
, 0, HSCX_ISTA
);
626 if (cs
->debug
& L1_DEB_HSCX
)
627 debugl1(cs
, "HSCX A interrupt %x", exval
);
628 Memhscx_interrupt(cs
, exval
, 0);
633 diva_irq_ipac_pci(int intno
, void *dev_id
, struct pt_regs
*regs
)
635 struct IsdnCardState
*cs
= dev_id
;
641 spin_lock_irqsave(&cs
->lock
, flags
);
642 cfg
= (u_char
*) cs
->hw
.diva
.pci_cfg
;
644 if (!(val
& PITA_INT0_STATUS
)) {
645 spin_unlock_irqrestore(&cs
->lock
, flags
);
646 return IRQ_NONE
; /* other shared IRQ */
648 *cfg
= PITA_INT0_STATUS
; /* Reset pending INT0 */
649 ista
= memreadreg(cs
->hw
.diva
.cfg_reg
, IPAC_ISTA
);
651 if (cs
->debug
& L1_DEB_IPAC
)
652 debugl1(cs
, "IPAC ISTA %02X", ista
);
654 val
= memreadreg(cs
->hw
.diva
.cfg_reg
, HSCX_ISTA
+ 0x40);
662 Memhscx_int_main(cs
, val
);
665 val
= 0xfe & memreadreg(cs
->hw
.diva
.cfg_reg
, ISAC_ISTA
+ 0x80);
667 isac_interrupt(cs
, val
);
672 isac_interrupt(cs
, val
);
674 ista
= memreadreg(cs
->hw
.diva
.cfg_reg
, IPAC_ISTA
);
675 if ((ista
& 0x3f) && icnt
) {
680 printk(KERN_WARNING
"DIVA IPAC PCI IRQ LOOP\n");
681 memwritereg(cs
->hw
.diva
.cfg_reg
, IPAC_MASK
, 0xFF);
682 memwritereg(cs
->hw
.diva
.cfg_reg
, IPAC_MASK
, 0xC0);
683 spin_unlock_irqrestore(&cs
->lock
, flags
);
688 diva_irq_ipacx_pci(int intno
, void *dev_id
, struct pt_regs
*regs
)
690 struct IsdnCardState
*cs
= dev_id
;
695 spin_lock_irqsave(&cs
->lock
, flags
);
696 cfg
= (u_char
*) cs
->hw
.diva
.pci_cfg
;
698 if (!(val
&PITA_INT0_STATUS
)) {
699 spin_unlock_irqrestore(&cs
->lock
, flags
);
700 return IRQ_NONE
; // other shared IRQ
702 interrupt_ipacx(cs
); // handler for chip
703 *cfg
= PITA_INT0_STATUS
; // Reset PLX interrupt
704 spin_unlock_irqrestore(&cs
->lock
, flags
);
709 release_io_diva(struct IsdnCardState
*cs
)
713 if ((cs
->subtyp
== DIVA_IPAC_PCI
) ||
714 (cs
->subtyp
== DIVA_IPACX_PCI
) ) {
715 u_int
*cfg
= (unsigned int *)cs
->hw
.diva
.pci_cfg
;
717 *cfg
= 0; /* disable INT0/1 */
718 *cfg
= 2; /* reset pending INT0 */
719 iounmap((void *)cs
->hw
.diva
.cfg_reg
);
720 iounmap((void *)cs
->hw
.diva
.pci_cfg
);
722 } else if (cs
->subtyp
!= DIVA_IPAC_ISA
) {
723 del_timer(&cs
->hw
.diva
.tl
);
724 if (cs
->hw
.diva
.cfg_reg
)
725 byteout(cs
->hw
.diva
.ctrl
, 0); /* LED off, Reset */
727 if ((cs
->subtyp
== DIVA_ISA
) || (cs
->subtyp
== DIVA_IPAC_ISA
))
731 if (cs
->hw
.diva
.cfg_reg
) {
732 release_region(cs
->hw
.diva
.cfg_reg
, bytecnt
);
737 reset_diva(struct IsdnCardState
*cs
)
739 if (cs
->subtyp
== DIVA_IPAC_ISA
) {
740 writereg(cs
->hw
.diva
.isac_adr
, cs
->hw
.diva
.isac
, IPAC_POTA2
, 0x20);
742 writereg(cs
->hw
.diva
.isac_adr
, cs
->hw
.diva
.isac
, IPAC_POTA2
, 0x00);
744 writereg(cs
->hw
.diva
.isac_adr
, cs
->hw
.diva
.isac
, IPAC_MASK
, 0xc0);
745 } else if (cs
->subtyp
== DIVA_IPAC_PCI
) {
746 unsigned int *ireg
= (unsigned int *)(cs
->hw
.diva
.pci_cfg
+
748 *ireg
= PITA_PARA_SOFTRESET
| PITA_PARA_MPX_MODE
;
750 *ireg
= PITA_PARA_MPX_MODE
;
752 memwritereg(cs
->hw
.diva
.cfg_reg
, IPAC_MASK
, 0xc0);
753 } else if (cs
->subtyp
== DIVA_IPACX_PCI
) {
754 unsigned int *ireg
= (unsigned int *)(cs
->hw
.diva
.pci_cfg
+
756 *ireg
= PITA_PARA_SOFTRESET
| PITA_PARA_MPX_MODE
;
758 *ireg
= PITA_PARA_MPX_MODE
| PITA_SER_SOFTRESET
;
760 MemWriteISAC_IPACX(cs
, IPACX_MASK
, 0xff); // Interrupts off
761 } else { /* DIVA 2.0 */
762 cs
->hw
.diva
.ctrl_reg
= 0; /* Reset On */
763 byteout(cs
->hw
.diva
.ctrl
, cs
->hw
.diva
.ctrl_reg
);
765 cs
->hw
.diva
.ctrl_reg
|= DIVA_RESET
; /* Reset Off */
766 byteout(cs
->hw
.diva
.ctrl
, cs
->hw
.diva
.ctrl_reg
);
768 if (cs
->subtyp
== DIVA_ISA
)
769 cs
->hw
.diva
.ctrl_reg
|= DIVA_ISA_LED_A
;
771 /* Workaround PCI9060 */
772 byteout(cs
->hw
.diva
.pci_cfg
+ 0x69, 9);
773 cs
->hw
.diva
.ctrl_reg
|= DIVA_PCI_LED_A
;
775 byteout(cs
->hw
.diva
.ctrl
, cs
->hw
.diva
.ctrl_reg
);
779 #define DIVA_ASSIGN 1
782 diva_led_handler(struct IsdnCardState
*cs
)
786 if ((cs
->subtyp
== DIVA_IPAC_ISA
) ||
787 (cs
->subtyp
== DIVA_IPAC_PCI
) ||
788 (cs
->subtyp
== DIVA_IPACX_PCI
) )
790 del_timer(&cs
->hw
.diva
.tl
);
791 if (cs
->hw
.diva
.status
& DIVA_ASSIGN
)
792 cs
->hw
.diva
.ctrl_reg
|= (DIVA_ISA
== cs
->subtyp
) ?
793 DIVA_ISA_LED_A
: DIVA_PCI_LED_A
;
795 cs
->hw
.diva
.ctrl_reg
^= (DIVA_ISA
== cs
->subtyp
) ?
796 DIVA_ISA_LED_A
: DIVA_PCI_LED_A
;
799 if (cs
->hw
.diva
.status
& 0xf000)
800 cs
->hw
.diva
.ctrl_reg
|= (DIVA_ISA
== cs
->subtyp
) ?
801 DIVA_ISA_LED_B
: DIVA_PCI_LED_B
;
802 else if (cs
->hw
.diva
.status
& 0x0f00) {
803 cs
->hw
.diva
.ctrl_reg
^= (DIVA_ISA
== cs
->subtyp
) ?
804 DIVA_ISA_LED_B
: DIVA_PCI_LED_B
;
807 cs
->hw
.diva
.ctrl_reg
&= ~((DIVA_ISA
== cs
->subtyp
) ?
808 DIVA_ISA_LED_B
: DIVA_PCI_LED_B
);
810 byteout(cs
->hw
.diva
.ctrl
, cs
->hw
.diva
.ctrl_reg
);
812 init_timer(&cs
->hw
.diva
.tl
);
813 cs
->hw
.diva
.tl
.expires
= jiffies
+ ((blink
* HZ
) / 1000);
814 add_timer(&cs
->hw
.diva
.tl
);
819 Diva_card_msg(struct IsdnCardState
*cs
, int mt
, void *arg
)
826 spin_lock_irqsave(&cs
->lock
, flags
);
828 spin_unlock_irqrestore(&cs
->lock
, flags
);
834 spin_lock_irqsave(&cs
->lock
, flags
);
836 if (cs
->subtyp
== DIVA_IPACX_PCI
) {
837 ireg
= (unsigned int *)cs
->hw
.diva
.pci_cfg
;
838 *ireg
= PITA_INT0_ENABLE
;
839 init_ipacx(cs
, 3); // init chip and enable interrupts
840 spin_unlock_irqrestore(&cs
->lock
, flags
);
843 if (cs
->subtyp
== DIVA_IPAC_PCI
) {
844 ireg
= (unsigned int *)cs
->hw
.diva
.pci_cfg
;
845 *ireg
= PITA_INT0_ENABLE
;
848 spin_unlock_irqrestore(&cs
->lock
, flags
);
852 case (MDL_REMOVE
| REQUEST
):
853 cs
->hw
.diva
.status
= 0;
855 case (MDL_ASSIGN
| REQUEST
):
856 cs
->hw
.diva
.status
|= DIVA_ASSIGN
;
860 cs
->hw
.diva
.status
|= 0x0200;
862 cs
->hw
.diva
.status
|= 0x0100;
866 cs
->hw
.diva
.status
|= 0x2000;
868 cs
->hw
.diva
.status
|= 0x1000;
872 cs
->hw
.diva
.status
&= ~0x2000;
873 cs
->hw
.diva
.status
&= ~0x0200;
875 cs
->hw
.diva
.status
&= ~0x1000;
876 cs
->hw
.diva
.status
&= ~0x0100;
880 if ((cs
->subtyp
!= DIVA_IPAC_ISA
) &&
881 (cs
->subtyp
!= DIVA_IPAC_PCI
) &&
882 (cs
->subtyp
!= DIVA_IPACX_PCI
)) {
883 spin_lock_irqsave(&cs
->lock
, flags
);
884 diva_led_handler(cs
);
885 spin_unlock_irqrestore(&cs
->lock
, flags
);
890 static struct pci_dev
*dev_diva __devinitdata
= NULL
;
891 static struct pci_dev
*dev_diva_u __devinitdata
= NULL
;
892 static struct pci_dev
*dev_diva201 __devinitdata
= NULL
;
893 static struct pci_dev
*dev_diva202 __devinitdata
= NULL
;
896 static struct isapnp_device_id diva_ids
[] __devinitdata
= {
897 { ISAPNP_VENDOR('G', 'D', 'I'), ISAPNP_FUNCTION(0x51),
898 ISAPNP_VENDOR('G', 'D', 'I'), ISAPNP_FUNCTION(0x51),
899 (unsigned long) "Diva picola" },
900 { ISAPNP_VENDOR('G', 'D', 'I'), ISAPNP_FUNCTION(0x51),
901 ISAPNP_VENDOR('E', 'I', 'C'), ISAPNP_FUNCTION(0x51),
902 (unsigned long) "Diva picola" },
903 { ISAPNP_VENDOR('G', 'D', 'I'), ISAPNP_FUNCTION(0x71),
904 ISAPNP_VENDOR('G', 'D', 'I'), ISAPNP_FUNCTION(0x71),
905 (unsigned long) "Diva 2.0" },
906 { ISAPNP_VENDOR('G', 'D', 'I'), ISAPNP_FUNCTION(0x71),
907 ISAPNP_VENDOR('E', 'I', 'C'), ISAPNP_FUNCTION(0x71),
908 (unsigned long) "Diva 2.0" },
909 { ISAPNP_VENDOR('G', 'D', 'I'), ISAPNP_FUNCTION(0xA1),
910 ISAPNP_VENDOR('G', 'D', 'I'), ISAPNP_FUNCTION(0xA1),
911 (unsigned long) "Diva 2.01" },
912 { ISAPNP_VENDOR('G', 'D', 'I'), ISAPNP_FUNCTION(0xA1),
913 ISAPNP_VENDOR('E', 'I', 'C'), ISAPNP_FUNCTION(0xA1),
914 (unsigned long) "Diva 2.01" },
918 static struct isapnp_device_id
*ipid __devinitdata
= &diva_ids
[0];
919 static struct pnp_card
*pnp_c __devinitdata
= NULL
;
924 setup_diva(struct IsdnCard
*card
)
928 struct IsdnCardState
*cs
= card
->cs
;
931 strcpy(tmp
, Diva_revision
);
932 printk(KERN_INFO
"HiSax: Eicon.Diehl Diva driver Rev. %s\n", HiSax_getrev(tmp
));
933 if (cs
->typ
!= ISDN_CTYPE_DIEHLDIVA
)
935 cs
->hw
.diva
.status
= 0;
937 cs
->hw
.diva
.ctrl_reg
= 0;
938 cs
->hw
.diva
.cfg_reg
= card
->para
[1];
939 val
= readreg(cs
->hw
.diva
.cfg_reg
+ DIVA_IPAC_ADR
,
940 cs
->hw
.diva
.cfg_reg
+ DIVA_IPAC_DATA
, IPAC_ID
);
941 printk(KERN_INFO
"Diva: IPAC version %x\n", val
);
942 if ((val
== 1) || (val
==2)) {
943 cs
->subtyp
= DIVA_IPAC_ISA
;
944 cs
->hw
.diva
.ctrl
= 0;
945 cs
->hw
.diva
.isac
= card
->para
[1] + DIVA_IPAC_DATA
;
946 cs
->hw
.diva
.hscx
= card
->para
[1] + DIVA_IPAC_DATA
;
947 cs
->hw
.diva
.isac_adr
= card
->para
[1] + DIVA_IPAC_ADR
;
948 cs
->hw
.diva
.hscx_adr
= card
->para
[1] + DIVA_IPAC_ADR
;
949 test_and_set_bit(HW_IPAC
, &cs
->HW_Flags
);
951 cs
->subtyp
= DIVA_ISA
;
952 cs
->hw
.diva
.ctrl
= card
->para
[1] + DIVA_ISA_CTRL
;
953 cs
->hw
.diva
.isac
= card
->para
[1] + DIVA_ISA_ISAC_DATA
;
954 cs
->hw
.diva
.hscx
= card
->para
[1] + DIVA_HSCX_DATA
;
955 cs
->hw
.diva
.isac_adr
= card
->para
[1] + DIVA_ISA_ISAC_ADR
;
956 cs
->hw
.diva
.hscx_adr
= card
->para
[1] + DIVA_HSCX_ADR
;
958 cs
->irq
= card
->para
[0];
961 if (isapnp_present()) {
962 struct pnp_dev
*pnp_d
;
963 while(ipid
->card_vendor
) {
964 if ((pnp_c
= pnp_find_card(ipid
->card_vendor
,
965 ipid
->card_device
, pnp_c
))) {
967 if ((pnp_d
= pnp_find_dev(pnp_c
,
968 ipid
->vendor
, ipid
->function
, pnp_d
))) {
971 printk(KERN_INFO
"HiSax: %s detected\n",
972 (char *)ipid
->driver_data
);
973 pnp_disable_dev(pnp_d
);
974 err
= pnp_activate_dev(pnp_d
);
976 printk(KERN_WARNING
"%s: pnp_activate_dev ret(%d)\n",
980 card
->para
[1] = pnp_port_start(pnp_d
, 0);
981 card
->para
[0] = pnp_irq(pnp_d
, 0);
982 if (!card
->para
[0] || !card
->para
[1]) {
983 printk(KERN_ERR
"Diva PnP:some resources are missing %ld/%lx\n",
984 card
->para
[0], card
->para
[1]);
985 pnp_disable_dev(pnp_d
);
988 cs
->hw
.diva
.cfg_reg
= card
->para
[1];
989 cs
->irq
= card
->para
[0];
990 if (ipid
->function
== ISAPNP_FUNCTION(0xA1)) {
991 cs
->subtyp
= DIVA_IPAC_ISA
;
992 cs
->hw
.diva
.ctrl
= 0;
994 card
->para
[1] + DIVA_IPAC_DATA
;
996 card
->para
[1] + DIVA_IPAC_DATA
;
997 cs
->hw
.diva
.isac_adr
=
998 card
->para
[1] + DIVA_IPAC_ADR
;
999 cs
->hw
.diva
.hscx_adr
=
1000 card
->para
[1] + DIVA_IPAC_ADR
;
1001 test_and_set_bit(HW_IPAC
, &cs
->HW_Flags
);
1003 cs
->subtyp
= DIVA_ISA
;
1005 card
->para
[1] + DIVA_ISA_CTRL
;
1007 card
->para
[1] + DIVA_ISA_ISAC_DATA
;
1009 card
->para
[1] + DIVA_HSCX_DATA
;
1010 cs
->hw
.diva
.isac_adr
=
1011 card
->para
[1] + DIVA_ISA_ISAC_ADR
;
1012 cs
->hw
.diva
.hscx_adr
=
1013 card
->para
[1] + DIVA_HSCX_ADR
;
1017 printk(KERN_ERR
"Diva PnP: PnP error card found, no device\n");
1024 if (!ipid
->card_vendor
) {
1025 printk(KERN_INFO
"Diva PnP: no ISAPnP card found\n");
1031 if ((dev_diva
= pci_find_device(PCI_VENDOR_ID_EICON
,
1032 PCI_DEVICE_ID_EICON_DIVA20
, dev_diva
))) {
1033 if (pci_enable_device(dev_diva
))
1035 cs
->subtyp
= DIVA_PCI
;
1036 cs
->irq
= dev_diva
->irq
;
1037 cs
->hw
.diva
.cfg_reg
= pci_resource_start(dev_diva
, 2);
1038 } else if ((dev_diva_u
= pci_find_device(PCI_VENDOR_ID_EICON
,
1039 PCI_DEVICE_ID_EICON_DIVA20_U
, dev_diva_u
))) {
1040 if (pci_enable_device(dev_diva_u
))
1042 cs
->subtyp
= DIVA_PCI
;
1043 cs
->irq
= dev_diva_u
->irq
;
1044 cs
->hw
.diva
.cfg_reg
= pci_resource_start(dev_diva_u
, 2);
1045 } else if ((dev_diva201
= pci_find_device(PCI_VENDOR_ID_EICON
,
1046 PCI_DEVICE_ID_EICON_DIVA201
, dev_diva201
))) {
1047 if (pci_enable_device(dev_diva201
))
1049 cs
->subtyp
= DIVA_IPAC_PCI
;
1050 cs
->irq
= dev_diva201
->irq
;
1051 cs
->hw
.diva
.pci_cfg
=
1052 (ulong
) ioremap(pci_resource_start(dev_diva201
, 0), 4096);
1053 cs
->hw
.diva
.cfg_reg
=
1054 (ulong
) ioremap(pci_resource_start(dev_diva201
, 1), 4096);
1055 } else if ((dev_diva202
= pci_find_device(PCI_VENDOR_ID_EICON
,
1056 PCI_DEVICE_ID_EICON_DIVA202
, dev_diva202
))) {
1057 if (pci_enable_device(dev_diva202
))
1059 cs
->subtyp
= DIVA_IPACX_PCI
;
1060 cs
->irq
= dev_diva202
->irq
;
1061 cs
->hw
.diva
.pci_cfg
=
1062 (ulong
) ioremap(pci_resource_start(dev_diva202
, 0), 4096);
1063 cs
->hw
.diva
.cfg_reg
=
1064 (ulong
) ioremap(pci_resource_start(dev_diva202
, 1), 4096);
1066 printk(KERN_WARNING
"Diva: No PCI card found\n");
1071 printk(KERN_WARNING
"Diva: No IRQ for PCI card found\n");
1075 if (!cs
->hw
.diva
.cfg_reg
) {
1076 printk(KERN_WARNING
"Diva: No IO-Adr for PCI card found\n");
1079 cs
->irq_flags
|= IRQF_SHARED
;
1081 printk(KERN_WARNING
"Diva: cfgreg 0 and NO_PCI_BIOS\n");
1082 printk(KERN_WARNING
"Diva: unable to config DIVA PCI\n");
1084 #endif /* CONFIG_PCI */
1085 if ((cs
->subtyp
== DIVA_IPAC_PCI
) ||
1086 (cs
->subtyp
== DIVA_IPACX_PCI
) ) {
1087 cs
->hw
.diva
.ctrl
= 0;
1088 cs
->hw
.diva
.isac
= 0;
1089 cs
->hw
.diva
.hscx
= 0;
1090 cs
->hw
.diva
.isac_adr
= 0;
1091 cs
->hw
.diva
.hscx_adr
= 0;
1092 test_and_set_bit(HW_IPAC
, &cs
->HW_Flags
);
1095 cs
->hw
.diva
.ctrl
= cs
->hw
.diva
.cfg_reg
+ DIVA_PCI_CTRL
;
1096 cs
->hw
.diva
.isac
= cs
->hw
.diva
.cfg_reg
+ DIVA_PCI_ISAC_DATA
;
1097 cs
->hw
.diva
.hscx
= cs
->hw
.diva
.cfg_reg
+ DIVA_HSCX_DATA
;
1098 cs
->hw
.diva
.isac_adr
= cs
->hw
.diva
.cfg_reg
+ DIVA_PCI_ISAC_ADR
;
1099 cs
->hw
.diva
.hscx_adr
= cs
->hw
.diva
.cfg_reg
+ DIVA_HSCX_ADR
;
1105 "Diva: %s card configured at %#lx IRQ %d\n",
1106 (cs
->subtyp
== DIVA_PCI
) ? "PCI" :
1107 (cs
->subtyp
== DIVA_ISA
) ? "ISA" :
1108 (cs
->subtyp
== DIVA_IPAC_ISA
) ? "IPAC ISA" :
1109 (cs
->subtyp
== DIVA_IPAC_PCI
) ? "IPAC PCI" : "IPACX PCI",
1110 cs
->hw
.diva
.cfg_reg
, cs
->irq
);
1111 if ((cs
->subtyp
== DIVA_IPAC_PCI
) ||
1112 (cs
->subtyp
== DIVA_IPACX_PCI
) ||
1113 (cs
->subtyp
== DIVA_PCI
) )
1114 printk(KERN_INFO
"Diva: %s space at %#lx\n",
1115 (cs
->subtyp
== DIVA_PCI
) ? "PCI" :
1116 (cs
->subtyp
== DIVA_IPAC_PCI
) ? "IPAC PCI" : "IPACX PCI",
1117 cs
->hw
.diva
.pci_cfg
);
1118 if ((cs
->subtyp
!= DIVA_IPAC_PCI
) &&
1119 (cs
->subtyp
!= DIVA_IPACX_PCI
) ) {
1120 if (!request_region(cs
->hw
.diva
.cfg_reg
, bytecnt
, "diva isdn")) {
1122 "HiSax: %s config port %lx-%lx already in use\n",
1123 CardType
[card
->typ
],
1124 cs
->hw
.diva
.cfg_reg
,
1125 cs
->hw
.diva
.cfg_reg
+ bytecnt
);
1129 cs
->BC_Read_Reg
= &ReadHSCX
;
1130 cs
->BC_Write_Reg
= &WriteHSCX
;
1131 cs
->BC_Send_Data
= &hscx_fill_fifo
;
1132 cs
->cardmsg
= &Diva_card_msg
;
1134 if (cs
->subtyp
== DIVA_IPAC_ISA
) {
1135 cs
->readisac
= &ReadISAC_IPAC
;
1136 cs
->writeisac
= &WriteISAC_IPAC
;
1137 cs
->readisacfifo
= &ReadISACfifo_IPAC
;
1138 cs
->writeisacfifo
= &WriteISACfifo_IPAC
;
1139 cs
->irq_func
= &diva_irq_ipac_isa
;
1140 val
= readreg(cs
->hw
.diva
.isac_adr
, cs
->hw
.diva
.isac
, IPAC_ID
);
1141 printk(KERN_INFO
"Diva: IPAC version %x\n", val
);
1142 } else if (cs
->subtyp
== DIVA_IPAC_PCI
) {
1143 cs
->readisac
= &MemReadISAC_IPAC
;
1144 cs
->writeisac
= &MemWriteISAC_IPAC
;
1145 cs
->readisacfifo
= &MemReadISACfifo_IPAC
;
1146 cs
->writeisacfifo
= &MemWriteISACfifo_IPAC
;
1147 cs
->BC_Read_Reg
= &MemReadHSCX
;
1148 cs
->BC_Write_Reg
= &MemWriteHSCX
;
1149 cs
->BC_Send_Data
= &Memhscx_fill_fifo
;
1150 cs
->irq_func
= &diva_irq_ipac_pci
;
1151 val
= memreadreg(cs
->hw
.diva
.cfg_reg
, IPAC_ID
);
1152 printk(KERN_INFO
"Diva: IPAC version %x\n", val
);
1153 } else if (cs
->subtyp
== DIVA_IPACX_PCI
) {
1154 cs
->readisac
= &MemReadISAC_IPACX
;
1155 cs
->writeisac
= &MemWriteISAC_IPACX
;
1156 cs
->readisacfifo
= &MemReadISACfifo_IPACX
;
1157 cs
->writeisacfifo
= &MemWriteISACfifo_IPACX
;
1158 cs
->BC_Read_Reg
= &MemReadHSCX_IPACX
;
1159 cs
->BC_Write_Reg
= &MemWriteHSCX_IPACX
;
1160 cs
->BC_Send_Data
= NULL
; // function located in ipacx module
1161 cs
->irq_func
= &diva_irq_ipacx_pci
;
1162 printk(KERN_INFO
"Diva: IPACX Design Id: %x\n",
1163 MemReadISAC_IPACX(cs
, IPACX_ID
) &0x3F);
1164 } else { /* DIVA 2.0 */
1165 cs
->hw
.diva
.tl
.function
= (void *) diva_led_handler
;
1166 cs
->hw
.diva
.tl
.data
= (long) cs
;
1167 init_timer(&cs
->hw
.diva
.tl
);
1168 cs
->readisac
= &ReadISAC
;
1169 cs
->writeisac
= &WriteISAC
;
1170 cs
->readisacfifo
= &ReadISACfifo
;
1171 cs
->writeisacfifo
= &WriteISACfifo
;
1172 cs
->irq_func
= &diva_interrupt
;
1173 ISACVersion(cs
, "Diva:");
1174 if (HscxVersion(cs
, "Diva:")) {
1176 "Diva: wrong HSCX versions check IO address\n");
1177 release_io_diva(cs
);