2 * BRIEF MODULE DESCRIPTION
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
10 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
11 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
12 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
13 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
14 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
15 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
16 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
17 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
18 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
19 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, write to the Free Software Foundation, Inc.,
23 * 675 Mass Ave, Cambridge, MA 02139, USA.
25 #include <linux/errno.h>
26 #include <linux/init.h>
27 #include <linux/irq.h>
28 #include <linux/kernel_stat.h>
29 #include <linux/module.h>
30 #include <linux/signal.h>
31 #include <linux/sched.h>
32 #include <linux/types.h>
33 #include <linux/interrupt.h>
34 #include <linux/ioport.h>
35 #include <linux/timex.h>
36 #include <linux/slab.h>
37 #include <linux/random.h>
38 #include <linux/delay.h>
40 #include <asm/bitops.h>
41 #include <asm/bootinfo.h>
43 #include <asm/mipsregs.h>
44 #include <asm/system.h>
45 #include <asm/mach-au1x00/au1000.h>
47 #ifdef CONFIG_MIPS_PB1200
48 #include <asm/mach-pb1x00/pb1200.h>
51 #ifdef CONFIG_MIPS_DB1200
52 #include <asm/mach-db1x00/db1200.h>
53 #define PB1200_INT_BEGIN DB1200_INT_BEGIN
54 #define PB1200_INT_END DB1200_INT_END
57 au1xxx_irq_map_t __initdata au1xxx_irq_map
[] = {
58 { AU1000_GPIO_7
, INTC_INT_LOW_LEVEL
, 0 }, // This is exteranl interrupt cascade
61 int __initdata au1xxx_nr_irqs
= ARRAY_SIZE(au1xxx_irq_map
);
64 * Support for External interrupts on the PbAu1200 Development platform.
66 static volatile int pb1200_cascade_en
=0;
68 irqreturn_t
pb1200_cascade_handler( int irq
, void *dev_id
, struct pt_regs
*regs
)
70 unsigned short bisr
= bcsr
->int_status
;
73 /* Clear all the edge interrupts. This has no effect on level */
74 bcsr
->int_status
= bisr
;
75 for( ; bisr
; bisr
&= (bisr
-1) )
77 extirq_nr
= (PB1200_INT_BEGIN
-1) + au_ffs(bisr
);
78 /* Ack and dispatch IRQ */
79 do_IRQ(extirq_nr
,regs
);
84 inline void pb1200_enable_irq(unsigned int irq_nr
)
86 bcsr
->intset_mask
= 1<<(irq_nr
- PB1200_INT_BEGIN
);
87 bcsr
->intset
= 1<<(irq_nr
- PB1200_INT_BEGIN
);
90 inline void pb1200_disable_irq(unsigned int irq_nr
)
92 bcsr
->intclr_mask
= 1<<(irq_nr
- PB1200_INT_BEGIN
);
93 bcsr
->intclr
= 1<<(irq_nr
- PB1200_INT_BEGIN
);
96 static unsigned int pb1200_startup_irq( unsigned int irq_nr
)
98 if (++pb1200_cascade_en
== 1)
100 request_irq(AU1000_GPIO_7
, &pb1200_cascade_handler
,
101 0, "Pb1200 Cascade", (void *)&pb1200_cascade_handler
);
102 #ifdef CONFIG_MIPS_PB1200
103 /* We have a problem with CPLD rev3. Enable a workaround */
104 if( ((bcsr
->whoami
& BCSR_WHOAMI_CPLD
)>>4) <= 3)
106 printk("\nWARNING!!!\n");
107 printk("\nWARNING!!!\n");
108 printk("\nWARNING!!!\n");
109 printk("\nWARNING!!!\n");
110 printk("\nWARNING!!!\n");
111 printk("\nWARNING!!!\n");
112 printk("Pb1200 must be at CPLD rev4. Please have Pb1200\n");
113 printk("updated to latest revision. This software will not\n");
114 printk("work on anything less than CPLD rev4\n");
115 printk("\nWARNING!!!\n");
116 printk("\nWARNING!!!\n");
117 printk("\nWARNING!!!\n");
118 printk("\nWARNING!!!\n");
119 printk("\nWARNING!!!\n");
120 printk("\nWARNING!!!\n");
125 pb1200_enable_irq(irq_nr
);
129 static void pb1200_shutdown_irq( unsigned int irq_nr
)
131 pb1200_disable_irq(irq_nr
);
132 if (--pb1200_cascade_en
== 0)
134 free_irq(AU1000_GPIO_7
,&pb1200_cascade_handler
);
139 static inline void pb1200_mask_and_ack_irq(unsigned int irq_nr
)
141 pb1200_disable_irq( irq_nr
);
144 static void pb1200_end_irq(unsigned int irq_nr
)
146 if (!(irq_desc
[irq_nr
].status
& (IRQ_DISABLED
|IRQ_INPROGRESS
))) {
147 pb1200_enable_irq(irq_nr
);
151 static struct irq_chip external_irq_type
=
153 #ifdef CONFIG_MIPS_PB1200
156 #ifdef CONFIG_MIPS_DB1200
163 pb1200_mask_and_ack_irq
,
168 void _board_init_irq(void)
172 for (irq_nr
= PB1200_INT_BEGIN
; irq_nr
<= PB1200_INT_END
; irq_nr
++)
174 irq_desc
[irq_nr
].chip
= &external_irq_type
;
175 pb1200_disable_irq(irq_nr
);
178 /* GPIO_7 can not be hooked here, so it is hooked upon first
179 request of any source attached to the cascade */