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ACPI: thermal: Use acpi_device's handle instead of driver's
[linux-2.6/verdex.git] / drivers / ide / ppc / pmac.c
blobe8ef3455ec356e4c9bf835f42532cb62cf57bea9
1 /*
2 * linux/drivers/ide/ide-pmac.c
3 *
4 * Support for IDE interfaces on PowerMacs.
5 * These IDE interfaces are memory-mapped and have a DBDMA channel
6 * for doing DMA.
7 *
8 * Copyright (C) 1998-2003 Paul Mackerras & Ben. Herrenschmidt
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License
12 * as published by the Free Software Foundation; either version
13 * 2 of the License, or (at your option) any later version.
14 *
15 * Some code taken from drivers/ide/ide-dma.c:
16 *
17 * Copyright (c) 1995-1998 Mark Lord
18 *
19 * TODO: - Use pre-calculated (kauai) timing tables all the time and
20 * get rid of the "rounded" tables used previously, so we have the
21 * same table format for all controllers and can then just have one
22 * big table
23 *
24 */
25 #include <linux/config.h>
26 #include <linux/types.h>
27 #include <linux/kernel.h>
28 #include <linux/sched.h>
29 #include <linux/init.h>
30 #include <linux/delay.h>
31 #include <linux/ide.h>
32 #include <linux/notifier.h>
33 #include <linux/reboot.h>
34 #include <linux/pci.h>
35 #include <linux/adb.h>
36 #include <linux/pmu.h>
37 #include <linux/scatterlist.h>
38
39 #include <asm/prom.h>
40 #include <asm/io.h>
41 #include <asm/dbdma.h>
42 #include <asm/ide.h>
43 #include <asm/pci-bridge.h>
44 #include <asm/machdep.h>
45 #include <asm/pmac_feature.h>
46 #include <asm/sections.h>
47 #include <asm/irq.h>
48
49 #ifndef CONFIG_PPC64
50 #include <asm/mediabay.h>
51 #endif
52
53 #include "ide-timing.h"
54
55 #undef IDE_PMAC_DEBUG
56
57 #define DMA_WAIT_TIMEOUT 50
58
59 typedef struct pmac_ide_hwif {
60 unsigned long regbase;
61 int irq;
62 int kind;
63 int aapl_bus_id;
64 unsigned cable_80 : 1;
65 unsigned mediabay : 1;
66 unsigned broken_dma : 1;
67 unsigned broken_dma_warn : 1;
68 struct device_node* node;
69 struct macio_dev *mdev;
70 u32 timings[4];
71 volatile u32 __iomem * *kauai_fcr;
72 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
73 /* Those fields are duplicating what is in hwif. We currently
74 * can't use the hwif ones because of some assumptions that are
75 * beeing done by the generic code about the kind of dma controller
76 * and format of the dma table. This will have to be fixed though.
77 */
78 volatile struct dbdma_regs __iomem * dma_regs;
79 struct dbdma_cmd* dma_table_cpu;
80 #endif
81
82 } pmac_ide_hwif_t;
83
84 static pmac_ide_hwif_t pmac_ide[MAX_HWIFS];
85 static int pmac_ide_count;
86
87 enum {
88 controller_ohare, /* OHare based */
89 controller_heathrow, /* Heathrow/Paddington */
90 controller_kl_ata3, /* KeyLargo ATA-3 */
91 controller_kl_ata4, /* KeyLargo ATA-4 */
92 controller_un_ata6, /* UniNorth2 ATA-6 */
93 controller_k2_ata6, /* K2 ATA-6 */
94 controller_sh_ata6, /* Shasta ATA-6 */
95 };
96
97 static const char* model_name[] = {
98 "OHare ATA", /* OHare based */
99 "Heathrow ATA", /* Heathrow/Paddington */
100 "KeyLargo ATA-3", /* KeyLargo ATA-3 (MDMA only) */
101 "KeyLargo ATA-4", /* KeyLargo ATA-4 (UDMA/66) */
102 "UniNorth ATA-6", /* UniNorth2 ATA-6 (UDMA/100) */
103 "K2 ATA-6", /* K2 ATA-6 (UDMA/100) */
104 "Shasta ATA-6", /* Shasta ATA-6 (UDMA/133) */
105 };
106
107 /*
108 * Extra registers, both 32-bit little-endian
109 */
110 #define IDE_TIMING_CONFIG 0x200
111 #define IDE_INTERRUPT 0x300
112
113 /* Kauai (U2) ATA has different register setup */
114 #define IDE_KAUAI_PIO_CONFIG 0x200
115 #define IDE_KAUAI_ULTRA_CONFIG 0x210
116 #define IDE_KAUAI_POLL_CONFIG 0x220
117
118 /*
119 * Timing configuration register definitions
120 */
121
122 /* Number of IDE_SYSCLK_NS ticks, argument is in nanoseconds */
123 #define SYSCLK_TICKS(t) (((t) + IDE_SYSCLK_NS - 1) / IDE_SYSCLK_NS)
124 #define SYSCLK_TICKS_66(t) (((t) + IDE_SYSCLK_66_NS - 1) / IDE_SYSCLK_66_NS)
125 #define IDE_SYSCLK_NS 30 /* 33Mhz cell */
126 #define IDE_SYSCLK_66_NS 15 /* 66Mhz cell */
127
128 /* 133Mhz cell, found in shasta.
129 * See comments about 100 Mhz Uninorth 2...
130 * Note that PIO_MASK and MDMA_MASK seem to overlap
131 */
132 #define TR_133_PIOREG_PIO_MASK 0xff000fff
133 #define TR_133_PIOREG_MDMA_MASK 0x00fff800
134 #define TR_133_UDMAREG_UDMA_MASK 0x0003ffff
135 #define TR_133_UDMAREG_UDMA_EN 0x00000001
136
137 /* 100Mhz cell, found in Uninorth 2. I don't have much infos about
138 * this one yet, it appears as a pci device (106b/0033) on uninorth
139 * internal PCI bus and it's clock is controlled like gem or fw. It
140 * appears to be an evolution of keylargo ATA4 with a timing register
141 * extended to 2 32bits registers and a similar DBDMA channel. Other
142 * registers seem to exist but I can't tell much about them.
143 *
144 * So far, I'm using pre-calculated tables for this extracted from
145 * the values used by the MacOS X driver.
146 *
147 * The "PIO" register controls PIO and MDMA timings, the "ULTRA"
148 * register controls the UDMA timings. At least, it seems bit 0
149 * of this one enables UDMA vs. MDMA, and bits 4..7 are the
150 * cycle time in units of 10ns. Bits 8..15 are used by I don't
151 * know their meaning yet
152 */
153 #define TR_100_PIOREG_PIO_MASK 0xff000fff
154 #define TR_100_PIOREG_MDMA_MASK 0x00fff000
155 #define TR_100_UDMAREG_UDMA_MASK 0x0000ffff
156 #define TR_100_UDMAREG_UDMA_EN 0x00000001
157
158
159 /* 66Mhz cell, found in KeyLargo. Can do ultra mode 0 to 2 on
160 * 40 connector cable and to 4 on 80 connector one.
161 * Clock unit is 15ns (66Mhz)
162 *
163 * 3 Values can be programmed:
164 * - Write data setup, which appears to match the cycle time. They
165 * also call it DIOW setup.
166 * - Ready to pause time (from spec)
167 * - Address setup. That one is weird. I don't see where exactly
168 * it fits in UDMA cycles, I got it's name from an obscure piece
169 * of commented out code in Darwin. They leave it to 0, we do as
170 * well, despite a comment that would lead to think it has a
171 * min value of 45ns.
172 * Apple also add 60ns to the write data setup (or cycle time ?) on
173 * reads.
174 */
175 #define TR_66_UDMA_MASK 0xfff00000
176 #define TR_66_UDMA_EN 0x00100000 /* Enable Ultra mode for DMA */
177 #define TR_66_UDMA_ADDRSETUP_MASK 0xe0000000 /* Address setup */
178 #define TR_66_UDMA_ADDRSETUP_SHIFT 29
179 #define TR_66_UDMA_RDY2PAUS_MASK 0x1e000000 /* Ready 2 pause time */
180 #define TR_66_UDMA_RDY2PAUS_SHIFT 25
181 #define TR_66_UDMA_WRDATASETUP_MASK 0x01e00000 /* Write data setup time */
182 #define TR_66_UDMA_WRDATASETUP_SHIFT 21
183 #define TR_66_MDMA_MASK 0x000ffc00
184 #define TR_66_MDMA_RECOVERY_MASK 0x000f8000
185 #define TR_66_MDMA_RECOVERY_SHIFT 15
186 #define TR_66_MDMA_ACCESS_MASK 0x00007c00
187 #define TR_66_MDMA_ACCESS_SHIFT 10
188 #define TR_66_PIO_MASK 0x000003ff
189 #define TR_66_PIO_RECOVERY_MASK 0x000003e0
190 #define TR_66_PIO_RECOVERY_SHIFT 5
191 #define TR_66_PIO_ACCESS_MASK 0x0000001f
192 #define TR_66_PIO_ACCESS_SHIFT 0
193
194 /* 33Mhz cell, found in OHare, Heathrow (& Paddington) and KeyLargo
195 * Can do pio & mdma modes, clock unit is 30ns (33Mhz)
196 *
197 * The access time and recovery time can be programmed. Some older
198 * Darwin code base limit OHare to 150ns cycle time. I decided to do
199 * the same here fore safety against broken old hardware ;)
200 * The HalfTick bit, when set, adds half a clock (15ns) to the access
201 * time and removes one from recovery. It's not supported on KeyLargo
202 * implementation afaik. The E bit appears to be set for PIO mode 0 and
203 * is used to reach long timings used in this mode.
204 */
205 #define TR_33_MDMA_MASK 0x003ff800
206 #define TR_33_MDMA_RECOVERY_MASK 0x001f0000
207 #define TR_33_MDMA_RECOVERY_SHIFT 16
208 #define TR_33_MDMA_ACCESS_MASK 0x0000f800
209 #define TR_33_MDMA_ACCESS_SHIFT 11
210 #define TR_33_MDMA_HALFTICK 0x00200000
211 #define TR_33_PIO_MASK 0x000007ff
212 #define TR_33_PIO_E 0x00000400
213 #define TR_33_PIO_RECOVERY_MASK 0x000003e0
214 #define TR_33_PIO_RECOVERY_SHIFT 5
215 #define TR_33_PIO_ACCESS_MASK 0x0000001f
216 #define TR_33_PIO_ACCESS_SHIFT 0
217
218 /*
219 * Interrupt register definitions
220 */
221 #define IDE_INTR_DMA 0x80000000
222 #define IDE_INTR_DEVICE 0x40000000
223
224 /*
225 * FCR Register on Kauai. Not sure what bit 0x4 is ...
226 */
227 #define KAUAI_FCR_UATA_MAGIC 0x00000004
228 #define KAUAI_FCR_UATA_RESET_N 0x00000002
229 #define KAUAI_FCR_UATA_ENABLE 0x00000001
230
231 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
232
233 /* Rounded Multiword DMA timings
234 *
235 * I gave up finding a generic formula for all controller
236 * types and instead, built tables based on timing values
237 * used by Apple in Darwin's implementation.
238 */
239 struct mdma_timings_t {
240 int accessTime;
241 int recoveryTime;
242 int cycleTime;
243 };
244
245 struct mdma_timings_t mdma_timings_33[] =
246 {
247 { 240, 240, 480 },
248 { 180, 180, 360 },
249 { 135, 135, 270 },
250 { 120, 120, 240 },
251 { 105, 105, 210 },
252 { 90, 90, 180 },
253 { 75, 75, 150 },
254 { 75, 45, 120 },
255 { 0, 0, 0 }
256 };
257
258 struct mdma_timings_t mdma_timings_33k[] =
259 {
260 { 240, 240, 480 },
261 { 180, 180, 360 },
262 { 150, 150, 300 },
263 { 120, 120, 240 },
264 { 90, 120, 210 },
265 { 90, 90, 180 },
266 { 90, 60, 150 },
267 { 90, 30, 120 },
268 { 0, 0, 0 }
269 };
270
271 struct mdma_timings_t mdma_timings_66[] =
272 {
273 { 240, 240, 480 },
274 { 180, 180, 360 },
275 { 135, 135, 270 },
276 { 120, 120, 240 },
277 { 105, 105, 210 },
278 { 90, 90, 180 },
279 { 90, 75, 165 },
280 { 75, 45, 120 },
281 { 0, 0, 0 }
282 };
283
284 /* KeyLargo ATA-4 Ultra DMA timings (rounded) */
285 struct {
286 int addrSetup; /* ??? */
287 int rdy2pause;
288 int wrDataSetup;
289 } kl66_udma_timings[] =
290 {
291 { 0, 180, 120 }, /* Mode 0 */
292 { 0, 150, 90 }, /* 1 */
293 { 0, 120, 60 }, /* 2 */
294 { 0, 90, 45 }, /* 3 */
295 { 0, 90, 30 } /* 4 */
296 };
297
298 /* UniNorth 2 ATA/100 timings */
299 struct kauai_timing {
300 int cycle_time;
301 u32 timing_reg;
302 };
303
304 static struct kauai_timing kauai_pio_timings[] =
305 {
306 { 930 , 0x08000fff },
307 { 600 , 0x08000a92 },
308 { 383 , 0x0800060f },
309 { 360 , 0x08000492 },
310 { 330 , 0x0800048f },
311 { 300 , 0x080003cf },
312 { 270 , 0x080003cc },
313 { 240 , 0x0800038b },
314 { 239 , 0x0800030c },
315 { 180 , 0x05000249 },
316 { 120 , 0x04000148 }
317 };
318
319 static struct kauai_timing kauai_mdma_timings[] =
320 {
321 { 1260 , 0x00fff000 },
322 { 480 , 0x00618000 },
323 { 360 , 0x00492000 },
324 { 270 , 0x0038e000 },
325 { 240 , 0x0030c000 },
326 { 210 , 0x002cb000 },
327 { 180 , 0x00249000 },
328 { 150 , 0x00209000 },
329 { 120 , 0x00148000 },
330 { 0 , 0 },
331 };
332
333 static struct kauai_timing kauai_udma_timings[] =
334 {
335 { 120 , 0x000070c0 },
336 { 90 , 0x00005d80 },
337 { 60 , 0x00004a60 },
338 { 45 , 0x00003a50 },
339 { 30 , 0x00002a30 },
340 { 20 , 0x00002921 },
341 { 0 , 0 },
342 };
343
344 static struct kauai_timing shasta_pio_timings[] =
345 {
346 { 930 , 0x08000fff },
347 { 600 , 0x0A000c97 },
348 { 383 , 0x07000712 },
349 { 360 , 0x040003cd },
350 { 330 , 0x040003cd },
351 { 300 , 0x040003cd },
352 { 270 , 0x040003cd },
353 { 240 , 0x040003cd },
354 { 239 , 0x040003cd },
355 { 180 , 0x0400028b },
356 { 120 , 0x0400010a }
357 };
358
359 static struct kauai_timing shasta_mdma_timings[] =
360 {
361 { 1260 , 0x00fff000 },
362 { 480 , 0x00820800 },
363 { 360 , 0x00820800 },
364 { 270 , 0x00820800 },
365 { 240 , 0x00820800 },
366 { 210 , 0x00820800 },
367 { 180 , 0x00820800 },
368 { 150 , 0x0028b000 },
369 { 120 , 0x001ca000 },
370 { 0 , 0 },
371 };
372
373 static struct kauai_timing shasta_udma133_timings[] =
374 {
375 { 120 , 0x00035901, },
376 { 90 , 0x000348b1, },
377 { 60 , 0x00033881, },
378 { 45 , 0x00033861, },
379 { 30 , 0x00033841, },
380 { 20 , 0x00033031, },
381 { 15 , 0x00033021, },
382 { 0 , 0 },
383 };
384
385
386 static inline u32
387 kauai_lookup_timing(struct kauai_timing* table, int cycle_time)
388 {
389 int i;
390
391 for (i=0; table[i].cycle_time; i++)
392 if (cycle_time > table[i+1].cycle_time)
393 return table[i].timing_reg;
394 return 0;
395 }
396
397 /* allow up to 256 DBDMA commands per xfer */
398 #define MAX_DCMDS 256
399
400 /*
401 * Wait 1s for disk to answer on IDE bus after a hard reset
402 * of the device (via GPIO/FCR).
403 *
404 * Some devices seem to "pollute" the bus even after dropping
405 * the BSY bit (typically some combo drives slave on the UDMA
406 * bus) after a hard reset. Since we hard reset all drives on
407 * KeyLargo ATA66, we have to keep that delay around. I may end
408 * up not hard resetting anymore on these and keep the delay only
409 * for older interfaces instead (we have to reset when coming
410 * from MacOS...) --BenH.
411 */
412 #define IDE_WAKEUP_DELAY (1*HZ)
413
414 static void pmac_ide_setup_dma(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif);
415 static int pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq);
416 static int pmac_ide_tune_chipset(ide_drive_t *drive, u8 speed);
417 static void pmac_ide_tuneproc(ide_drive_t *drive, u8 pio);
418 static void pmac_ide_selectproc(ide_drive_t *drive);
419 static void pmac_ide_kauai_selectproc(ide_drive_t *drive);
420
421 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
422
423 /*
424 * N.B. this can't be an initfunc, because the media-bay task can
425 * call ide_[un]register at any time.
426 */
427 void
428 pmac_ide_init_hwif_ports(hw_regs_t *hw,
429 unsigned long data_port, unsigned long ctrl_port,
430 int *irq)
431 {
432 int i, ix;
433
434 if (data_port == 0)
435 return;
436
437 for (ix = 0; ix < MAX_HWIFS; ++ix)
438 if (data_port == pmac_ide[ix].regbase)
439 break;
440
441 if (ix >= MAX_HWIFS) {
442 /* Probably a PCI interface... */
443 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; ++i)
444 hw->io_ports[i] = data_port + i - IDE_DATA_OFFSET;
445 hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
446 return;
447 }
448
449 for (i = 0; i < 8; ++i)
450 hw->io_ports[i] = data_port + i * 0x10;
451 hw->io_ports[8] = data_port + 0x160;
452
453 if (irq != NULL)
454 *irq = pmac_ide[ix].irq;
455
456 hw->dev = &pmac_ide[ix].mdev->ofdev.dev;
457 }
458
459 #define PMAC_IDE_REG(x) ((void __iomem *)(IDE_DATA_REG+(x)))
460
461 /*
462 * Apply the timings of the proper unit (master/slave) to the shared
463 * timing register when selecting that unit. This version is for
464 * ASICs with a single timing register
465 */
466 static void
467 pmac_ide_selectproc(ide_drive_t *drive)
468 {
469 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
470
471 if (pmif == NULL)
472 return;
473
474 if (drive->select.b.unit & 0x01)
475 writel(pmif->timings[1], PMAC_IDE_REG(IDE_TIMING_CONFIG));
476 else
477 writel(pmif->timings[0], PMAC_IDE_REG(IDE_TIMING_CONFIG));
478 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
479 }
480
481 /*
482 * Apply the timings of the proper unit (master/slave) to the shared
483 * timing register when selecting that unit. This version is for
484 * ASICs with a dual timing register (Kauai)
485 */
486 static void
487 pmac_ide_kauai_selectproc(ide_drive_t *drive)
488 {
489 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
490
491 if (pmif == NULL)
492 return;
493
494 if (drive->select.b.unit & 0x01) {
495 writel(pmif->timings[1], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
496 writel(pmif->timings[3], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
497 } else {
498 writel(pmif->timings[0], PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
499 writel(pmif->timings[2], PMAC_IDE_REG(IDE_KAUAI_ULTRA_CONFIG));
500 }
501 (void)readl(PMAC_IDE_REG(IDE_KAUAI_PIO_CONFIG));
502 }
503
504 /*
505 * Force an update of controller timing values for a given drive
506 */
507 static void
508 pmac_ide_do_update_timings(ide_drive_t *drive)
509 {
510 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
511
512 if (pmif == NULL)
513 return;
514
515 if (pmif->kind == controller_sh_ata6 ||
516 pmif->kind == controller_un_ata6 ||
517 pmif->kind == controller_k2_ata6)
518 pmac_ide_kauai_selectproc(drive);
519 else
520 pmac_ide_selectproc(drive);
521 }
522
523 static void
524 pmac_outbsync(ide_drive_t *drive, u8 value, unsigned long port)
525 {
526 u32 tmp;
527
528 writeb(value, (void __iomem *) port);
529 tmp = readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
530 }
531
532 /*
533 * Send the SET_FEATURE IDE command to the drive and update drive->id with
534 * the new state. We currently don't use the generic routine as it used to
535 * cause various trouble, especially with older mediabays.
536 * This code is sometimes triggering a spurrious interrupt though, I need
537 * to sort that out sooner or later and see if I can finally get the
538 * common version to work properly in all cases
539 */
540 static int
541 pmac_ide_do_setfeature(ide_drive_t *drive, u8 command)
542 {
543 ide_hwif_t *hwif = HWIF(drive);
544 int result = 1;
545
546 disable_irq_nosync(hwif->irq);
547 udelay(1);
548 SELECT_DRIVE(drive);
549 SELECT_MASK(drive, 0);
550 udelay(1);
551 /* Get rid of pending error state */
552 (void) hwif->INB(IDE_STATUS_REG);
553 /* Timeout bumped for some powerbooks */
554 if (wait_for_ready(drive, 2000)) {
555 /* Timeout bumped for some powerbooks */
556 printk(KERN_ERR "%s: pmac_ide_do_setfeature disk not ready "
557 "before SET_FEATURE!\n", drive->name);
558 goto out;
559 }
560 udelay(10);
561 hwif->OUTB(drive->ctl | 2, IDE_CONTROL_REG);
562 hwif->OUTB(command, IDE_NSECTOR_REG);
563 hwif->OUTB(SETFEATURES_XFER, IDE_FEATURE_REG);
564 hwif->OUTBSYNC(drive, WIN_SETFEATURES, IDE_COMMAND_REG);
565 udelay(1);
566 /* Timeout bumped for some powerbooks */
567 result = wait_for_ready(drive, 2000);
568 hwif->OUTB(drive->ctl, IDE_CONTROL_REG);
569 if (result)
570 printk(KERN_ERR "%s: pmac_ide_do_setfeature disk not ready "
571 "after SET_FEATURE !\n", drive->name);
572 out:
573 SELECT_MASK(drive, 0);
574 if (result == 0) {
575 drive->id->dma_ultra &= ~0xFF00;
576 drive->id->dma_mword &= ~0x0F00;
577 drive->id->dma_1word &= ~0x0F00;
578 switch(command) {
579 case XFER_UDMA_7:
580 drive->id->dma_ultra |= 0x8080; break;
581 case XFER_UDMA_6:
582 drive->id->dma_ultra |= 0x4040; break;
583 case XFER_UDMA_5:
584 drive->id->dma_ultra |= 0x2020; break;
585 case XFER_UDMA_4:
586 drive->id->dma_ultra |= 0x1010; break;
587 case XFER_UDMA_3:
588 drive->id->dma_ultra |= 0x0808; break;
589 case XFER_UDMA_2:
590 drive->id->dma_ultra |= 0x0404; break;
591 case XFER_UDMA_1:
592 drive->id->dma_ultra |= 0x0202; break;
593 case XFER_UDMA_0:
594 drive->id->dma_ultra |= 0x0101; break;
595 case XFER_MW_DMA_2:
596 drive->id->dma_mword |= 0x0404; break;
597 case XFER_MW_DMA_1:
598 drive->id->dma_mword |= 0x0202; break;
599 case XFER_MW_DMA_0:
600 drive->id->dma_mword |= 0x0101; break;
601 case XFER_SW_DMA_2:
602 drive->id->dma_1word |= 0x0404; break;
603 case XFER_SW_DMA_1:
604 drive->id->dma_1word |= 0x0202; break;
605 case XFER_SW_DMA_0:
606 drive->id->dma_1word |= 0x0101; break;
607 default: break;
608 }
609 }
610 enable_irq(hwif->irq);
611 return result;
612 }
613
614 /*
615 * Old tuning functions (called on hdparm -p), sets up drive PIO timings
616 */
617 static void
618 pmac_ide_tuneproc(ide_drive_t *drive, u8 pio)
619 {
620 ide_pio_data_t d;
621 u32 *timings;
622 unsigned accessTicks, recTicks;
623 unsigned accessTime, recTime;
624 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
625
626 if (pmif == NULL)
627 return;
628
629 /* which drive is it ? */
630 timings = &pmif->timings[drive->select.b.unit & 0x01];
631
632 pio = ide_get_best_pio_mode(drive, pio, 4, &d);
633
634 switch (pmif->kind) {
635 case controller_sh_ata6: {
636 /* 133Mhz cell */
637 u32 tr = kauai_lookup_timing(shasta_pio_timings, d.cycle_time);
638 if (tr == 0)
639 return;
640 *timings = ((*timings) & ~TR_133_PIOREG_PIO_MASK) | tr;
641 break;
642 }
643 case controller_un_ata6:
644 case controller_k2_ata6: {
645 /* 100Mhz cell */
646 u32 tr = kauai_lookup_timing(kauai_pio_timings, d.cycle_time);
647 if (tr == 0)
648 return;
649 *timings = ((*timings) & ~TR_100_PIOREG_PIO_MASK) | tr;
650 break;
651 }
652 case controller_kl_ata4:
653 /* 66Mhz cell */
654 recTime = d.cycle_time - ide_pio_timings[pio].active_time
655 - ide_pio_timings[pio].setup_time;
656 recTime = max(recTime, 150U);
657 accessTime = ide_pio_timings[pio].active_time;
658 accessTime = max(accessTime, 150U);
659 accessTicks = SYSCLK_TICKS_66(accessTime);
660 accessTicks = min(accessTicks, 0x1fU);
661 recTicks = SYSCLK_TICKS_66(recTime);
662 recTicks = min(recTicks, 0x1fU);
663 *timings = ((*timings) & ~TR_66_PIO_MASK) |
664 (accessTicks << TR_66_PIO_ACCESS_SHIFT) |
665 (recTicks << TR_66_PIO_RECOVERY_SHIFT);
666 break;
667 default: {
668 /* 33Mhz cell */
669 int ebit = 0;
670 recTime = d.cycle_time - ide_pio_timings[pio].active_time
671 - ide_pio_timings[pio].setup_time;
672 recTime = max(recTime, 150U);
673 accessTime = ide_pio_timings[pio].active_time;
674 accessTime = max(accessTime, 150U);
675 accessTicks = SYSCLK_TICKS(accessTime);
676 accessTicks = min(accessTicks, 0x1fU);
677 accessTicks = max(accessTicks, 4U);
678 recTicks = SYSCLK_TICKS(recTime);
679 recTicks = min(recTicks, 0x1fU);
680 recTicks = max(recTicks, 5U) - 4;
681 if (recTicks > 9) {
682 recTicks--; /* guess, but it's only for PIO0, so... */
683 ebit = 1;
684 }
685 *timings = ((*timings) & ~TR_33_PIO_MASK) |
686 (accessTicks << TR_33_PIO_ACCESS_SHIFT) |
687 (recTicks << TR_33_PIO_RECOVERY_SHIFT);
688 if (ebit)
689 *timings |= TR_33_PIO_E;
690 break;
691 }
692 }
693
694 #ifdef IDE_PMAC_DEBUG
695 printk(KERN_ERR "%s: Set PIO timing for mode %d, reg: 0x%08x\n",
696 drive->name, pio, *timings);
697 #endif
698
699 if (drive->select.all == HWIF(drive)->INB(IDE_SELECT_REG))
700 pmac_ide_do_update_timings(drive);
701 }
702
703 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
704
705 /*
706 * Calculate KeyLargo ATA/66 UDMA timings
707 */
708 static int
709 set_timings_udma_ata4(u32 *timings, u8 speed)
710 {
711 unsigned rdyToPauseTicks, wrDataSetupTicks, addrTicks;
712
713 if (speed > XFER_UDMA_4)
714 return 1;
715
716 rdyToPauseTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].rdy2pause);
717 wrDataSetupTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].wrDataSetup);
718 addrTicks = SYSCLK_TICKS_66(kl66_udma_timings[speed & 0xf].addrSetup);
719
720 *timings = ((*timings) & ~(TR_66_UDMA_MASK | TR_66_MDMA_MASK)) |
721 (wrDataSetupTicks << TR_66_UDMA_WRDATASETUP_SHIFT) |
722 (rdyToPauseTicks << TR_66_UDMA_RDY2PAUS_SHIFT) |
723 (addrTicks <<TR_66_UDMA_ADDRSETUP_SHIFT) |
724 TR_66_UDMA_EN;
725 #ifdef IDE_PMAC_DEBUG
726 printk(KERN_ERR "ide_pmac: Set UDMA timing for mode %d, reg: 0x%08x\n",
727 speed & 0xf, *timings);
728 #endif
729
730 return 0;
731 }
732
733 /*
734 * Calculate Kauai ATA/100 UDMA timings
735 */
736 static int
737 set_timings_udma_ata6(u32 *pio_timings, u32 *ultra_timings, u8 speed)
738 {
739 struct ide_timing *t = ide_timing_find_mode(speed);
740 u32 tr;
741
742 if (speed > XFER_UDMA_5 || t == NULL)
743 return 1;
744 tr = kauai_lookup_timing(kauai_udma_timings, (int)t->udma);
745 if (tr == 0)
746 return 1;
747 *ultra_timings = ((*ultra_timings) & ~TR_100_UDMAREG_UDMA_MASK) | tr;
748 *ultra_timings = (*ultra_timings) | TR_100_UDMAREG_UDMA_EN;
749
750 return 0;
751 }
752
753 /*
754 * Calculate Shasta ATA/133 UDMA timings
755 */
756 static int
757 set_timings_udma_shasta(u32 *pio_timings, u32 *ultra_timings, u8 speed)
758 {
759 struct ide_timing *t = ide_timing_find_mode(speed);
760 u32 tr;
761
762 if (speed > XFER_UDMA_6 || t == NULL)
763 return 1;
764 tr = kauai_lookup_timing(shasta_udma133_timings, (int)t->udma);
765 if (tr == 0)
766 return 1;
767 *ultra_timings = ((*ultra_timings) & ~TR_133_UDMAREG_UDMA_MASK) | tr;
768 *ultra_timings = (*ultra_timings) | TR_133_UDMAREG_UDMA_EN;
769
770 return 0;
771 }
772
773 /*
774 * Calculate MDMA timings for all cells
775 */
776 static int
777 set_timings_mdma(ide_drive_t *drive, int intf_type, u32 *timings, u32 *timings2,
778 u8 speed, int drive_cycle_time)
779 {
780 int cycleTime, accessTime = 0, recTime = 0;
781 unsigned accessTicks, recTicks;
782 struct mdma_timings_t* tm = NULL;
783 int i;
784
785 /* Get default cycle time for mode */
786 switch(speed & 0xf) {
787 case 0: cycleTime = 480; break;
788 case 1: cycleTime = 150; break;
789 case 2: cycleTime = 120; break;
790 default:
791 return 1;
792 }
793 /* Adjust for drive */
794 if (drive_cycle_time && drive_cycle_time > cycleTime)
795 cycleTime = drive_cycle_time;
796 /* OHare limits according to some old Apple sources */
797 if ((intf_type == controller_ohare) && (cycleTime < 150))
798 cycleTime = 150;
799 /* Get the proper timing array for this controller */
800 switch(intf_type) {
801 case controller_sh_ata6:
802 case controller_un_ata6:
803 case controller_k2_ata6:
804 break;
805 case controller_kl_ata4:
806 tm = mdma_timings_66;
807 break;
808 case controller_kl_ata3:
809 tm = mdma_timings_33k;
810 break;
811 default:
812 tm = mdma_timings_33;
813 break;
814 }
815 if (tm != NULL) {
816 /* Lookup matching access & recovery times */
817 i = -1;
818 for (;;) {
819 if (tm[i+1].cycleTime < cycleTime)
820 break;
821 i++;
822 }
823 if (i < 0)
824 return 1;
825 cycleTime = tm[i].cycleTime;
826 accessTime = tm[i].accessTime;
827 recTime = tm[i].recoveryTime;
828
829 #ifdef IDE_PMAC_DEBUG
830 printk(KERN_ERR "%s: MDMA, cycleTime: %d, accessTime: %d, recTime: %d\n",
831 drive->name, cycleTime, accessTime, recTime);
832 #endif
833 }
834 switch(intf_type) {
835 case controller_sh_ata6: {
836 /* 133Mhz cell */
837 u32 tr = kauai_lookup_timing(shasta_mdma_timings, cycleTime);
838 if (tr == 0)
839 return 1;
840 *timings = ((*timings) & ~TR_133_PIOREG_MDMA_MASK) | tr;
841 *timings2 = (*timings2) & ~TR_133_UDMAREG_UDMA_EN;
842 }
843 case controller_un_ata6:
844 case controller_k2_ata6: {
845 /* 100Mhz cell */
846 u32 tr = kauai_lookup_timing(kauai_mdma_timings, cycleTime);
847 if (tr == 0)
848 return 1;
849 *timings = ((*timings) & ~TR_100_PIOREG_MDMA_MASK) | tr;
850 *timings2 = (*timings2) & ~TR_100_UDMAREG_UDMA_EN;
851 }
852 break;
853 case controller_kl_ata4:
854 /* 66Mhz cell */
855 accessTicks = SYSCLK_TICKS_66(accessTime);
856 accessTicks = min(accessTicks, 0x1fU);
857 accessTicks = max(accessTicks, 0x1U);
858 recTicks = SYSCLK_TICKS_66(recTime);
859 recTicks = min(recTicks, 0x1fU);
860 recTicks = max(recTicks, 0x3U);
861 /* Clear out mdma bits and disable udma */
862 *timings = ((*timings) & ~(TR_66_MDMA_MASK | TR_66_UDMA_MASK)) |
863 (accessTicks << TR_66_MDMA_ACCESS_SHIFT) |
864 (recTicks << TR_66_MDMA_RECOVERY_SHIFT);
865 break;
866 case controller_kl_ata3:
867 /* 33Mhz cell on KeyLargo */
868 accessTicks = SYSCLK_TICKS(accessTime);
869 accessTicks = max(accessTicks, 1U);
870 accessTicks = min(accessTicks, 0x1fU);
871 accessTime = accessTicks * IDE_SYSCLK_NS;
872 recTicks = SYSCLK_TICKS(recTime);
873 recTicks = max(recTicks, 1U);
874 recTicks = min(recTicks, 0x1fU);
875 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
876 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
877 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
878 break;
879 default: {
880 /* 33Mhz cell on others */
881 int halfTick = 0;
882 int origAccessTime = accessTime;
883 int origRecTime = recTime;
884
885 accessTicks = SYSCLK_TICKS(accessTime);
886 accessTicks = max(accessTicks, 1U);
887 accessTicks = min(accessTicks, 0x1fU);
888 accessTime = accessTicks * IDE_SYSCLK_NS;
889 recTicks = SYSCLK_TICKS(recTime);
890 recTicks = max(recTicks, 2U) - 1;
891 recTicks = min(recTicks, 0x1fU);
892 recTime = (recTicks + 1) * IDE_SYSCLK_NS;
893 if ((accessTicks > 1) &&
894 ((accessTime - IDE_SYSCLK_NS/2) >= origAccessTime) &&
895 ((recTime - IDE_SYSCLK_NS/2) >= origRecTime)) {
896 halfTick = 1;
897 accessTicks--;
898 }
899 *timings = ((*timings) & ~TR_33_MDMA_MASK) |
900 (accessTicks << TR_33_MDMA_ACCESS_SHIFT) |
901 (recTicks << TR_33_MDMA_RECOVERY_SHIFT);
902 if (halfTick)
903 *timings |= TR_33_MDMA_HALFTICK;
904 }
905 }
906 #ifdef IDE_PMAC_DEBUG
907 printk(KERN_ERR "%s: Set MDMA timing for mode %d, reg: 0x%08x\n",
908 drive->name, speed & 0xf, *timings);
909 #endif
910 return 0;
911 }
912 #endif /* #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC */
913
914 /*
915 * Speedproc. This function is called by the core to set any of the standard
916 * timing (PIO, MDMA or UDMA) to both the drive and the controller.
917 * You may notice we don't use this function on normal "dma check" operation,
918 * our dedicated function is more precise as it uses the drive provided
919 * cycle time value. We should probably fix this one to deal with that too...
920 */
921 static int
922 pmac_ide_tune_chipset (ide_drive_t *drive, byte speed)
923 {
924 int unit = (drive->select.b.unit & 0x01);
925 int ret = 0;
926 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
927 u32 *timings, *timings2;
928
929 if (pmif == NULL)
930 return 1;
931
932 timings = &pmif->timings[unit];
933 timings2 = &pmif->timings[unit+2];
934
935 switch(speed) {
936 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
937 case XFER_UDMA_6:
938 if (pmif->kind != controller_sh_ata6)
939 return 1;
940 case XFER_UDMA_5:
941 if (pmif->kind != controller_un_ata6 &&
942 pmif->kind != controller_k2_ata6 &&
943 pmif->kind != controller_sh_ata6)
944 return 1;
945 case XFER_UDMA_4:
946 case XFER_UDMA_3:
947 if (HWIF(drive)->udma_four == 0)
948 return 1;
949 case XFER_UDMA_2:
950 case XFER_UDMA_1:
951 case XFER_UDMA_0:
952 if (pmif->kind == controller_kl_ata4)
953 ret = set_timings_udma_ata4(timings, speed);
954 else if (pmif->kind == controller_un_ata6
955 || pmif->kind == controller_k2_ata6)
956 ret = set_timings_udma_ata6(timings, timings2, speed);
957 else if (pmif->kind == controller_sh_ata6)
958 ret = set_timings_udma_shasta(timings, timings2, speed);
959 else
960 ret = 1;
961 break;
962 case XFER_MW_DMA_2:
963 case XFER_MW_DMA_1:
964 case XFER_MW_DMA_0:
965 ret = set_timings_mdma(drive, pmif->kind, timings, timings2, speed, 0);
966 break;
967 case XFER_SW_DMA_2:
968 case XFER_SW_DMA_1:
969 case XFER_SW_DMA_0:
970 return 1;
971 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
972 case XFER_PIO_4:
973 case XFER_PIO_3:
974 case XFER_PIO_2:
975 case XFER_PIO_1:
976 case XFER_PIO_0:
977 pmac_ide_tuneproc(drive, speed & 0x07);
978 break;
979 default:
980 ret = 1;
981 }
982 if (ret)
983 return ret;
984
985 ret = pmac_ide_do_setfeature(drive, speed);
986 if (ret)
987 return ret;
988
989 pmac_ide_do_update_timings(drive);
990 drive->current_speed = speed;
991
992 return 0;
993 }
994
995 /*
996 * Blast some well known "safe" values to the timing registers at init or
997 * wakeup from sleep time, before we do real calculation
998 */
999 static void
1000 sanitize_timings(pmac_ide_hwif_t *pmif)
1001 {
1002 unsigned int value, value2 = 0;
1003
1004 switch(pmif->kind) {
1005 case controller_sh_ata6:
1006 value = 0x0a820c97;
1007 value2 = 0x00033031;
1008 break;
1009 case controller_un_ata6:
1010 case controller_k2_ata6:
1011 value = 0x08618a92;
1012 value2 = 0x00002921;
1013 break;
1014 case controller_kl_ata4:
1015 value = 0x0008438c;
1016 break;
1017 case controller_kl_ata3:
1018 value = 0x00084526;
1019 break;
1020 case controller_heathrow:
1021 case controller_ohare:
1022 default:
1023 value = 0x00074526;
1024 break;
1025 }
1026 pmif->timings[0] = pmif->timings[1] = value;
1027 pmif->timings[2] = pmif->timings[3] = value2;
1028 }
1029
1030 unsigned long
1031 pmac_ide_get_base(int index)
1032 {
1033 return pmac_ide[index].regbase;
1034 }
1035
1036 int
1037 pmac_ide_check_base(unsigned long base)
1038 {
1039 int ix;
1040
1041 for (ix = 0; ix < MAX_HWIFS; ++ix)
1042 if (base == pmac_ide[ix].regbase)
1043 return ix;
1044 return -1;
1045 }
1046
1047 int
1048 pmac_ide_get_irq(unsigned long base)
1049 {
1050 int ix;
1051
1052 for (ix = 0; ix < MAX_HWIFS; ++ix)
1053 if (base == pmac_ide[ix].regbase)
1054 return pmac_ide[ix].irq;
1055 return 0;
1056 }
1057
1058 static int ide_majors[] = { 3, 22, 33, 34, 56, 57 };
1059
1060 dev_t __init
1061 pmac_find_ide_boot(char *bootdevice, int n)
1062 {
1063 int i;
1064
1065 /*
1066 * Look through the list of IDE interfaces for this one.
1067 */
1068 for (i = 0; i < pmac_ide_count; ++i) {
1069 char *name;
1070 if (!pmac_ide[i].node || !pmac_ide[i].node->full_name)
1071 continue;
1072 name = pmac_ide[i].node->full_name;
1073 if (memcmp(name, bootdevice, n) == 0 && name[n] == 0) {
1074 /* XXX should cope with the 2nd drive as well... */
1075 return MKDEV(ide_majors[i], 0);
1076 }
1077 }
1078
1079 return 0;
1080 }
1081
1082 /* Suspend call back, should be called after the child devices
1083 * have actually been suspended
1084 */
1085 static int
1086 pmac_ide_do_suspend(ide_hwif_t *hwif)
1087 {
1088 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1089
1090 /* We clear the timings */
1091 pmif->timings[0] = 0;
1092 pmif->timings[1] = 0;
1093
1094 disable_irq(pmif->irq);
1095
1096 /* The media bay will handle itself just fine */
1097 if (pmif->mediabay)
1098 return 0;
1099
1100 /* Kauai has bus control FCRs directly here */
1101 if (pmif->kauai_fcr) {
1102 u32 fcr = readl(pmif->kauai_fcr);
1103 fcr &= ~(KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE);
1104 writel(fcr, pmif->kauai_fcr);
1105 }
1106
1107 /* Disable the bus on older machines and the cell on kauai */
1108 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id,
1109 0);
1110
1111 return 0;
1112 }
1113
1114 /* Resume call back, should be called before the child devices
1115 * are resumed
1116 */
1117 static int
1118 pmac_ide_do_resume(ide_hwif_t *hwif)
1119 {
1120 pmac_ide_hwif_t *pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1121
1122 /* Hard reset & re-enable controller (do we really need to reset ? -BenH) */
1123 if (!pmif->mediabay) {
1124 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 1);
1125 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, pmif->node, pmif->aapl_bus_id, 1);
1126 msleep(10);
1127 ppc_md.feature_call(PMAC_FTR_IDE_RESET, pmif->node, pmif->aapl_bus_id, 0);
1128
1129 /* Kauai has it different */
1130 if (pmif->kauai_fcr) {
1131 u32 fcr = readl(pmif->kauai_fcr);
1132 fcr |= KAUAI_FCR_UATA_RESET_N | KAUAI_FCR_UATA_ENABLE;
1133 writel(fcr, pmif->kauai_fcr);
1134 }
1135
1136 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
1137 }
1138
1139 /* Sanitize drive timings */
1140 sanitize_timings(pmif);
1141
1142 enable_irq(pmif->irq);
1143
1144 return 0;
1145 }
1146
1147 /*
1148 * Setup, register & probe an IDE channel driven by this driver, this is
1149 * called by one of the 2 probe functions (macio or PCI). Note that a channel
1150 * that ends up beeing free of any device is not kept around by this driver
1151 * (it is kept in 2.4). This introduce an interface numbering change on some
1152 * rare machines unfortunately, but it's better this way.
1153 */
1154 static int
1155 pmac_ide_setup_device(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif)
1156 {
1157 struct device_node *np = pmif->node;
1158 int *bidp;
1159
1160 pmif->cable_80 = 0;
1161 pmif->broken_dma = pmif->broken_dma_warn = 0;
1162 if (device_is_compatible(np, "shasta-ata"))
1163 pmif->kind = controller_sh_ata6;
1164 else if (device_is_compatible(np, "kauai-ata"))
1165 pmif->kind = controller_un_ata6;
1166 else if (device_is_compatible(np, "K2-UATA"))
1167 pmif->kind = controller_k2_ata6;
1168 else if (device_is_compatible(np, "keylargo-ata")) {
1169 if (strcmp(np->name, "ata-4") == 0)
1170 pmif->kind = controller_kl_ata4;
1171 else
1172 pmif->kind = controller_kl_ata3;
1173 } else if (device_is_compatible(np, "heathrow-ata"))
1174 pmif->kind = controller_heathrow;
1175 else {
1176 pmif->kind = controller_ohare;
1177 pmif->broken_dma = 1;
1178 }
1179
1180 bidp = (int *)get_property(np, "AAPL,bus-id", NULL);
1181 pmif->aapl_bus_id = bidp ? *bidp : 0;
1182
1183 /* Get cable type from device-tree */
1184 if (pmif->kind == controller_kl_ata4 || pmif->kind == controller_un_ata6
1185 || pmif->kind == controller_k2_ata6
1186 || pmif->kind == controller_sh_ata6) {
1187 char* cable = get_property(np, "cable-type", NULL);
1188 if (cable && !strncmp(cable, "80-", 3))
1189 pmif->cable_80 = 1;
1190 }
1191 /* G5's seem to have incorrect cable type in device-tree. Let's assume
1192 * they have a 80 conductor cable, this seem to be always the case unless
1193 * the user mucked around
1194 */
1195 if (device_is_compatible(np, "K2-UATA") ||
1196 device_is_compatible(np, "shasta-ata"))
1197 pmif->cable_80 = 1;
1198
1199 /* On Kauai-type controllers, we make sure the FCR is correct */
1200 if (pmif->kauai_fcr)
1201 writel(KAUAI_FCR_UATA_MAGIC |
1202 KAUAI_FCR_UATA_RESET_N |
1203 KAUAI_FCR_UATA_ENABLE, pmif->kauai_fcr);
1204
1205 pmif->mediabay = 0;
1206
1207 /* Make sure we have sane timings */
1208 sanitize_timings(pmif);
1209
1210 #ifndef CONFIG_PPC64
1211 /* XXX FIXME: Media bay stuff need re-organizing */
1212 if (np->parent && np->parent->name
1213 && strcasecmp(np->parent->name, "media-bay") == 0) {
1214 #ifdef CONFIG_PMAC_MEDIABAY
1215 media_bay_set_ide_infos(np->parent, pmif->regbase, pmif->irq, hwif->index);
1216 #endif /* CONFIG_PMAC_MEDIABAY */
1217 pmif->mediabay = 1;
1218 if (!bidp)
1219 pmif->aapl_bus_id = 1;
1220 } else if (pmif->kind == controller_ohare) {
1221 /* The code below is having trouble on some ohare machines
1222 * (timing related ?). Until I can put my hand on one of these
1223 * units, I keep the old way
1224 */
1225 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, 0, 1);
1226 } else
1227 #endif
1228 {
1229 /* This is necessary to enable IDE when net-booting */
1230 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 1);
1231 ppc_md.feature_call(PMAC_FTR_IDE_ENABLE, np, pmif->aapl_bus_id, 1);
1232 msleep(10);
1233 ppc_md.feature_call(PMAC_FTR_IDE_RESET, np, pmif->aapl_bus_id, 0);
1234 msleep(jiffies_to_msecs(IDE_WAKEUP_DELAY));
1235 }
1236
1237 /* Setup MMIO ops */
1238 default_hwif_mmiops(hwif);
1239 hwif->OUTBSYNC = pmac_outbsync;
1240
1241 /* Tell common code _not_ to mess with resources */
1242 hwif->mmio = 2;
1243 hwif->hwif_data = pmif;
1244 pmac_ide_init_hwif_ports(&hwif->hw, pmif->regbase, 0, &hwif->irq);
1245 memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->io_ports));
1246 hwif->chipset = ide_pmac;
1247 hwif->noprobe = !hwif->io_ports[IDE_DATA_OFFSET] || pmif->mediabay;
1248 hwif->hold = pmif->mediabay;
1249 hwif->udma_four = pmif->cable_80;
1250 hwif->drives[0].unmask = 1;
1251 hwif->drives[1].unmask = 1;
1252 hwif->tuneproc = pmac_ide_tuneproc;
1253 if (pmif->kind == controller_un_ata6
1254 || pmif->kind == controller_k2_ata6
1255 || pmif->kind == controller_sh_ata6)
1256 hwif->selectproc = pmac_ide_kauai_selectproc;
1257 else
1258 hwif->selectproc = pmac_ide_selectproc;
1259 hwif->speedproc = pmac_ide_tune_chipset;
1260
1261 printk(KERN_INFO "ide%d: Found Apple %s controller, bus ID %d%s, irq %d\n",
1262 hwif->index, model_name[pmif->kind], pmif->aapl_bus_id,
1263 pmif->mediabay ? " (mediabay)" : "", hwif->irq);
1264
1265 #ifdef CONFIG_PMAC_MEDIABAY
1266 if (pmif->mediabay && check_media_bay_by_base(pmif->regbase, MB_CD) == 0)
1267 hwif->noprobe = 0;
1268 #endif /* CONFIG_PMAC_MEDIABAY */
1269
1270 hwif->sg_max_nents = MAX_DCMDS;
1271
1272 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1273 /* has a DBDMA controller channel */
1274 if (pmif->dma_regs)
1275 pmac_ide_setup_dma(pmif, hwif);
1276 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1277
1278 /* We probe the hwif now */
1279 probe_hwif_init(hwif);
1280
1281 return 0;
1282 }
1283
1284 /*
1285 * Attach to a macio probed interface
1286 */
1287 static int __devinit
1288 pmac_ide_macio_attach(struct macio_dev *mdev, const struct of_device_id *match)
1289 {
1290 void __iomem *base;
1291 unsigned long regbase;
1292 int irq;
1293 ide_hwif_t *hwif;
1294 pmac_ide_hwif_t *pmif;
1295 int i, rc;
1296
1297 i = 0;
1298 while (i < MAX_HWIFS && (ide_hwifs[i].io_ports[IDE_DATA_OFFSET] != 0
1299 || pmac_ide[i].node != NULL))
1300 ++i;
1301 if (i >= MAX_HWIFS) {
1302 printk(KERN_ERR "ide-pmac: MacIO interface attach with no slot\n");
1303 printk(KERN_ERR " %s\n", mdev->ofdev.node->full_name);
1304 return -ENODEV;
1305 }
1306
1307 pmif = &pmac_ide[i];
1308 hwif = &ide_hwifs[i];
1309
1310 if (macio_resource_count(mdev) == 0) {
1311 printk(KERN_WARNING "ide%d: no address for %s\n",
1312 i, mdev->ofdev.node->full_name);
1313 return -ENXIO;
1314 }
1315
1316 /* Request memory resource for IO ports */
1317 if (macio_request_resource(mdev, 0, "ide-pmac (ports)")) {
1318 printk(KERN_ERR "ide%d: can't request mmio resource !\n", i);
1319 return -EBUSY;
1320 }
1321
1322 /* XXX This is bogus. Should be fixed in the registry by checking
1323 * the kind of host interrupt controller, a bit like gatwick
1324 * fixes in irq.c. That works well enough for the single case
1325 * where that happens though...
1326 */
1327 if (macio_irq_count(mdev) == 0) {
1328 printk(KERN_WARNING "ide%d: no intrs for device %s, using 13\n",
1329 i, mdev->ofdev.node->full_name);
1330 irq = 13;
1331 } else
1332 irq = macio_irq(mdev, 0);
1333
1334 base = ioremap(macio_resource_start(mdev, 0), 0x400);
1335 regbase = (unsigned long) base;
1336
1337 hwif->pci_dev = mdev->bus->pdev;
1338 hwif->gendev.parent = &mdev->ofdev.dev;
1339
1340 pmif->mdev = mdev;
1341 pmif->node = mdev->ofdev.node;
1342 pmif->regbase = regbase;
1343 pmif->irq = irq;
1344 pmif->kauai_fcr = NULL;
1345 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1346 if (macio_resource_count(mdev) >= 2) {
1347 if (macio_request_resource(mdev, 1, "ide-pmac (dma)"))
1348 printk(KERN_WARNING "ide%d: can't request DMA resource !\n", i);
1349 else
1350 pmif->dma_regs = ioremap(macio_resource_start(mdev, 1), 0x1000);
1351 } else
1352 pmif->dma_regs = NULL;
1353 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1354 dev_set_drvdata(&mdev->ofdev.dev, hwif);
1355
1356 rc = pmac_ide_setup_device(pmif, hwif);
1357 if (rc != 0) {
1358 /* The inteface is released to the common IDE layer */
1359 dev_set_drvdata(&mdev->ofdev.dev, NULL);
1360 iounmap(base);
1361 if (pmif->dma_regs)
1362 iounmap(pmif->dma_regs);
1363 memset(pmif, 0, sizeof(*pmif));
1364 macio_release_resource(mdev, 0);
1365 if (pmif->dma_regs)
1366 macio_release_resource(mdev, 1);
1367 }
1368
1369 return rc;
1370 }
1371
1372 static int
1373 pmac_ide_macio_suspend(struct macio_dev *mdev, pm_message_t state)
1374 {
1375 ide_hwif_t *hwif = (ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1376 int rc = 0;
1377
1378 if (state.event != mdev->ofdev.dev.power.power_state.event && state.event >= PM_EVENT_SUSPEND) {
1379 rc = pmac_ide_do_suspend(hwif);
1380 if (rc == 0)
1381 mdev->ofdev.dev.power.power_state = state;
1382 }
1383
1384 return rc;
1385 }
1386
1387 static int
1388 pmac_ide_macio_resume(struct macio_dev *mdev)
1389 {
1390 ide_hwif_t *hwif = (ide_hwif_t *)dev_get_drvdata(&mdev->ofdev.dev);
1391 int rc = 0;
1392
1393 if (mdev->ofdev.dev.power.power_state.event != PM_EVENT_ON) {
1394 rc = pmac_ide_do_resume(hwif);
1395 if (rc == 0)
1396 mdev->ofdev.dev.power.power_state = PMSG_ON;
1397 }
1398
1399 return rc;
1400 }
1401
1402 /*
1403 * Attach to a PCI probed interface
1404 */
1405 static int __devinit
1406 pmac_ide_pci_attach(struct pci_dev *pdev, const struct pci_device_id *id)
1407 {
1408 ide_hwif_t *hwif;
1409 struct device_node *np;
1410 pmac_ide_hwif_t *pmif;
1411 void __iomem *base;
1412 unsigned long rbase, rlen;
1413 int i, rc;
1414
1415 np = pci_device_to_OF_node(pdev);
1416 if (np == NULL) {
1417 printk(KERN_ERR "ide-pmac: cannot find MacIO node for Kauai ATA interface\n");
1418 return -ENODEV;
1419 }
1420 i = 0;
1421 while (i < MAX_HWIFS && (ide_hwifs[i].io_ports[IDE_DATA_OFFSET] != 0
1422 || pmac_ide[i].node != NULL))
1423 ++i;
1424 if (i >= MAX_HWIFS) {
1425 printk(KERN_ERR "ide-pmac: PCI interface attach with no slot\n");
1426 printk(KERN_ERR " %s\n", np->full_name);
1427 return -ENODEV;
1428 }
1429
1430 pmif = &pmac_ide[i];
1431 hwif = &ide_hwifs[i];
1432
1433 if (pci_enable_device(pdev)) {
1434 printk(KERN_WARNING "ide%i: Can't enable PCI device for %s\n",
1435 i, np->full_name);
1436 return -ENXIO;
1437 }
1438 pci_set_master(pdev);
1439
1440 if (pci_request_regions(pdev, "Kauai ATA")) {
1441 printk(KERN_ERR "ide%d: Cannot obtain PCI resources for %s\n",
1442 i, np->full_name);
1443 return -ENXIO;
1444 }
1445
1446 hwif->pci_dev = pdev;
1447 hwif->gendev.parent = &pdev->dev;
1448 pmif->mdev = NULL;
1449 pmif->node = np;
1450
1451 rbase = pci_resource_start(pdev, 0);
1452 rlen = pci_resource_len(pdev, 0);
1453
1454 base = ioremap(rbase, rlen);
1455 pmif->regbase = (unsigned long) base + 0x2000;
1456 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1457 pmif->dma_regs = base + 0x1000;
1458 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
1459 pmif->kauai_fcr = base;
1460 pmif->irq = pdev->irq;
1461
1462 pci_set_drvdata(pdev, hwif);
1463
1464 rc = pmac_ide_setup_device(pmif, hwif);
1465 if (rc != 0) {
1466 /* The inteface is released to the common IDE layer */
1467 pci_set_drvdata(pdev, NULL);
1468 iounmap(base);
1469 memset(pmif, 0, sizeof(*pmif));
1470 pci_release_regions(pdev);
1471 }
1472
1473 return rc;
1474 }
1475
1476 static int
1477 pmac_ide_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1478 {
1479 ide_hwif_t *hwif = (ide_hwif_t *)pci_get_drvdata(pdev);
1480 int rc = 0;
1481
1482 if (state.event != pdev->dev.power.power_state.event && state.event >= 2) {
1483 rc = pmac_ide_do_suspend(hwif);
1484 if (rc == 0)
1485 pdev->dev.power.power_state = state;
1486 }
1487
1488 return rc;
1489 }
1490
1491 static int
1492 pmac_ide_pci_resume(struct pci_dev *pdev)
1493 {
1494 ide_hwif_t *hwif = (ide_hwif_t *)pci_get_drvdata(pdev);
1495 int rc = 0;
1496
1497 if (pdev->dev.power.power_state.event != PM_EVENT_ON) {
1498 rc = pmac_ide_do_resume(hwif);
1499 if (rc == 0)
1500 pdev->dev.power.power_state = PMSG_ON;
1501 }
1502
1503 return rc;
1504 }
1505
1506 static struct of_device_id pmac_ide_macio_match[] =
1507 {
1508 {
1509 .name = "IDE",
1510 },
1511 {
1512 .name = "ATA",
1513 },
1514 {
1515 .type = "ide",
1516 },
1517 {
1518 .type = "ata",
1519 },
1520 {},
1521 };
1522
1523 static struct macio_driver pmac_ide_macio_driver =
1524 {
1525 .name = "ide-pmac",
1526 .match_table = pmac_ide_macio_match,
1527 .probe = pmac_ide_macio_attach,
1528 .suspend = pmac_ide_macio_suspend,
1529 .resume = pmac_ide_macio_resume,
1530 };
1531
1532 static struct pci_device_id pmac_ide_pci_match[] = {
1533 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_ATA,
1534 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1535 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID_ATA100,
1536 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1537 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_K2_ATA100,
1538 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1539 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_SH_ATA,
1540 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1541 { PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_IPID2_ATA,
1542 PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
1543 };
1544
1545 static struct pci_driver pmac_ide_pci_driver = {
1546 .name = "ide-pmac",
1547 .id_table = pmac_ide_pci_match,
1548 .probe = pmac_ide_pci_attach,
1549 .suspend = pmac_ide_pci_suspend,
1550 .resume = pmac_ide_pci_resume,
1551 };
1552 MODULE_DEVICE_TABLE(pci, pmac_ide_pci_match);
1553
1554 void __init
1555 pmac_ide_probe(void)
1556 {
1557 if (!machine_is(powermac))
1558 return;
1559
1560 #ifdef CONFIG_BLK_DEV_IDE_PMAC_ATA100FIRST
1561 pci_register_driver(&pmac_ide_pci_driver);
1562 macio_register_driver(&pmac_ide_macio_driver);
1563 #else
1564 macio_register_driver(&pmac_ide_macio_driver);
1565 pci_register_driver(&pmac_ide_pci_driver);
1566 #endif
1567 }
1568
1569 #ifdef CONFIG_BLK_DEV_IDEDMA_PMAC
1570
1571 /*
1572 * pmac_ide_build_dmatable builds the DBDMA command list
1573 * for a transfer and sets the DBDMA channel to point to it.
1574 */
1575 static int
1576 pmac_ide_build_dmatable(ide_drive_t *drive, struct request *rq)
1577 {
1578 struct dbdma_cmd *table;
1579 int i, count = 0;
1580 ide_hwif_t *hwif = HWIF(drive);
1581 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1582 volatile struct dbdma_regs __iomem *dma = pmif->dma_regs;
1583 struct scatterlist *sg;
1584 int wr = (rq_data_dir(rq) == WRITE);
1585
1586 /* DMA table is already aligned */
1587 table = (struct dbdma_cmd *) pmif->dma_table_cpu;
1588
1589 /* Make sure DMA controller is stopped (necessary ?) */
1590 writel((RUN|PAUSE|FLUSH|WAKE|DEAD) << 16, &dma->control);
1591 while (readl(&dma->status) & RUN)
1592 udelay(1);
1593
1594 hwif->sg_nents = i = ide_build_sglist(drive, rq);
1595
1596 if (!i)
1597 return 0;
1598
1599 /* Build DBDMA commands list */
1600 sg = hwif->sg_table;
1601 while (i && sg_dma_len(sg)) {
1602 u32 cur_addr;
1603 u32 cur_len;
1604
1605 cur_addr = sg_dma_address(sg);
1606 cur_len = sg_dma_len(sg);
1607
1608 if (pmif->broken_dma && cur_addr & (L1_CACHE_BYTES - 1)) {
1609 if (pmif->broken_dma_warn == 0) {
1610 printk(KERN_WARNING "%s: DMA on non aligned address,"
1611 "switching to PIO on Ohare chipset\n", drive->name);
1612 pmif->broken_dma_warn = 1;
1613 }
1614 goto use_pio_instead;
1615 }
1616 while (cur_len) {
1617 unsigned int tc = (cur_len < 0xfe00)? cur_len: 0xfe00;
1618
1619 if (count++ >= MAX_DCMDS) {
1620 printk(KERN_WARNING "%s: DMA table too small\n",
1621 drive->name);
1622 goto use_pio_instead;
1623 }
1624 st_le16(&table->command, wr? OUTPUT_MORE: INPUT_MORE);
1625 st_le16(&table->req_count, tc);
1626 st_le32(&table->phy_addr, cur_addr);
1627 table->cmd_dep = 0;
1628 table->xfer_status = 0;
1629 table->res_count = 0;
1630 cur_addr += tc;
1631 cur_len -= tc;
1632 ++table;
1633 }
1634 sg++;
1635 i--;
1636 }
1637
1638 /* convert the last command to an input/output last command */
1639 if (count) {
1640 st_le16(&table[-1].command, wr? OUTPUT_LAST: INPUT_LAST);
1641 /* add the stop command to the end of the list */
1642 memset(table, 0, sizeof(struct dbdma_cmd));
1643 st_le16(&table->command, DBDMA_STOP);
1644 mb();
1645 writel(hwif->dmatable_dma, &dma->cmdptr);
1646 return 1;
1647 }
1648
1649 printk(KERN_DEBUG "%s: empty DMA table?\n", drive->name);
1650 use_pio_instead:
1651 pci_unmap_sg(hwif->pci_dev,
1652 hwif->sg_table,
1653 hwif->sg_nents,
1654 hwif->sg_dma_direction);
1655 return 0; /* revert to PIO for this request */
1656 }
1657
1658 /* Teardown mappings after DMA has completed. */
1659 static void
1660 pmac_ide_destroy_dmatable (ide_drive_t *drive)
1661 {
1662 ide_hwif_t *hwif = drive->hwif;
1663 struct pci_dev *dev = HWIF(drive)->pci_dev;
1664 struct scatterlist *sg = hwif->sg_table;
1665 int nents = hwif->sg_nents;
1666
1667 if (nents) {
1668 pci_unmap_sg(dev, sg, nents, hwif->sg_dma_direction);
1669 hwif->sg_nents = 0;
1670 }
1671 }
1672
1673 /*
1674 * Pick up best MDMA timing for the drive and apply it
1675 */
1676 static int
1677 pmac_ide_mdma_enable(ide_drive_t *drive, u16 mode)
1678 {
1679 ide_hwif_t *hwif = HWIF(drive);
1680 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1681 int drive_cycle_time;
1682 struct hd_driveid *id = drive->id;
1683 u32 *timings, *timings2;
1684 u32 timing_local[2];
1685 int ret;
1686
1687 /* which drive is it ? */
1688 timings = &pmif->timings[drive->select.b.unit & 0x01];
1689 timings2 = &pmif->timings[(drive->select.b.unit & 0x01) + 2];
1690
1691 /* Check if drive provide explicit cycle time */
1692 if ((id->field_valid & 2) && (id->eide_dma_time))
1693 drive_cycle_time = id->eide_dma_time;
1694 else
1695 drive_cycle_time = 0;
1696
1697 /* Copy timings to local image */
1698 timing_local[0] = *timings;
1699 timing_local[1] = *timings2;
1700
1701 /* Calculate controller timings */
1702 ret = set_timings_mdma( drive, pmif->kind,
1703 &timing_local[0],
1704 &timing_local[1],
1705 mode,
1706 drive_cycle_time);
1707 if (ret)
1708 return 0;
1709
1710 /* Set feature on drive */
1711 printk(KERN_INFO "%s: Enabling MultiWord DMA %d\n", drive->name, mode & 0xf);
1712 ret = pmac_ide_do_setfeature(drive, mode);
1713 if (ret) {
1714 printk(KERN_WARNING "%s: Failed !\n", drive->name);
1715 return 0;
1716 }
1717
1718 /* Apply timings to controller */
1719 *timings = timing_local[0];
1720 *timings2 = timing_local[1];
1721
1722 /* Set speed info in drive */
1723 drive->current_speed = mode;
1724 if (!drive->init_speed)
1725 drive->init_speed = mode;
1726
1727 return 1;
1728 }
1729
1730 /*
1731 * Pick up best UDMA timing for the drive and apply it
1732 */
1733 static int
1734 pmac_ide_udma_enable(ide_drive_t *drive, u16 mode)
1735 {
1736 ide_hwif_t *hwif = HWIF(drive);
1737 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1738 u32 *timings, *timings2;
1739 u32 timing_local[2];
1740 int ret;
1741
1742 /* which drive is it ? */
1743 timings = &pmif->timings[drive->select.b.unit & 0x01];
1744 timings2 = &pmif->timings[(drive->select.b.unit & 0x01) + 2];
1745
1746 /* Copy timings to local image */
1747 timing_local[0] = *timings;
1748 timing_local[1] = *timings2;
1749
1750 /* Calculate timings for interface */
1751 if (pmif->kind == controller_un_ata6
1752 || pmif->kind == controller_k2_ata6)
1753 ret = set_timings_udma_ata6( &timing_local[0],
1754 &timing_local[1],
1755 mode);
1756 else if (pmif->kind == controller_sh_ata6)
1757 ret = set_timings_udma_shasta( &timing_local[0],
1758 &timing_local[1],
1759 mode);
1760 else
1761 ret = set_timings_udma_ata4(&timing_local[0], mode);
1762 if (ret)
1763 return 0;
1764
1765 /* Set feature on drive */
1766 printk(KERN_INFO "%s: Enabling Ultra DMA %d\n", drive->name, mode & 0x0f);
1767 ret = pmac_ide_do_setfeature(drive, mode);
1768 if (ret) {
1769 printk(KERN_WARNING "%s: Failed !\n", drive->name);
1770 return 0;
1771 }
1772
1773 /* Apply timings to controller */
1774 *timings = timing_local[0];
1775 *timings2 = timing_local[1];
1776
1777 /* Set speed info in drive */
1778 drive->current_speed = mode;
1779 if (!drive->init_speed)
1780 drive->init_speed = mode;
1781
1782 return 1;
1783 }
1784
1785 /*
1786 * Check what is the best DMA timing setting for the drive and
1787 * call appropriate functions to apply it.
1788 */
1789 static int
1790 pmac_ide_dma_check(ide_drive_t *drive)
1791 {
1792 struct hd_driveid *id = drive->id;
1793 ide_hwif_t *hwif = HWIF(drive);
1794 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1795 int enable = 1;
1796 int map;
1797 drive->using_dma = 0;
1798
1799 if (drive->media == ide_floppy)
1800 enable = 0;
1801 if (((id->capability & 1) == 0) && !__ide_dma_good_drive(drive))
1802 enable = 0;
1803 if (__ide_dma_bad_drive(drive))
1804 enable = 0;
1805
1806 if (enable) {
1807 short mode;
1808
1809 map = XFER_MWDMA;
1810 if (pmif->kind == controller_kl_ata4
1811 || pmif->kind == controller_un_ata6
1812 || pmif->kind == controller_k2_ata6
1813 || pmif->kind == controller_sh_ata6) {
1814 map |= XFER_UDMA;
1815 if (pmif->cable_80) {
1816 map |= XFER_UDMA_66;
1817 if (pmif->kind == controller_un_ata6 ||
1818 pmif->kind == controller_k2_ata6 ||
1819 pmif->kind == controller_sh_ata6)
1820 map |= XFER_UDMA_100;
1821 if (pmif->kind == controller_sh_ata6)
1822 map |= XFER_UDMA_133;
1823 }
1824 }
1825 mode = ide_find_best_mode(drive, map);
1826 if (mode & XFER_UDMA)
1827 drive->using_dma = pmac_ide_udma_enable(drive, mode);
1828 else if (mode & XFER_MWDMA)
1829 drive->using_dma = pmac_ide_mdma_enable(drive, mode);
1830 hwif->OUTB(0, IDE_CONTROL_REG);
1831 /* Apply settings to controller */
1832 pmac_ide_do_update_timings(drive);
1833 }
1834 return 0;
1835 }
1836
1837 /*
1838 * Prepare a DMA transfer. We build the DMA table, adjust the timings for
1839 * a read on KeyLargo ATA/66 and mark us as waiting for DMA completion
1840 */
1841 static int
1842 pmac_ide_dma_setup(ide_drive_t *drive)
1843 {
1844 ide_hwif_t *hwif = HWIF(drive);
1845 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)hwif->hwif_data;
1846 struct request *rq = HWGROUP(drive)->rq;
1847 u8 unit = (drive->select.b.unit & 0x01);
1848 u8 ata4;
1849
1850 if (pmif == NULL)
1851 return 1;
1852 ata4 = (pmif->kind == controller_kl_ata4);
1853
1854 if (!pmac_ide_build_dmatable(drive, rq)) {
1855 ide_map_sg(drive, rq);
1856 return 1;
1857 }
1858
1859 /* Apple adds 60ns to wrDataSetup on reads */
1860 if (ata4 && (pmif->timings[unit] & TR_66_UDMA_EN)) {
1861 writel(pmif->timings[unit] + (!rq_data_dir(rq) ? 0x00800000UL : 0),
1862 PMAC_IDE_REG(IDE_TIMING_CONFIG));
1863 (void)readl(PMAC_IDE_REG(IDE_TIMING_CONFIG));
1864 }
1865
1866 drive->waiting_for_dma = 1;
1867
1868 return 0;
1869 }
1870
1871 static void
1872 pmac_ide_dma_exec_cmd(ide_drive_t *drive, u8 command)
1873 {
1874 /* issue cmd to drive */
1875 ide_execute_command(drive, command, &ide_dma_intr, 2*WAIT_CMD, NULL);
1876 }
1877
1878 /*
1879 * Kick the DMA controller into life after the DMA command has been issued
1880 * to the drive.
1881 */
1882 static void
1883 pmac_ide_dma_start(ide_drive_t *drive)
1884 {
1885 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1886 volatile struct dbdma_regs __iomem *dma;
1887
1888 dma = pmif->dma_regs;
1889
1890 writel((RUN << 16) | RUN, &dma->control);
1891 /* Make sure it gets to the controller right now */
1892 (void)readl(&dma->control);
1893 }
1894
1895 /*
1896 * After a DMA transfer, make sure the controller is stopped
1897 */
1898 static int
1899 pmac_ide_dma_end (ide_drive_t *drive)
1900 {
1901 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1902 volatile struct dbdma_regs __iomem *dma;
1903 u32 dstat;
1904
1905 if (pmif == NULL)
1906 return 0;
1907 dma = pmif->dma_regs;
1908
1909 drive->waiting_for_dma = 0;
1910 dstat = readl(&dma->status);
1911 writel(((RUN|WAKE|DEAD) << 16), &dma->control);
1912 pmac_ide_destroy_dmatable(drive);
1913 /* verify good dma status. we don't check for ACTIVE beeing 0. We should...
1914 * in theory, but with ATAPI decices doing buffer underruns, that would
1915 * cause us to disable DMA, which isn't what we want
1916 */
1917 return (dstat & (RUN|DEAD)) != RUN;
1918 }
1919
1920 /*
1921 * Check out that the interrupt we got was for us. We can't always know this
1922 * for sure with those Apple interfaces (well, we could on the recent ones but
1923 * that's not implemented yet), on the other hand, we don't have shared interrupts
1924 * so it's not really a problem
1925 */
1926 static int
1927 pmac_ide_dma_test_irq (ide_drive_t *drive)
1928 {
1929 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1930 volatile struct dbdma_regs __iomem *dma;
1931 unsigned long status, timeout;
1932
1933 if (pmif == NULL)
1934 return 0;
1935 dma = pmif->dma_regs;
1936
1937 /* We have to things to deal with here:
1938 *
1939 * - The dbdma won't stop if the command was started
1940 * but completed with an error without transferring all
1941 * datas. This happens when bad blocks are met during
1942 * a multi-block transfer.
1943 *
1944 * - The dbdma fifo hasn't yet finished flushing to
1945 * to system memory when the disk interrupt occurs.
1946 *
1947 */
1948
1949 /* If ACTIVE is cleared, the STOP command have passed and
1950 * transfer is complete.
1951 */
1952 status = readl(&dma->status);
1953 if (!(status & ACTIVE))
1954 return 1;
1955 if (!drive->waiting_for_dma)
1956 printk(KERN_WARNING "ide%d, ide_dma_test_irq \
1957 called while not waiting\n", HWIF(drive)->index);
1958
1959 /* If dbdma didn't execute the STOP command yet, the
1960 * active bit is still set. We consider that we aren't
1961 * sharing interrupts (which is hopefully the case with
1962 * those controllers) and so we just try to flush the
1963 * channel for pending data in the fifo
1964 */
1965 udelay(1);
1966 writel((FLUSH << 16) | FLUSH, &dma->control);
1967 timeout = 0;
1968 for (;;) {
1969 udelay(1);
1970 status = readl(&dma->status);
1971 if ((status & FLUSH) == 0)
1972 break;
1973 if (++timeout > 100) {
1974 printk(KERN_WARNING "ide%d, ide_dma_test_irq \
1975 timeout flushing channel\n", HWIF(drive)->index);
1976 break;
1977 }
1978 }
1979 return 1;
1980 }
1981
1982 static int
1983 pmac_ide_dma_host_off (ide_drive_t *drive)
1984 {
1985 return 0;
1986 }
1987
1988 static int
1989 pmac_ide_dma_host_on (ide_drive_t *drive)
1990 {
1991 return 0;
1992 }
1993
1994 static int
1995 pmac_ide_dma_lostirq (ide_drive_t *drive)
1996 {
1997 pmac_ide_hwif_t* pmif = (pmac_ide_hwif_t *)HWIF(drive)->hwif_data;
1998 volatile struct dbdma_regs __iomem *dma;
1999 unsigned long status;
2000
2001 if (pmif == NULL)
2002 return 0;
2003 dma = pmif->dma_regs;
2004
2005 status = readl(&dma->status);
2006 printk(KERN_ERR "ide-pmac lost interrupt, dma status: %lx\n", status);
2007 return 0;
2008 }
2009
2010 /*
2011 * Allocate the data structures needed for using DMA with an interface
2012 * and fill the proper list of functions pointers
2013 */
2014 static void __init
2015 pmac_ide_setup_dma(pmac_ide_hwif_t *pmif, ide_hwif_t *hwif)
2016 {
2017 /* We won't need pci_dev if we switch to generic consistent
2018 * DMA routines ...
2019 */
2020 if (hwif->pci_dev == NULL)
2021 return;
2022 /*
2023 * Allocate space for the DBDMA commands.
2024 * The +2 is +1 for the stop command and +1 to allow for
2025 * aligning the start address to a multiple of 16 bytes.
2026 */
2027 pmif->dma_table_cpu = (struct dbdma_cmd*)pci_alloc_consistent(
2028 hwif->pci_dev,
2029 (MAX_DCMDS + 2) * sizeof(struct dbdma_cmd),
2030 &hwif->dmatable_dma);
2031 if (pmif->dma_table_cpu == NULL) {
2032 printk(KERN_ERR "%s: unable to allocate DMA command list\n",
2033 hwif->name);
2034 return;
2035 }
2036
2037 hwif->ide_dma_off_quietly = &__ide_dma_off_quietly;
2038 hwif->ide_dma_on = &__ide_dma_on;
2039 hwif->ide_dma_check = &pmac_ide_dma_check;
2040 hwif->dma_setup = &pmac_ide_dma_setup;
2041 hwif->dma_exec_cmd = &pmac_ide_dma_exec_cmd;
2042 hwif->dma_start = &pmac_ide_dma_start;
2043 hwif->ide_dma_end = &pmac_ide_dma_end;
2044 hwif->ide_dma_test_irq = &pmac_ide_dma_test_irq;
2045 hwif->ide_dma_host_off = &pmac_ide_dma_host_off;
2046 hwif->ide_dma_host_on = &pmac_ide_dma_host_on;
2047 hwif->ide_dma_timeout = &__ide_dma_timeout;
2048 hwif->ide_dma_lostirq = &pmac_ide_dma_lostirq;
2049
2050 hwif->atapi_dma = 1;
2051 switch(pmif->kind) {
2052 case controller_sh_ata6:
2053 hwif->ultra_mask = pmif->cable_80 ? 0x7f : 0x07;
2054 hwif->mwdma_mask = 0x07;
2055 hwif->swdma_mask = 0x00;
2056 break;
2057 case controller_un_ata6:
2058 case controller_k2_ata6:
2059 hwif->ultra_mask = pmif->cable_80 ? 0x3f : 0x07;
2060 hwif->mwdma_mask = 0x07;
2061 hwif->swdma_mask = 0x00;
2062 break;
2063 case controller_kl_ata4:
2064 hwif->ultra_mask = pmif->cable_80 ? 0x1f : 0x07;
2065 hwif->mwdma_mask = 0x07;
2066 hwif->swdma_mask = 0x00;
2067 break;
2068 default:
2069 hwif->ultra_mask = 0x00;
2070 hwif->mwdma_mask = 0x07;
2071 hwif->swdma_mask = 0x00;
2072 break;
2073 }
2074 }
2075
2076 #endif /* CONFIG_BLK_DEV_IDEDMA_PMAC */
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