2 * Local APIC handling, local APIC timers
4 * (c) 1999, 2000 Ingo Molnar <mingo@redhat.com>
7 * Maciej W. Rozycki : Bits for genuine 82489DX APICs;
8 * thanks to Eric Gilmore
10 * for testing these extensively.
11 * Maciej W. Rozycki : Various updates and fixes.
12 * Mikael Pettersson : Power Management for UP-APIC.
14 * Mikael Pettersson : PM converted to driver model.
17 #include <linux/config.h>
18 #include <linux/init.h>
21 #include <linux/delay.h>
22 #include <linux/bootmem.h>
23 #include <linux/smp_lock.h>
24 #include <linux/interrupt.h>
25 #include <linux/mc146818rtc.h>
26 #include <linux/kernel_stat.h>
27 #include <linux/sysdev.h>
29 #include <asm/atomic.h>
32 #include <asm/mpspec.h>
33 #include <asm/pgalloc.h>
34 #include <asm/mach_apic.h>
39 int disable_apic_timer __initdata
;
41 /* Using APIC to generate smp_local_timer_interrupt? */
42 int using_apic_timer
= 0;
44 static DEFINE_PER_CPU(int, prof_multiplier
) = 1;
45 static DEFINE_PER_CPU(int, prof_old_multiplier
) = 1;
46 static DEFINE_PER_CPU(int, prof_counter
) = 1;
48 static void apic_pm_activate(void);
50 void enable_NMI_through_LVT0 (void * dummy
)
54 ver
= apic_read(APIC_LVR
);
55 ver
= GET_APIC_VERSION(ver
);
56 v
= APIC_DM_NMI
; /* unmask and set to NMI */
57 apic_write_around(APIC_LVT0
, v
);
62 unsigned int v
, ver
, maxlvt
;
64 v
= apic_read(APIC_LVR
);
65 ver
= GET_APIC_VERSION(v
);
66 maxlvt
= GET_APIC_MAXLVT(v
);
70 void clear_local_APIC(void)
75 maxlvt
= get_maxlvt();
78 * Masking an LVT entry on a P6 can trigger a local APIC error
79 * if the vector is zero. Mask LVTERR first to prevent this.
82 v
= ERROR_APIC_VECTOR
; /* any non-zero vector will do */
83 apic_write_around(APIC_LVTERR
, v
| APIC_LVT_MASKED
);
86 * Careful: we have to set masks only first to deassert
87 * any level-triggered sources.
89 v
= apic_read(APIC_LVTT
);
90 apic_write_around(APIC_LVTT
, v
| APIC_LVT_MASKED
);
91 v
= apic_read(APIC_LVT0
);
92 apic_write_around(APIC_LVT0
, v
| APIC_LVT_MASKED
);
93 v
= apic_read(APIC_LVT1
);
94 apic_write_around(APIC_LVT1
, v
| APIC_LVT_MASKED
);
96 v
= apic_read(APIC_LVTPC
);
97 apic_write_around(APIC_LVTPC
, v
| APIC_LVT_MASKED
);
101 * Clean APIC state for other OSs:
103 apic_write_around(APIC_LVTT
, APIC_LVT_MASKED
);
104 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
);
105 apic_write_around(APIC_LVT1
, APIC_LVT_MASKED
);
107 apic_write_around(APIC_LVTERR
, APIC_LVT_MASKED
);
109 apic_write_around(APIC_LVTPC
, APIC_LVT_MASKED
);
110 v
= GET_APIC_VERSION(apic_read(APIC_LVR
));
111 apic_write(APIC_ESR
, 0);
115 void __init
connect_bsp_APIC(void)
119 * Do not trust the local APIC being empty at bootup.
123 * PIC mode, enable APIC mode in the IMCR, i.e.
124 * connect BSP's local APIC to INT and NMI lines.
126 apic_printk(APIC_VERBOSE
, "leaving PIC mode, enabling APIC mode.\n");
132 void disconnect_bsp_APIC(int virt_wire_setup
)
136 * Put the board back into PIC mode (has an effect
137 * only on certain older boards). Note that APIC
138 * interrupts, including IPIs, won't work beyond
139 * this point! The only exception are INIT IPIs.
141 apic_printk(APIC_QUIET
, "disabling APIC mode, entering PIC mode.\n");
146 /* Go back to Virtual Wire compatibility mode */
149 /* For the spurious interrupt use vector F, and enable it */
150 value
= apic_read(APIC_SPIV
);
151 value
&= ~APIC_VECTOR_MASK
;
152 value
|= APIC_SPIV_APIC_ENABLED
;
154 apic_write_around(APIC_SPIV
, value
);
156 if (!virt_wire_setup
) {
157 /* For LVT0 make it edge triggered, active high, external and enabled */
158 value
= apic_read(APIC_LVT0
);
159 value
&= ~(APIC_MODE_MASK
| APIC_SEND_PENDING
|
160 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
161 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
162 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
163 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_EXTINT
);
164 apic_write_around(APIC_LVT0
, value
);
168 apic_write_around(APIC_LVT0
, APIC_LVT_MASKED
);
171 /* For LVT1 make it edge triggered, active high, nmi and enabled */
172 value
= apic_read(APIC_LVT1
);
174 APIC_MODE_MASK
| APIC_SEND_PENDING
|
175 APIC_INPUT_POLARITY
| APIC_LVT_REMOTE_IRR
|
176 APIC_LVT_LEVEL_TRIGGER
| APIC_LVT_MASKED
);
177 value
|= APIC_LVT_REMOTE_IRR
| APIC_SEND_PENDING
;
178 value
= SET_APIC_DELIVERY_MODE(value
, APIC_MODE_NMI
);
179 apic_write_around(APIC_LVT1
, value
);
183 void disable_local_APIC(void)
190 * Disable APIC (implies clearing of registers
193 value
= apic_read(APIC_SPIV
);
194 value
&= ~APIC_SPIV_APIC_ENABLED
;
195 apic_write_around(APIC_SPIV
, value
);
199 * This is to verify that we're looking at a real local APIC.
200 * Check these against your board if the CPUs aren't getting
201 * started for no apparent reason.
203 int __init
verify_local_APIC(void)
205 unsigned int reg0
, reg1
;
208 * The version register is read-only in a real APIC.
210 reg0
= apic_read(APIC_LVR
);
211 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg0
);
212 apic_write(APIC_LVR
, reg0
^ APIC_LVR_MASK
);
213 reg1
= apic_read(APIC_LVR
);
214 apic_printk(APIC_DEBUG
, "Getting VERSION: %x\n", reg1
);
217 * The two version reads above should print the same
218 * numbers. If the second one is different, then we
219 * poke at a non-APIC.
225 * Check if the version looks reasonably.
227 reg1
= GET_APIC_VERSION(reg0
);
228 if (reg1
== 0x00 || reg1
== 0xff)
231 if (reg1
< 0x02 || reg1
== 0xff)
235 * The ID register is read/write in a real APIC.
237 reg0
= apic_read(APIC_ID
);
238 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg0
);
239 apic_write(APIC_ID
, reg0
^ APIC_ID_MASK
);
240 reg1
= apic_read(APIC_ID
);
241 apic_printk(APIC_DEBUG
, "Getting ID: %x\n", reg1
);
242 apic_write(APIC_ID
, reg0
);
243 if (reg1
!= (reg0
^ APIC_ID_MASK
))
247 * The next two are just to see if we have sane values.
248 * They're only really relevant if we're in Virtual Wire
249 * compatibility mode, but most boxes are anymore.
251 reg0
= apic_read(APIC_LVT0
);
252 apic_printk(APIC_DEBUG
,"Getting LVT0: %x\n", reg0
);
253 reg1
= apic_read(APIC_LVT1
);
254 apic_printk(APIC_DEBUG
, "Getting LVT1: %x\n", reg1
);
259 void __init
sync_Arb_IDs(void)
261 /* Unsupported on P4 - see Intel Dev. Manual Vol. 3, Ch. 8.6.1 */
262 unsigned int ver
= GET_APIC_VERSION(apic_read(APIC_LVR
));
263 if (ver
>= 0x14) /* P4 or higher */
269 apic_wait_icr_idle();
271 apic_printk(APIC_DEBUG
, "Synchronizing Arb IDs.\n");
272 apic_write_around(APIC_ICR
, APIC_DEST_ALLINC
| APIC_INT_LEVELTRIG
276 extern void __error_in_apic_c (void);
279 * An initial setup of the virtual wire mode.
281 void __init
init_bsp_APIC(void)
283 unsigned int value
, ver
;
286 * Don't do the setup now if we have a SMP BIOS as the
287 * through-I/O-APIC virtual wire mode might be active.
289 if (smp_found_config
|| !cpu_has_apic
)
292 value
= apic_read(APIC_LVR
);
293 ver
= GET_APIC_VERSION(value
);
296 * Do not trust the local APIC being empty at bootup.
303 value
= apic_read(APIC_SPIV
);
304 value
&= ~APIC_VECTOR_MASK
;
305 value
|= APIC_SPIV_APIC_ENABLED
;
306 value
|= APIC_SPIV_FOCUS_DISABLED
;
307 value
|= SPURIOUS_APIC_VECTOR
;
308 apic_write_around(APIC_SPIV
, value
);
311 * Set up the virtual wire mode.
313 apic_write_around(APIC_LVT0
, APIC_DM_EXTINT
);
315 apic_write_around(APIC_LVT1
, value
);
318 void __cpuinit
setup_local_APIC (void)
320 unsigned int value
, ver
, maxlvt
;
322 value
= apic_read(APIC_LVR
);
323 ver
= GET_APIC_VERSION(value
);
325 if ((SPURIOUS_APIC_VECTOR
& 0x0f) != 0x0f)
329 * Double-check whether this APIC is really registered.
330 * This is meaningless in clustered apic mode, so we skip it.
332 if (!apic_id_registered())
336 * Intel recommends to set DFR, LDR and TPR before enabling
337 * an APIC. See e.g. "AP-388 82489DX User's Manual" (Intel
338 * document number 292116). So here it goes...
343 * Set Task Priority to 'accept all'. We never change this
346 value
= apic_read(APIC_TASKPRI
);
347 value
&= ~APIC_TPRI_MASK
;
348 apic_write_around(APIC_TASKPRI
, value
);
351 * Now that we are all set up, enable the APIC
353 value
= apic_read(APIC_SPIV
);
354 value
&= ~APIC_VECTOR_MASK
;
358 value
|= APIC_SPIV_APIC_ENABLED
;
361 * Some unknown Intel IO/APIC (or APIC) errata is biting us with
362 * certain networking cards. If high frequency interrupts are
363 * happening on a particular IOAPIC pin, plus the IOAPIC routing
364 * entry is masked/unmasked at a high rate as well then sooner or
365 * later IOAPIC line gets 'stuck', no more interrupts are received
366 * from the device. If focus CPU is disabled then the hang goes
369 * [ This bug can be reproduced easily with a level-triggered
370 * PCI Ne2000 networking cards and PII/PIII processors, dual
374 * Actually disabling the focus CPU check just makes the hang less
375 * frequent as it makes the interrupt distributon model be more
376 * like LRU than MRU (the short-term load is more even across CPUs).
377 * See also the comment in end_level_ioapic_irq(). --macro
380 /* Enable focus processor (bit==0) */
381 value
&= ~APIC_SPIV_FOCUS_DISABLED
;
383 /* Disable focus processor (bit==1) */
384 value
|= APIC_SPIV_FOCUS_DISABLED
;
387 * Set spurious IRQ vector
389 value
|= SPURIOUS_APIC_VECTOR
;
390 apic_write_around(APIC_SPIV
, value
);
395 * set up through-local-APIC on the BP's LINT0. This is not
396 * strictly necessary in pure symmetric-IO mode, but sometimes
397 * we delegate interrupts to the 8259A.
400 * TODO: set up through-local-APIC from through-I/O-APIC? --macro
402 value
= apic_read(APIC_LVT0
) & APIC_LVT_MASKED
;
403 if (!smp_processor_id() && (pic_mode
|| !value
)) {
404 value
= APIC_DM_EXTINT
;
405 apic_printk(APIC_VERBOSE
, "enabled ExtINT on CPU#%d\n", smp_processor_id());
407 value
= APIC_DM_EXTINT
| APIC_LVT_MASKED
;
408 apic_printk(APIC_VERBOSE
, "masked ExtINT on CPU#%d\n", smp_processor_id());
410 apic_write_around(APIC_LVT0
, value
);
413 * only the BP should see the LINT1 NMI signal, obviously.
415 if (!smp_processor_id())
418 value
= APIC_DM_NMI
| APIC_LVT_MASKED
;
419 apic_write_around(APIC_LVT1
, value
);
423 maxlvt
= get_maxlvt();
424 oldvalue
= apic_read(APIC_ESR
);
425 value
= ERROR_APIC_VECTOR
; // enables sending errors
426 apic_write_around(APIC_LVTERR
, value
);
428 * spec says clear errors after enabling vector.
431 apic_write(APIC_ESR
, 0);
432 value
= apic_read(APIC_ESR
);
433 if (value
!= oldvalue
)
434 apic_printk(APIC_VERBOSE
,
435 "ESR value after enabling vector: %08x, after %08x\n",
439 nmi_watchdog_default();
440 if (nmi_watchdog
== NMI_LOCAL_APIC
)
441 setup_apic_nmi_watchdog();
448 /* 'active' is true if the local APIC was enabled by us and
449 not the BIOS; this signifies that we are also responsible
450 for disabling it before entering apm/acpi suspend */
452 /* r/w apic fields */
453 unsigned int apic_id
;
454 unsigned int apic_taskpri
;
455 unsigned int apic_ldr
;
456 unsigned int apic_dfr
;
457 unsigned int apic_spiv
;
458 unsigned int apic_lvtt
;
459 unsigned int apic_lvtpc
;
460 unsigned int apic_lvt0
;
461 unsigned int apic_lvt1
;
462 unsigned int apic_lvterr
;
463 unsigned int apic_tmict
;
464 unsigned int apic_tdcr
;
465 unsigned int apic_thmr
;
468 static int lapic_suspend(struct sys_device
*dev
, pm_message_t state
)
472 if (!apic_pm_state
.active
)
475 apic_pm_state
.apic_id
= apic_read(APIC_ID
);
476 apic_pm_state
.apic_taskpri
= apic_read(APIC_TASKPRI
);
477 apic_pm_state
.apic_ldr
= apic_read(APIC_LDR
);
478 apic_pm_state
.apic_dfr
= apic_read(APIC_DFR
);
479 apic_pm_state
.apic_spiv
= apic_read(APIC_SPIV
);
480 apic_pm_state
.apic_lvtt
= apic_read(APIC_LVTT
);
481 apic_pm_state
.apic_lvtpc
= apic_read(APIC_LVTPC
);
482 apic_pm_state
.apic_lvt0
= apic_read(APIC_LVT0
);
483 apic_pm_state
.apic_lvt1
= apic_read(APIC_LVT1
);
484 apic_pm_state
.apic_lvterr
= apic_read(APIC_LVTERR
);
485 apic_pm_state
.apic_tmict
= apic_read(APIC_TMICT
);
486 apic_pm_state
.apic_tdcr
= apic_read(APIC_TDCR
);
487 apic_pm_state
.apic_thmr
= apic_read(APIC_LVTTHMR
);
488 local_save_flags(flags
);
490 disable_local_APIC();
491 local_irq_restore(flags
);
495 static int lapic_resume(struct sys_device
*dev
)
500 if (!apic_pm_state
.active
)
503 /* XXX: Pavel needs this for S3 resume, but can't explain why */
504 set_fixmap_nocache(FIX_APIC_BASE
, APIC_DEFAULT_PHYS_BASE
);
506 local_irq_save(flags
);
507 rdmsr(MSR_IA32_APICBASE
, l
, h
);
508 l
&= ~MSR_IA32_APICBASE_BASE
;
509 l
|= MSR_IA32_APICBASE_ENABLE
| APIC_DEFAULT_PHYS_BASE
;
510 wrmsr(MSR_IA32_APICBASE
, l
, h
);
511 apic_write(APIC_LVTERR
, ERROR_APIC_VECTOR
| APIC_LVT_MASKED
);
512 apic_write(APIC_ID
, apic_pm_state
.apic_id
);
513 apic_write(APIC_DFR
, apic_pm_state
.apic_dfr
);
514 apic_write(APIC_LDR
, apic_pm_state
.apic_ldr
);
515 apic_write(APIC_TASKPRI
, apic_pm_state
.apic_taskpri
);
516 apic_write(APIC_SPIV
, apic_pm_state
.apic_spiv
);
517 apic_write(APIC_LVT0
, apic_pm_state
.apic_lvt0
);
518 apic_write(APIC_LVT1
, apic_pm_state
.apic_lvt1
);
519 apic_write(APIC_LVTTHMR
, apic_pm_state
.apic_thmr
);
520 apic_write(APIC_LVTPC
, apic_pm_state
.apic_lvtpc
);
521 apic_write(APIC_LVTT
, apic_pm_state
.apic_lvtt
);
522 apic_write(APIC_TDCR
, apic_pm_state
.apic_tdcr
);
523 apic_write(APIC_TMICT
, apic_pm_state
.apic_tmict
);
524 apic_write(APIC_ESR
, 0);
526 apic_write(APIC_LVTERR
, apic_pm_state
.apic_lvterr
);
527 apic_write(APIC_ESR
, 0);
529 local_irq_restore(flags
);
533 static struct sysdev_class lapic_sysclass
= {
534 set_kset_name("lapic"),
535 .resume
= lapic_resume
,
536 .suspend
= lapic_suspend
,
539 static struct sys_device device_lapic
= {
541 .cls
= &lapic_sysclass
,
544 static void __cpuinit
apic_pm_activate(void)
546 apic_pm_state
.active
= 1;
549 static int __init
init_lapic_sysfs(void)
554 /* XXX: remove suspend/resume procs if !apic_pm_state.active? */
555 error
= sysdev_class_register(&lapic_sysclass
);
557 error
= sysdev_register(&device_lapic
);
560 device_initcall(init_lapic_sysfs
);
562 #else /* CONFIG_PM */
564 static void apic_pm_activate(void) { }
566 #endif /* CONFIG_PM */
568 static int __init
apic_set_verbosity(char *str
)
570 if (strcmp("debug", str
) == 0)
571 apic_verbosity
= APIC_DEBUG
;
572 else if (strcmp("verbose", str
) == 0)
573 apic_verbosity
= APIC_VERBOSE
;
575 printk(KERN_WARNING
"APIC Verbosity level %s not recognised"
576 " use apic=verbose or apic=debug", str
);
581 __setup("apic=", apic_set_verbosity
);
584 * Detect and enable local APICs on non-SMP boards.
585 * Original code written by Keir Fraser.
586 * On AMD64 we trust the BIOS - if it says no APIC it is likely
587 * not correctly set up (usually the APIC timer won't work etc.)
590 static int __init
detect_init_APIC (void)
593 printk(KERN_INFO
"No local APIC present\n");
597 mp_lapic_addr
= APIC_DEFAULT_PHYS_BASE
;
602 void __init
init_apic_mappings(void)
604 unsigned long apic_phys
;
607 * If no local APIC can be found then set up a fake all
608 * zeroes page to simulate the local APIC and another
609 * one for the IO-APIC.
611 if (!smp_found_config
&& detect_init_APIC()) {
612 apic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
613 apic_phys
= __pa(apic_phys
);
615 apic_phys
= mp_lapic_addr
;
617 set_fixmap_nocache(FIX_APIC_BASE
, apic_phys
);
618 apic_printk(APIC_VERBOSE
,"mapped APIC to %16lx (%16lx)\n", APIC_BASE
, apic_phys
);
621 * Fetch the APIC ID of the BSP in case we have a
622 * default configuration (or the MP table is broken).
624 boot_cpu_id
= GET_APIC_ID(apic_read(APIC_ID
));
626 #ifdef CONFIG_X86_IO_APIC
628 unsigned long ioapic_phys
, idx
= FIX_IO_APIC_BASE_0
;
631 for (i
= 0; i
< nr_ioapics
; i
++) {
632 if (smp_found_config
) {
633 ioapic_phys
= mp_ioapics
[i
].mpc_apicaddr
;
635 ioapic_phys
= (unsigned long) alloc_bootmem_pages(PAGE_SIZE
);
636 ioapic_phys
= __pa(ioapic_phys
);
638 set_fixmap_nocache(idx
, ioapic_phys
);
639 apic_printk(APIC_VERBOSE
,"mapped IOAPIC to %016lx (%016lx)\n",
640 __fix_to_virt(idx
), ioapic_phys
);
648 * This function sets up the local APIC timer, with a timeout of
649 * 'clocks' APIC bus clock. During calibration we actually call
650 * this function twice on the boot CPU, once with a bogus timeout
651 * value, second time for real. The other (noncalibrating) CPUs
652 * call this function only once, with the real, calibrated value.
654 * We do reads before writes even if unnecessary, to get around the
655 * P5 APIC double write bug.
658 #define APIC_DIVISOR 16
660 static void __setup_APIC_LVTT(unsigned int clocks
)
662 unsigned int lvtt_value
, tmp_value
, ver
;
664 ver
= GET_APIC_VERSION(apic_read(APIC_LVR
));
665 lvtt_value
= APIC_LVT_TIMER_PERIODIC
| LOCAL_TIMER_VECTOR
;
666 apic_write_around(APIC_LVTT
, lvtt_value
);
671 tmp_value
= apic_read(APIC_TDCR
);
672 apic_write_around(APIC_TDCR
, (tmp_value
673 & ~(APIC_TDR_DIV_1
| APIC_TDR_DIV_TMBASE
))
676 apic_write_around(APIC_TMICT
, clocks
/APIC_DIVISOR
);
679 static void setup_APIC_timer(unsigned int clocks
)
683 local_irq_save(flags
);
685 /* For some reasons this doesn't work on Simics, so fake it for now */
686 if (!strstr(boot_cpu_data
.x86_model_id
, "Screwdriver")) {
687 __setup_APIC_LVTT(clocks
);
691 /* wait for irq slice */
692 if (vxtime
.hpet_address
) {
693 int trigger
= hpet_readl(HPET_T0_CMP
);
694 while (hpet_readl(HPET_COUNTER
) >= trigger
)
696 while (hpet_readl(HPET_COUNTER
) < trigger
)
702 c2
|= inb_p(0x40) << 8;
707 c2
|= inb_p(0x40) << 8;
708 } while (c2
- c1
< 300);
711 __setup_APIC_LVTT(clocks
);
713 local_irq_restore(flags
);
717 * In this function we calibrate APIC bus clocks to the external
718 * timer. Unfortunately we cannot use jiffies and the timer irq
719 * to calibrate, since some later bootup code depends on getting
720 * the first irq? Ugh.
722 * We want to do the calibration only once since we
723 * want to have local timer irqs syncron. CPUs connected
724 * by the same APIC bus have the very same bus frequency.
725 * And we want to have irqs off anyways, no accidental
729 #define TICK_COUNT 100000000
731 static int __init
calibrate_APIC_clock(void)
733 int apic
, apic_start
, tsc
, tsc_start
;
736 * Put whatever arbitrary (but long enough) timeout
737 * value into the APIC clock, we just want to get the
738 * counter running for calibration.
740 __setup_APIC_LVTT(1000000000);
742 apic_start
= apic_read(APIC_TMCCT
);
746 apic
= apic_read(APIC_TMCCT
);
748 } while ((tsc
- tsc_start
) < TICK_COUNT
&& (apic
- apic_start
) < TICK_COUNT
);
750 result
= (apic_start
- apic
) * 1000L * cpu_khz
/ (tsc
- tsc_start
);
752 printk(KERN_INFO
"Detected %d.%03d MHz APIC timer.\n",
753 result
/ 1000 / 1000, result
/ 1000 % 1000);
755 return result
* APIC_DIVISOR
/ HZ
;
758 static unsigned int calibration_result
;
760 void __init
setup_boot_APIC_clock (void)
762 if (disable_apic_timer
) {
763 printk(KERN_INFO
"Disabling APIC timer\n");
767 printk(KERN_INFO
"Using local APIC timer interrupts.\n");
768 using_apic_timer
= 1;
772 calibration_result
= calibrate_APIC_clock();
774 * Now set up the timer for real.
776 setup_APIC_timer(calibration_result
);
781 void __cpuinit
setup_secondary_APIC_clock(void)
783 local_irq_disable(); /* FIXME: Do we need this? --RR */
784 setup_APIC_timer(calibration_result
);
788 void __cpuinit
disable_APIC_timer(void)
790 if (using_apic_timer
) {
793 v
= apic_read(APIC_LVTT
);
794 apic_write_around(APIC_LVTT
, v
| APIC_LVT_MASKED
);
798 void enable_APIC_timer(void)
800 if (using_apic_timer
) {
803 v
= apic_read(APIC_LVTT
);
804 apic_write_around(APIC_LVTT
, v
& ~APIC_LVT_MASKED
);
809 * the frequency of the profiling timer can be changed
810 * by writing a multiplier value into /proc/profile.
812 int setup_profiling_timer(unsigned int multiplier
)
817 * Sanity check. [at least 500 APIC cycles should be
818 * between APIC interrupts as a rule of thumb, to avoid
821 if ( (!multiplier
) || (calibration_result
/multiplier
< 500))
825 * Set the new multiplier for each CPU. CPUs don't start using the
826 * new values until the next timer interrupt in which they do process
827 * accounting. At that time they also adjust their APIC timers
830 for (i
= 0; i
< NR_CPUS
; ++i
)
831 per_cpu(prof_multiplier
, i
) = multiplier
;
839 * Local timer interrupt handler. It does both profiling and
840 * process statistics/rescheduling.
842 * We do profiling in every local tick, statistics/rescheduling
843 * happen only every 'profiling multiplier' ticks. The default
844 * multiplier is 1 and it can be changed by writing the new multiplier
845 * value into /proc/profile.
848 void smp_local_timer_interrupt(struct pt_regs
*regs
)
850 int cpu
= smp_processor_id();
852 profile_tick(CPU_PROFILING
, regs
);
853 if (--per_cpu(prof_counter
, cpu
) <= 0) {
855 * The multiplier may have changed since the last time we got
856 * to this point as a result of the user writing to
857 * /proc/profile. In this case we need to adjust the APIC
860 * Interrupts are already masked off at this point.
862 per_cpu(prof_counter
, cpu
) = per_cpu(prof_multiplier
, cpu
);
863 if (per_cpu(prof_counter
, cpu
) !=
864 per_cpu(prof_old_multiplier
, cpu
)) {
865 __setup_APIC_LVTT(calibration_result
/
866 per_cpu(prof_counter
, cpu
));
867 per_cpu(prof_old_multiplier
, cpu
) =
868 per_cpu(prof_counter
, cpu
);
872 update_process_times(user_mode(regs
));
877 * We take the 'long' return path, and there every subsystem
878 * grabs the appropriate locks (kernel lock/ irq lock).
880 * we might want to decouple profiling from the 'long path',
881 * and do the profiling totally in assembly.
883 * Currently this isn't too much of an issue (performance wise),
884 * we can take more than 100K local irqs per second on a 100 MHz P5.
889 * Local APIC timer interrupt. This is the most natural way for doing
890 * local interrupts, but local timer interrupts can be emulated by
891 * broadcast interrupts too. [in case the hw doesn't support APIC timers]
893 * [ if a single-CPU system runs an SMP kernel then we call the local
894 * interrupt as well. Thus we cannot inline the local irq ... ]
896 void smp_apic_timer_interrupt(struct pt_regs
*regs
)
899 * the NMI deadlock-detector uses this.
901 add_pda(apic_timer_irqs
, 1);
904 * NOTE! We'd better ACK the irq immediately,
905 * because timer handling can be slow.
909 * update_process_times() expects us to have done irq_enter().
910 * Besides, if we don't timer interrupts ignore the global
911 * interrupt lock, which is the WrongThing (tm) to do.
914 smp_local_timer_interrupt(regs
);
919 * oem_force_hpet_timer -- force HPET mode for some boxes.
921 * Thus far, the major user of this is IBM's Summit2 series:
923 * Clustered boxes may have unsynced TSC problems if they are
924 * multi-chassis. Use available data to take a good guess.
925 * If in doubt, go HPET.
927 __init
int oem_force_hpet_timer(void)
929 int i
, clusters
, zeros
;
931 DECLARE_BITMAP(clustermap
, NUM_APIC_CLUSTERS
);
933 bitmap_zero(clustermap
, NUM_APIC_CLUSTERS
);
935 for (i
= 0; i
< NR_CPUS
; i
++) {
936 id
= bios_cpu_apicid
[i
];
937 if (id
!= BAD_APICID
)
938 __set_bit(APIC_CLUSTERID(id
), clustermap
);
941 /* Problem: Partially populated chassis may not have CPUs in some of
942 * the APIC clusters they have been allocated. Only present CPUs have
943 * bios_cpu_apicid entries, thus causing zeroes in the bitmap. Since
944 * clusters are allocated sequentially, count zeros only if they are
949 for (i
= 0; i
< NUM_APIC_CLUSTERS
; i
++) {
950 if (test_bit(i
, clustermap
)) {
951 clusters
+= 1 + zeros
;
958 * If clusters > 2, then should be multi-chassis. Return 1 for HPET.
959 * Else return 0 to use TSC.
960 * May have to revisit this when multi-core + hyperthreaded CPUs come
961 * out, but AFAIK this will work even for them.
963 return (clusters
> 2);
967 * This interrupt should _never_ happen with our APIC/SMP architecture
969 asmlinkage
void smp_spurious_interrupt(void)
974 * Check if this really is a spurious interrupt and ACK it
975 * if it is a vectored one. Just in case...
976 * Spurious interrupts should not be ACKed.
978 v
= apic_read(APIC_ISR
+ ((SPURIOUS_APIC_VECTOR
& ~0x1f) >> 1));
979 if (v
& (1 << (SPURIOUS_APIC_VECTOR
& 0x1f)))
983 static unsigned long last_warning
;
984 static unsigned long skipped
;
986 /* see sw-dev-man vol 3, chapter 7.4.13.5 */
987 if (time_before(last_warning
+30*HZ
,jiffies
)) {
988 printk(KERN_INFO
"spurious APIC interrupt on CPU#%d, %ld skipped.\n",
989 smp_processor_id(), skipped
);
990 last_warning
= jiffies
;
1000 * This interrupt should never happen with our APIC/SMP architecture
1003 asmlinkage
void smp_error_interrupt(void)
1008 /* First tickle the hardware, only then report what went on. -- REW */
1009 v
= apic_read(APIC_ESR
);
1010 apic_write(APIC_ESR
, 0);
1011 v1
= apic_read(APIC_ESR
);
1013 atomic_inc(&irq_err_count
);
1015 /* Here is what the APIC error bits mean:
1018 2: Send accept error
1019 3: Receive accept error
1021 5: Send illegal vector
1022 6: Received illegal vector
1023 7: Illegal register address
1025 printk (KERN_DEBUG
"APIC error on CPU%d: %02x(%02x)\n",
1026 smp_processor_id(), v
, v1
);
1033 * This initializes the IO-APIC and APIC hardware if this is
1036 int __init
APIC_init_uniprocessor (void)
1039 printk(KERN_INFO
"Apic disabled\n");
1042 if (!cpu_has_apic
) {
1044 printk(KERN_INFO
"Apic disabled by BIOS\n");
1048 verify_local_APIC();
1052 phys_cpu_present_map
= physid_mask_of_physid(boot_cpu_id
);
1053 apic_write_around(APIC_ID
, boot_cpu_id
);
1057 #ifdef CONFIG_X86_IO_APIC
1058 if (smp_found_config
&& !skip_ioapic_setup
&& nr_ioapics
)
1063 setup_boot_APIC_clock();
1064 check_nmi_watchdog();
1068 static __init
int setup_disableapic(char *str
)
1074 static __init
int setup_nolapic(char *str
)
1080 static __init
int setup_noapictimer(char *str
)
1082 disable_apic_timer
= 1;
1086 /* dummy parsing: see setup.c */
1088 __setup("disableapic", setup_disableapic
);
1089 __setup("nolapic", setup_nolapic
); /* same as disableapic, for compatibility */
1091 __setup("noapictimer", setup_noapictimer
);
1093 /* no "lapic" flag - we only use the lapic when the BIOS tells us so. */