drivers/media/dvb/frontends/mt312.c

   1 /*
   2     Driver for Zarlink VP310/MT312 Satellite Channel Decoder
   3
   4     Copyright (C) 2003 Andreas Oberritter <obi@linuxtv.org>
   5
   6     This program is free software; you can redistribute it and/or modify
   7     it under the terms of the GNU General Public License as published by
   8     the Free Software Foundation; either version 2 of the License, or
   9     (at your option) any later version.
  10
  11     This program is distributed in the hope that it will be useful,
  12     but WITHOUT ANY WARRANTY; without even the implied warranty of
  13     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14
  15     GNU General Public License for more details.
  16
  17     You should have received a copy of the GNU General Public License
  18     along with this program; if not, write to the Free Software
  19     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  20
  21     References:
  22     http://products.zarlink.com/product_profiles/MT312.htm
  23     http://products.zarlink.com/product_profiles/SL1935.htm
  24 */
  25
  26 #include <linux/delay.h>
  27 #include <linux/errno.h>
  28 #include <linux/init.h>
  29 #include <linux/kernel.h>
  30 #include <linux/module.h>
  31 #include <linux/string.h>
  32 #include <linux/slab.h>
  33
  34 #include "dvb_frontend.h"
  35 #include "mt312_priv.h"
  36 #include "mt312.h"
  37
  38
  39 struct mt312_state {
  40         struct i2c_adapter* i2c;
  41         /* configuration settings */
  42         const struct mt312_config* config;
  43         struct dvb_frontend frontend;
  44
  45         u8 id;
  46         u8 frequency;
  47 };
  48
  49 static int debug;
  50 #define dprintk(args...) \
  51         do { \
  52                 if (debug) printk(KERN_DEBUG "mt312: " args); \
  53         } while (0)
  54
  55 #define MT312_SYS_CLK           90000000UL      /* 90 MHz */
  56 #define MT312_LPOWER_SYS_CLK    60000000UL      /* 60 MHz */
  57 #define MT312_PLL_CLK           10000000UL      /* 10 MHz */
  58
  59 static int mt312_read(struct mt312_state* state, const enum mt312_reg_addr reg,
  60                       void *buf, const size_t count)
  61 {
  62         int ret;
  63         struct i2c_msg msg[2];
  64         u8 regbuf[1] = { reg };
  65
  66         msg[0].addr = state->config->demod_address;
  67         msg[0].flags = 0;
  68         msg[0].buf = regbuf;
  69         msg[0].len = 1;
  70         msg[1].addr = state->config->demod_address;
  71         msg[1].flags = I2C_M_RD;
  72         msg[1].buf = buf;
  73         msg[1].len = count;
  74
  75         ret = i2c_transfer(state->i2c, msg, 2);
  76
  77         if (ret != 2) {
  78                 printk(KERN_ERR "%s: ret == %d\n", __FUNCTION__, ret);
  79                 return -EREMOTEIO;
  80         }
  81
  82         if(debug) {
  83                 int i;
  84                 dprintk("R(%d):", reg & 0x7f);
  85                 for (i = 0; i < count; i++)
  86                         printk(" %02x", ((const u8 *) buf)[i]);
  87                 printk("\n");
  88         }
  89
  90         return 0;
  91 }
  92
  93 static int mt312_write(struct mt312_state* state, const enum mt312_reg_addr reg,
  94                        const void *src, const size_t count)
  95 {
  96         int ret;
  97         u8 buf[count + 1];
  98         struct i2c_msg msg;
  99
 100         if(debug) {
 101                 int i;
 102                 dprintk("W(%d):", reg & 0x7f);
 103                 for (i = 0; i < count; i++)
 104                         printk(" %02x", ((const u8 *) src)[i]);
 105                 printk("\n");
 106         }
 107
 108         buf[0] = reg;
 109         memcpy(&buf[1], src, count);
 110
 111         msg.addr = state->config->demod_address;
 112         msg.flags = 0;
 113         msg.buf = buf;
 114         msg.len = count + 1;
 115
 116         ret = i2c_transfer(state->i2c, &msg, 1);
 117
 118         if (ret != 1) {
 119                 dprintk("%s: ret == %d\n", __FUNCTION__, ret);
 120                 return -EREMOTEIO;
 121         }
 122
 123         return 0;
 124 }
 125
 126 static inline int mt312_readreg(struct mt312_state* state,
 127                                 const enum mt312_reg_addr reg, u8 *val)
 128 {
 129         return mt312_read(state, reg, val, 1);
 130 }
 131
 132 static inline int mt312_writereg(struct mt312_state* state,
 133                                  const enum mt312_reg_addr reg, const u8 val)
 134 {
 135         return mt312_write(state, reg, &val, 1);
 136 }
 137
 138 static inline u32 mt312_div(u32 a, u32 b)
 139 {
 140         return (a + (b / 2)) / b;
 141 }
 142
 143 static int mt312_reset(struct mt312_state* state, const u8 full)
 144 {
 145         return mt312_writereg(state, RESET, full ? 0x80 : 0x40);
 146 }
 147
 148 static int mt312_get_inversion(struct mt312_state* state,
 149                                fe_spectral_inversion_t *i)
 150 {
 151         int ret;
 152         u8 vit_mode;
 153
 154         if ((ret = mt312_readreg(state, VIT_MODE, &vit_mode)) < 0)
 155                 return ret;
 156
 157         if (vit_mode & 0x80)    /* auto inversion was used */
 158                 *i = (vit_mode & 0x40) ? INVERSION_ON : INVERSION_OFF;
 159
 160         return 0;
 161 }
 162
 163 static int mt312_get_symbol_rate(struct mt312_state* state, u32 *sr)
 164 {
 165         int ret;
 166         u8 sym_rate_h;
 167         u8 dec_ratio;
 168         u16 sym_rat_op;
 169         u16 monitor;
 170         u8 buf[2];
 171
 172         if ((ret = mt312_readreg(state, SYM_RATE_H, &sym_rate_h)) < 0)
 173                 return ret;
 174
 175         if (sym_rate_h & 0x80) {        /* symbol rate search was used */
 176                 if ((ret = mt312_writereg(state, MON_CTRL, 0x03)) < 0)
 177                         return ret;
 178
 179                 if ((ret = mt312_read(state, MONITOR_H, buf, sizeof(buf))) < 0)
 180                         return ret;
 181
 182                 monitor = (buf[0] << 8) | buf[1];
 183
 184                 dprintk(KERN_DEBUG "sr(auto) = %u\n",
 185                        mt312_div(monitor * 15625, 4));
 186         } else {
 187                 if ((ret = mt312_writereg(state, MON_CTRL, 0x05)) < 0)
 188                         return ret;
 189
 190                 if ((ret = mt312_read(state, MONITOR_H, buf, sizeof(buf))) < 0)
 191                         return ret;
 192
 193                 dec_ratio = ((buf[0] >> 5) & 0x07) * 32;
 194
 195                 if ((ret = mt312_read(state, SYM_RAT_OP_H, buf, sizeof(buf))) < 0)
 196                         return ret;
 197
 198                 sym_rat_op = (buf[0] << 8) | buf[1];
 199
 200                 dprintk(KERN_DEBUG "sym_rat_op=%d dec_ratio=%d\n",
 201                        sym_rat_op, dec_ratio);
 202                 dprintk(KERN_DEBUG "*sr(manual) = %lu\n",
 203                        (((MT312_PLL_CLK * 8192) / (sym_rat_op + 8192)) *
 204                         2) - dec_ratio);
 205         }
 206
 207         return 0;
 208 }
 209
 210 static int mt312_get_code_rate(struct mt312_state* state, fe_code_rate_t *cr)
 211 {
 212         const fe_code_rate_t fec_tab[8] =
 213             { FEC_1_2, FEC_2_3, FEC_3_4, FEC_5_6, FEC_6_7, FEC_7_8,
 214                 FEC_AUTO, FEC_AUTO };
 215
 216         int ret;
 217         u8 fec_status;
 218
 219         if ((ret = mt312_readreg(state, FEC_STATUS, &fec_status)) < 0)
 220                 return ret;
 221
 222         *cr = fec_tab[(fec_status >> 4) & 0x07];
 223
 224         return 0;
 225 }
 226
 227 static int mt312_initfe(struct dvb_frontend* fe)
 228 {
 229         struct mt312_state *state = fe->demodulator_priv;
 230         int ret;
 231         u8 buf[2];
 232
 233         /* wake up */
 234         if ((ret = mt312_writereg(state, CONFIG, (state->frequency == 60 ? 0x88 : 0x8c))) < 0)
 235                 return ret;
 236
 237         /* wait at least 150 usec */
 238         udelay(150);
 239
 240         /* full reset */
 241         if ((ret = mt312_reset(state, 1)) < 0)
 242                 return ret;
 243
 244 // Per datasheet, write correct values. 09/28/03 ACCJr.
 245 // If we don't do this, we won't get FE_HAS_VITERBI in the VP310.
 246         {
 247                 u8 buf_def[8]={0x14, 0x12, 0x03, 0x02, 0x01, 0x00, 0x00, 0x00};
 248
 249                 if ((ret = mt312_write(state, VIT_SETUP, buf_def, sizeof(buf_def))) < 0)
 250                         return ret;
 251         }
 252
 253         /* SYS_CLK */
 254         buf[0] = mt312_div((state->frequency == 60 ? MT312_LPOWER_SYS_CLK : MT312_SYS_CLK) * 2, 1000000);
 255
 256         /* DISEQC_RATIO */
 257         buf[1] = mt312_div(MT312_PLL_CLK, 15000 * 4);
 258
 259         if ((ret = mt312_write(state, SYS_CLK, buf, sizeof(buf))) < 0)
 260                 return ret;
 261
 262         if ((ret = mt312_writereg(state, SNR_THS_HIGH, 0x32)) < 0)
 263                 return ret;
 264
 265         if ((ret = mt312_writereg(state, OP_CTRL, 0x53)) < 0)
 266                 return ret;
 267
 268         /* TS_SW_LIM */
 269         buf[0] = 0x8c;
 270         buf[1] = 0x98;
 271
 272         if ((ret = mt312_write(state, TS_SW_LIM_L, buf, sizeof(buf))) < 0)
 273                 return ret;
 274
 275         if ((ret = mt312_writereg(state, CS_SW_LIM, 0x69)) < 0)
 276                 return ret;
 277
 278         return 0;
 279 }
 280
 281 static int mt312_send_master_cmd(struct dvb_frontend* fe,
 282                                  struct dvb_diseqc_master_cmd *c)
 283 {
 284         struct mt312_state *state = fe->demodulator_priv;
 285         int ret;
 286         u8 diseqc_mode;
 287
 288         if ((c->msg_len == 0) || (c->msg_len > sizeof(c->msg)))
 289                 return -EINVAL;
 290
 291         if ((ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode)) < 0)
 292                 return ret;
 293
 294         if ((ret =
 295              mt312_write(state, (0x80 | DISEQC_INSTR), c->msg, c->msg_len)) < 0)
 296                 return ret;
 297
 298         if ((ret =
 299              mt312_writereg(state, DISEQC_MODE,
 300                             (diseqc_mode & 0x40) | ((c->msg_len - 1) << 3)
 301                             | 0x04)) < 0)
 302                 return ret;
 303
 304         /* set DISEQC_MODE[2:0] to zero if a return message is expected */
 305         if (c->msg[0] & 0x02)
 306                 if ((ret =
 307                      mt312_writereg(state, DISEQC_MODE, (diseqc_mode & 0x40))) < 0)
 308                         return ret;
 309
 310         return 0;
 311 }
 312
 313 static int mt312_send_burst(struct dvb_frontend* fe, const fe_sec_mini_cmd_t c)
 314 {
 315         struct mt312_state *state = fe->demodulator_priv;
 316         const u8 mini_tab[2] = { 0x02, 0x03 };
 317
 318         int ret;
 319         u8 diseqc_mode;
 320
 321         if (c > SEC_MINI_B)
 322                 return -EINVAL;
 323
 324         if ((ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode)) < 0)
 325                 return ret;
 326
 327         if ((ret =
 328              mt312_writereg(state, DISEQC_MODE,
 329                             (diseqc_mode & 0x40) | mini_tab[c])) < 0)
 330                 return ret;
 331
 332         return 0;
 333 }
 334
 335 static int mt312_set_tone(struct dvb_frontend* fe, const fe_sec_tone_mode_t t)
 336 {
 337         struct mt312_state *state = fe->demodulator_priv;
 338         const u8 tone_tab[2] = { 0x01, 0x00 };
 339
 340         int ret;
 341         u8 diseqc_mode;
 342
 343         if (t > SEC_TONE_OFF)
 344                 return -EINVAL;
 345
 346         if ((ret = mt312_readreg(state, DISEQC_MODE, &diseqc_mode)) < 0)
 347                 return ret;
 348
 349         if ((ret =
 350              mt312_writereg(state, DISEQC_MODE,
 351                             (diseqc_mode & 0x40) | tone_tab[t])) < 0)
 352                 return ret;
 353
 354         return 0;
 355 }
 356
 357 static int mt312_set_voltage(struct dvb_frontend* fe, const fe_sec_voltage_t v)
 358 {
 359         struct mt312_state *state = fe->demodulator_priv;
 360         const u8 volt_tab[3] = { 0x00, 0x40, 0x00 };
 361
 362         if (v > SEC_VOLTAGE_OFF)
 363                 return -EINVAL;
 364
 365         return mt312_writereg(state, DISEQC_MODE, volt_tab[v]);
 366 }
 367
 368 static int mt312_read_status(struct dvb_frontend* fe, fe_status_t *s)
 369 {
 370         struct mt312_state *state = fe->demodulator_priv;
 371         int ret;
 372         u8 status[3];
 373
 374         *s = 0;
 375
 376         if ((ret = mt312_read(state, QPSK_STAT_H, status, sizeof(status))) < 0)
 377                 return ret;
 378
 379         dprintk(KERN_DEBUG "QPSK_STAT_H: 0x%02x, QPSK_STAT_L: 0x%02x, FEC_STATUS: 0x%02x\n", status[0], status[1], status[2]);
 380
 381         if (status[0] & 0xc0)
 382                 *s |= FE_HAS_SIGNAL;    /* signal noise ratio */
 383         if (status[0] & 0x04)
 384                 *s |= FE_HAS_CARRIER;   /* qpsk carrier lock */
 385         if (status[2] & 0x02)
 386                 *s |= FE_HAS_VITERBI;   /* viterbi lock */
 387         if (status[2] & 0x04)
 388                 *s |= FE_HAS_SYNC;      /* byte align lock */
 389         if (status[0] & 0x01)
 390                 *s |= FE_HAS_LOCK;      /* qpsk lock */
 391
 392         return 0;
 393 }
 394
 395 static int mt312_read_ber(struct dvb_frontend* fe, u32 *ber)
 396 {
 397         struct mt312_state *state = fe->demodulator_priv;
 398         int ret;
 399         u8 buf[3];
 400
 401         if ((ret = mt312_read(state, RS_BERCNT_H, buf, 3)) < 0)
 402                 return ret;
 403
 404         *ber = ((buf[0] << 16) | (buf[1] << 8) | buf[2]) * 64;
 405
 406         return 0;
 407 }
 408
 409 static int mt312_read_signal_strength(struct dvb_frontend* fe, u16 *signal_strength)
 410 {
 411         struct mt312_state *state = fe->demodulator_priv;
 412         int ret;
 413         u8 buf[3];
 414         u16 agc;
 415         s16 err_db;
 416
 417         if ((ret = mt312_read(state, AGC_H, buf, sizeof(buf))) < 0)
 418                 return ret;
 419
 420         agc = (buf[0] << 6) | (buf[1] >> 2);
 421         err_db = (s16) (((buf[1] & 0x03) << 14) | buf[2] << 6) >> 6;
 422
 423         *signal_strength = agc;
 424
 425         dprintk(KERN_DEBUG "agc=%08x err_db=%hd\n", agc, err_db);
 426
 427         return 0;
 428 }
 429
 430 static int mt312_read_snr(struct dvb_frontend* fe, u16 *snr)
 431 {
 432         struct mt312_state *state = fe->demodulator_priv;
 433         int ret;
 434         u8 buf[2];
 435
 436         if ((ret = mt312_read(state, M_SNR_H, &buf, sizeof(buf))) < 0)
 437                 return ret;
 438
 439         *snr = 0xFFFF - ((((buf[0] & 0x7f) << 8) | buf[1]) << 1);
 440
 441         return 0;
 442 }
 443
 444 static int mt312_read_ucblocks(struct dvb_frontend* fe, u32 *ubc)
 445 {
 446         struct mt312_state *state = fe->demodulator_priv;
 447         int ret;
 448         u8 buf[2];
 449
 450         if ((ret = mt312_read(state, RS_UBC_H, &buf, sizeof(buf))) < 0)
 451                 return ret;
 452
 453         *ubc = (buf[0] << 8) | buf[1];
 454
 455         return 0;
 456 }
 457
 458 static int mt312_set_frontend(struct dvb_frontend* fe,
 459                               struct dvb_frontend_parameters *p)
 460 {
 461         struct mt312_state *state = fe->demodulator_priv;
 462         int ret;
 463         u8 buf[5], config_val;
 464         u16 sr;
 465
 466         const u8 fec_tab[10] =
 467             { 0x00, 0x01, 0x02, 0x04, 0x3f, 0x08, 0x10, 0x20, 0x3f, 0x3f };
 468         const u8 inv_tab[3] = { 0x00, 0x40, 0x80 };
 469
 470         dprintk("%s: Freq %d\n", __FUNCTION__, p->frequency);
 471
 472         if ((p->frequency < fe->ops.info.frequency_min)
 473             || (p->frequency > fe->ops.info.frequency_max))
 474                 return -EINVAL;
 475
 476         if ((p->inversion < INVERSION_OFF)
 477             || (p->inversion > INVERSION_ON))
 478                 return -EINVAL;
 479
 480         if ((p->u.qpsk.symbol_rate < fe->ops.info.symbol_rate_min)
 481             || (p->u.qpsk.symbol_rate > fe->ops.info.symbol_rate_max))
 482                 return -EINVAL;
 483
 484         if ((p->u.qpsk.fec_inner < FEC_NONE)
 485             || (p->u.qpsk.fec_inner > FEC_AUTO))
 486                 return -EINVAL;
 487
 488         if ((p->u.qpsk.fec_inner == FEC_4_5)
 489             || (p->u.qpsk.fec_inner == FEC_8_9))
 490                 return -EINVAL;
 491
 492         switch (state->id) {
 493         case ID_VP310:
 494         // For now we will do this only for the VP310.
 495         // It should be better for the mt312 as well, but tunning will be slower. ACCJr 09/29/03
 496                 ret = mt312_readreg(state, CONFIG, &config_val);
 497                 if (ret < 0)
 498                         return ret;
 499                 if (p->u.qpsk.symbol_rate >= 30000000) //Note that 30MS/s should use 90MHz
 500                 {
 501                         if ((config_val & 0x0c) == 0x08) { //We are running 60MHz
 502                                 state->frequency = 90;
 503                                 if ((ret = mt312_initfe(fe)) < 0)
 504                                         return ret;
 505                         }
 506                 }
 507                 else
 508                 {
 509                         if ((config_val & 0x0c) == 0x0C) { //We are running 90MHz
 510                                 state->frequency = 60;
 511                                 if ((ret = mt312_initfe(fe)) < 0)
 512                                         return ret;
 513                         }
 514                 }
 515                 break;
 516
 517         case ID_MT312:
 518                 break;
 519
 520         default:
 521                 return -EINVAL;
 522         }
 523
 524         if (fe->ops.tuner_ops.set_params) {
 525                 fe->ops.tuner_ops.set_params(fe, p);
 526                 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);
 527         }
 528
 529         /* sr = (u16)(sr * 256.0 / 1000000.0) */
 530         sr = mt312_div(p->u.qpsk.symbol_rate * 4, 15625);
 531
 532         /* SYM_RATE */
 533         buf[0] = (sr >> 8) & 0x3f;
 534         buf[1] = (sr >> 0) & 0xff;
 535
 536         /* VIT_MODE */
 537         buf[2] = inv_tab[p->inversion] | fec_tab[p->u.qpsk.fec_inner];
 538
 539         /* QPSK_CTRL */
 540         buf[3] = 0x40;          /* swap I and Q before QPSK demodulation */
 541
 542         if (p->u.qpsk.symbol_rate < 10000000)
 543                 buf[3] |= 0x04; /* use afc mode */
 544
 545         /* GO */
 546         buf[4] = 0x01;
 547
 548         if ((ret = mt312_write(state, SYM_RATE_H, buf, sizeof(buf))) < 0)
 549                 return ret;
 550
 551         mt312_reset(state, 0);
 552
 553         return 0;
 554 }
 555
 556 static int mt312_get_frontend(struct dvb_frontend* fe,
 557                               struct dvb_frontend_parameters *p)
 558 {
 559         struct mt312_state *state = fe->demodulator_priv;
 560         int ret;
 561
 562         if ((ret = mt312_get_inversion(state, &p->inversion)) < 0)
 563                 return ret;
 564
 565         if ((ret = mt312_get_symbol_rate(state, &p->u.qpsk.symbol_rate)) < 0)
 566                 return ret;
 567
 568         if ((ret = mt312_get_code_rate(state, &p->u.qpsk.fec_inner)) < 0)
 569                 return ret;
 570
 571         return 0;
 572 }
 573
 574 static int mt312_i2c_gate_ctrl(struct dvb_frontend* fe, int enable)
 575 {
 576         struct mt312_state* state = fe->demodulator_priv;
 577
 578         if (enable) {
 579                 return mt312_writereg(state, GPP_CTRL, 0x40);
 580         } else {
 581                 return mt312_writereg(state, GPP_CTRL, 0x00);
 582         }
 583 }
 584
 585 static int mt312_sleep(struct dvb_frontend* fe)
 586 {
 587         struct mt312_state *state = fe->demodulator_priv;
 588         int ret;
 589         u8 config;
 590
 591         /* reset all registers to defaults */
 592         if ((ret = mt312_reset(state, 1)) < 0)
 593                 return ret;
 594
 595         if ((ret = mt312_readreg(state, CONFIG, &config)) < 0)
 596                 return ret;
 597
 598         /* enter standby */
 599         if ((ret = mt312_writereg(state, CONFIG, config & 0x7f)) < 0)
 600                 return ret;
 601
 602         return 0;
 603 }
 604
 605 static int mt312_get_tune_settings(struct dvb_frontend* fe, struct dvb_frontend_tune_settings* fesettings)
 606 {
 607         fesettings->min_delay_ms = 50;
 608         fesettings->step_size = 0;
 609         fesettings->max_drift = 0;
 610         return 0;
 611 }
 612
 613 static void mt312_release(struct dvb_frontend* fe)
 614 {
 615         struct mt312_state* state = fe->demodulator_priv;
 616         kfree(state);
 617 }
 618
 619 static struct dvb_frontend_ops vp310_mt312_ops = {
 620
 621         .info = {
 622                 .name = "Zarlink ???? DVB-S",
 623                 .type = FE_QPSK,
 624                 .frequency_min = 950000,
 625                 .frequency_max = 2150000,
 626                 .frequency_stepsize = (MT312_PLL_CLK / 1000) / 128,
 627                 .symbol_rate_min = MT312_SYS_CLK / 128,
 628                 .symbol_rate_max = MT312_SYS_CLK / 2,
 629                 .caps =
 630                     FE_CAN_FEC_1_2 | FE_CAN_FEC_2_3 |
 631                     FE_CAN_FEC_3_4 | FE_CAN_FEC_5_6 | FE_CAN_FEC_7_8 |
 632                     FE_CAN_FEC_AUTO | FE_CAN_QPSK | FE_CAN_MUTE_TS |
 633                     FE_CAN_RECOVER
 634         },
 635
 636         .release = mt312_release,
 637
 638         .init = mt312_initfe,
 639         .sleep = mt312_sleep,
 640         .i2c_gate_ctrl = mt312_i2c_gate_ctrl,
 641
 642         .set_frontend = mt312_set_frontend,
 643         .get_frontend = mt312_get_frontend,
 644         .get_tune_settings = mt312_get_tune_settings,
 645
 646         .read_status = mt312_read_status,
 647         .read_ber = mt312_read_ber,
 648         .read_signal_strength = mt312_read_signal_strength,
 649         .read_snr = mt312_read_snr,
 650         .read_ucblocks = mt312_read_ucblocks,
 651
 652         .diseqc_send_master_cmd = mt312_send_master_cmd,
 653         .diseqc_send_burst = mt312_send_burst,
 654         .set_tone = mt312_set_tone,
 655         .set_voltage = mt312_set_voltage,
 656 };
 657
 658 struct dvb_frontend* vp310_mt312_attach(const struct mt312_config* config,
 659                                         struct i2c_adapter* i2c)
 660 {
 661         struct mt312_state* state = NULL;
 662
 663         /* allocate memory for the internal state */
 664         state = kmalloc(sizeof(struct mt312_state), GFP_KERNEL);
 665         if (state == NULL)
 666                 goto error;
 667
 668         /* setup the state */
 669         state->config = config;
 670         state->i2c = i2c;
 671
 672         /* check if the demod is there */
 673         if (mt312_readreg(state, ID, &state->id) < 0)
 674                 goto error;
 675
 676         /* create dvb_frontend */
 677         memcpy(&state->frontend.ops, &vp310_mt312_ops, sizeof(struct dvb_frontend_ops));
 678         state->frontend.demodulator_priv = state;
 679
 680         switch (state->id) {
 681         case ID_VP310:
 682                 strcpy(state->frontend.ops.info.name, "Zarlink VP310 DVB-S");
 683                 state->frequency = 90;
 684                 break;
 685         case ID_MT312:
 686                 strcpy(state->frontend.ops.info.name, "Zarlink MT312 DVB-S");
 687                 state->frequency = 60;
 688                 break;
 689         default:
 690                 printk (KERN_WARNING "Only Zarlink VP310/MT312 are supported chips.\n");
 691                 goto error;
 692         }
 693
 694         return &state->frontend;
 695
 696 error:
 697         kfree(state);
 698         return NULL;
 699 }
 700
 701 module_param(debug, int, 0644);
 702 MODULE_PARM_DESC(debug, "Turn on/off frontend debugging (default:off).");
 703
 704 MODULE_DESCRIPTION("Zarlink VP310/MT312 DVB-S Demodulator driver");
 705 MODULE_AUTHOR("Andreas Oberritter <obi@linuxtv.org>");
 706 MODULE_LICENSE("GPL");
 707
 708 EXPORT_SYMBOL(vp310_mt312_attach);