?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
V4L/DVB (6715): ivtv: Remove unnecessary register update
[linux-2.6/verdex.git] / drivers / media / video / pvrusb2 / pvrusb2-hdw.c
blob54d2c4ab7a318278170df4ab1234b7b62ff174d5
1 /*
2 *
3 * $Id$
4 *
5 * Copyright (C) 2005 Mike Isely <isely@pobox.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 *
20 */
21
22 #include <linux/errno.h>
23 #include <linux/string.h>
24 #include <linux/slab.h>
25 #include <linux/firmware.h>
26 #include <linux/videodev2.h>
27 #include <media/v4l2-common.h>
28 #include <asm/semaphore.h>
29 #include "pvrusb2.h"
30 #include "pvrusb2-std.h"
31 #include "pvrusb2-util.h"
32 #include "pvrusb2-hdw.h"
33 #include "pvrusb2-i2c-core.h"
34 #include "pvrusb2-tuner.h"
35 #include "pvrusb2-eeprom.h"
36 #include "pvrusb2-hdw-internal.h"
37 #include "pvrusb2-encoder.h"
38 #include "pvrusb2-debug.h"
39 #include "pvrusb2-fx2-cmd.h"
40
41 #define TV_MIN_FREQ 55250000L
42 #define TV_MAX_FREQ 850000000L
43
44 static struct pvr2_hdw *unit_pointers[PVR_NUM] = {[ 0 ... PVR_NUM-1 ] = NULL};
45 static DEFINE_MUTEX(pvr2_unit_mtx);
46
47 static int ctlchg = 0;
48 static int initusbreset = 1;
49 static int procreload = 0;
50 static int tuner[PVR_NUM] = { [0 ... PVR_NUM-1] = -1 };
51 static int tolerance[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
52 static int video_std[PVR_NUM] = { [0 ... PVR_NUM-1] = 0 };
53 static int init_pause_msec = 0;
54
55 module_param(ctlchg, int, S_IRUGO|S_IWUSR);
56 MODULE_PARM_DESC(ctlchg, "0=optimize ctl change 1=always accept new ctl value");
57 module_param(init_pause_msec, int, S_IRUGO|S_IWUSR);
58 MODULE_PARM_DESC(init_pause_msec, "hardware initialization settling delay");
59 module_param(initusbreset, int, S_IRUGO|S_IWUSR);
60 MODULE_PARM_DESC(initusbreset, "Do USB reset device on probe");
61 module_param(procreload, int, S_IRUGO|S_IWUSR);
62 MODULE_PARM_DESC(procreload,
63 "Attempt init failure recovery with firmware reload");
64 module_param_array(tuner, int, NULL, 0444);
65 MODULE_PARM_DESC(tuner,"specify installed tuner type");
66 module_param_array(video_std, int, NULL, 0444);
67 MODULE_PARM_DESC(video_std,"specify initial video standard");
68 module_param_array(tolerance, int, NULL, 0444);
69 MODULE_PARM_DESC(tolerance,"specify stream error tolerance");
70
71 #define PVR2_CTL_WRITE_ENDPOINT 0x01
72 #define PVR2_CTL_READ_ENDPOINT 0x81
73
74 #define PVR2_GPIO_IN 0x9008
75 #define PVR2_GPIO_OUT 0x900c
76 #define PVR2_GPIO_DIR 0x9020
77
78 #define trace_firmware(...) pvr2_trace(PVR2_TRACE_FIRMWARE,__VA_ARGS__)
79
80 #define PVR2_FIRMWARE_ENDPOINT 0x02
81
82 /* size of a firmware chunk */
83 #define FIRMWARE_CHUNK_SIZE 0x2000
84
85 /* Define the list of additional controls we'll dynamically construct based
86 on query of the cx2341x module. */
87 struct pvr2_mpeg_ids {
88 const char *strid;
89 int id;
90 };
91 static const struct pvr2_mpeg_ids mpeg_ids[] = {
92 {
93 .strid = "audio_layer",
94 .id = V4L2_CID_MPEG_AUDIO_ENCODING,
95 },{
96 .strid = "audio_bitrate",
97 .id = V4L2_CID_MPEG_AUDIO_L2_BITRATE,
98 },{
99 /* Already using audio_mode elsewhere :-( */
100 .strid = "mpeg_audio_mode",
101 .id = V4L2_CID_MPEG_AUDIO_MODE,
102 },{
103 .strid = "mpeg_audio_mode_extension",
104 .id = V4L2_CID_MPEG_AUDIO_MODE_EXTENSION,
105 },{
106 .strid = "audio_emphasis",
107 .id = V4L2_CID_MPEG_AUDIO_EMPHASIS,
108 },{
109 .strid = "audio_crc",
110 .id = V4L2_CID_MPEG_AUDIO_CRC,
111 },{
112 .strid = "video_aspect",
113 .id = V4L2_CID_MPEG_VIDEO_ASPECT,
114 },{
115 .strid = "video_b_frames",
116 .id = V4L2_CID_MPEG_VIDEO_B_FRAMES,
117 },{
118 .strid = "video_gop_size",
119 .id = V4L2_CID_MPEG_VIDEO_GOP_SIZE,
120 },{
121 .strid = "video_gop_closure",
122 .id = V4L2_CID_MPEG_VIDEO_GOP_CLOSURE,
123 },{
124 .strid = "video_bitrate_mode",
125 .id = V4L2_CID_MPEG_VIDEO_BITRATE_MODE,
126 },{
127 .strid = "video_bitrate",
128 .id = V4L2_CID_MPEG_VIDEO_BITRATE,
129 },{
130 .strid = "video_bitrate_peak",
131 .id = V4L2_CID_MPEG_VIDEO_BITRATE_PEAK,
132 },{
133 .strid = "video_temporal_decimation",
134 .id = V4L2_CID_MPEG_VIDEO_TEMPORAL_DECIMATION,
135 },{
136 .strid = "stream_type",
137 .id = V4L2_CID_MPEG_STREAM_TYPE,
138 },{
139 .strid = "video_spatial_filter_mode",
140 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER_MODE,
141 },{
142 .strid = "video_spatial_filter",
143 .id = V4L2_CID_MPEG_CX2341X_VIDEO_SPATIAL_FILTER,
144 },{
145 .strid = "video_luma_spatial_filter_type",
146 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_SPATIAL_FILTER_TYPE,
147 },{
148 .strid = "video_chroma_spatial_filter_type",
149 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_SPATIAL_FILTER_TYPE,
150 },{
151 .strid = "video_temporal_filter_mode",
152 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER_MODE,
153 },{
154 .strid = "video_temporal_filter",
155 .id = V4L2_CID_MPEG_CX2341X_VIDEO_TEMPORAL_FILTER,
156 },{
157 .strid = "video_median_filter_type",
158 .id = V4L2_CID_MPEG_CX2341X_VIDEO_MEDIAN_FILTER_TYPE,
159 },{
160 .strid = "video_luma_median_filter_top",
161 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_TOP,
162 },{
163 .strid = "video_luma_median_filter_bottom",
164 .id = V4L2_CID_MPEG_CX2341X_VIDEO_LUMA_MEDIAN_FILTER_BOTTOM,
165 },{
166 .strid = "video_chroma_median_filter_top",
167 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_TOP,
168 },{
169 .strid = "video_chroma_median_filter_bottom",
170 .id = V4L2_CID_MPEG_CX2341X_VIDEO_CHROMA_MEDIAN_FILTER_BOTTOM,
171 }
172 };
173 #define MPEGDEF_COUNT ARRAY_SIZE(mpeg_ids)
174
175
176 static const char *control_values_srate[] = {
177 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_44100] = "44.1 kHz",
178 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000] = "48 kHz",
179 [V4L2_MPEG_AUDIO_SAMPLING_FREQ_32000] = "32 kHz",
180 };
181
182
183
184 static const char *control_values_input[] = {
185 [PVR2_CVAL_INPUT_TV] = "television", /*xawtv needs this name*/
186 [PVR2_CVAL_INPUT_RADIO] = "radio",
187 [PVR2_CVAL_INPUT_SVIDEO] = "s-video",
188 [PVR2_CVAL_INPUT_COMPOSITE] = "composite",
189 };
190
191
192 static const char *control_values_audiomode[] = {
193 [V4L2_TUNER_MODE_MONO] = "Mono",
194 [V4L2_TUNER_MODE_STEREO] = "Stereo",
195 [V4L2_TUNER_MODE_LANG1] = "Lang1",
196 [V4L2_TUNER_MODE_LANG2] = "Lang2",
197 [V4L2_TUNER_MODE_LANG1_LANG2] = "Lang1+Lang2",
198 };
199
200
201 static const char *control_values_hsm[] = {
202 [PVR2_CVAL_HSM_FAIL] = "Fail",
203 [PVR2_CVAL_HSM_HIGH] = "High",
204 [PVR2_CVAL_HSM_FULL] = "Full",
205 };
206
207
208 static const char *pvr2_state_names[] = {
209 [PVR2_STATE_NONE] = "none",
210 [PVR2_STATE_DEAD] = "dead",
211 [PVR2_STATE_COLD] = "cold",
212 [PVR2_STATE_WARM] = "warm",
213 [PVR2_STATE_ERROR] = "error",
214 [PVR2_STATE_READY] = "ready",
215 [PVR2_STATE_RUN] = "run",
216 };
217
218
219 static void pvr2_hdw_state_sched(struct pvr2_hdw *);
220 static int pvr2_hdw_state_eval(struct pvr2_hdw *);
221 static void pvr2_hdw_set_cur_freq(struct pvr2_hdw *,unsigned long);
222 static void pvr2_hdw_worker_i2c(struct work_struct *work);
223 static void pvr2_hdw_worker_poll(struct work_struct *work);
224 static void pvr2_hdw_worker_init(struct work_struct *work);
225 static int pvr2_hdw_wait(struct pvr2_hdw *,int state);
226 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *);
227 static void pvr2_hdw_state_log_state(struct pvr2_hdw *);
228 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl);
229 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw);
230 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw);
231 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw);
232 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw);
233 static void pvr2_hdw_quiescent_timeout(unsigned long);
234 static void pvr2_hdw_encoder_wait_timeout(unsigned long);
235 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
236 unsigned int timeout,int probe_fl,
237 void *write_data,unsigned int write_len,
238 void *read_data,unsigned int read_len);
239
240
241 static void trace_stbit(const char *name,int val)
242 {
243 pvr2_trace(PVR2_TRACE_STBITS,
244 "State bit %s <-- %s",
245 name,(val ? "true" : "false"));
246 }
247
248 static int ctrl_channelfreq_get(struct pvr2_ctrl *cptr,int *vp)
249 {
250 struct pvr2_hdw *hdw = cptr->hdw;
251 if ((hdw->freqProgSlot > 0) && (hdw->freqProgSlot <= FREQTABLE_SIZE)) {
252 *vp = hdw->freqTable[hdw->freqProgSlot-1];
253 } else {
254 *vp = 0;
255 }
256 return 0;
257 }
258
259 static int ctrl_channelfreq_set(struct pvr2_ctrl *cptr,int m,int v)
260 {
261 struct pvr2_hdw *hdw = cptr->hdw;
262 unsigned int slotId = hdw->freqProgSlot;
263 if ((slotId > 0) && (slotId <= FREQTABLE_SIZE)) {
264 hdw->freqTable[slotId-1] = v;
265 /* Handle side effects correctly - if we're tuned to this
266 slot, then forgot the slot id relation since the stored
267 frequency has been changed. */
268 if (hdw->freqSelector) {
269 if (hdw->freqSlotRadio == slotId) {
270 hdw->freqSlotRadio = 0;
271 }
272 } else {
273 if (hdw->freqSlotTelevision == slotId) {
274 hdw->freqSlotTelevision = 0;
275 }
276 }
277 }
278 return 0;
279 }
280
281 static int ctrl_channelprog_get(struct pvr2_ctrl *cptr,int *vp)
282 {
283 *vp = cptr->hdw->freqProgSlot;
284 return 0;
285 }
286
287 static int ctrl_channelprog_set(struct pvr2_ctrl *cptr,int m,int v)
288 {
289 struct pvr2_hdw *hdw = cptr->hdw;
290 if ((v >= 0) && (v <= FREQTABLE_SIZE)) {
291 hdw->freqProgSlot = v;
292 }
293 return 0;
294 }
295
296 static int ctrl_channel_get(struct pvr2_ctrl *cptr,int *vp)
297 {
298 struct pvr2_hdw *hdw = cptr->hdw;
299 *vp = hdw->freqSelector ? hdw->freqSlotRadio : hdw->freqSlotTelevision;
300 return 0;
301 }
302
303 static int ctrl_channel_set(struct pvr2_ctrl *cptr,int m,int slotId)
304 {
305 unsigned freq = 0;
306 struct pvr2_hdw *hdw = cptr->hdw;
307 if ((slotId < 0) || (slotId > FREQTABLE_SIZE)) return 0;
308 if (slotId > 0) {
309 freq = hdw->freqTable[slotId-1];
310 if (!freq) return 0;
311 pvr2_hdw_set_cur_freq(hdw,freq);
312 }
313 if (hdw->freqSelector) {
314 hdw->freqSlotRadio = slotId;
315 } else {
316 hdw->freqSlotTelevision = slotId;
317 }
318 return 0;
319 }
320
321 static int ctrl_freq_get(struct pvr2_ctrl *cptr,int *vp)
322 {
323 *vp = pvr2_hdw_get_cur_freq(cptr->hdw);
324 return 0;
325 }
326
327 static int ctrl_freq_is_dirty(struct pvr2_ctrl *cptr)
328 {
329 return cptr->hdw->freqDirty != 0;
330 }
331
332 static void ctrl_freq_clear_dirty(struct pvr2_ctrl *cptr)
333 {
334 cptr->hdw->freqDirty = 0;
335 }
336
337 static int ctrl_freq_set(struct pvr2_ctrl *cptr,int m,int v)
338 {
339 pvr2_hdw_set_cur_freq(cptr->hdw,v);
340 return 0;
341 }
342
343 static int ctrl_vres_max_get(struct pvr2_ctrl *cptr,int *vp)
344 {
345 /* Actual maximum depends on the video standard in effect. */
346 if (cptr->hdw->std_mask_cur & V4L2_STD_525_60) {
347 *vp = 480;
348 } else {
349 *vp = 576;
350 }
351 return 0;
352 }
353
354 static int ctrl_vres_min_get(struct pvr2_ctrl *cptr,int *vp)
355 {
356 /* Actual minimum depends on device digitizer type. */
357 if (cptr->hdw->hdw_desc->flag_has_cx25840) {
358 *vp = 75;
359 } else {
360 *vp = 17;
361 }
362 return 0;
363 }
364
365 static int ctrl_get_input(struct pvr2_ctrl *cptr,int *vp)
366 {
367 *vp = cptr->hdw->input_val;
368 return 0;
369 }
370
371 static int ctrl_set_input(struct pvr2_ctrl *cptr,int m,int v)
372 {
373 struct pvr2_hdw *hdw = cptr->hdw;
374
375 if (hdw->input_val != v) {
376 hdw->input_val = v;
377 hdw->input_dirty = !0;
378 }
379
380 /* Handle side effects - if we switch to a mode that needs the RF
381 tuner, then select the right frequency choice as well and mark
382 it dirty. */
383 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
384 hdw->freqSelector = 0;
385 hdw->freqDirty = !0;
386 } else if (hdw->input_val == PVR2_CVAL_INPUT_TV) {
387 hdw->freqSelector = 1;
388 hdw->freqDirty = !0;
389 }
390 return 0;
391 }
392
393 static int ctrl_isdirty_input(struct pvr2_ctrl *cptr)
394 {
395 return cptr->hdw->input_dirty != 0;
396 }
397
398 static void ctrl_cleardirty_input(struct pvr2_ctrl *cptr)
399 {
400 cptr->hdw->input_dirty = 0;
401 }
402
403
404 static int ctrl_freq_max_get(struct pvr2_ctrl *cptr, int *vp)
405 {
406 unsigned long fv;
407 struct pvr2_hdw *hdw = cptr->hdw;
408 if (hdw->tuner_signal_stale) {
409 pvr2_i2c_core_status_poll(hdw);
410 }
411 fv = hdw->tuner_signal_info.rangehigh;
412 if (!fv) {
413 /* Safety fallback */
414 *vp = TV_MAX_FREQ;
415 return 0;
416 }
417 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
418 fv = (fv * 125) / 2;
419 } else {
420 fv = fv * 62500;
421 }
422 *vp = fv;
423 return 0;
424 }
425
426 static int ctrl_freq_min_get(struct pvr2_ctrl *cptr, int *vp)
427 {
428 unsigned long fv;
429 struct pvr2_hdw *hdw = cptr->hdw;
430 if (hdw->tuner_signal_stale) {
431 pvr2_i2c_core_status_poll(hdw);
432 }
433 fv = hdw->tuner_signal_info.rangelow;
434 if (!fv) {
435 /* Safety fallback */
436 *vp = TV_MIN_FREQ;
437 return 0;
438 }
439 if (hdw->tuner_signal_info.capability & V4L2_TUNER_CAP_LOW) {
440 fv = (fv * 125) / 2;
441 } else {
442 fv = fv * 62500;
443 }
444 *vp = fv;
445 return 0;
446 }
447
448 static int ctrl_cx2341x_is_dirty(struct pvr2_ctrl *cptr)
449 {
450 return cptr->hdw->enc_stale != 0;
451 }
452
453 static void ctrl_cx2341x_clear_dirty(struct pvr2_ctrl *cptr)
454 {
455 cptr->hdw->enc_stale = 0;
456 cptr->hdw->enc_unsafe_stale = 0;
457 }
458
459 static int ctrl_cx2341x_get(struct pvr2_ctrl *cptr,int *vp)
460 {
461 int ret;
462 struct v4l2_ext_controls cs;
463 struct v4l2_ext_control c1;
464 memset(&cs,0,sizeof(cs));
465 memset(&c1,0,sizeof(c1));
466 cs.controls = &c1;
467 cs.count = 1;
468 c1.id = cptr->info->v4l_id;
469 ret = cx2341x_ext_ctrls(&cptr->hdw->enc_ctl_state, 0, &cs,
470 VIDIOC_G_EXT_CTRLS);
471 if (ret) return ret;
472 *vp = c1.value;
473 return 0;
474 }
475
476 static int ctrl_cx2341x_set(struct pvr2_ctrl *cptr,int m,int v)
477 {
478 int ret;
479 struct pvr2_hdw *hdw = cptr->hdw;
480 struct v4l2_ext_controls cs;
481 struct v4l2_ext_control c1;
482 memset(&cs,0,sizeof(cs));
483 memset(&c1,0,sizeof(c1));
484 cs.controls = &c1;
485 cs.count = 1;
486 c1.id = cptr->info->v4l_id;
487 c1.value = v;
488 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
489 hdw->state_encoder_run, &cs,
490 VIDIOC_S_EXT_CTRLS);
491 if (ret == -EBUSY) {
492 /* Oops. cx2341x is telling us it's not safe to change
493 this control while we're capturing. Make a note of this
494 fact so that the pipeline will be stopped the next time
495 controls are committed. Then go on ahead and store this
496 change anyway. */
497 ret = cx2341x_ext_ctrls(&hdw->enc_ctl_state,
498 0, &cs,
499 VIDIOC_S_EXT_CTRLS);
500 if (!ret) hdw->enc_unsafe_stale = !0;
501 }
502 if (ret) return ret;
503 hdw->enc_stale = !0;
504 return 0;
505 }
506
507 static unsigned int ctrl_cx2341x_getv4lflags(struct pvr2_ctrl *cptr)
508 {
509 struct v4l2_queryctrl qctrl;
510 struct pvr2_ctl_info *info;
511 qctrl.id = cptr->info->v4l_id;
512 cx2341x_ctrl_query(&cptr->hdw->enc_ctl_state,&qctrl);
513 /* Strip out the const so we can adjust a function pointer. It's
514 OK to do this here because we know this is a dynamically created
515 control, so the underlying storage for the info pointer is (a)
516 private to us, and (b) not in read-only storage. Either we do
517 this or we significantly complicate the underlying control
518 implementation. */
519 info = (struct pvr2_ctl_info *)(cptr->info);
520 if (qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY) {
521 if (info->set_value) {
522 info->set_value = NULL;
523 }
524 } else {
525 if (!(info->set_value)) {
526 info->set_value = ctrl_cx2341x_set;
527 }
528 }
529 return qctrl.flags;
530 }
531
532 static int ctrl_streamingenabled_get(struct pvr2_ctrl *cptr,int *vp)
533 {
534 *vp = cptr->hdw->state_pipeline_req;
535 return 0;
536 }
537
538 static int ctrl_masterstate_get(struct pvr2_ctrl *cptr,int *vp)
539 {
540 *vp = cptr->hdw->master_state;
541 return 0;
542 }
543
544 static int ctrl_hsm_get(struct pvr2_ctrl *cptr,int *vp)
545 {
546 int result = pvr2_hdw_is_hsm(cptr->hdw);
547 *vp = PVR2_CVAL_HSM_FULL;
548 if (result < 0) *vp = PVR2_CVAL_HSM_FAIL;
549 if (result) *vp = PVR2_CVAL_HSM_HIGH;
550 return 0;
551 }
552
553 static int ctrl_stdavail_get(struct pvr2_ctrl *cptr,int *vp)
554 {
555 *vp = cptr->hdw->std_mask_avail;
556 return 0;
557 }
558
559 static int ctrl_stdavail_set(struct pvr2_ctrl *cptr,int m,int v)
560 {
561 struct pvr2_hdw *hdw = cptr->hdw;
562 v4l2_std_id ns;
563 ns = hdw->std_mask_avail;
564 ns = (ns & ~m) | (v & m);
565 if (ns == hdw->std_mask_avail) return 0;
566 hdw->std_mask_avail = ns;
567 pvr2_hdw_internal_set_std_avail(hdw);
568 pvr2_hdw_internal_find_stdenum(hdw);
569 return 0;
570 }
571
572 static int ctrl_std_val_to_sym(struct pvr2_ctrl *cptr,int msk,int val,
573 char *bufPtr,unsigned int bufSize,
574 unsigned int *len)
575 {
576 *len = pvr2_std_id_to_str(bufPtr,bufSize,msk & val);
577 return 0;
578 }
579
580 static int ctrl_std_sym_to_val(struct pvr2_ctrl *cptr,
581 const char *bufPtr,unsigned int bufSize,
582 int *mskp,int *valp)
583 {
584 int ret;
585 v4l2_std_id id;
586 ret = pvr2_std_str_to_id(&id,bufPtr,bufSize);
587 if (ret < 0) return ret;
588 if (mskp) *mskp = id;
589 if (valp) *valp = id;
590 return 0;
591 }
592
593 static int ctrl_stdcur_get(struct pvr2_ctrl *cptr,int *vp)
594 {
595 *vp = cptr->hdw->std_mask_cur;
596 return 0;
597 }
598
599 static int ctrl_stdcur_set(struct pvr2_ctrl *cptr,int m,int v)
600 {
601 struct pvr2_hdw *hdw = cptr->hdw;
602 v4l2_std_id ns;
603 ns = hdw->std_mask_cur;
604 ns = (ns & ~m) | (v & m);
605 if (ns == hdw->std_mask_cur) return 0;
606 hdw->std_mask_cur = ns;
607 hdw->std_dirty = !0;
608 pvr2_hdw_internal_find_stdenum(hdw);
609 return 0;
610 }
611
612 static int ctrl_stdcur_is_dirty(struct pvr2_ctrl *cptr)
613 {
614 return cptr->hdw->std_dirty != 0;
615 }
616
617 static void ctrl_stdcur_clear_dirty(struct pvr2_ctrl *cptr)
618 {
619 cptr->hdw->std_dirty = 0;
620 }
621
622 static int ctrl_signal_get(struct pvr2_ctrl *cptr,int *vp)
623 {
624 struct pvr2_hdw *hdw = cptr->hdw;
625 pvr2_i2c_core_status_poll(hdw);
626 *vp = hdw->tuner_signal_info.signal;
627 return 0;
628 }
629
630 static int ctrl_audio_modes_present_get(struct pvr2_ctrl *cptr,int *vp)
631 {
632 int val = 0;
633 unsigned int subchan;
634 struct pvr2_hdw *hdw = cptr->hdw;
635 pvr2_i2c_core_status_poll(hdw);
636 subchan = hdw->tuner_signal_info.rxsubchans;
637 if (subchan & V4L2_TUNER_SUB_MONO) {
638 val |= (1 << V4L2_TUNER_MODE_MONO);
639 }
640 if (subchan & V4L2_TUNER_SUB_STEREO) {
641 val |= (1 << V4L2_TUNER_MODE_STEREO);
642 }
643 if (subchan & V4L2_TUNER_SUB_LANG1) {
644 val |= (1 << V4L2_TUNER_MODE_LANG1);
645 }
646 if (subchan & V4L2_TUNER_SUB_LANG2) {
647 val |= (1 << V4L2_TUNER_MODE_LANG2);
648 }
649 *vp = val;
650 return 0;
651 }
652
653
654 static int ctrl_stdenumcur_set(struct pvr2_ctrl *cptr,int m,int v)
655 {
656 struct pvr2_hdw *hdw = cptr->hdw;
657 if (v < 0) return -EINVAL;
658 if (v > hdw->std_enum_cnt) return -EINVAL;
659 hdw->std_enum_cur = v;
660 if (!v) return 0;
661 v--;
662 if (hdw->std_mask_cur == hdw->std_defs[v].id) return 0;
663 hdw->std_mask_cur = hdw->std_defs[v].id;
664 hdw->std_dirty = !0;
665 return 0;
666 }
667
668
669 static int ctrl_stdenumcur_get(struct pvr2_ctrl *cptr,int *vp)
670 {
671 *vp = cptr->hdw->std_enum_cur;
672 return 0;
673 }
674
675
676 static int ctrl_stdenumcur_is_dirty(struct pvr2_ctrl *cptr)
677 {
678 return cptr->hdw->std_dirty != 0;
679 }
680
681
682 static void ctrl_stdenumcur_clear_dirty(struct pvr2_ctrl *cptr)
683 {
684 cptr->hdw->std_dirty = 0;
685 }
686
687
688 #define DEFINT(vmin,vmax) \
689 .type = pvr2_ctl_int, \
690 .def.type_int.min_value = vmin, \
691 .def.type_int.max_value = vmax
692
693 #define DEFENUM(tab) \
694 .type = pvr2_ctl_enum, \
695 .def.type_enum.count = ARRAY_SIZE(tab), \
696 .def.type_enum.value_names = tab
697
698 #define DEFBOOL \
699 .type = pvr2_ctl_bool
700
701 #define DEFMASK(msk,tab) \
702 .type = pvr2_ctl_bitmask, \
703 .def.type_bitmask.valid_bits = msk, \
704 .def.type_bitmask.bit_names = tab
705
706 #define DEFREF(vname) \
707 .set_value = ctrl_set_##vname, \
708 .get_value = ctrl_get_##vname, \
709 .is_dirty = ctrl_isdirty_##vname, \
710 .clear_dirty = ctrl_cleardirty_##vname
711
712
713 #define VCREATE_FUNCS(vname) \
714 static int ctrl_get_##vname(struct pvr2_ctrl *cptr,int *vp) \
715 {*vp = cptr->hdw->vname##_val; return 0;} \
716 static int ctrl_set_##vname(struct pvr2_ctrl *cptr,int m,int v) \
717 {cptr->hdw->vname##_val = v; cptr->hdw->vname##_dirty = !0; return 0;} \
718 static int ctrl_isdirty_##vname(struct pvr2_ctrl *cptr) \
719 {return cptr->hdw->vname##_dirty != 0;} \
720 static void ctrl_cleardirty_##vname(struct pvr2_ctrl *cptr) \
721 {cptr->hdw->vname##_dirty = 0;}
722
723 VCREATE_FUNCS(brightness)
724 VCREATE_FUNCS(contrast)
725 VCREATE_FUNCS(saturation)
726 VCREATE_FUNCS(hue)
727 VCREATE_FUNCS(volume)
728 VCREATE_FUNCS(balance)
729 VCREATE_FUNCS(bass)
730 VCREATE_FUNCS(treble)
731 VCREATE_FUNCS(mute)
732 VCREATE_FUNCS(audiomode)
733 VCREATE_FUNCS(res_hor)
734 VCREATE_FUNCS(res_ver)
735 VCREATE_FUNCS(srate)
736
737 /* Table definition of all controls which can be manipulated */
738 static const struct pvr2_ctl_info control_defs[] = {
739 {
740 .v4l_id = V4L2_CID_BRIGHTNESS,
741 .desc = "Brightness",
742 .name = "brightness",
743 .default_value = 128,
744 DEFREF(brightness),
745 DEFINT(0,255),
746 },{
747 .v4l_id = V4L2_CID_CONTRAST,
748 .desc = "Contrast",
749 .name = "contrast",
750 .default_value = 68,
751 DEFREF(contrast),
752 DEFINT(0,127),
753 },{
754 .v4l_id = V4L2_CID_SATURATION,
755 .desc = "Saturation",
756 .name = "saturation",
757 .default_value = 64,
758 DEFREF(saturation),
759 DEFINT(0,127),
760 },{
761 .v4l_id = V4L2_CID_HUE,
762 .desc = "Hue",
763 .name = "hue",
764 .default_value = 0,
765 DEFREF(hue),
766 DEFINT(-128,127),
767 },{
768 .v4l_id = V4L2_CID_AUDIO_VOLUME,
769 .desc = "Volume",
770 .name = "volume",
771 .default_value = 62000,
772 DEFREF(volume),
773 DEFINT(0,65535),
774 },{
775 .v4l_id = V4L2_CID_AUDIO_BALANCE,
776 .desc = "Balance",
777 .name = "balance",
778 .default_value = 0,
779 DEFREF(balance),
780 DEFINT(-32768,32767),
781 },{
782 .v4l_id = V4L2_CID_AUDIO_BASS,
783 .desc = "Bass",
784 .name = "bass",
785 .default_value = 0,
786 DEFREF(bass),
787 DEFINT(-32768,32767),
788 },{
789 .v4l_id = V4L2_CID_AUDIO_TREBLE,
790 .desc = "Treble",
791 .name = "treble",
792 .default_value = 0,
793 DEFREF(treble),
794 DEFINT(-32768,32767),
795 },{
796 .v4l_id = V4L2_CID_AUDIO_MUTE,
797 .desc = "Mute",
798 .name = "mute",
799 .default_value = 0,
800 DEFREF(mute),
801 DEFBOOL,
802 },{
803 .desc = "Video Source",
804 .name = "input",
805 .internal_id = PVR2_CID_INPUT,
806 .default_value = PVR2_CVAL_INPUT_TV,
807 DEFREF(input),
808 DEFENUM(control_values_input),
809 },{
810 .desc = "Audio Mode",
811 .name = "audio_mode",
812 .internal_id = PVR2_CID_AUDIOMODE,
813 .default_value = V4L2_TUNER_MODE_STEREO,
814 DEFREF(audiomode),
815 DEFENUM(control_values_audiomode),
816 },{
817 .desc = "Horizontal capture resolution",
818 .name = "resolution_hor",
819 .internal_id = PVR2_CID_HRES,
820 .default_value = 720,
821 DEFREF(res_hor),
822 DEFINT(19,720),
823 },{
824 .desc = "Vertical capture resolution",
825 .name = "resolution_ver",
826 .internal_id = PVR2_CID_VRES,
827 .default_value = 480,
828 DEFREF(res_ver),
829 DEFINT(17,576),
830 /* Hook in check for video standard and adjust maximum
831 depending on the standard. */
832 .get_max_value = ctrl_vres_max_get,
833 .get_min_value = ctrl_vres_min_get,
834 },{
835 .v4l_id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ,
836 .default_value = V4L2_MPEG_AUDIO_SAMPLING_FREQ_48000,
837 .desc = "Audio Sampling Frequency",
838 .name = "srate",
839 DEFREF(srate),
840 DEFENUM(control_values_srate),
841 },{
842 .desc = "Tuner Frequency (Hz)",
843 .name = "frequency",
844 .internal_id = PVR2_CID_FREQUENCY,
845 .default_value = 0,
846 .set_value = ctrl_freq_set,
847 .get_value = ctrl_freq_get,
848 .is_dirty = ctrl_freq_is_dirty,
849 .clear_dirty = ctrl_freq_clear_dirty,
850 DEFINT(0,0),
851 /* Hook in check for input value (tv/radio) and adjust
852 max/min values accordingly */
853 .get_max_value = ctrl_freq_max_get,
854 .get_min_value = ctrl_freq_min_get,
855 },{
856 .desc = "Channel",
857 .name = "channel",
858 .set_value = ctrl_channel_set,
859 .get_value = ctrl_channel_get,
860 DEFINT(0,FREQTABLE_SIZE),
861 },{
862 .desc = "Channel Program Frequency",
863 .name = "freq_table_value",
864 .set_value = ctrl_channelfreq_set,
865 .get_value = ctrl_channelfreq_get,
866 DEFINT(0,0),
867 /* Hook in check for input value (tv/radio) and adjust
868 max/min values accordingly */
869 .get_max_value = ctrl_freq_max_get,
870 .get_min_value = ctrl_freq_min_get,
871 },{
872 .desc = "Channel Program ID",
873 .name = "freq_table_channel",
874 .set_value = ctrl_channelprog_set,
875 .get_value = ctrl_channelprog_get,
876 DEFINT(0,FREQTABLE_SIZE),
877 },{
878 .desc = "Streaming Enabled",
879 .name = "streaming_enabled",
880 .get_value = ctrl_streamingenabled_get,
881 DEFBOOL,
882 },{
883 .desc = "USB Speed",
884 .name = "usb_speed",
885 .get_value = ctrl_hsm_get,
886 DEFENUM(control_values_hsm),
887 },{
888 .desc = "Master State",
889 .name = "master_state",
890 .get_value = ctrl_masterstate_get,
891 DEFENUM(pvr2_state_names),
892 },{
893 .desc = "Signal Present",
894 .name = "signal_present",
895 .get_value = ctrl_signal_get,
896 DEFINT(0,65535),
897 },{
898 .desc = "Audio Modes Present",
899 .name = "audio_modes_present",
900 .get_value = ctrl_audio_modes_present_get,
901 /* For this type we "borrow" the V4L2_TUNER_MODE enum from
902 v4l. Nothing outside of this module cares about this,
903 but I reuse it in order to also reuse the
904 control_values_audiomode string table. */
905 DEFMASK(((1 << V4L2_TUNER_MODE_MONO)|
906 (1 << V4L2_TUNER_MODE_STEREO)|
907 (1 << V4L2_TUNER_MODE_LANG1)|
908 (1 << V4L2_TUNER_MODE_LANG2)),
909 control_values_audiomode),
910 },{
911 .desc = "Video Standards Available Mask",
912 .name = "video_standard_mask_available",
913 .internal_id = PVR2_CID_STDAVAIL,
914 .skip_init = !0,
915 .get_value = ctrl_stdavail_get,
916 .set_value = ctrl_stdavail_set,
917 .val_to_sym = ctrl_std_val_to_sym,
918 .sym_to_val = ctrl_std_sym_to_val,
919 .type = pvr2_ctl_bitmask,
920 },{
921 .desc = "Video Standards In Use Mask",
922 .name = "video_standard_mask_active",
923 .internal_id = PVR2_CID_STDCUR,
924 .skip_init = !0,
925 .get_value = ctrl_stdcur_get,
926 .set_value = ctrl_stdcur_set,
927 .is_dirty = ctrl_stdcur_is_dirty,
928 .clear_dirty = ctrl_stdcur_clear_dirty,
929 .val_to_sym = ctrl_std_val_to_sym,
930 .sym_to_val = ctrl_std_sym_to_val,
931 .type = pvr2_ctl_bitmask,
932 },{
933 .desc = "Video Standard Name",
934 .name = "video_standard",
935 .internal_id = PVR2_CID_STDENUM,
936 .skip_init = !0,
937 .get_value = ctrl_stdenumcur_get,
938 .set_value = ctrl_stdenumcur_set,
939 .is_dirty = ctrl_stdenumcur_is_dirty,
940 .clear_dirty = ctrl_stdenumcur_clear_dirty,
941 .type = pvr2_ctl_enum,
942 }
943 };
944
945 #define CTRLDEF_COUNT ARRAY_SIZE(control_defs)
946
947
948 const char *pvr2_config_get_name(enum pvr2_config cfg)
949 {
950 switch (cfg) {
951 case pvr2_config_empty: return "empty";
952 case pvr2_config_mpeg: return "mpeg";
953 case pvr2_config_vbi: return "vbi";
954 case pvr2_config_pcm: return "pcm";
955 case pvr2_config_rawvideo: return "raw video";
956 }
957 return "<unknown>";
958 }
959
960
961 struct usb_device *pvr2_hdw_get_dev(struct pvr2_hdw *hdw)
962 {
963 return hdw->usb_dev;
964 }
965
966
967 unsigned long pvr2_hdw_get_sn(struct pvr2_hdw *hdw)
968 {
969 return hdw->serial_number;
970 }
971
972
973 const char *pvr2_hdw_get_bus_info(struct pvr2_hdw *hdw)
974 {
975 return hdw->bus_info;
976 }
977
978
979 unsigned long pvr2_hdw_get_cur_freq(struct pvr2_hdw *hdw)
980 {
981 return hdw->freqSelector ? hdw->freqValTelevision : hdw->freqValRadio;
982 }
983
984 /* Set the currently tuned frequency and account for all possible
985 driver-core side effects of this action. */
986 void pvr2_hdw_set_cur_freq(struct pvr2_hdw *hdw,unsigned long val)
987 {
988 if (hdw->input_val == PVR2_CVAL_INPUT_RADIO) {
989 if (hdw->freqSelector) {
990 /* Swing over to radio frequency selection */
991 hdw->freqSelector = 0;
992 hdw->freqDirty = !0;
993 }
994 if (hdw->freqValRadio != val) {
995 hdw->freqValRadio = val;
996 hdw->freqSlotRadio = 0;
997 hdw->freqDirty = !0;
998 }
999 } else {
1000 if (!(hdw->freqSelector)) {
1001 /* Swing over to television frequency selection */
1002 hdw->freqSelector = 1;
1003 hdw->freqDirty = !0;
1004 }
1005 if (hdw->freqValTelevision != val) {
1006 hdw->freqValTelevision = val;
1007 hdw->freqSlotTelevision = 0;
1008 hdw->freqDirty = !0;
1009 }
1010 }
1011 }
1012
1013 int pvr2_hdw_get_unit_number(struct pvr2_hdw *hdw)
1014 {
1015 return hdw->unit_number;
1016 }
1017
1018
1019 /* Attempt to locate one of the given set of files. Messages are logged
1020 appropriate to what has been found. The return value will be 0 or
1021 greater on success (it will be the index of the file name found) and
1022 fw_entry will be filled in. Otherwise a negative error is returned on
1023 failure. If the return value is -ENOENT then no viable firmware file
1024 could be located. */
1025 static int pvr2_locate_firmware(struct pvr2_hdw *hdw,
1026 const struct firmware **fw_entry,
1027 const char *fwtypename,
1028 unsigned int fwcount,
1029 const char *fwnames[])
1030 {
1031 unsigned int idx;
1032 int ret = -EINVAL;
1033 for (idx = 0; idx < fwcount; idx++) {
1034 ret = request_firmware(fw_entry,
1035 fwnames[idx],
1036 &hdw->usb_dev->dev);
1037 if (!ret) {
1038 trace_firmware("Located %s firmware: %s;"
1039 " uploading...",
1040 fwtypename,
1041 fwnames[idx]);
1042 return idx;
1043 }
1044 if (ret == -ENOENT) continue;
1045 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1046 "request_firmware fatal error with code=%d",ret);
1047 return ret;
1048 }
1049 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1050 "***WARNING***"
1051 " Device %s firmware"
1052 " seems to be missing.",
1053 fwtypename);
1054 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1055 "Did you install the pvrusb2 firmware files"
1056 " in their proper location?");
1057 if (fwcount == 1) {
1058 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1059 "request_firmware unable to locate %s file %s",
1060 fwtypename,fwnames[0]);
1061 } else {
1062 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1063 "request_firmware unable to locate"
1064 " one of the following %s files:",
1065 fwtypename);
1066 for (idx = 0; idx < fwcount; idx++) {
1067 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1068 "request_firmware: Failed to find %s",
1069 fwnames[idx]);
1070 }
1071 }
1072 return ret;
1073 }
1074
1075
1076 /*
1077 * pvr2_upload_firmware1().
1078 *
1079 * Send the 8051 firmware to the device. After the upload, arrange for
1080 * device to re-enumerate.
1081 *
1082 * NOTE : the pointer to the firmware data given by request_firmware()
1083 * is not suitable for an usb transaction.
1084 *
1085 */
1086 static int pvr2_upload_firmware1(struct pvr2_hdw *hdw)
1087 {
1088 const struct firmware *fw_entry = NULL;
1089 void *fw_ptr;
1090 unsigned int pipe;
1091 int ret;
1092 u16 address;
1093
1094 if (!hdw->hdw_desc->fx2_firmware.cnt) {
1095 hdw->fw1_state = FW1_STATE_OK;
1096 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1097 "Connected device type defines"
1098 " no firmware to upload; ignoring firmware");
1099 return -ENOTTY;
1100 }
1101
1102 hdw->fw1_state = FW1_STATE_FAILED; // default result
1103
1104 trace_firmware("pvr2_upload_firmware1");
1105
1106 ret = pvr2_locate_firmware(hdw,&fw_entry,"fx2 controller",
1107 hdw->hdw_desc->fx2_firmware.cnt,
1108 hdw->hdw_desc->fx2_firmware.lst);
1109 if (ret < 0) {
1110 if (ret == -ENOENT) hdw->fw1_state = FW1_STATE_MISSING;
1111 return ret;
1112 }
1113
1114 usb_settoggle(hdw->usb_dev, 0 & 0xf, !(0 & USB_DIR_IN), 0);
1115 usb_clear_halt(hdw->usb_dev, usb_sndbulkpipe(hdw->usb_dev, 0 & 0x7f));
1116
1117 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
1118
1119 if (fw_entry->size != 0x2000){
1120 pvr2_trace(PVR2_TRACE_ERROR_LEGS,"wrong fx2 firmware size");
1121 release_firmware(fw_entry);
1122 return -ENOMEM;
1123 }
1124
1125 fw_ptr = kmalloc(0x800, GFP_KERNEL);
1126 if (fw_ptr == NULL){
1127 release_firmware(fw_entry);
1128 return -ENOMEM;
1129 }
1130
1131 /* We have to hold the CPU during firmware upload. */
1132 pvr2_hdw_cpureset_assert(hdw,1);
1133
1134 /* upload the firmware to address 0000-1fff in 2048 (=0x800) bytes
1135 chunk. */
1136
1137 ret = 0;
1138 for(address = 0; address < fw_entry->size; address += 0x800) {
1139 memcpy(fw_ptr, fw_entry->data + address, 0x800);
1140 ret += usb_control_msg(hdw->usb_dev, pipe, 0xa0, 0x40, address,
1141 0, fw_ptr, 0x800, HZ);
1142 }
1143
1144 trace_firmware("Upload done, releasing device's CPU");
1145
1146 /* Now release the CPU. It will disconnect and reconnect later. */
1147 pvr2_hdw_cpureset_assert(hdw,0);
1148
1149 kfree(fw_ptr);
1150 release_firmware(fw_entry);
1151
1152 trace_firmware("Upload done (%d bytes sent)",ret);
1153
1154 /* We should have written 8192 bytes */
1155 if (ret == 8192) {
1156 hdw->fw1_state = FW1_STATE_RELOAD;
1157 return 0;
1158 }
1159
1160 return -EIO;
1161 }
1162
1163
1164 /*
1165 * pvr2_upload_firmware2()
1166 *
1167 * This uploads encoder firmware on endpoint 2.
1168 *
1169 */
1170
1171 int pvr2_upload_firmware2(struct pvr2_hdw *hdw)
1172 {
1173 const struct firmware *fw_entry = NULL;
1174 void *fw_ptr;
1175 unsigned int pipe, fw_len, fw_done, bcnt, icnt;
1176 int actual_length;
1177 int ret = 0;
1178 int fwidx;
1179 static const char *fw_files[] = {
1180 CX2341X_FIRM_ENC_FILENAME,
1181 };
1182
1183 if (hdw->hdw_desc->flag_skip_cx23416_firmware) {
1184 return 0;
1185 }
1186
1187 trace_firmware("pvr2_upload_firmware2");
1188
1189 ret = pvr2_locate_firmware(hdw,&fw_entry,"encoder",
1190 ARRAY_SIZE(fw_files), fw_files);
1191 if (ret < 0) return ret;
1192 fwidx = ret;
1193 ret = 0;
1194 /* Since we're about to completely reinitialize the encoder,
1195 invalidate our cached copy of its configuration state. Next
1196 time we configure the encoder, then we'll fully configure it. */
1197 hdw->enc_cur_valid = 0;
1198
1199 /* First prepare firmware loading */
1200 ret |= pvr2_write_register(hdw, 0x0048, 0xffffffff); /*interrupt mask*/
1201 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000088); /*gpio dir*/
1202 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1203 ret |= pvr2_hdw_cmd_deep_reset(hdw);
1204 ret |= pvr2_write_register(hdw, 0xa064, 0x00000000); /*APU command*/
1205 ret |= pvr2_hdw_gpio_chg_dir(hdw,0xffffffff,0x00000408); /*gpio dir*/
1206 ret |= pvr2_hdw_gpio_chg_out(hdw,0xffffffff,0x00000008); /*gpio output state*/
1207 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffed); /*VPU ctrl*/
1208 ret |= pvr2_write_register(hdw, 0x9054, 0xfffffffd); /*reset hw blocks*/
1209 ret |= pvr2_write_register(hdw, 0x07f8, 0x80000800); /*encoder SDRAM refresh*/
1210 ret |= pvr2_write_register(hdw, 0x07fc, 0x0000001a); /*encoder SDRAM pre-charge*/
1211 ret |= pvr2_write_register(hdw, 0x0700, 0x00000000); /*I2C clock*/
1212 ret |= pvr2_write_register(hdw, 0xaa00, 0x00000000); /*unknown*/
1213 ret |= pvr2_write_register(hdw, 0xaa04, 0x00057810); /*unknown*/
1214 ret |= pvr2_write_register(hdw, 0xaa10, 0x00148500); /*unknown*/
1215 ret |= pvr2_write_register(hdw, 0xaa18, 0x00840000); /*unknown*/
1216 LOCK_TAKE(hdw->ctl_lock); do {
1217 hdw->cmd_buffer[0] = FX2CMD_FWPOST1;
1218 ret |= pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
1219 hdw->cmd_buffer[0] = FX2CMD_MEMSEL;
1220 hdw->cmd_buffer[1] = 0;
1221 ret |= pvr2_send_request(hdw,hdw->cmd_buffer,2,NULL,0);
1222 } while (0); LOCK_GIVE(hdw->ctl_lock);
1223
1224 if (ret) {
1225 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1226 "firmware2 upload prep failed, ret=%d",ret);
1227 release_firmware(fw_entry);
1228 return ret;
1229 }
1230
1231 /* Now send firmware */
1232
1233 fw_len = fw_entry->size;
1234
1235 if (fw_len % sizeof(u32)) {
1236 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1237 "size of %s firmware"
1238 " must be a multiple of %zu bytes",
1239 fw_files[fwidx],sizeof(u32));
1240 release_firmware(fw_entry);
1241 return -1;
1242 }
1243
1244 fw_ptr = kmalloc(FIRMWARE_CHUNK_SIZE, GFP_KERNEL);
1245 if (fw_ptr == NULL){
1246 release_firmware(fw_entry);
1247 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1248 "failed to allocate memory for firmware2 upload");
1249 return -ENOMEM;
1250 }
1251
1252 pipe = usb_sndbulkpipe(hdw->usb_dev, PVR2_FIRMWARE_ENDPOINT);
1253
1254 fw_done = 0;
1255 for (fw_done = 0; fw_done < fw_len;) {
1256 bcnt = fw_len - fw_done;
1257 if (bcnt > FIRMWARE_CHUNK_SIZE) bcnt = FIRMWARE_CHUNK_SIZE;
1258 memcpy(fw_ptr, fw_entry->data + fw_done, bcnt);
1259 /* Usbsnoop log shows that we must swap bytes... */
1260 for (icnt = 0; icnt < bcnt/4 ; icnt++)
1261 ((u32 *)fw_ptr)[icnt] =
1262 ___swab32(((u32 *)fw_ptr)[icnt]);
1263
1264 ret |= usb_bulk_msg(hdw->usb_dev, pipe, fw_ptr,bcnt,
1265 &actual_length, HZ);
1266 ret |= (actual_length != bcnt);
1267 if (ret) break;
1268 fw_done += bcnt;
1269 }
1270
1271 trace_firmware("upload of %s : %i / %i ",
1272 fw_files[fwidx],fw_done,fw_len);
1273
1274 kfree(fw_ptr);
1275 release_firmware(fw_entry);
1276
1277 if (ret) {
1278 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1279 "firmware2 upload transfer failure");
1280 return ret;
1281 }
1282
1283 /* Finish upload */
1284
1285 ret |= pvr2_write_register(hdw, 0x9054, 0xffffffff); /*reset hw blocks*/
1286 ret |= pvr2_write_register(hdw, 0x9058, 0xffffffe8); /*VPU ctrl*/
1287 LOCK_TAKE(hdw->ctl_lock); do {
1288 hdw->cmd_buffer[0] = FX2CMD_MEMSEL;
1289 hdw->cmd_buffer[1] = 0;
1290 ret |= pvr2_send_request(hdw,hdw->cmd_buffer,2,NULL,0);
1291 } while (0); LOCK_GIVE(hdw->ctl_lock);
1292
1293 if (ret) {
1294 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1295 "firmware2 upload post-proc failure");
1296 }
1297 return ret;
1298 }
1299
1300
1301 static const char *pvr2_get_state_name(unsigned int st)
1302 {
1303 if (st < ARRAY_SIZE(pvr2_state_names)) {
1304 return pvr2_state_names[st];
1305 }
1306 return "???";
1307 }
1308
1309 static int pvr2_decoder_enable(struct pvr2_hdw *hdw,int enablefl)
1310 {
1311 if (!hdw->decoder_ctrl) {
1312 if (!hdw->flag_decoder_missed) {
1313 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1314 "WARNING: No decoder present");
1315 hdw->flag_decoder_missed = !0;
1316 trace_stbit("flag_decoder_missed",
1317 hdw->flag_decoder_missed);
1318 }
1319 return -EIO;
1320 }
1321 hdw->decoder_ctrl->enable(hdw->decoder_ctrl->ctxt,enablefl);
1322 return 0;
1323 }
1324
1325
1326 void pvr2_hdw_set_decoder(struct pvr2_hdw *hdw,struct pvr2_decoder_ctrl *ptr)
1327 {
1328 if (hdw->decoder_ctrl == ptr) return;
1329 hdw->decoder_ctrl = ptr;
1330 if (hdw->decoder_ctrl && hdw->flag_decoder_missed) {
1331 hdw->flag_decoder_missed = 0;
1332 trace_stbit("flag_decoder_missed",
1333 hdw->flag_decoder_missed);
1334 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1335 "Decoder has appeared");
1336 pvr2_hdw_state_sched(hdw);
1337 }
1338 }
1339
1340
1341 int pvr2_hdw_get_state(struct pvr2_hdw *hdw)
1342 {
1343 return hdw->master_state;
1344 }
1345
1346
1347 static int pvr2_hdw_untrip_unlocked(struct pvr2_hdw *hdw)
1348 {
1349 if (!hdw->flag_tripped) return 0;
1350 hdw->flag_tripped = 0;
1351 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1352 "Clearing driver error statuss");
1353 return !0;
1354 }
1355
1356
1357 int pvr2_hdw_untrip(struct pvr2_hdw *hdw)
1358 {
1359 int fl;
1360 LOCK_TAKE(hdw->big_lock); do {
1361 fl = pvr2_hdw_untrip_unlocked(hdw);
1362 } while (0); LOCK_GIVE(hdw->big_lock);
1363 if (fl) pvr2_hdw_state_sched(hdw);
1364 return 0;
1365 }
1366
1367
1368 const char *pvr2_hdw_get_state_name(unsigned int id)
1369 {
1370 if (id >= ARRAY_SIZE(pvr2_state_names)) return NULL;
1371 return pvr2_state_names[id];
1372 }
1373
1374
1375 int pvr2_hdw_get_streaming(struct pvr2_hdw *hdw)
1376 {
1377 return hdw->state_pipeline_req != 0;
1378 }
1379
1380
1381 int pvr2_hdw_set_streaming(struct pvr2_hdw *hdw,int enable_flag)
1382 {
1383 int ret,st;
1384 LOCK_TAKE(hdw->big_lock); do {
1385 pvr2_hdw_untrip_unlocked(hdw);
1386 if ((!enable_flag) != !(hdw->state_pipeline_req)) {
1387 hdw->state_pipeline_req = enable_flag != 0;
1388 pvr2_trace(PVR2_TRACE_START_STOP,
1389 "/*--TRACE_STREAM--*/ %s",
1390 enable_flag ? "enable" : "disable");
1391 }
1392 pvr2_hdw_state_sched(hdw);
1393 } while (0); LOCK_GIVE(hdw->big_lock);
1394 if ((ret = pvr2_hdw_wait(hdw,0)) < 0) return ret;
1395 if (enable_flag) {
1396 while ((st = hdw->master_state) != PVR2_STATE_RUN) {
1397 if (st != PVR2_STATE_READY) return -EIO;
1398 if ((ret = pvr2_hdw_wait(hdw,st)) < 0) return ret;
1399 }
1400 }
1401 return 0;
1402 }
1403
1404
1405 int pvr2_hdw_set_stream_type(struct pvr2_hdw *hdw,enum pvr2_config config)
1406 {
1407 int fl;
1408 LOCK_TAKE(hdw->big_lock);
1409 if ((fl = (hdw->desired_stream_type != config)) != 0) {
1410 hdw->desired_stream_type = config;
1411 hdw->state_pipeline_config = 0;
1412 trace_stbit("state_pipeline_config",
1413 hdw->state_pipeline_config);
1414 pvr2_hdw_state_sched(hdw);
1415 }
1416 LOCK_GIVE(hdw->big_lock);
1417 if (fl) return 0;
1418 return pvr2_hdw_wait(hdw,0);
1419 }
1420
1421
1422 static int get_default_tuner_type(struct pvr2_hdw *hdw)
1423 {
1424 int unit_number = hdw->unit_number;
1425 int tp = -1;
1426 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1427 tp = tuner[unit_number];
1428 }
1429 if (tp < 0) return -EINVAL;
1430 hdw->tuner_type = tp;
1431 hdw->tuner_updated = !0;
1432 return 0;
1433 }
1434
1435
1436 static v4l2_std_id get_default_standard(struct pvr2_hdw *hdw)
1437 {
1438 int unit_number = hdw->unit_number;
1439 int tp = 0;
1440 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1441 tp = video_std[unit_number];
1442 if (tp) return tp;
1443 }
1444 return 0;
1445 }
1446
1447
1448 static unsigned int get_default_error_tolerance(struct pvr2_hdw *hdw)
1449 {
1450 int unit_number = hdw->unit_number;
1451 int tp = 0;
1452 if ((unit_number >= 0) && (unit_number < PVR_NUM)) {
1453 tp = tolerance[unit_number];
1454 }
1455 return tp;
1456 }
1457
1458
1459 static int pvr2_hdw_check_firmware(struct pvr2_hdw *hdw)
1460 {
1461 /* Try a harmless request to fetch the eeprom's address over
1462 endpoint 1. See what happens. Only the full FX2 image can
1463 respond to this. If this probe fails then likely the FX2
1464 firmware needs be loaded. */
1465 int result;
1466 LOCK_TAKE(hdw->ctl_lock); do {
1467 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
1468 result = pvr2_send_request_ex(hdw,HZ*1,!0,
1469 hdw->cmd_buffer,1,
1470 hdw->cmd_buffer,1);
1471 if (result < 0) break;
1472 } while(0); LOCK_GIVE(hdw->ctl_lock);
1473 if (result) {
1474 pvr2_trace(PVR2_TRACE_INIT,
1475 "Probe of device endpoint 1 result status %d",
1476 result);
1477 } else {
1478 pvr2_trace(PVR2_TRACE_INIT,
1479 "Probe of device endpoint 1 succeeded");
1480 }
1481 return result == 0;
1482 }
1483
1484 struct pvr2_std_hack {
1485 v4l2_std_id pat; /* Pattern to match */
1486 v4l2_std_id msk; /* Which bits we care about */
1487 v4l2_std_id std; /* What additional standards or default to set */
1488 };
1489
1490 /* This data structure labels specific combinations of standards from
1491 tveeprom that we'll try to recognize. If we recognize one, then assume
1492 a specified default standard to use. This is here because tveeprom only
1493 tells us about available standards not the intended default standard (if
1494 any) for the device in question. We guess the default based on what has
1495 been reported as available. Note that this is only for guessing a
1496 default - which can always be overridden explicitly - and if the user
1497 has otherwise named a default then that default will always be used in
1498 place of this table. */
1499 const static struct pvr2_std_hack std_eeprom_maps[] = {
1500 { /* PAL(B/G) */
1501 .pat = V4L2_STD_B|V4L2_STD_GH,
1502 .std = V4L2_STD_PAL_B|V4L2_STD_PAL_B1|V4L2_STD_PAL_G,
1503 },
1504 { /* NTSC(M) */
1505 .pat = V4L2_STD_MN,
1506 .std = V4L2_STD_NTSC_M,
1507 },
1508 { /* PAL(I) */
1509 .pat = V4L2_STD_PAL_I,
1510 .std = V4L2_STD_PAL_I,
1511 },
1512 { /* SECAM(L/L') */
1513 .pat = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1514 .std = V4L2_STD_SECAM_L|V4L2_STD_SECAM_LC,
1515 },
1516 { /* PAL(D/D1/K) */
1517 .pat = V4L2_STD_DK,
1518 .std = V4L2_STD_PAL_D|V4L2_STD_PAL_D1|V4L2_STD_PAL_K,
1519 },
1520 };
1521
1522 static void pvr2_hdw_setup_std(struct pvr2_hdw *hdw)
1523 {
1524 char buf[40];
1525 unsigned int bcnt;
1526 v4l2_std_id std1,std2,std3;
1527
1528 std1 = get_default_standard(hdw);
1529 std3 = std1 ? 0 : hdw->hdw_desc->default_std_mask;
1530
1531 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),hdw->std_mask_eeprom);
1532 pvr2_trace(PVR2_TRACE_STD,
1533 "Supported video standard(s) reported available"
1534 " in hardware: %.*s",
1535 bcnt,buf);
1536
1537 hdw->std_mask_avail = hdw->std_mask_eeprom;
1538
1539 std2 = (std1|std3) & ~hdw->std_mask_avail;
1540 if (std2) {
1541 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std2);
1542 pvr2_trace(PVR2_TRACE_STD,
1543 "Expanding supported video standards"
1544 " to include: %.*s",
1545 bcnt,buf);
1546 hdw->std_mask_avail |= std2;
1547 }
1548
1549 pvr2_hdw_internal_set_std_avail(hdw);
1550
1551 if (std1) {
1552 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std1);
1553 pvr2_trace(PVR2_TRACE_STD,
1554 "Initial video standard forced to %.*s",
1555 bcnt,buf);
1556 hdw->std_mask_cur = std1;
1557 hdw->std_dirty = !0;
1558 pvr2_hdw_internal_find_stdenum(hdw);
1559 return;
1560 }
1561 if (std3) {
1562 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),std3);
1563 pvr2_trace(PVR2_TRACE_STD,
1564 "Initial video standard"
1565 " (determined by device type): %.*s",bcnt,buf);
1566 hdw->std_mask_cur = std3;
1567 hdw->std_dirty = !0;
1568 pvr2_hdw_internal_find_stdenum(hdw);
1569 return;
1570 }
1571
1572 {
1573 unsigned int idx;
1574 for (idx = 0; idx < ARRAY_SIZE(std_eeprom_maps); idx++) {
1575 if (std_eeprom_maps[idx].msk ?
1576 ((std_eeprom_maps[idx].pat ^
1577 hdw->std_mask_eeprom) &
1578 std_eeprom_maps[idx].msk) :
1579 (std_eeprom_maps[idx].pat !=
1580 hdw->std_mask_eeprom)) continue;
1581 bcnt = pvr2_std_id_to_str(buf,sizeof(buf),
1582 std_eeprom_maps[idx].std);
1583 pvr2_trace(PVR2_TRACE_STD,
1584 "Initial video standard guessed as %.*s",
1585 bcnt,buf);
1586 hdw->std_mask_cur = std_eeprom_maps[idx].std;
1587 hdw->std_dirty = !0;
1588 pvr2_hdw_internal_find_stdenum(hdw);
1589 return;
1590 }
1591 }
1592
1593 if (hdw->std_enum_cnt > 1) {
1594 // Autoselect the first listed standard
1595 hdw->std_enum_cur = 1;
1596 hdw->std_mask_cur = hdw->std_defs[hdw->std_enum_cur-1].id;
1597 hdw->std_dirty = !0;
1598 pvr2_trace(PVR2_TRACE_STD,
1599 "Initial video standard auto-selected to %s",
1600 hdw->std_defs[hdw->std_enum_cur-1].name);
1601 return;
1602 }
1603
1604 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1605 "Unable to select a viable initial video standard");
1606 }
1607
1608
1609 static void pvr2_hdw_setup_low(struct pvr2_hdw *hdw)
1610 {
1611 int ret;
1612 unsigned int idx;
1613 struct pvr2_ctrl *cptr;
1614 int reloadFl = 0;
1615 if (hdw->hdw_desc->fx2_firmware.cnt) {
1616 if (!reloadFl) {
1617 reloadFl =
1618 (hdw->usb_intf->cur_altsetting->desc.bNumEndpoints
1619 == 0);
1620 if (reloadFl) {
1621 pvr2_trace(PVR2_TRACE_INIT,
1622 "USB endpoint config looks strange"
1623 "; possibly firmware needs to be"
1624 " loaded");
1625 }
1626 }
1627 if (!reloadFl) {
1628 reloadFl = !pvr2_hdw_check_firmware(hdw);
1629 if (reloadFl) {
1630 pvr2_trace(PVR2_TRACE_INIT,
1631 "Check for FX2 firmware failed"
1632 "; possibly firmware needs to be"
1633 " loaded");
1634 }
1635 }
1636 if (reloadFl) {
1637 if (pvr2_upload_firmware1(hdw) != 0) {
1638 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1639 "Failure uploading firmware1");
1640 }
1641 return;
1642 }
1643 }
1644 hdw->fw1_state = FW1_STATE_OK;
1645
1646 if (initusbreset) {
1647 pvr2_hdw_device_reset(hdw);
1648 }
1649 if (!pvr2_hdw_dev_ok(hdw)) return;
1650
1651 for (idx = 0; idx < hdw->hdw_desc->client_modules.cnt; idx++) {
1652 request_module(hdw->hdw_desc->client_modules.lst[idx]);
1653 }
1654
1655 if (!hdw->hdw_desc->flag_no_powerup) {
1656 pvr2_hdw_cmd_powerup(hdw);
1657 if (!pvr2_hdw_dev_ok(hdw)) return;
1658 }
1659
1660 // This step MUST happen after the earlier powerup step.
1661 pvr2_i2c_core_init(hdw);
1662 if (!pvr2_hdw_dev_ok(hdw)) return;
1663
1664 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
1665 cptr = hdw->controls + idx;
1666 if (cptr->info->skip_init) continue;
1667 if (!cptr->info->set_value) continue;
1668 cptr->info->set_value(cptr,~0,cptr->info->default_value);
1669 }
1670
1671 /* Set up special default values for the television and radio
1672 frequencies here. It's not really important what these defaults
1673 are, but I set them to something usable in the Chicago area just
1674 to make driver testing a little easier. */
1675
1676 /* US Broadcast channel 7 (175.25 MHz) */
1677 hdw->freqValTelevision = 175250000L;
1678 /* 104.3 MHz, a usable FM station for my area */
1679 hdw->freqValRadio = 104300000L;
1680
1681 // Do not use pvr2_reset_ctl_endpoints() here. It is not
1682 // thread-safe against the normal pvr2_send_request() mechanism.
1683 // (We should make it thread safe).
1684
1685 if (hdw->hdw_desc->flag_has_hauppauge_rom) {
1686 ret = pvr2_hdw_get_eeprom_addr(hdw);
1687 if (!pvr2_hdw_dev_ok(hdw)) return;
1688 if (ret < 0) {
1689 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1690 "Unable to determine location of eeprom,"
1691 " skipping");
1692 } else {
1693 hdw->eeprom_addr = ret;
1694 pvr2_eeprom_analyze(hdw);
1695 if (!pvr2_hdw_dev_ok(hdw)) return;
1696 }
1697 } else {
1698 hdw->tuner_type = hdw->hdw_desc->default_tuner_type;
1699 hdw->tuner_updated = !0;
1700 hdw->std_mask_eeprom = V4L2_STD_ALL;
1701 }
1702
1703 pvr2_hdw_setup_std(hdw);
1704
1705 if (!get_default_tuner_type(hdw)) {
1706 pvr2_trace(PVR2_TRACE_INIT,
1707 "pvr2_hdw_setup: Tuner type overridden to %d",
1708 hdw->tuner_type);
1709 }
1710
1711 pvr2_i2c_core_check_stale(hdw);
1712 hdw->tuner_updated = 0;
1713
1714 if (!pvr2_hdw_dev_ok(hdw)) return;
1715
1716 pvr2_hdw_commit_setup(hdw);
1717
1718 hdw->vid_stream = pvr2_stream_create();
1719 if (!pvr2_hdw_dev_ok(hdw)) return;
1720 pvr2_trace(PVR2_TRACE_INIT,
1721 "pvr2_hdw_setup: video stream is %p",hdw->vid_stream);
1722 if (hdw->vid_stream) {
1723 idx = get_default_error_tolerance(hdw);
1724 if (idx) {
1725 pvr2_trace(PVR2_TRACE_INIT,
1726 "pvr2_hdw_setup: video stream %p"
1727 " setting tolerance %u",
1728 hdw->vid_stream,idx);
1729 }
1730 pvr2_stream_setup(hdw->vid_stream,hdw->usb_dev,
1731 PVR2_VID_ENDPOINT,idx);
1732 }
1733
1734 if (!pvr2_hdw_dev_ok(hdw)) return;
1735
1736 hdw->flag_init_ok = !0;
1737
1738 pvr2_hdw_state_sched(hdw);
1739 }
1740
1741
1742 /* Set up the structure and attempt to put the device into a usable state.
1743 This can be a time-consuming operation, which is why it is not done
1744 internally as part of the create() step. */
1745 static void pvr2_hdw_setup(struct pvr2_hdw *hdw)
1746 {
1747 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) begin",hdw);
1748 do {
1749 pvr2_hdw_setup_low(hdw);
1750 pvr2_trace(PVR2_TRACE_INIT,
1751 "pvr2_hdw_setup(hdw=%p) done, ok=%d init_ok=%d",
1752 hdw,pvr2_hdw_dev_ok(hdw),hdw->flag_init_ok);
1753 if (pvr2_hdw_dev_ok(hdw)) {
1754 if (hdw->flag_init_ok) {
1755 pvr2_trace(
1756 PVR2_TRACE_INFO,
1757 "Device initialization"
1758 " completed successfully.");
1759 break;
1760 }
1761 if (hdw->fw1_state == FW1_STATE_RELOAD) {
1762 pvr2_trace(
1763 PVR2_TRACE_INFO,
1764 "Device microcontroller firmware"
1765 " (re)loaded; it should now reset"
1766 " and reconnect.");
1767 break;
1768 }
1769 pvr2_trace(
1770 PVR2_TRACE_ERROR_LEGS,
1771 "Device initialization was not successful.");
1772 if (hdw->fw1_state == FW1_STATE_MISSING) {
1773 pvr2_trace(
1774 PVR2_TRACE_ERROR_LEGS,
1775 "Giving up since device"
1776 " microcontroller firmware"
1777 " appears to be missing.");
1778 break;
1779 }
1780 }
1781 if (procreload) {
1782 pvr2_trace(
1783 PVR2_TRACE_ERROR_LEGS,
1784 "Attempting pvrusb2 recovery by reloading"
1785 " primary firmware.");
1786 pvr2_trace(
1787 PVR2_TRACE_ERROR_LEGS,
1788 "If this works, device should disconnect"
1789 " and reconnect in a sane state.");
1790 hdw->fw1_state = FW1_STATE_UNKNOWN;
1791 pvr2_upload_firmware1(hdw);
1792 } else {
1793 pvr2_trace(
1794 PVR2_TRACE_ERROR_LEGS,
1795 "***WARNING*** pvrusb2 device hardware"
1796 " appears to be jammed"
1797 " and I can't clear it.");
1798 pvr2_trace(
1799 PVR2_TRACE_ERROR_LEGS,
1800 "You might need to power cycle"
1801 " the pvrusb2 device"
1802 " in order to recover.");
1803 }
1804 } while (0);
1805 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_setup(hdw=%p) end",hdw);
1806 }
1807
1808
1809 /* Create and return a structure for interacting with the underlying
1810 hardware */
1811 struct pvr2_hdw *pvr2_hdw_create(struct usb_interface *intf,
1812 const struct usb_device_id *devid)
1813 {
1814 unsigned int idx,cnt1,cnt2;
1815 struct pvr2_hdw *hdw;
1816 unsigned int hdw_type;
1817 int valid_std_mask;
1818 struct pvr2_ctrl *cptr;
1819 const struct pvr2_device_desc *hdw_desc;
1820 __u8 ifnum;
1821 struct v4l2_queryctrl qctrl;
1822 struct pvr2_ctl_info *ciptr;
1823
1824 hdw_type = devid - pvr2_device_table;
1825 if (hdw_type >= pvr2_device_count) {
1826 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
1827 "Bogus device type of %u reported",hdw_type);
1828 return NULL;
1829 }
1830 hdw_desc = pvr2_device_descriptions + hdw_type;
1831
1832 hdw = kzalloc(sizeof(*hdw),GFP_KERNEL);
1833 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_create: hdw=%p, type \"%s\"",
1834 hdw,hdw_desc->description);
1835 if (!hdw) goto fail;
1836
1837 init_timer(&hdw->quiescent_timer);
1838 hdw->quiescent_timer.data = (unsigned long)hdw;
1839 hdw->quiescent_timer.function = pvr2_hdw_quiescent_timeout;
1840
1841 init_timer(&hdw->encoder_wait_timer);
1842 hdw->encoder_wait_timer.data = (unsigned long)hdw;
1843 hdw->encoder_wait_timer.function = pvr2_hdw_encoder_wait_timeout;
1844
1845 hdw->master_state = PVR2_STATE_DEAD;
1846
1847 init_waitqueue_head(&hdw->state_wait_data);
1848
1849 hdw->tuner_signal_stale = !0;
1850 cx2341x_fill_defaults(&hdw->enc_ctl_state);
1851
1852 hdw->control_cnt = CTRLDEF_COUNT;
1853 hdw->control_cnt += MPEGDEF_COUNT;
1854 hdw->controls = kzalloc(sizeof(struct pvr2_ctrl) * hdw->control_cnt,
1855 GFP_KERNEL);
1856 if (!hdw->controls) goto fail;
1857 hdw->hdw_desc = hdw_desc;
1858 for (idx = 0; idx < hdw->control_cnt; idx++) {
1859 cptr = hdw->controls + idx;
1860 cptr->hdw = hdw;
1861 }
1862 for (idx = 0; idx < 32; idx++) {
1863 hdw->std_mask_ptrs[idx] = hdw->std_mask_names[idx];
1864 }
1865 for (idx = 0; idx < CTRLDEF_COUNT; idx++) {
1866 cptr = hdw->controls + idx;
1867 cptr->info = control_defs+idx;
1868 }
1869 /* Define and configure additional controls from cx2341x module. */
1870 hdw->mpeg_ctrl_info = kzalloc(
1871 sizeof(*(hdw->mpeg_ctrl_info)) * MPEGDEF_COUNT, GFP_KERNEL);
1872 if (!hdw->mpeg_ctrl_info) goto fail;
1873 for (idx = 0; idx < MPEGDEF_COUNT; idx++) {
1874 cptr = hdw->controls + idx + CTRLDEF_COUNT;
1875 ciptr = &(hdw->mpeg_ctrl_info[idx].info);
1876 ciptr->desc = hdw->mpeg_ctrl_info[idx].desc;
1877 ciptr->name = mpeg_ids[idx].strid;
1878 ciptr->v4l_id = mpeg_ids[idx].id;
1879 ciptr->skip_init = !0;
1880 ciptr->get_value = ctrl_cx2341x_get;
1881 ciptr->get_v4lflags = ctrl_cx2341x_getv4lflags;
1882 ciptr->is_dirty = ctrl_cx2341x_is_dirty;
1883 if (!idx) ciptr->clear_dirty = ctrl_cx2341x_clear_dirty;
1884 qctrl.id = ciptr->v4l_id;
1885 cx2341x_ctrl_query(&hdw->enc_ctl_state,&qctrl);
1886 if (!(qctrl.flags & V4L2_CTRL_FLAG_READ_ONLY)) {
1887 ciptr->set_value = ctrl_cx2341x_set;
1888 }
1889 strncpy(hdw->mpeg_ctrl_info[idx].desc,qctrl.name,
1890 PVR2_CTLD_INFO_DESC_SIZE);
1891 hdw->mpeg_ctrl_info[idx].desc[PVR2_CTLD_INFO_DESC_SIZE-1] = 0;
1892 ciptr->default_value = qctrl.default_value;
1893 switch (qctrl.type) {
1894 default:
1895 case V4L2_CTRL_TYPE_INTEGER:
1896 ciptr->type = pvr2_ctl_int;
1897 ciptr->def.type_int.min_value = qctrl.minimum;
1898 ciptr->def.type_int.max_value = qctrl.maximum;
1899 break;
1900 case V4L2_CTRL_TYPE_BOOLEAN:
1901 ciptr->type = pvr2_ctl_bool;
1902 break;
1903 case V4L2_CTRL_TYPE_MENU:
1904 ciptr->type = pvr2_ctl_enum;
1905 ciptr->def.type_enum.value_names =
1906 cx2341x_ctrl_get_menu(ciptr->v4l_id);
1907 for (cnt1 = 0;
1908 ciptr->def.type_enum.value_names[cnt1] != NULL;
1909 cnt1++) { }
1910 ciptr->def.type_enum.count = cnt1;
1911 break;
1912 }
1913 cptr->info = ciptr;
1914 }
1915
1916 // Initialize video standard enum dynamic control
1917 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDENUM);
1918 if (cptr) {
1919 memcpy(&hdw->std_info_enum,cptr->info,
1920 sizeof(hdw->std_info_enum));
1921 cptr->info = &hdw->std_info_enum;
1922
1923 }
1924 // Initialize control data regarding video standard masks
1925 valid_std_mask = pvr2_std_get_usable();
1926 for (idx = 0; idx < 32; idx++) {
1927 if (!(valid_std_mask & (1 << idx))) continue;
1928 cnt1 = pvr2_std_id_to_str(
1929 hdw->std_mask_names[idx],
1930 sizeof(hdw->std_mask_names[idx])-1,
1931 1 << idx);
1932 hdw->std_mask_names[idx][cnt1] = 0;
1933 }
1934 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDAVAIL);
1935 if (cptr) {
1936 memcpy(&hdw->std_info_avail,cptr->info,
1937 sizeof(hdw->std_info_avail));
1938 cptr->info = &hdw->std_info_avail;
1939 hdw->std_info_avail.def.type_bitmask.bit_names =
1940 hdw->std_mask_ptrs;
1941 hdw->std_info_avail.def.type_bitmask.valid_bits =
1942 valid_std_mask;
1943 }
1944 cptr = pvr2_hdw_get_ctrl_by_id(hdw,PVR2_CID_STDCUR);
1945 if (cptr) {
1946 memcpy(&hdw->std_info_cur,cptr->info,
1947 sizeof(hdw->std_info_cur));
1948 cptr->info = &hdw->std_info_cur;
1949 hdw->std_info_cur.def.type_bitmask.bit_names =
1950 hdw->std_mask_ptrs;
1951 hdw->std_info_avail.def.type_bitmask.valid_bits =
1952 valid_std_mask;
1953 }
1954
1955 hdw->eeprom_addr = -1;
1956 hdw->unit_number = -1;
1957 hdw->v4l_minor_number_video = -1;
1958 hdw->v4l_minor_number_vbi = -1;
1959 hdw->v4l_minor_number_radio = -1;
1960 hdw->ctl_write_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
1961 if (!hdw->ctl_write_buffer) goto fail;
1962 hdw->ctl_read_buffer = kmalloc(PVR2_CTL_BUFFSIZE,GFP_KERNEL);
1963 if (!hdw->ctl_read_buffer) goto fail;
1964 hdw->ctl_write_urb = usb_alloc_urb(0,GFP_KERNEL);
1965 if (!hdw->ctl_write_urb) goto fail;
1966 hdw->ctl_read_urb = usb_alloc_urb(0,GFP_KERNEL);
1967 if (!hdw->ctl_read_urb) goto fail;
1968
1969 mutex_lock(&pvr2_unit_mtx); do {
1970 for (idx = 0; idx < PVR_NUM; idx++) {
1971 if (unit_pointers[idx]) continue;
1972 hdw->unit_number = idx;
1973 unit_pointers[idx] = hdw;
1974 break;
1975 }
1976 } while (0); mutex_unlock(&pvr2_unit_mtx);
1977
1978 cnt1 = 0;
1979 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"pvrusb2");
1980 cnt1 += cnt2;
1981 if (hdw->unit_number >= 0) {
1982 cnt2 = scnprintf(hdw->name+cnt1,sizeof(hdw->name)-cnt1,"_%c",
1983 ('a' + hdw->unit_number));
1984 cnt1 += cnt2;
1985 }
1986 if (cnt1 >= sizeof(hdw->name)) cnt1 = sizeof(hdw->name)-1;
1987 hdw->name[cnt1] = 0;
1988
1989 hdw->workqueue = create_singlethread_workqueue(hdw->name);
1990 INIT_WORK(&hdw->workpoll,pvr2_hdw_worker_poll);
1991 INIT_WORK(&hdw->worki2csync,pvr2_hdw_worker_i2c);
1992 INIT_WORK(&hdw->workinit,pvr2_hdw_worker_init);
1993
1994 pvr2_trace(PVR2_TRACE_INIT,"Driver unit number is %d, name is %s",
1995 hdw->unit_number,hdw->name);
1996
1997 hdw->tuner_type = -1;
1998 hdw->flag_ok = !0;
1999
2000 hdw->usb_intf = intf;
2001 hdw->usb_dev = interface_to_usbdev(intf);
2002
2003 scnprintf(hdw->bus_info,sizeof(hdw->bus_info),
2004 "usb %s address %d",
2005 hdw->usb_dev->dev.bus_id,
2006 hdw->usb_dev->devnum);
2007
2008 ifnum = hdw->usb_intf->cur_altsetting->desc.bInterfaceNumber;
2009 usb_set_interface(hdw->usb_dev,ifnum,0);
2010
2011 mutex_init(&hdw->ctl_lock_mutex);
2012 mutex_init(&hdw->big_lock_mutex);
2013
2014 queue_work(hdw->workqueue,&hdw->workinit);
2015 return hdw;
2016 fail:
2017 if (hdw) {
2018 del_timer_sync(&hdw->quiescent_timer);
2019 del_timer_sync(&hdw->encoder_wait_timer);
2020 if (hdw->workqueue) {
2021 flush_workqueue(hdw->workqueue);
2022 destroy_workqueue(hdw->workqueue);
2023 hdw->workqueue = NULL;
2024 }
2025 usb_free_urb(hdw->ctl_read_urb);
2026 usb_free_urb(hdw->ctl_write_urb);
2027 kfree(hdw->ctl_read_buffer);
2028 kfree(hdw->ctl_write_buffer);
2029 kfree(hdw->controls);
2030 kfree(hdw->mpeg_ctrl_info);
2031 kfree(hdw->std_defs);
2032 kfree(hdw->std_enum_names);
2033 kfree(hdw);
2034 }
2035 return NULL;
2036 }
2037
2038
2039 /* Remove _all_ associations between this driver and the underlying USB
2040 layer. */
2041 static void pvr2_hdw_remove_usb_stuff(struct pvr2_hdw *hdw)
2042 {
2043 if (hdw->flag_disconnected) return;
2044 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_remove_usb_stuff: hdw=%p",hdw);
2045 if (hdw->ctl_read_urb) {
2046 usb_kill_urb(hdw->ctl_read_urb);
2047 usb_free_urb(hdw->ctl_read_urb);
2048 hdw->ctl_read_urb = NULL;
2049 }
2050 if (hdw->ctl_write_urb) {
2051 usb_kill_urb(hdw->ctl_write_urb);
2052 usb_free_urb(hdw->ctl_write_urb);
2053 hdw->ctl_write_urb = NULL;
2054 }
2055 if (hdw->ctl_read_buffer) {
2056 kfree(hdw->ctl_read_buffer);
2057 hdw->ctl_read_buffer = NULL;
2058 }
2059 if (hdw->ctl_write_buffer) {
2060 kfree(hdw->ctl_write_buffer);
2061 hdw->ctl_write_buffer = NULL;
2062 }
2063 hdw->flag_disconnected = !0;
2064 hdw->usb_dev = NULL;
2065 hdw->usb_intf = NULL;
2066 pvr2_hdw_render_useless(hdw);
2067 }
2068
2069
2070 /* Destroy hardware interaction structure */
2071 void pvr2_hdw_destroy(struct pvr2_hdw *hdw)
2072 {
2073 if (!hdw) return;
2074 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_destroy: hdw=%p",hdw);
2075 del_timer_sync(&hdw->quiescent_timer);
2076 del_timer_sync(&hdw->encoder_wait_timer);
2077 if (hdw->workqueue) {
2078 flush_workqueue(hdw->workqueue);
2079 destroy_workqueue(hdw->workqueue);
2080 hdw->workqueue = NULL;
2081 }
2082 if (hdw->fw_buffer) {
2083 kfree(hdw->fw_buffer);
2084 hdw->fw_buffer = NULL;
2085 }
2086 if (hdw->vid_stream) {
2087 pvr2_stream_destroy(hdw->vid_stream);
2088 hdw->vid_stream = NULL;
2089 }
2090 if (hdw->decoder_ctrl) {
2091 hdw->decoder_ctrl->detach(hdw->decoder_ctrl->ctxt);
2092 }
2093 pvr2_i2c_core_done(hdw);
2094 pvr2_hdw_remove_usb_stuff(hdw);
2095 mutex_lock(&pvr2_unit_mtx); do {
2096 if ((hdw->unit_number >= 0) &&
2097 (hdw->unit_number < PVR_NUM) &&
2098 (unit_pointers[hdw->unit_number] == hdw)) {
2099 unit_pointers[hdw->unit_number] = NULL;
2100 }
2101 } while (0); mutex_unlock(&pvr2_unit_mtx);
2102 kfree(hdw->controls);
2103 kfree(hdw->mpeg_ctrl_info);
2104 kfree(hdw->std_defs);
2105 kfree(hdw->std_enum_names);
2106 kfree(hdw);
2107 }
2108
2109
2110 int pvr2_hdw_dev_ok(struct pvr2_hdw *hdw)
2111 {
2112 return (hdw && hdw->flag_ok);
2113 }
2114
2115
2116 /* Called when hardware has been unplugged */
2117 void pvr2_hdw_disconnect(struct pvr2_hdw *hdw)
2118 {
2119 pvr2_trace(PVR2_TRACE_INIT,"pvr2_hdw_disconnect(hdw=%p)",hdw);
2120 LOCK_TAKE(hdw->big_lock);
2121 LOCK_TAKE(hdw->ctl_lock);
2122 pvr2_hdw_remove_usb_stuff(hdw);
2123 LOCK_GIVE(hdw->ctl_lock);
2124 LOCK_GIVE(hdw->big_lock);
2125 }
2126
2127
2128 // Attempt to autoselect an appropriate value for std_enum_cur given
2129 // whatever is currently in std_mask_cur
2130 static void pvr2_hdw_internal_find_stdenum(struct pvr2_hdw *hdw)
2131 {
2132 unsigned int idx;
2133 for (idx = 1; idx < hdw->std_enum_cnt; idx++) {
2134 if (hdw->std_defs[idx-1].id == hdw->std_mask_cur) {
2135 hdw->std_enum_cur = idx;
2136 return;
2137 }
2138 }
2139 hdw->std_enum_cur = 0;
2140 }
2141
2142
2143 // Calculate correct set of enumerated standards based on currently known
2144 // set of available standards bits.
2145 static void pvr2_hdw_internal_set_std_avail(struct pvr2_hdw *hdw)
2146 {
2147 struct v4l2_standard *newstd;
2148 unsigned int std_cnt;
2149 unsigned int idx;
2150
2151 newstd = pvr2_std_create_enum(&std_cnt,hdw->std_mask_avail);
2152
2153 if (hdw->std_defs) {
2154 kfree(hdw->std_defs);
2155 hdw->std_defs = NULL;
2156 }
2157 hdw->std_enum_cnt = 0;
2158 if (hdw->std_enum_names) {
2159 kfree(hdw->std_enum_names);
2160 hdw->std_enum_names = NULL;
2161 }
2162
2163 if (!std_cnt) {
2164 pvr2_trace(
2165 PVR2_TRACE_ERROR_LEGS,
2166 "WARNING: Failed to identify any viable standards");
2167 }
2168 hdw->std_enum_names = kmalloc(sizeof(char *)*(std_cnt+1),GFP_KERNEL);
2169 hdw->std_enum_names[0] = "none";
2170 for (idx = 0; idx < std_cnt; idx++) {
2171 hdw->std_enum_names[idx+1] =
2172 newstd[idx].name;
2173 }
2174 // Set up the dynamic control for this standard
2175 hdw->std_info_enum.def.type_enum.value_names = hdw->std_enum_names;
2176 hdw->std_info_enum.def.type_enum.count = std_cnt+1;
2177 hdw->std_defs = newstd;
2178 hdw->std_enum_cnt = std_cnt+1;
2179 hdw->std_enum_cur = 0;
2180 hdw->std_info_cur.def.type_bitmask.valid_bits = hdw->std_mask_avail;
2181 }
2182
2183
2184 int pvr2_hdw_get_stdenum_value(struct pvr2_hdw *hdw,
2185 struct v4l2_standard *std,
2186 unsigned int idx)
2187 {
2188 int ret = -EINVAL;
2189 if (!idx) return ret;
2190 LOCK_TAKE(hdw->big_lock); do {
2191 if (idx >= hdw->std_enum_cnt) break;
2192 idx--;
2193 memcpy(std,hdw->std_defs+idx,sizeof(*std));
2194 ret = 0;
2195 } while (0); LOCK_GIVE(hdw->big_lock);
2196 return ret;
2197 }
2198
2199
2200 /* Get the number of defined controls */
2201 unsigned int pvr2_hdw_get_ctrl_count(struct pvr2_hdw *hdw)
2202 {
2203 return hdw->control_cnt;
2204 }
2205
2206
2207 /* Retrieve a control handle given its index (0..count-1) */
2208 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_index(struct pvr2_hdw *hdw,
2209 unsigned int idx)
2210 {
2211 if (idx >= hdw->control_cnt) return NULL;
2212 return hdw->controls + idx;
2213 }
2214
2215
2216 /* Retrieve a control handle given its index (0..count-1) */
2217 struct pvr2_ctrl *pvr2_hdw_get_ctrl_by_id(struct pvr2_hdw *hdw,
2218 unsigned int ctl_id)
2219 {
2220 struct pvr2_ctrl *cptr;
2221 unsigned int idx;
2222 int i;
2223
2224 /* This could be made a lot more efficient, but for now... */
2225 for (idx = 0; idx < hdw->control_cnt; idx++) {
2226 cptr = hdw->controls + idx;
2227 i = cptr->info->internal_id;
2228 if (i && (i == ctl_id)) return cptr;
2229 }
2230 return NULL;
2231 }
2232
2233
2234 /* Given a V4L ID, retrieve the control structure associated with it. */
2235 struct pvr2_ctrl *pvr2_hdw_get_ctrl_v4l(struct pvr2_hdw *hdw,unsigned int ctl_id)
2236 {
2237 struct pvr2_ctrl *cptr;
2238 unsigned int idx;
2239 int i;
2240
2241 /* This could be made a lot more efficient, but for now... */
2242 for (idx = 0; idx < hdw->control_cnt; idx++) {
2243 cptr = hdw->controls + idx;
2244 i = cptr->info->v4l_id;
2245 if (i && (i == ctl_id)) return cptr;
2246 }
2247 return NULL;
2248 }
2249
2250
2251 /* Given a V4L ID for its immediate predecessor, retrieve the control
2252 structure associated with it. */
2253 struct pvr2_ctrl *pvr2_hdw_get_ctrl_nextv4l(struct pvr2_hdw *hdw,
2254 unsigned int ctl_id)
2255 {
2256 struct pvr2_ctrl *cptr,*cp2;
2257 unsigned int idx;
2258 int i;
2259
2260 /* This could be made a lot more efficient, but for now... */
2261 cp2 = NULL;
2262 for (idx = 0; idx < hdw->control_cnt; idx++) {
2263 cptr = hdw->controls + idx;
2264 i = cptr->info->v4l_id;
2265 if (!i) continue;
2266 if (i <= ctl_id) continue;
2267 if (cp2 && (cp2->info->v4l_id < i)) continue;
2268 cp2 = cptr;
2269 }
2270 return cp2;
2271 return NULL;
2272 }
2273
2274
2275 static const char *get_ctrl_typename(enum pvr2_ctl_type tp)
2276 {
2277 switch (tp) {
2278 case pvr2_ctl_int: return "integer";
2279 case pvr2_ctl_enum: return "enum";
2280 case pvr2_ctl_bool: return "boolean";
2281 case pvr2_ctl_bitmask: return "bitmask";
2282 }
2283 return "";
2284 }
2285
2286
2287 /* Figure out if we need to commit control changes. If so, mark internal
2288 state flags to indicate this fact and return true. Otherwise do nothing
2289 else and return false. */
2290 static int pvr2_hdw_commit_setup(struct pvr2_hdw *hdw)
2291 {
2292 unsigned int idx;
2293 struct pvr2_ctrl *cptr;
2294 int value;
2295 int commit_flag = 0;
2296 char buf[100];
2297 unsigned int bcnt,ccnt;
2298
2299 for (idx = 0; idx < hdw->control_cnt; idx++) {
2300 cptr = hdw->controls + idx;
2301 if (cptr->info->is_dirty == 0) continue;
2302 if (!cptr->info->is_dirty(cptr)) continue;
2303 commit_flag = !0;
2304
2305 if (!(pvrusb2_debug & PVR2_TRACE_CTL)) continue;
2306 bcnt = scnprintf(buf,sizeof(buf),"\"%s\" <-- ",
2307 cptr->info->name);
2308 value = 0;
2309 cptr->info->get_value(cptr,&value);
2310 pvr2_ctrl_value_to_sym_internal(cptr,~0,value,
2311 buf+bcnt,
2312 sizeof(buf)-bcnt,&ccnt);
2313 bcnt += ccnt;
2314 bcnt += scnprintf(buf+bcnt,sizeof(buf)-bcnt," <%s>",
2315 get_ctrl_typename(cptr->info->type));
2316 pvr2_trace(PVR2_TRACE_CTL,
2317 "/*--TRACE_COMMIT--*/ %.*s",
2318 bcnt,buf);
2319 }
2320
2321 if (!commit_flag) {
2322 /* Nothing has changed */
2323 return 0;
2324 }
2325
2326 hdw->state_pipeline_config = 0;
2327 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
2328 pvr2_hdw_state_sched(hdw);
2329
2330 return !0;
2331 }
2332
2333
2334 /* Perform all operations needed to commit all control changes. This must
2335 be performed in synchronization with the pipeline state and is thus
2336 expected to be called as part of the driver's worker thread. Return
2337 true if commit successful, otherwise return false to indicate that
2338 commit isn't possible at this time. */
2339 static int pvr2_hdw_commit_execute(struct pvr2_hdw *hdw)
2340 {
2341 unsigned int idx;
2342 struct pvr2_ctrl *cptr;
2343 int disruptive_change;
2344
2345 /* When video standard changes, reset the hres and vres values -
2346 but if the user has pending changes there, then let the changes
2347 take priority. */
2348 if (hdw->std_dirty) {
2349 /* Rewrite the vertical resolution to be appropriate to the
2350 video standard that has been selected. */
2351 int nvres;
2352 if (hdw->std_mask_cur & V4L2_STD_525_60) {
2353 nvres = 480;
2354 } else {
2355 nvres = 576;
2356 }
2357 if (nvres != hdw->res_ver_val) {
2358 hdw->res_ver_val = nvres;
2359 hdw->res_ver_dirty = !0;
2360 }
2361 }
2362
2363 /* If any of the below has changed, then we can't do the update
2364 while the pipeline is running. Pipeline must be paused first
2365 and decoder -> encoder connection be made quiescent before we
2366 can proceed. */
2367 disruptive_change =
2368 (hdw->std_dirty ||
2369 hdw->enc_unsafe_stale ||
2370 hdw->srate_dirty ||
2371 hdw->res_ver_dirty ||
2372 hdw->res_hor_dirty ||
2373 hdw->input_dirty ||
2374 (hdw->active_stream_type != hdw->desired_stream_type));
2375 if (disruptive_change && !hdw->state_pipeline_idle) {
2376 /* Pipeline is not idle; we can't proceed. Arrange to
2377 cause pipeline to stop so that we can try this again
2378 later.... */
2379 hdw->state_pipeline_pause = !0;
2380 return 0;
2381 }
2382
2383 if (hdw->srate_dirty) {
2384 /* Write new sample rate into control structure since
2385 * the master copy is stale. We must track srate
2386 * separate from the mpeg control structure because
2387 * other logic also uses this value. */
2388 struct v4l2_ext_controls cs;
2389 struct v4l2_ext_control c1;
2390 memset(&cs,0,sizeof(cs));
2391 memset(&c1,0,sizeof(c1));
2392 cs.controls = &c1;
2393 cs.count = 1;
2394 c1.id = V4L2_CID_MPEG_AUDIO_SAMPLING_FREQ;
2395 c1.value = hdw->srate_val;
2396 cx2341x_ext_ctrls(&hdw->enc_ctl_state, 0, &cs,VIDIOC_S_EXT_CTRLS);
2397 }
2398
2399 /* Scan i2c core at this point - before we clear all the dirty
2400 bits. Various parts of the i2c core will notice dirty bits as
2401 appropriate and arrange to broadcast or directly send updates to
2402 the client drivers in order to keep everything in sync */
2403 pvr2_i2c_core_check_stale(hdw);
2404
2405 for (idx = 0; idx < hdw->control_cnt; idx++) {
2406 cptr = hdw->controls + idx;
2407 if (!cptr->info->clear_dirty) continue;
2408 cptr->info->clear_dirty(cptr);
2409 }
2410
2411 if (hdw->active_stream_type != hdw->desired_stream_type) {
2412 /* Handle any side effects of stream config here */
2413 hdw->active_stream_type = hdw->desired_stream_type;
2414 }
2415
2416 /* Now execute i2c core update */
2417 pvr2_i2c_core_sync(hdw);
2418
2419 if (hdw->state_encoder_run) {
2420 /* If encoder isn't running, then this will get worked out
2421 later when we start the encoder. */
2422 if (pvr2_encoder_adjust(hdw) < 0) return !0;
2423 }
2424
2425 hdw->state_pipeline_config = !0;
2426 trace_stbit("state_pipeline_config",hdw->state_pipeline_config);
2427 return !0;
2428 }
2429
2430
2431 int pvr2_hdw_commit_ctl(struct pvr2_hdw *hdw)
2432 {
2433 int fl;
2434 LOCK_TAKE(hdw->big_lock);
2435 fl = pvr2_hdw_commit_setup(hdw);
2436 LOCK_GIVE(hdw->big_lock);
2437 if (!fl) return 0;
2438 return pvr2_hdw_wait(hdw,0);
2439 }
2440
2441
2442 static void pvr2_hdw_worker_i2c(struct work_struct *work)
2443 {
2444 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,worki2csync);
2445 LOCK_TAKE(hdw->big_lock); do {
2446 pvr2_i2c_core_sync(hdw);
2447 } while (0); LOCK_GIVE(hdw->big_lock);
2448 }
2449
2450
2451 static void pvr2_hdw_worker_poll(struct work_struct *work)
2452 {
2453 int fl = 0;
2454 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workpoll);
2455 LOCK_TAKE(hdw->big_lock); do {
2456 fl = pvr2_hdw_state_eval(hdw);
2457 } while (0); LOCK_GIVE(hdw->big_lock);
2458 if (fl && hdw->state_func) {
2459 hdw->state_func(hdw->state_data);
2460 }
2461 }
2462
2463
2464 static void pvr2_hdw_worker_init(struct work_struct *work)
2465 {
2466 struct pvr2_hdw *hdw = container_of(work,struct pvr2_hdw,workinit);
2467 LOCK_TAKE(hdw->big_lock); do {
2468 pvr2_hdw_setup(hdw);
2469 } while (0); LOCK_GIVE(hdw->big_lock);
2470 }
2471
2472
2473 static int pvr2_hdw_wait(struct pvr2_hdw *hdw,int state)
2474 {
2475 return wait_event_interruptible(
2476 hdw->state_wait_data,
2477 (hdw->state_stale == 0) &&
2478 (!state || (hdw->master_state != state)));
2479 }
2480
2481
2482 void pvr2_hdw_set_state_callback(struct pvr2_hdw *hdw,
2483 void (*callback_func)(void *),
2484 void *callback_data)
2485 {
2486 LOCK_TAKE(hdw->big_lock); do {
2487 hdw->state_data = callback_data;
2488 hdw->state_func = callback_func;
2489 } while (0); LOCK_GIVE(hdw->big_lock);
2490 }
2491
2492
2493 /* Return name for this driver instance */
2494 const char *pvr2_hdw_get_driver_name(struct pvr2_hdw *hdw)
2495 {
2496 return hdw->name;
2497 }
2498
2499
2500 const char *pvr2_hdw_get_desc(struct pvr2_hdw *hdw)
2501 {
2502 return hdw->hdw_desc->description;
2503 }
2504
2505
2506 const char *pvr2_hdw_get_type(struct pvr2_hdw *hdw)
2507 {
2508 return hdw->hdw_desc->shortname;
2509 }
2510
2511
2512 int pvr2_hdw_is_hsm(struct pvr2_hdw *hdw)
2513 {
2514 int result;
2515 LOCK_TAKE(hdw->ctl_lock); do {
2516 hdw->cmd_buffer[0] = FX2CMD_GET_USB_SPEED;
2517 result = pvr2_send_request(hdw,
2518 hdw->cmd_buffer,1,
2519 hdw->cmd_buffer,1);
2520 if (result < 0) break;
2521 result = (hdw->cmd_buffer[0] != 0);
2522 } while(0); LOCK_GIVE(hdw->ctl_lock);
2523 return result;
2524 }
2525
2526
2527 /* Execute poll of tuner status */
2528 void pvr2_hdw_execute_tuner_poll(struct pvr2_hdw *hdw)
2529 {
2530 LOCK_TAKE(hdw->big_lock); do {
2531 pvr2_i2c_core_status_poll(hdw);
2532 } while (0); LOCK_GIVE(hdw->big_lock);
2533 }
2534
2535
2536 /* Return information about the tuner */
2537 int pvr2_hdw_get_tuner_status(struct pvr2_hdw *hdw,struct v4l2_tuner *vtp)
2538 {
2539 LOCK_TAKE(hdw->big_lock); do {
2540 if (hdw->tuner_signal_stale) {
2541 pvr2_i2c_core_status_poll(hdw);
2542 }
2543 memcpy(vtp,&hdw->tuner_signal_info,sizeof(struct v4l2_tuner));
2544 } while (0); LOCK_GIVE(hdw->big_lock);
2545 return 0;
2546 }
2547
2548
2549 /* Get handle to video output stream */
2550 struct pvr2_stream *pvr2_hdw_get_video_stream(struct pvr2_hdw *hp)
2551 {
2552 return hp->vid_stream;
2553 }
2554
2555
2556 void pvr2_hdw_trigger_module_log(struct pvr2_hdw *hdw)
2557 {
2558 int nr = pvr2_hdw_get_unit_number(hdw);
2559 LOCK_TAKE(hdw->big_lock); do {
2560 hdw->log_requested = !0;
2561 printk(KERN_INFO "pvrusb2: ================= START STATUS CARD #%d =================\n", nr);
2562 pvr2_i2c_core_check_stale(hdw);
2563 hdw->log_requested = 0;
2564 pvr2_i2c_core_sync(hdw);
2565 pvr2_trace(PVR2_TRACE_INFO,"cx2341x config:");
2566 cx2341x_log_status(&hdw->enc_ctl_state, "pvrusb2");
2567 pvr2_hdw_state_log_state(hdw);
2568 printk(KERN_INFO "pvrusb2: ================== END STATUS CARD #%d ==================\n", nr);
2569 } while (0); LOCK_GIVE(hdw->big_lock);
2570 }
2571
2572
2573 /* Grab EEPROM contents, needed for direct method. */
2574 #define EEPROM_SIZE 8192
2575 #define trace_eeprom(...) pvr2_trace(PVR2_TRACE_EEPROM,__VA_ARGS__)
2576 static u8 *pvr2_full_eeprom_fetch(struct pvr2_hdw *hdw)
2577 {
2578 struct i2c_msg msg[2];
2579 u8 *eeprom;
2580 u8 iadd[2];
2581 u8 addr;
2582 u16 eepromSize;
2583 unsigned int offs;
2584 int ret;
2585 int mode16 = 0;
2586 unsigned pcnt,tcnt;
2587 eeprom = kmalloc(EEPROM_SIZE,GFP_KERNEL);
2588 if (!eeprom) {
2589 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2590 "Failed to allocate memory"
2591 " required to read eeprom");
2592 return NULL;
2593 }
2594
2595 trace_eeprom("Value for eeprom addr from controller was 0x%x",
2596 hdw->eeprom_addr);
2597 addr = hdw->eeprom_addr;
2598 /* Seems that if the high bit is set, then the *real* eeprom
2599 address is shifted right now bit position (noticed this in
2600 newer PVR USB2 hardware) */
2601 if (addr & 0x80) addr >>= 1;
2602
2603 /* FX2 documentation states that a 16bit-addressed eeprom is
2604 expected if the I2C address is an odd number (yeah, this is
2605 strange but it's what they do) */
2606 mode16 = (addr & 1);
2607 eepromSize = (mode16 ? EEPROM_SIZE : 256);
2608 trace_eeprom("Examining %d byte eeprom at location 0x%x"
2609 " using %d bit addressing",eepromSize,addr,
2610 mode16 ? 16 : 8);
2611
2612 msg[0].addr = addr;
2613 msg[0].flags = 0;
2614 msg[0].len = mode16 ? 2 : 1;
2615 msg[0].buf = iadd;
2616 msg[1].addr = addr;
2617 msg[1].flags = I2C_M_RD;
2618
2619 /* We have to do the actual eeprom data fetch ourselves, because
2620 (1) we're only fetching part of the eeprom, and (2) if we were
2621 getting the whole thing our I2C driver can't grab it in one
2622 pass - which is what tveeprom is otherwise going to attempt */
2623 memset(eeprom,0,EEPROM_SIZE);
2624 for (tcnt = 0; tcnt < EEPROM_SIZE; tcnt += pcnt) {
2625 pcnt = 16;
2626 if (pcnt + tcnt > EEPROM_SIZE) pcnt = EEPROM_SIZE-tcnt;
2627 offs = tcnt + (eepromSize - EEPROM_SIZE);
2628 if (mode16) {
2629 iadd[0] = offs >> 8;
2630 iadd[1] = offs;
2631 } else {
2632 iadd[0] = offs;
2633 }
2634 msg[1].len = pcnt;
2635 msg[1].buf = eeprom+tcnt;
2636 if ((ret = i2c_transfer(&hdw->i2c_adap,
2637 msg,ARRAY_SIZE(msg))) != 2) {
2638 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2639 "eeprom fetch set offs err=%d",ret);
2640 kfree(eeprom);
2641 return NULL;
2642 }
2643 }
2644 return eeprom;
2645 }
2646
2647
2648 void pvr2_hdw_cpufw_set_enabled(struct pvr2_hdw *hdw,
2649 int prom_flag,
2650 int enable_flag)
2651 {
2652 int ret;
2653 u16 address;
2654 unsigned int pipe;
2655 LOCK_TAKE(hdw->big_lock); do {
2656 if ((hdw->fw_buffer == 0) == !enable_flag) break;
2657
2658 if (!enable_flag) {
2659 pvr2_trace(PVR2_TRACE_FIRMWARE,
2660 "Cleaning up after CPU firmware fetch");
2661 kfree(hdw->fw_buffer);
2662 hdw->fw_buffer = NULL;
2663 hdw->fw_size = 0;
2664 if (hdw->fw_cpu_flag) {
2665 /* Now release the CPU. It will disconnect
2666 and reconnect later. */
2667 pvr2_hdw_cpureset_assert(hdw,0);
2668 }
2669 break;
2670 }
2671
2672 hdw->fw_cpu_flag = (prom_flag == 0);
2673 if (hdw->fw_cpu_flag) {
2674 pvr2_trace(PVR2_TRACE_FIRMWARE,
2675 "Preparing to suck out CPU firmware");
2676 hdw->fw_size = 0x2000;
2677 hdw->fw_buffer = kzalloc(hdw->fw_size,GFP_KERNEL);
2678 if (!hdw->fw_buffer) {
2679 hdw->fw_size = 0;
2680 break;
2681 }
2682
2683 /* We have to hold the CPU during firmware upload. */
2684 pvr2_hdw_cpureset_assert(hdw,1);
2685
2686 /* download the firmware from address 0000-1fff in 2048
2687 (=0x800) bytes chunk. */
2688
2689 pvr2_trace(PVR2_TRACE_FIRMWARE,
2690 "Grabbing CPU firmware");
2691 pipe = usb_rcvctrlpipe(hdw->usb_dev, 0);
2692 for(address = 0; address < hdw->fw_size;
2693 address += 0x800) {
2694 ret = usb_control_msg(hdw->usb_dev,pipe,
2695 0xa0,0xc0,
2696 address,0,
2697 hdw->fw_buffer+address,
2698 0x800,HZ);
2699 if (ret < 0) break;
2700 }
2701
2702 pvr2_trace(PVR2_TRACE_FIRMWARE,
2703 "Done grabbing CPU firmware");
2704 } else {
2705 pvr2_trace(PVR2_TRACE_FIRMWARE,
2706 "Sucking down EEPROM contents");
2707 hdw->fw_buffer = pvr2_full_eeprom_fetch(hdw);
2708 if (!hdw->fw_buffer) {
2709 pvr2_trace(PVR2_TRACE_FIRMWARE,
2710 "EEPROM content suck failed.");
2711 break;
2712 }
2713 hdw->fw_size = EEPROM_SIZE;
2714 pvr2_trace(PVR2_TRACE_FIRMWARE,
2715 "Done sucking down EEPROM contents");
2716 }
2717
2718 } while (0); LOCK_GIVE(hdw->big_lock);
2719 }
2720
2721
2722 /* Return true if we're in a mode for retrieval CPU firmware */
2723 int pvr2_hdw_cpufw_get_enabled(struct pvr2_hdw *hdw)
2724 {
2725 return hdw->fw_buffer != 0;
2726 }
2727
2728
2729 int pvr2_hdw_cpufw_get(struct pvr2_hdw *hdw,unsigned int offs,
2730 char *buf,unsigned int cnt)
2731 {
2732 int ret = -EINVAL;
2733 LOCK_TAKE(hdw->big_lock); do {
2734 if (!buf) break;
2735 if (!cnt) break;
2736
2737 if (!hdw->fw_buffer) {
2738 ret = -EIO;
2739 break;
2740 }
2741
2742 if (offs >= hdw->fw_size) {
2743 pvr2_trace(PVR2_TRACE_FIRMWARE,
2744 "Read firmware data offs=%d EOF",
2745 offs);
2746 ret = 0;
2747 break;
2748 }
2749
2750 if (offs + cnt > hdw->fw_size) cnt = hdw->fw_size - offs;
2751
2752 memcpy(buf,hdw->fw_buffer+offs,cnt);
2753
2754 pvr2_trace(PVR2_TRACE_FIRMWARE,
2755 "Read firmware data offs=%d cnt=%d",
2756 offs,cnt);
2757 ret = cnt;
2758 } while (0); LOCK_GIVE(hdw->big_lock);
2759
2760 return ret;
2761 }
2762
2763
2764 int pvr2_hdw_v4l_get_minor_number(struct pvr2_hdw *hdw,
2765 enum pvr2_v4l_type index)
2766 {
2767 switch (index) {
2768 case pvr2_v4l_type_video: return hdw->v4l_minor_number_video;
2769 case pvr2_v4l_type_vbi: return hdw->v4l_minor_number_vbi;
2770 case pvr2_v4l_type_radio: return hdw->v4l_minor_number_radio;
2771 default: return -1;
2772 }
2773 }
2774
2775
2776 /* Store a v4l minor device number */
2777 void pvr2_hdw_v4l_store_minor_number(struct pvr2_hdw *hdw,
2778 enum pvr2_v4l_type index,int v)
2779 {
2780 switch (index) {
2781 case pvr2_v4l_type_video: hdw->v4l_minor_number_video = v;
2782 case pvr2_v4l_type_vbi: hdw->v4l_minor_number_vbi = v;
2783 case pvr2_v4l_type_radio: hdw->v4l_minor_number_radio = v;
2784 default: break;
2785 }
2786 }
2787
2788
2789 static void pvr2_ctl_write_complete(struct urb *urb)
2790 {
2791 struct pvr2_hdw *hdw = urb->context;
2792 hdw->ctl_write_pend_flag = 0;
2793 if (hdw->ctl_read_pend_flag) return;
2794 complete(&hdw->ctl_done);
2795 }
2796
2797
2798 static void pvr2_ctl_read_complete(struct urb *urb)
2799 {
2800 struct pvr2_hdw *hdw = urb->context;
2801 hdw->ctl_read_pend_flag = 0;
2802 if (hdw->ctl_write_pend_flag) return;
2803 complete(&hdw->ctl_done);
2804 }
2805
2806
2807 static void pvr2_ctl_timeout(unsigned long data)
2808 {
2809 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
2810 if (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2811 hdw->ctl_timeout_flag = !0;
2812 if (hdw->ctl_write_pend_flag)
2813 usb_unlink_urb(hdw->ctl_write_urb);
2814 if (hdw->ctl_read_pend_flag)
2815 usb_unlink_urb(hdw->ctl_read_urb);
2816 }
2817 }
2818
2819
2820 /* Issue a command and get a response from the device. This extended
2821 version includes a probe flag (which if set means that device errors
2822 should not be logged or treated as fatal) and a timeout in jiffies.
2823 This can be used to non-lethally probe the health of endpoint 1. */
2824 static int pvr2_send_request_ex(struct pvr2_hdw *hdw,
2825 unsigned int timeout,int probe_fl,
2826 void *write_data,unsigned int write_len,
2827 void *read_data,unsigned int read_len)
2828 {
2829 unsigned int idx;
2830 int status = 0;
2831 struct timer_list timer;
2832 if (!hdw->ctl_lock_held) {
2833 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2834 "Attempted to execute control transfer"
2835 " without lock!!");
2836 return -EDEADLK;
2837 }
2838 if (!hdw->flag_ok && !probe_fl) {
2839 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2840 "Attempted to execute control transfer"
2841 " when device not ok");
2842 return -EIO;
2843 }
2844 if (!(hdw->ctl_read_urb && hdw->ctl_write_urb)) {
2845 if (!probe_fl) {
2846 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2847 "Attempted to execute control transfer"
2848 " when USB is disconnected");
2849 }
2850 return -ENOTTY;
2851 }
2852
2853 /* Ensure that we have sane parameters */
2854 if (!write_data) write_len = 0;
2855 if (!read_data) read_len = 0;
2856 if (write_len > PVR2_CTL_BUFFSIZE) {
2857 pvr2_trace(
2858 PVR2_TRACE_ERROR_LEGS,
2859 "Attempted to execute %d byte"
2860 " control-write transfer (limit=%d)",
2861 write_len,PVR2_CTL_BUFFSIZE);
2862 return -EINVAL;
2863 }
2864 if (read_len > PVR2_CTL_BUFFSIZE) {
2865 pvr2_trace(
2866 PVR2_TRACE_ERROR_LEGS,
2867 "Attempted to execute %d byte"
2868 " control-read transfer (limit=%d)",
2869 write_len,PVR2_CTL_BUFFSIZE);
2870 return -EINVAL;
2871 }
2872 if ((!write_len) && (!read_len)) {
2873 pvr2_trace(
2874 PVR2_TRACE_ERROR_LEGS,
2875 "Attempted to execute null control transfer?");
2876 return -EINVAL;
2877 }
2878
2879
2880 hdw->cmd_debug_state = 1;
2881 if (write_len) {
2882 hdw->cmd_debug_code = ((unsigned char *)write_data)[0];
2883 } else {
2884 hdw->cmd_debug_code = 0;
2885 }
2886 hdw->cmd_debug_write_len = write_len;
2887 hdw->cmd_debug_read_len = read_len;
2888
2889 /* Initialize common stuff */
2890 init_completion(&hdw->ctl_done);
2891 hdw->ctl_timeout_flag = 0;
2892 hdw->ctl_write_pend_flag = 0;
2893 hdw->ctl_read_pend_flag = 0;
2894 init_timer(&timer);
2895 timer.expires = jiffies + timeout;
2896 timer.data = (unsigned long)hdw;
2897 timer.function = pvr2_ctl_timeout;
2898
2899 if (write_len) {
2900 hdw->cmd_debug_state = 2;
2901 /* Transfer write data to internal buffer */
2902 for (idx = 0; idx < write_len; idx++) {
2903 hdw->ctl_write_buffer[idx] =
2904 ((unsigned char *)write_data)[idx];
2905 }
2906 /* Initiate a write request */
2907 usb_fill_bulk_urb(hdw->ctl_write_urb,
2908 hdw->usb_dev,
2909 usb_sndbulkpipe(hdw->usb_dev,
2910 PVR2_CTL_WRITE_ENDPOINT),
2911 hdw->ctl_write_buffer,
2912 write_len,
2913 pvr2_ctl_write_complete,
2914 hdw);
2915 hdw->ctl_write_urb->actual_length = 0;
2916 hdw->ctl_write_pend_flag = !0;
2917 status = usb_submit_urb(hdw->ctl_write_urb,GFP_KERNEL);
2918 if (status < 0) {
2919 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2920 "Failed to submit write-control"
2921 " URB status=%d",status);
2922 hdw->ctl_write_pend_flag = 0;
2923 goto done;
2924 }
2925 }
2926
2927 if (read_len) {
2928 hdw->cmd_debug_state = 3;
2929 memset(hdw->ctl_read_buffer,0x43,read_len);
2930 /* Initiate a read request */
2931 usb_fill_bulk_urb(hdw->ctl_read_urb,
2932 hdw->usb_dev,
2933 usb_rcvbulkpipe(hdw->usb_dev,
2934 PVR2_CTL_READ_ENDPOINT),
2935 hdw->ctl_read_buffer,
2936 read_len,
2937 pvr2_ctl_read_complete,
2938 hdw);
2939 hdw->ctl_read_urb->actual_length = 0;
2940 hdw->ctl_read_pend_flag = !0;
2941 status = usb_submit_urb(hdw->ctl_read_urb,GFP_KERNEL);
2942 if (status < 0) {
2943 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2944 "Failed to submit read-control"
2945 " URB status=%d",status);
2946 hdw->ctl_read_pend_flag = 0;
2947 goto done;
2948 }
2949 }
2950
2951 /* Start timer */
2952 add_timer(&timer);
2953
2954 /* Now wait for all I/O to complete */
2955 hdw->cmd_debug_state = 4;
2956 while (hdw->ctl_write_pend_flag || hdw->ctl_read_pend_flag) {
2957 wait_for_completion(&hdw->ctl_done);
2958 }
2959 hdw->cmd_debug_state = 5;
2960
2961 /* Stop timer */
2962 del_timer_sync(&timer);
2963
2964 hdw->cmd_debug_state = 6;
2965 status = 0;
2966
2967 if (hdw->ctl_timeout_flag) {
2968 status = -ETIMEDOUT;
2969 if (!probe_fl) {
2970 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2971 "Timed out control-write");
2972 }
2973 goto done;
2974 }
2975
2976 if (write_len) {
2977 /* Validate results of write request */
2978 if ((hdw->ctl_write_urb->status != 0) &&
2979 (hdw->ctl_write_urb->status != -ENOENT) &&
2980 (hdw->ctl_write_urb->status != -ESHUTDOWN) &&
2981 (hdw->ctl_write_urb->status != -ECONNRESET)) {
2982 /* USB subsystem is reporting some kind of failure
2983 on the write */
2984 status = hdw->ctl_write_urb->status;
2985 if (!probe_fl) {
2986 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2987 "control-write URB failure,"
2988 " status=%d",
2989 status);
2990 }
2991 goto done;
2992 }
2993 if (hdw->ctl_write_urb->actual_length < write_len) {
2994 /* Failed to write enough data */
2995 status = -EIO;
2996 if (!probe_fl) {
2997 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
2998 "control-write URB short,"
2999 " expected=%d got=%d",
3000 write_len,
3001 hdw->ctl_write_urb->actual_length);
3002 }
3003 goto done;
3004 }
3005 }
3006 if (read_len) {
3007 /* Validate results of read request */
3008 if ((hdw->ctl_read_urb->status != 0) &&
3009 (hdw->ctl_read_urb->status != -ENOENT) &&
3010 (hdw->ctl_read_urb->status != -ESHUTDOWN) &&
3011 (hdw->ctl_read_urb->status != -ECONNRESET)) {
3012 /* USB subsystem is reporting some kind of failure
3013 on the read */
3014 status = hdw->ctl_read_urb->status;
3015 if (!probe_fl) {
3016 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3017 "control-read URB failure,"
3018 " status=%d",
3019 status);
3020 }
3021 goto done;
3022 }
3023 if (hdw->ctl_read_urb->actual_length < read_len) {
3024 /* Failed to read enough data */
3025 status = -EIO;
3026 if (!probe_fl) {
3027 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3028 "control-read URB short,"
3029 " expected=%d got=%d",
3030 read_len,
3031 hdw->ctl_read_urb->actual_length);
3032 }
3033 goto done;
3034 }
3035 /* Transfer retrieved data out from internal buffer */
3036 for (idx = 0; idx < read_len; idx++) {
3037 ((unsigned char *)read_data)[idx] =
3038 hdw->ctl_read_buffer[idx];
3039 }
3040 }
3041
3042 done:
3043
3044 hdw->cmd_debug_state = 0;
3045 if ((status < 0) && (!probe_fl)) {
3046 pvr2_hdw_render_useless(hdw);
3047 }
3048 return status;
3049 }
3050
3051
3052 int pvr2_send_request(struct pvr2_hdw *hdw,
3053 void *write_data,unsigned int write_len,
3054 void *read_data,unsigned int read_len)
3055 {
3056 return pvr2_send_request_ex(hdw,HZ*4,0,
3057 write_data,write_len,
3058 read_data,read_len);
3059 }
3060
3061 int pvr2_write_register(struct pvr2_hdw *hdw, u16 reg, u32 data)
3062 {
3063 int ret;
3064
3065 LOCK_TAKE(hdw->ctl_lock);
3066
3067 hdw->cmd_buffer[0] = FX2CMD_REG_WRITE; /* write register prefix */
3068 PVR2_DECOMPOSE_LE(hdw->cmd_buffer,1,data);
3069 hdw->cmd_buffer[5] = 0;
3070 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3071 hdw->cmd_buffer[7] = reg & 0xff;
3072
3073
3074 ret = pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 0);
3075
3076 LOCK_GIVE(hdw->ctl_lock);
3077
3078 return ret;
3079 }
3080
3081
3082 static int pvr2_read_register(struct pvr2_hdw *hdw, u16 reg, u32 *data)
3083 {
3084 int ret = 0;
3085
3086 LOCK_TAKE(hdw->ctl_lock);
3087
3088 hdw->cmd_buffer[0] = FX2CMD_REG_READ; /* read register prefix */
3089 hdw->cmd_buffer[1] = 0;
3090 hdw->cmd_buffer[2] = 0;
3091 hdw->cmd_buffer[3] = 0;
3092 hdw->cmd_buffer[4] = 0;
3093 hdw->cmd_buffer[5] = 0;
3094 hdw->cmd_buffer[6] = (reg >> 8) & 0xff;
3095 hdw->cmd_buffer[7] = reg & 0xff;
3096
3097 ret |= pvr2_send_request(hdw, hdw->cmd_buffer, 8, hdw->cmd_buffer, 4);
3098 *data = PVR2_COMPOSE_LE(hdw->cmd_buffer,0);
3099
3100 LOCK_GIVE(hdw->ctl_lock);
3101
3102 return ret;
3103 }
3104
3105
3106 void pvr2_hdw_render_useless(struct pvr2_hdw *hdw)
3107 {
3108 if (!hdw->flag_ok) return;
3109 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3110 "Device being rendered inoperable");
3111 if (hdw->vid_stream) {
3112 pvr2_stream_setup(hdw->vid_stream,NULL,0,0);
3113 }
3114 hdw->flag_ok = 0;
3115 trace_stbit("flag_ok",hdw->flag_ok);
3116 pvr2_hdw_state_sched(hdw);
3117 }
3118
3119
3120 void pvr2_hdw_device_reset(struct pvr2_hdw *hdw)
3121 {
3122 int ret;
3123 pvr2_trace(PVR2_TRACE_INIT,"Performing a device reset...");
3124 ret = usb_lock_device_for_reset(hdw->usb_dev,NULL);
3125 if (ret == 1) {
3126 ret = usb_reset_device(hdw->usb_dev);
3127 usb_unlock_device(hdw->usb_dev);
3128 } else {
3129 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3130 "Failed to lock USB device ret=%d",ret);
3131 }
3132 if (init_pause_msec) {
3133 pvr2_trace(PVR2_TRACE_INFO,
3134 "Waiting %u msec for hardware to settle",
3135 init_pause_msec);
3136 msleep(init_pause_msec);
3137 }
3138
3139 }
3140
3141
3142 void pvr2_hdw_cpureset_assert(struct pvr2_hdw *hdw,int val)
3143 {
3144 char da[1];
3145 unsigned int pipe;
3146 int ret;
3147
3148 if (!hdw->usb_dev) return;
3149
3150 pvr2_trace(PVR2_TRACE_INIT,"cpureset_assert(%d)",val);
3151
3152 da[0] = val ? 0x01 : 0x00;
3153
3154 /* Write the CPUCS register on the 8051. The lsb of the register
3155 is the reset bit; a 1 asserts reset while a 0 clears it. */
3156 pipe = usb_sndctrlpipe(hdw->usb_dev, 0);
3157 ret = usb_control_msg(hdw->usb_dev,pipe,0xa0,0x40,0xe600,0,da,1,HZ);
3158 if (ret < 0) {
3159 pvr2_trace(PVR2_TRACE_ERROR_LEGS,
3160 "cpureset_assert(%d) error=%d",val,ret);
3161 pvr2_hdw_render_useless(hdw);
3162 }
3163 }
3164
3165
3166 int pvr2_hdw_cmd_deep_reset(struct pvr2_hdw *hdw)
3167 {
3168 int status;
3169 LOCK_TAKE(hdw->ctl_lock); do {
3170 pvr2_trace(PVR2_TRACE_INIT,"Requesting uproc hard reset");
3171 hdw->cmd_buffer[0] = FX2CMD_DEEP_RESET;
3172 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
3173 } while (0); LOCK_GIVE(hdw->ctl_lock);
3174 return status;
3175 }
3176
3177
3178 int pvr2_hdw_cmd_powerup(struct pvr2_hdw *hdw)
3179 {
3180 int status;
3181 LOCK_TAKE(hdw->ctl_lock); do {
3182 pvr2_trace(PVR2_TRACE_INIT,"Requesting powerup");
3183 hdw->cmd_buffer[0] = FX2CMD_POWER_ON;
3184 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
3185 } while (0); LOCK_GIVE(hdw->ctl_lock);
3186 return status;
3187 }
3188
3189
3190 int pvr2_hdw_cmd_decoder_reset(struct pvr2_hdw *hdw)
3191 {
3192 if (!hdw->decoder_ctrl) {
3193 pvr2_trace(PVR2_TRACE_INIT,
3194 "Unable to reset decoder: nothing attached");
3195 return -ENOTTY;
3196 }
3197
3198 if (!hdw->decoder_ctrl->force_reset) {
3199 pvr2_trace(PVR2_TRACE_INIT,
3200 "Unable to reset decoder: not implemented");
3201 return -ENOTTY;
3202 }
3203
3204 pvr2_trace(PVR2_TRACE_INIT,
3205 "Requesting decoder reset");
3206 hdw->decoder_ctrl->force_reset(hdw->decoder_ctrl->ctxt);
3207 return 0;
3208 }
3209
3210
3211 /* Stop / start video stream transport */
3212 static int pvr2_hdw_cmd_usbstream(struct pvr2_hdw *hdw,int runFl)
3213 {
3214 int status;
3215 LOCK_TAKE(hdw->ctl_lock); do {
3216 hdw->cmd_buffer[0] =
3217 (runFl ? FX2CMD_STREAMING_ON : FX2CMD_STREAMING_OFF);
3218 status = pvr2_send_request(hdw,hdw->cmd_buffer,1,NULL,0);
3219 } while (0); LOCK_GIVE(hdw->ctl_lock);
3220 return status;
3221 }
3222
3223
3224 /* Evaluate whether or not state_encoder_ok can change */
3225 static int state_eval_encoder_ok(struct pvr2_hdw *hdw)
3226 {
3227 if (hdw->state_encoder_ok) return 0;
3228 if (hdw->flag_tripped) return 0;
3229 if (hdw->state_encoder_run) return 0;
3230 if (hdw->state_encoder_config) return 0;
3231 if (hdw->state_decoder_run) return 0;
3232 if (hdw->state_usbstream_run) return 0;
3233 if (pvr2_upload_firmware2(hdw) < 0) {
3234 hdw->flag_tripped = !0;
3235 trace_stbit("flag_tripped",hdw->flag_tripped);
3236 return !0;
3237 }
3238 hdw->state_encoder_ok = !0;
3239 trace_stbit("state_encoder_ok",hdw->state_encoder_ok);
3240 return !0;
3241 }
3242
3243
3244 /* Evaluate whether or not state_encoder_config can change */
3245 static int state_eval_encoder_config(struct pvr2_hdw *hdw)
3246 {
3247 if (hdw->state_encoder_config) {
3248 if (hdw->state_encoder_ok) {
3249 if (hdw->state_pipeline_req &&
3250 !hdw->state_pipeline_pause) return 0;
3251 }
3252 hdw->state_encoder_config = 0;
3253 hdw->state_encoder_waitok = 0;
3254 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
3255 /* paranoia - solve race if timer just completed */
3256 del_timer_sync(&hdw->encoder_wait_timer);
3257 } else {
3258 if (!hdw->state_encoder_ok ||
3259 !hdw->state_pipeline_idle ||
3260 hdw->state_pipeline_pause ||
3261 !hdw->state_pipeline_req ||
3262 !hdw->state_pipeline_config) {
3263 /* We must reset the enforced wait interval if
3264 anything has happened that might have disturbed
3265 the encoder. This should be a rare case. */
3266 if (timer_pending(&hdw->encoder_wait_timer)) {
3267 del_timer_sync(&hdw->encoder_wait_timer);
3268 }
3269 if (hdw->state_encoder_waitok) {
3270 /* Must clear the state - therefore we did
3271 something to a state bit and must also
3272 return true. */
3273 hdw->state_encoder_waitok = 0;
3274 trace_stbit("state_encoder_waitok",
3275 hdw->state_encoder_waitok);
3276 return !0;
3277 }
3278 return 0;
3279 }
3280 if (!hdw->state_encoder_waitok) {
3281 if (!timer_pending(&hdw->encoder_wait_timer)) {
3282 /* waitok flag wasn't set and timer isn't
3283 running. Check flag once more to avoid
3284 a race then start the timer. This is
3285 the point when we measure out a minimal
3286 quiet interval before doing something to
3287 the encoder. */
3288 if (!hdw->state_encoder_waitok) {
3289 hdw->encoder_wait_timer.expires =
3290 jiffies + (HZ*50/1000);
3291 add_timer(&hdw->encoder_wait_timer);
3292 }
3293 }
3294 /* We can't continue until we know we have been
3295 quiet for the interval measured by this
3296 timer. */
3297 return 0;
3298 }
3299 pvr2_encoder_configure(hdw);
3300 if (hdw->state_encoder_ok) hdw->state_encoder_config = !0;
3301 }
3302 trace_stbit("state_encoder_config",hdw->state_encoder_config);
3303 return !0;
3304 }
3305
3306
3307 /* Evaluate whether or not state_encoder_run can change */
3308 static int state_eval_encoder_run(struct pvr2_hdw *hdw)
3309 {
3310 if (hdw->state_encoder_run) {
3311 if (hdw->state_encoder_ok) {
3312 if (hdw->state_decoder_run) return 0;
3313 if (pvr2_encoder_stop(hdw) < 0) return !0;
3314 }
3315 hdw->state_encoder_run = 0;
3316 } else {
3317 if (!hdw->state_encoder_ok) return 0;
3318 if (!hdw->state_decoder_run) return 0;
3319 if (pvr2_encoder_start(hdw) < 0) return !0;
3320 hdw->state_encoder_run = !0;
3321 }
3322 trace_stbit("state_encoder_run",hdw->state_encoder_run);
3323 return !0;
3324 }
3325
3326
3327 /* Timeout function for quiescent timer. */
3328 static void pvr2_hdw_quiescent_timeout(unsigned long data)
3329 {
3330 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3331 hdw->state_decoder_quiescent = !0;
3332 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
3333 hdw->state_stale = !0;
3334 queue_work(hdw->workqueue,&hdw->workpoll);
3335 }
3336
3337
3338 /* Timeout function for encoder wait timer. */
3339 static void pvr2_hdw_encoder_wait_timeout(unsigned long data)
3340 {
3341 struct pvr2_hdw *hdw = (struct pvr2_hdw *)data;
3342 hdw->state_encoder_waitok = !0;
3343 trace_stbit("state_encoder_waitok",hdw->state_encoder_waitok);
3344 hdw->state_stale = !0;
3345 queue_work(hdw->workqueue,&hdw->workpoll);
3346 }
3347
3348
3349 /* Evaluate whether or not state_decoder_run can change */
3350 static int state_eval_decoder_run(struct pvr2_hdw *hdw)
3351 {
3352 if (hdw->state_decoder_run) {
3353 if (hdw->state_encoder_ok) {
3354 if (hdw->state_pipeline_req &&
3355 !hdw->state_pipeline_pause) return 0;
3356 }
3357 if (!hdw->flag_decoder_missed) {
3358 pvr2_decoder_enable(hdw,0);
3359 }
3360 hdw->state_decoder_quiescent = 0;
3361 hdw->state_decoder_run = 0;
3362 /* paranoia - solve race if timer just completed */
3363 del_timer_sync(&hdw->quiescent_timer);
3364 } else {
3365 if (!hdw->state_decoder_quiescent) {
3366 if (!timer_pending(&hdw->quiescent_timer)) {
3367 /* We don't do something about the
3368 quiescent timer until right here because
3369 we also want to catch cases where the
3370 decoder was already not running (like
3371 after initialization) as opposed to
3372 knowing that we had just stopped it.
3373 The second flag check is here to cover a
3374 race - the timer could have run and set
3375 this flag just after the previous check
3376 but before we did the pending check. */
3377 if (!hdw->state_decoder_quiescent) {
3378 hdw->quiescent_timer.expires =
3379 jiffies + (HZ*50/1000);
3380 add_timer(&hdw->quiescent_timer);
3381 }
3382 }
3383 /* Don't allow decoder to start again until it has
3384 been quiesced first. This little detail should
3385 hopefully further stabilize the encoder. */
3386 return 0;
3387 }
3388 if (!hdw->state_pipeline_req ||
3389 hdw->state_pipeline_pause ||
3390 !hdw->state_pipeline_config ||
3391 !hdw->state_encoder_config ||
3392 !hdw->state_encoder_ok) return 0;
3393 del_timer_sync(&hdw->quiescent_timer);
3394 if (hdw->flag_decoder_missed) return 0;
3395 if (pvr2_decoder_enable(hdw,!0) < 0) return 0;
3396 hdw->state_decoder_quiescent = 0;
3397 hdw->state_decoder_run = !0;
3398 }
3399 trace_stbit("state_decoder_quiescent",hdw->state_decoder_quiescent);
3400 trace_stbit("state_decoder_run",hdw->state_decoder_run);
3401 return !0;
3402 }
3403
3404
3405 /* Evaluate whether or not state_usbstream_run can change */
3406 static int state_eval_usbstream_run(struct pvr2_hdw *hdw)
3407 {
3408 if (hdw->state_usbstream_run) {
3409 if (hdw->state_encoder_ok) {
3410 if (hdw->state_encoder_run) return 0;
3411 }
3412 pvr2_hdw_cmd_usbstream(hdw,0);
3413 hdw->state_usbstream_run = 0;
3414 } else {
3415 if (!hdw->state_encoder_ok ||
3416 !hdw->state_encoder_run ||
3417 !hdw->state_pipeline_req ||
3418 hdw->state_pipeline_pause) return 0;
3419 if (pvr2_hdw_cmd_usbstream(hdw,!0) < 0) return 0;
3420 hdw->state_usbstream_run = !0;
3421 }
3422 trace_stbit("state_usbstream_run",hdw->state_usbstream_run);
3423 return !0;
3424 }
3425
3426
3427 /* Attempt to configure pipeline, if needed */
3428 static int state_eval_pipeline_config(struct pvr2_hdw *hdw)
3429 {
3430 if (hdw->state_pipeline_config ||
3431 hdw->state_pipeline_pause) return 0;
3432 pvr2_hdw_commit_execute(hdw);
3433 return !0;
3434 }
3435
3436
3437 /* Update pipeline idle and pipeline pause tracking states based on other
3438 inputs. This must be called whenever the other relevant inputs have
3439 changed. */
3440 static int state_update_pipeline_state(struct pvr2_hdw *hdw)
3441 {
3442 unsigned int st;
3443 int updatedFl = 0;
3444 /* Update pipeline state */
3445 st = !(hdw->state_encoder_run ||
3446 hdw->state_decoder_run ||
3447 hdw->state_usbstream_run ||
3448 (!hdw->state_decoder_quiescent));
3449 if (!st != !hdw->state_pipeline_idle) {
3450 hdw->state_pipeline_idle = st;
3451 updatedFl = !0;
3452 }
3453 if (hdw->state_pipeline_idle && hdw->state_pipeline_pause) {
3454 hdw->state_pipeline_pause = 0;
3455 updatedFl = !0;
3456 }
3457 return updatedFl;
3458 }
3459
3460
3461 typedef int (*state_eval_func)(struct pvr2_hdw *);
3462
3463 /* Set of functions to be run to evaluate various states in the driver. */
3464 const static state_eval_func eval_funcs[] = {
3465 state_eval_pipeline_config,
3466 state_eval_encoder_ok,
3467 state_eval_encoder_config,
3468 state_eval_decoder_run,
3469 state_eval_encoder_run,
3470 state_eval_usbstream_run,
3471 };
3472
3473
3474 /* Process various states and return true if we did anything interesting. */
3475 static int pvr2_hdw_state_update(struct pvr2_hdw *hdw)
3476 {
3477 unsigned int i;
3478 int state_updated = 0;
3479 int check_flag;
3480
3481 if (!hdw->state_stale) return 0;
3482 if ((hdw->fw1_state != FW1_STATE_OK) ||
3483 !hdw->flag_ok) {
3484 hdw->state_stale = 0;
3485 return !0;
3486 }
3487 /* This loop is the heart of the entire driver. It keeps trying to
3488 evaluate various bits of driver state until nothing changes for
3489 one full iteration. Each "bit of state" tracks some global
3490 aspect of the driver, e.g. whether decoder should run, if
3491 pipeline is configured, usb streaming is on, etc. We separately
3492 evaluate each of those questions based on other driver state to
3493 arrive at the correct running configuration. */
3494 do {
3495 check_flag = 0;
3496 state_update_pipeline_state(hdw);
3497 /* Iterate over each bit of state */
3498 for (i = 0; (i<ARRAY_SIZE(eval_funcs)) && hdw->flag_ok; i++) {
3499 if ((*eval_funcs[i])(hdw)) {
3500 check_flag = !0;
3501 state_updated = !0;
3502 state_update_pipeline_state(hdw);
3503 }
3504 }
3505 } while (check_flag && hdw->flag_ok);
3506 hdw->state_stale = 0;
3507 trace_stbit("state_stale",hdw->state_stale);
3508 return state_updated;
3509 }
3510
3511
3512 static unsigned int pvr2_hdw_report_unlocked(struct pvr2_hdw *hdw,int which,
3513 char *buf,unsigned int acnt)
3514 {
3515 switch (which) {
3516 case 0:
3517 return scnprintf(
3518 buf,acnt,
3519 "driver:%s%s%s%s%s",
3520 (hdw->flag_ok ? " <ok>" : " <fail>"),
3521 (hdw->flag_init_ok ? " <init>" : " <uninitialized>"),
3522 (hdw->flag_disconnected ? " <disconnected>" :
3523 " <connected>"),
3524 (hdw->flag_tripped ? " <tripped>" : ""),
3525 (hdw->flag_decoder_missed ? " <no decoder>" : ""));
3526 case 1:
3527 return scnprintf(
3528 buf,acnt,
3529 "pipeline:%s%s%s%s",
3530 (hdw->state_pipeline_idle ? " <idle>" : ""),
3531 (hdw->state_pipeline_config ?
3532 " <configok>" : " <stale>"),
3533 (hdw->state_pipeline_req ? " <req>" : ""),
3534 (hdw->state_pipeline_pause ? " <pause>" : ""));
3535 case 2:
3536 return scnprintf(
3537 buf,acnt,
3538 "worker:%s%s%s%s%s%s",
3539 (hdw->state_decoder_run ?
3540 " <decode:run>" :
3541 (hdw->state_decoder_quiescent ?
3542 "" : " <decode:stop>")),
3543 (hdw->state_decoder_quiescent ?
3544 " <decode:quiescent>" : ""),
3545 (hdw->state_encoder_ok ?
3546 "" : " <encode:init>"),
3547 (hdw->state_encoder_run ?
3548 " <encode:run>" : " <encode:stop>"),
3549 (hdw->state_encoder_config ?
3550 " <encode:configok>" :
3551 (hdw->state_encoder_waitok ?
3552 "" : " <encode:wait>")),
3553 (hdw->state_usbstream_run ?
3554 " <usb:run>" : " <usb:stop>"));
3555 break;
3556 case 3:
3557 return scnprintf(
3558 buf,acnt,
3559 "state: %s",
3560 pvr2_get_state_name(hdw->master_state));
3561 break;
3562 default: break;
3563 }
3564 return 0;
3565 }
3566
3567
3568 unsigned int pvr2_hdw_state_report(struct pvr2_hdw *hdw,
3569 char *buf,unsigned int acnt)
3570 {
3571 unsigned int bcnt,ccnt,idx;
3572 bcnt = 0;
3573 LOCK_TAKE(hdw->big_lock);
3574 for (idx = 0; ; idx++) {
3575 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,acnt);
3576 if (!ccnt) break;
3577 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
3578 if (!acnt) break;
3579 buf[0] = '\n'; ccnt = 1;
3580 bcnt += ccnt; acnt -= ccnt; buf += ccnt;
3581 }
3582 LOCK_GIVE(hdw->big_lock);
3583 return bcnt;
3584 }
3585
3586
3587 static void pvr2_hdw_state_log_state(struct pvr2_hdw *hdw)
3588 {
3589 char buf[128];
3590 unsigned int idx,ccnt;
3591
3592 for (idx = 0; ; idx++) {
3593 ccnt = pvr2_hdw_report_unlocked(hdw,idx,buf,sizeof(buf));
3594 if (!ccnt) break;
3595 printk(KERN_INFO "%s %.*s\n",hdw->name,ccnt,buf);
3596 }
3597 }
3598
3599
3600 /* Evaluate and update the driver's current state, taking various actions
3601 as appropriate for the update. */
3602 static int pvr2_hdw_state_eval(struct pvr2_hdw *hdw)
3603 {
3604 unsigned int st;
3605 int state_updated = 0;
3606 int callback_flag = 0;
3607
3608 pvr2_trace(PVR2_TRACE_STBITS,
3609 "Drive state check START");
3610 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
3611 pvr2_hdw_state_log_state(hdw);
3612 }
3613
3614 /* Process all state and get back over disposition */
3615 state_updated = pvr2_hdw_state_update(hdw);
3616
3617 /* Update master state based upon all other states. */
3618 if (!hdw->flag_ok) {
3619 st = PVR2_STATE_DEAD;
3620 } else if (hdw->fw1_state != FW1_STATE_OK) {
3621 st = PVR2_STATE_COLD;
3622 } else if (!hdw->state_encoder_ok) {
3623 st = PVR2_STATE_WARM;
3624 } else if (hdw->flag_tripped || hdw->flag_decoder_missed) {
3625 st = PVR2_STATE_ERROR;
3626 } else if (hdw->state_encoder_run &&
3627 hdw->state_decoder_run &&
3628 hdw->state_usbstream_run) {
3629 st = PVR2_STATE_RUN;
3630 } else {
3631 st = PVR2_STATE_READY;
3632 }
3633 if (hdw->master_state != st) {
3634 pvr2_trace(PVR2_TRACE_STATE,
3635 "Device state change from %s to %s",
3636 pvr2_get_state_name(hdw->master_state),
3637 pvr2_get_state_name(st));
3638 hdw->master_state = st;
3639 state_updated = !0;
3640 callback_flag = !0;
3641 }
3642 if (state_updated) {
3643 /* Trigger anyone waiting on any state changes here. */
3644 wake_up(&hdw->state_wait_data);
3645 }
3646
3647 if (pvrusb2_debug & PVR2_TRACE_STBITS) {
3648 pvr2_hdw_state_log_state(hdw);
3649 }
3650 pvr2_trace(PVR2_TRACE_STBITS,
3651 "Drive state check DONE callback=%d",callback_flag);
3652
3653 return callback_flag;
3654 }
3655
3656
3657 /* Cause kernel thread to check / update driver state */
3658 static void pvr2_hdw_state_sched(struct pvr2_hdw *hdw)
3659 {
3660 if (hdw->state_stale) return;
3661 hdw->state_stale = !0;
3662 trace_stbit("state_stale",hdw->state_stale);
3663 queue_work(hdw->workqueue,&hdw->workpoll);
3664 }
3665
3666
3667 void pvr2_hdw_get_debug_info_unlocked(const struct pvr2_hdw *hdw,
3668 struct pvr2_hdw_debug_info *ptr)
3669 {
3670 ptr->big_lock_held = hdw->big_lock_held;
3671 ptr->ctl_lock_held = hdw->ctl_lock_held;
3672 ptr->flag_disconnected = hdw->flag_disconnected;
3673 ptr->flag_init_ok = hdw->flag_init_ok;
3674 ptr->flag_ok = hdw->flag_ok;
3675 ptr->fw1_state = hdw->fw1_state;
3676 ptr->flag_decoder_missed = hdw->flag_decoder_missed;
3677 ptr->flag_tripped = hdw->flag_tripped;
3678 ptr->state_encoder_ok = hdw->state_encoder_ok;
3679 ptr->state_encoder_run = hdw->state_encoder_run;
3680 ptr->state_decoder_run = hdw->state_decoder_run;
3681 ptr->state_usbstream_run = hdw->state_usbstream_run;
3682 ptr->state_decoder_quiescent = hdw->state_decoder_quiescent;
3683 ptr->state_pipeline_config = hdw->state_pipeline_config;
3684 ptr->state_pipeline_req = hdw->state_pipeline_req;
3685 ptr->state_pipeline_pause = hdw->state_pipeline_pause;
3686 ptr->state_pipeline_idle = hdw->state_pipeline_idle;
3687 ptr->cmd_debug_state = hdw->cmd_debug_state;
3688 ptr->cmd_code = hdw->cmd_debug_code;
3689 ptr->cmd_debug_write_len = hdw->cmd_debug_write_len;
3690 ptr->cmd_debug_read_len = hdw->cmd_debug_read_len;
3691 ptr->cmd_debug_timeout = hdw->ctl_timeout_flag;
3692 ptr->cmd_debug_write_pend = hdw->ctl_write_pend_flag;
3693 ptr->cmd_debug_read_pend = hdw->ctl_read_pend_flag;
3694 ptr->cmd_debug_rstatus = hdw->ctl_read_urb->status;
3695 ptr->cmd_debug_wstatus = hdw->ctl_read_urb->status;
3696 }
3697
3698
3699 void pvr2_hdw_get_debug_info_locked(struct pvr2_hdw *hdw,
3700 struct pvr2_hdw_debug_info *ptr)
3701 {
3702 LOCK_TAKE(hdw->ctl_lock); do {
3703 pvr2_hdw_get_debug_info_unlocked(hdw,ptr);
3704 } while(0); LOCK_GIVE(hdw->ctl_lock);
3705 }
3706
3707
3708 int pvr2_hdw_gpio_get_dir(struct pvr2_hdw *hdw,u32 *dp)
3709 {
3710 return pvr2_read_register(hdw,PVR2_GPIO_DIR,dp);
3711 }
3712
3713
3714 int pvr2_hdw_gpio_get_out(struct pvr2_hdw *hdw,u32 *dp)
3715 {
3716 return pvr2_read_register(hdw,PVR2_GPIO_OUT,dp);
3717 }
3718
3719
3720 int pvr2_hdw_gpio_get_in(struct pvr2_hdw *hdw,u32 *dp)
3721 {
3722 return pvr2_read_register(hdw,PVR2_GPIO_IN,dp);
3723 }
3724
3725
3726 int pvr2_hdw_gpio_chg_dir(struct pvr2_hdw *hdw,u32 msk,u32 val)
3727 {
3728 u32 cval,nval;
3729 int ret;
3730 if (~msk) {
3731 ret = pvr2_read_register(hdw,PVR2_GPIO_DIR,&cval);
3732 if (ret) return ret;
3733 nval = (cval & ~msk) | (val & msk);
3734 pvr2_trace(PVR2_TRACE_GPIO,
3735 "GPIO direction changing 0x%x:0x%x"
3736 " from 0x%x to 0x%x",
3737 msk,val,cval,nval);
3738 } else {
3739 nval = val;
3740 pvr2_trace(PVR2_TRACE_GPIO,
3741 "GPIO direction changing to 0x%x",nval);
3742 }
3743 return pvr2_write_register(hdw,PVR2_GPIO_DIR,nval);
3744 }
3745
3746
3747 int pvr2_hdw_gpio_chg_out(struct pvr2_hdw *hdw,u32 msk,u32 val)
3748 {
3749 u32 cval,nval;
3750 int ret;
3751 if (~msk) {
3752 ret = pvr2_read_register(hdw,PVR2_GPIO_OUT,&cval);
3753 if (ret) return ret;
3754 nval = (cval & ~msk) | (val & msk);
3755 pvr2_trace(PVR2_TRACE_GPIO,
3756 "GPIO output changing 0x%x:0x%x from 0x%x to 0x%x",
3757 msk,val,cval,nval);
3758 } else {
3759 nval = val;
3760 pvr2_trace(PVR2_TRACE_GPIO,
3761 "GPIO output changing to 0x%x",nval);
3762 }
3763 return pvr2_write_register(hdw,PVR2_GPIO_OUT,nval);
3764 }
3765
3766
3767 /* Find I2C address of eeprom */
3768 static int pvr2_hdw_get_eeprom_addr(struct pvr2_hdw *hdw)
3769 {
3770 int result;
3771 LOCK_TAKE(hdw->ctl_lock); do {
3772 hdw->cmd_buffer[0] = FX2CMD_GET_EEPROM_ADDR;
3773 result = pvr2_send_request(hdw,
3774 hdw->cmd_buffer,1,
3775 hdw->cmd_buffer,1);
3776 if (result < 0) break;
3777 result = hdw->cmd_buffer[0];
3778 } while(0); LOCK_GIVE(hdw->ctl_lock);
3779 return result;
3780 }
3781
3782
3783 int pvr2_hdw_register_access(struct pvr2_hdw *hdw,
3784 u32 match_type, u32 match_chip, u64 reg_id,
3785 int setFl,u64 *val_ptr)
3786 {
3787 #ifdef CONFIG_VIDEO_ADV_DEBUG
3788 struct pvr2_i2c_client *cp;
3789 struct v4l2_register req;
3790 int stat = 0;
3791 int okFl = 0;
3792
3793 if (!capable(CAP_SYS_ADMIN)) return -EPERM;
3794
3795 req.match_type = match_type;
3796 req.match_chip = match_chip;
3797 req.reg = reg_id;
3798 if (setFl) req.val = *val_ptr;
3799 mutex_lock(&hdw->i2c_list_lock); do {
3800 list_for_each_entry(cp, &hdw->i2c_clients, list) {
3801 if (!v4l2_chip_match_i2c_client(
3802 cp->client,
3803 req.match_type, req.match_chip)) {
3804 continue;
3805 }
3806 stat = pvr2_i2c_client_cmd(
3807 cp,(setFl ? VIDIOC_DBG_S_REGISTER :
3808 VIDIOC_DBG_G_REGISTER),&req);
3809 if (!setFl) *val_ptr = req.val;
3810 okFl = !0;
3811 break;
3812 }
3813 } while (0); mutex_unlock(&hdw->i2c_list_lock);
3814 if (okFl) {
3815 return stat;
3816 }
3817 return -EINVAL;
3818 #else
3819 return -ENOSYS;
3820 #endif
3821 }
3822
3823
3824 /*
3825 Stuff for Emacs to see, in order to encourage consistent editing style:
3826 *** Local Variables: ***
3827 *** mode: c ***
3828 *** fill-column: 75 ***
3829 *** tab-width: 8 ***
3830 *** c-basic-offset: 8 ***
3831 *** End: ***
3832 */
Verdex Pro support